MB9G711 LSI Product Specifications PRELIMINARY

MB9G711 LSI Product Specifications

Aug, 2010 the 0.6 edition

FUJITSU SEMICONDUCTOR PROPRIETARY AND CONFIDENTIAL

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Preface

Objectives and Intended Reader Thank you very much for your continued special support for Fujitsu semiconductor products. This manual describes functions and operations of MB9G711 for engineers who design products using MB9G711. Read through this manual before use.

Trademarks ARM is a registered trademark of ARM Limited in UK, USA and Taiwan. ARM is a trademark of ARM Limited in Japan and Korea. ARM Powered logo is a registered trademark of ARM Limited in Japan, UK, USA, and Taiwan. ARM Powered logo is a trademark of ARM Limited in Korea. ARM946ES is a trademark of ARM Limited. The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Hardware Related Manuals MB9G711 hardware related manuals are shown below. Refer to them as the situation demands.

• MB9G711 LSI product specification SD memory controller (Note) Note) This specification document is for SD card licensee.

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· The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering. · The information, such as descriptions of function and application circuit examples, in this document are

presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

· Any information in this document, including descriptions of function and schematic diagrams, shall not be

construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein.

· The products described in this document are designed, developed and manufactured as contemplated for

general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

· Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or

loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

· Exportation/release of any products described in this document may require necessary procedures in

accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

· The company names and brand names herein are the trademarks or registered trademarks of their respective

owners. Copyright © 2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved.

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Revision History Date Ver. Details

2009/Nov/11 0.0 First release 2010/Jan/06 0.1 All sections

• Changed part name from MB9F981 to MB9G711 Section 1.4 Package dimension

• Added FPT-144P-M08 package dimension. Section 1.7 Device handling

• Added description for power on sequence and added power on reset sub-section. Section 20:

• Corrected input mistakes. Section 23 NAND Flash interface

• Changed the section number of NAND Flash Interface from 22 to 23. Section 23.6.4 Flash area register (FAREA)

• Change the ADDR field in Flash area register (FAREA) to reserved values. • Change the description of the ADDR field

Section 23.9.1 NAND Flash Access • Corrected NAND Read and write access flow chart. • Added more descriptions in notes for NAND read/write access. • Specified External NAND flash base address to 0x0400_00003.

2010/Jan/08 0.2 Section 1.5 Pin assignment (Preliminary) • Corrected color for UAVSB (Pin11) and UAVDB (Pin13) • Pin113: Corrected NFALE to NFWEX • Pin133: Corrected NFWEX to NFALE

Section 23.6.3 Flash timing register (FTIM) • Added RACC field description.

2010/Jan/19 0.3 Section 1.6.5 USB 2.0 Host related pin • Changed pin names as follows: • UAVSF1-1 -> UAVSF1-2 • UAVSF1-2 -> UAVSF1-3 • UAVSF1-3 -> UAVSF1-4

Section 1.6.8 SIO related pin • Changed pin names as follows: • SIO0CK -> SIO0SCK • SIO1CK -> SIO1SCK • SIO2CK -> SIO2SCK • SIO3CK -> SIO3SCK • SIO4CK -> SIO4SCK

Section 1.6.12 SPI related pin • Changed pin names as follows: • SPI0SCK -> SPI0CK • SPI0SCK -> SPI1CK • SPI0DO -> SPI1DO • SPI0DI -> SPI1DI • SPI0CX -> SPI1CX

Section 1.7 Device handling • Added RSTX Low time for 65us during the use of RTC.

2010/Mar/26 0.4 Section 26.6.43 PHY Mode Setting 1 Register • Corrected the initial value.

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Date Ver. Details 2010/Jun/28 0.5 Section 1.5 Pin Assignment

• Removed (Preliminary) from the section title. Section 3.3 Register map

• Corrected IR0DICR0/1 register explanation in IRC0 mirror. • Corrected register name and explanation for address FFFE_8014H and FFFE_8018H. • Added IRC1 mirror address content. • Corrected register name for Timer0/1. • Corrected the name of the module from FFF8_00A8H to FFF8_1FFFH from USB 2.0 EHCI

Host to USB 2.0 OHCI Host. Section 4. CPR (ARM946E-S core part)

• Corrected the model number of the CPU from ARM946J-S to ARM946E-S. Section 4.3. Block diagram

• Corrected the model number of the core block from ARM946JS to ARM946ES. Section 5.4.2. PLL control register (CRPR)

• Corrected PLL lookup waiting time when LUWMODE[1:0] is 00h and CLK is 48MHz. • Corrected the bit name of XCLKMODE from XCLKMODE[4:0] to XCLKMODE[2:0].

Section 5.4.4. Reset/Standby control register (CRSR) • Rewrote the bit description of SRST and SWRST bit.

Section 5.4.5. Clock divider control register A (CRDA) • Added description for maximum input frequency of clock domains.

Section 5.4.6. Clock divider control register B (CRDB) • Added description for maximum input frequency of AHB2 clock domain.

Section 5.4.7. AHB (AHB1) bus clock gate control register (CRHA) • Corrected HACK2 description, deleted SRAM0 because it used in HACK5. • Corrected HACK5 description, deleted SRAM1 because it used in HACK2.

Section 5.4.11. ARM core clock gate control register (CRAM) • Corrected bit 4 from reserved to USBGATE.

Section 5.5.2. Clock generation • Added more Ln value for 64 and 128 in Figure 5-3. • Corrected CRIPM[3:0] to PLLMODE[4:0] in Frequency change description. • Added Figure 5-9 description.

Section 6.4.2: PLL control register (AUCGPR) • Added maximum frequency of FCCLK.

Section 6.4.6: Audio clock gate control register (AUCGGC) • Correct based register address to FFF5_3800H.

Section 6.4.4: Clock divider control register A (AUCGDA) • Updated description of I2S0DM and I2S1DM.

Section 6.5.1: Clock generation • Correct clock generation chart.

Section 8.4.2 Extension IRQ interrupt vector of IRC0/IRC1 • Changed the “Expansion IRQ” to “Extension IRQ” to match the same term in Table 8-2.

Section 8.5.1 Register list • Corrected IRC1 base address from FFFF_0000 H to FFFE_5000 H in Table 8-4.

Section 8.5.2 to Section 8.5.10 • Corrected IRC1 base address in register description.

Section 8.5.5. ICR monitoring register (IR0ICRMN/IR1ICRMN) • Re-wrote the description for IR0ICRMN/IR1ICRMN

Section 8.5.6 and 8.5.7: Delay interrupt control register 0/1 • Deleted IRC1 address because there is no register for delay interrupt in IRC1.

Section 8.5.7. Delay interrupt control register 1 (IR0DICR1) • Added description for DLYI1 bit.

Section 8.5.9. Interrupt vector register (IR0VCT/IR1VCT) • Changed the reference table description of VCT31-0

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Date Ver. Details 2010/Jun/28 0.5 Section 8.5.10 Interrupt control register (IR0ICR31/IR1ICR31 – IR0ICR00/IR1ICR00)

• Corrected the register description to match with “smaller” symbol. Section 9.6.5. DMAC source address register (DMACSAx)

• Corrected transfer width (DMACB/TW) description. Section 10.4.1 Register list

• Corrected base address of timer1. Sections 10.4.2, 10.4.3, 10.4.8

• Corrected Register bit[7:4] Read/Write attribute from R0 to R/W. Section 10.4.5. Timer interrupt clear register (TIMERxxINTCLR)

• Added detail description for register TIMERxxINTCLR. Section 12.4.5 Port function select register (CPSEL)

• Corrected CPSEL[16] = 1 to CPSEL[21 = 1 and CPSEL[17] = 1 to CPSEL[22] = 1 in the priority table.

Section 13.6.2. External interrupt enable register (EIENBx) • Added address descriptions.

Section 13.6.3. External interrupt request register (EIREQx) • Added address descriptions.

Section 13.6.4. External interrupt level register (EILVLx) • Added address descriptions.

Section 14.7.6. PWMx status register (PWMxCR) • Updated bit description of EXEDG and EXTRG.

Section 15.7.3. Data Transfer from Audio Output Data FIFO (AUFIFO) to Delta-Sigma D/A Converter (DAC)

• Added DMA transfer usage description. Section 16.6.3 ADC mode register (ADMR)

• Corrected MD[1:0] description – ADCNT.APDC should be 0 for ADC power down on completion.

Section 16.6.2 ADC control register (ADCNT) • Update description for TGS[1:0] field.

Section 17.6.4 Communication Pre-scalar (SIOxCDCR) • Updated description for MD and DIV[3:0] fields.

Section 17.8 Notes on Application • Changed description in “Notes on program setting”.

Section 18.6.1. Divider latch register (URTxDLL&URTxDLM) • Changed CRIPM[3:0] to CRG.CRPR.PLLMODE[3:0] in Table 18-3.

Section 18.6.11. Divide latch register (URTxDLL&URTxDLM) • Corrected DL[15:0] to DL[15:8] in [DLM].

Section 23.6.3 Flash timing register (FTIM) • Corrected the description of RACC.

Section 23.6.5 ECC control register (ECCR) • Corrected the description of the value of the DECERR0/1 bit being “1”.

Section 24.5.3 Second interval register (RTCPRSR) • Corrected the description of PRSR[17:0].

Section 24.5.5. Date register (RTCDATE) • Corrected DAY[4:0] in bit description table.

Section 24.5.8. Time compare register (RTCCOMP) • Corrected spacing in the register bit table.

Section 25.5.6. Timer control status register (IPTCSR) • Updated the description for MSI[2:0] field.

Section 26.6.43 PHY Mode Setting 1 Register (PHYModeSetting1) • Added descriptions for RESET and ANPD bits.

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Date Ver. Details 2010/Aug/27 0.6 Section 1.5. Pin Assignment

• Added color shading for ADVDD and ADVSS in Figure 1-3. Section 1.6.17. Audio D/A converter related pin

• Corrected AULCP and AURCP from input to output. Section 2.1 Operating modes

• Modified Table 1. Section 3.2 Register access

• Added CAN registers for half-world access only in Table 3-1. Section 3.3 Register map

• Corrected TMRxx to TIMERxx for Timer0/1 in Table 3-2 • Corrected NFIF address for reserved area.

Section 4. CPR (ARM946E-S core part) • Corrected the model number of the CPU from ARM946J-S to ARM946E-S.

Section 4.3. Block diagram • Corrected the model number of the core block from ARM946JS to ARM946ES.

Section 5.4.1. Register list, CRAM • Removed “and USB core clock and”.

Section 5.4.2. PLL control register (CRPR), register bit-8 PLLRDY • Corrected typo, “LUMMODE” -> “LUWMODE”. • Corrected R/W access of XCLKMODE[2:0]

Section 5.4.4. Reset/Standby control register (CRSR), register bit-7 STOPEN • Changed “standby mode” to “standby wait for interrupt”. • Added “when ARM core goes into” after “This bit stops all bus clock operations”

Section 5.4.7. AHB (AHB1) bus clock gate control register (CRHA) • Changed “AHB (AHB1)” to “AHB (A)”. • Added “AHB1 bus matrix, AHB2 bus matrix” to “HACLK0”.

Section 5.4.8. APB (A) bus clock gate control register (CRPA) • Deleted UART5 in PACLK13 in field PAGATE[15:0]

Section 5.4.9 APB (B) bus clock gate control register (CRPB) • Deleted SIO5 in PBCLK2 in field PBGATE[15:0].

Section 5.4.11. ARM core clock gate control register (CRAM) • Added description about watchdog reset clears ARMCLK gate.

Section 5.5.1. Generation of reset • Changed “When external pin” to “After external reset” in “1.External reset”. • Changed “standby mode (standby mode = 1)” to “stop or sleep mode” in “5.Watchdog reset”. • Changed “standby mode of ARM9” to “standby wait of interrupt (STANDBYWFI) of

ARM9” in “5.Watchdog reset”. Section 5.5.2. Clock generation

• Changed “Standby mode” to “Low power consumption modes” which includes “stop mode”, “sleep mode” and “clock gating”.

• Removed “Initial value at start up is determined by external pin, ” in “Frequency change”. • Added reference to section 13.9 in Stop mode section.

Section 7.1. Outline • Modified the paragraph for better description

Section 7.3 Block diagram • Corrected VINITHI to fixed L in Figure 7-1. • Delete Table 7-1 because VINITHI has no external port function in this LSI

Section 7.5.3 VINITHI control register A (RBVIHA) • Corrected the initial value of VIHA field and modified the description

Section 7.6.1 RBC reset • Modified the reset description of RBVIHA

Section 7.6.3 VINITHI control • Modified the initial value description of RBVIHA.

Section 8.5.7. Delay interrupt control register 1 (IR0DICR1) • Modified description of DLY11 field

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Date Ver. Details 2010/Aug/27 0.6 Section 8.5.9. Interrupt vector register (IR0VCT/IR1VCT)

• Modified description of VCT31-0 field. Section 9.3 DMA requests signals

• Add more description for I2S DMA in Table 9-1. Section 9.6.4 DMA configuration B register (DMACBx)

• Added description of SP and DP bits. Section 9.8.1. DMA start in single channel

• Modified the remark in Figure 9-11. Section 10.4.1 Register list

• Corrected base address of timer1. • Corrected TIMER02BGLOAD to TIMER12BGLOAD. • Corrected table number of Table 10-1.

Section 11.6.1 Direction control • Modified Note in this section.

Section 12.4.6 NFRDY interrupt register (CNFR) • Modified field description of NFRE.

Section 12.4.8 Peripheral data wrapper control register (CDWS) • Modified field description of SDCDWS[1:0], I2SxDWS[1:0], USBDWS[1:0].

Section 13 • Corrected all table and figure number.

Section 13.6.2 External interrupt enable register (EIENBx) • Modified field description of ENB3-0.

Section 13.6.3 External interrupt request register (EIREQx) • Modified field description of REQ3-0.

Section 13.6.4 External interrupt level register (EILVLx) • Modified field description of LVLx[1:0].

Section 15.6.2 Audio Output Data Buffer Register (AUFIFO) • Added output voltage description for AUFIFO[31:0] value.

Section 15.6.3 Audio Control and Status Register (AUCSR) • Modified field description of FFST[3:0], INT, FS[3:0].

Section 15.8 Application Notes • Add description between APB and DAC clock timing.

Section 16.4 Related Pin • Corrected ADAVD and ADAVS to ADVDD and ADVSS.

Section 18.6.2. Reception FIFO register (URTxRFR) • Modified the field description of RFR[7:0].

Section 18.6.3. Transmission FIFO register (URTxTFR) • Modified field description of TFR[7:0].

Section 18.6.5. Interrupt ID register (URTxIIR) • Corrected the description of ID2:0, NINT field.

Section 18.6.8. Modem control register (URTxMCR) • Modified the field description of LOOP, OUT1/2, RTS and DTR.

Section 18.6.9. Line status register (URTxLSR) • Modified the field description of ERRF, BI, OE.

Section 18.6.10. Modem status register (URTxMSR) • Modified the field description of DCD, RI, DSR, CTS.

Section 18.6.11. Divider latch register (URTxDLL&URTxDLM) • Modified notes in DLM register.

Section 18.7.4. Basic transmission operation • Modified the description of this section.

Section 18.7.5. Basic reception operation • Modified the description of this section.

Section 18.7.6. Line status • Modified the description of FE flag and BI flag, PE flag, ERRF flag.

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Date Ver. Details 2010/Aug/27 0.6 Section 19.1. Outline

• Modified the content. Section 19.6.2. Bus status register (I2CxBSR)

• Modified the description of AL field. Section 19.6.4. Clock control register (I2CxCCR)

• Modified the description of field CS4-0. Section 19.6.6. Data register (I2CxDAR)

• Added description for address transmission. Section 19.6.8. Expansion CS register (I2CxECSR)

• Modified the field description of CS[10:5]. Section 19.8. Notice

• Modified the description of “Restrictions” part. • Corrected mistakes in “System clock and fscl of this module”.

Section 20 • Added SPI1 related register description. • Corrected SPI_SS to SPIxCX. • Corrected SPI_SCK to SPIxCK. • Corrected SPI_DI to SPIxDI. • Corrected SPI_DO to SPIxDO.

Section 20.6.1. Register list • Modified SPI register list description.

Section 21.4. Register • Modified description of this section.

Section 22.4. Related pin • Modified the description of this section.

Section 22.6.2. I2SxRXFDAT register • Modified the field description of RXDATA[31:0]. • Corrected FIFO size from 18 words to 66 words.

Section 22.6.3. I2SxTXFDAT register • Modified the field description of TXDATA[31:0]. • Corrected FIFO size from 18 words to 66 words.

Section 22.6.4. I2SxCNTREG register • Modified the field description of OVHD[9:0], RHLL, BEXT, SMPL and CPOL • Added a note for recommendation of frame rate setting in OVHD field.

Section 22.6.5. I2SxMCR0REG register • Corrected the field description of S0CHL[4:0] and S0WDL[4:0].

Section 22.6.6. I2SxMCR1REG register • Modified field description.

Section 22.6.11. I2SxSTATUS register • Modified the field description of TBERR, RBERR, TXFI, RXFI, TXNUM[7:0] and

RXNUM[7:0]. • Modified bit [7:6] and [15:14] from reserved to RXNUM and TXNUM value because the

maximum FIFO data size can be up to 132. • Changed size of TXNUM and RXNUM from 6 bits to 8 bits.

Section 22.6.12. I2SxDMAACT register • Corrected typo in RDMACT field. • Added further description of DMA in TDMACT and RDMACT

Section 22.7.1. Outline • Correct the FIFO size from 18 words to 66 words.

Section 22.7.3.1 1. sub frame construction • Modified the description.

Section 22.7.3.3. Bit alignment • Modified the description.

Section 22.7.4. FIFO construction and description • Corrected TX and RX FIFO value from 18 words to 66 words.

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Date Ver. Details 2010/Aug/27 0.6 Section 23.6.1. Register list

• Modified the register description in Table 23-2. Section 23.6.3 Flash timing register (FTIM)

• Modified the field description for WACC. • Added the reserved cycle setting in Read Idle Cycle (RIDLC).

Section 23.6.4 Flash area register (FAREA) • Modified the field description of MASK.

Section 23.8. Example of access waveform • Modified Figure 23-4.

Section 23.9.1 NAND Flash Access • Modified the content.

Section 24.5.1. Register list • Modified the description of RTCPRSR register in Table 24-2.

Section 24.5.3. Second interval register (RTCPRSR) • Modified the content of Note.

Section 24.5.4. Time register (RTCTIME) • Modified field description of HRS, MIN, SEC.

Section 24.5.5. Date register (RTCDATE) • Modified field description of YRS, MON, DAY.

Section 25.5.4. Timer compare register (IPCPCLR) • Modified the field description of the CLR field.

Section 26.6.7. USB Interrupt Enable Register (USBINTR) Modified field description of all fields in this register.

Section 26.6.12. Configured Flag Register (CONFIGFLAG) Modified the field description of the CF field.

Section 26.6.22. Command/Status Register (HcCommandStatus) Modified the field description of the SOC, BLF fields. Corrected R/W field of OCR, BLF, CLF, HCR from R to R/W.

Section 26.6.27. Periodic Current ED Register (HcPeriodCurrentED) Corrected the R/W field of PCED from R/W to R.

Section 26.6.32. Done Head Register (HcDoneHead) Corrected the R/W field of PCED from R/W to R.

Section 26.6.38. Root Hub Descriptor A Register (HcRhDescriptorA) Modified the field description of the NDP field.

Section 26.6.4.1 Root Hub Port Status/Control Register 1 • Modified the field description of the LSDA, PPS, PES fields.

Section 27 SD memory controller (SDMC) • Modified description and add note for DMA transfer setting in this LSI.

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Contents 1. Overview ........................................................................................................... 1-1

1.1. Feature .................................................................................................................................................. 1-1 1.2. Block diagram ...................................................................................................................................... 1-2 1.3. Function list .......................................................................................................................................... 1-4 1.4. Package dimension ............................................................................................................................... 1-6 1.5. Pin assignment ..................................................................................................................................... 1-8 1.6. Pin function .......................................................................................................................................... 1-9

1.6.1. Pin Multiplex ................................................................................................................................ 1-9 1.6.2. Pin function description ............................................................................................................. 1-10 1.6.3. NandFlash interface related pin .................................................................................................. 1-11 1.6.4. SD memory controller related pin .............................................................................................. 1-11 1.6.5. USB 2.0 Host related pin ............................................................................................................ 1-11 1.6.6. External interrupt controller related pin ..................................................................................... 1-12 1.6.7. UART related pin ....................................................................................................................... 1-12 1.6.8. SIO related pin ........................................................................................................................... 1-12 1.6.9. CAN related pin ......................................................................................................................... 1-13 1.6.10. I2S related pin ............................................................................................................................. 1-13 1.6.11. I2C related pin ............................................................................................................................ 1-13 1.6.12. SPI related pin ............................................................................................................................ 1-13 1.6.13. PWM related pin ........................................................................................................................ 1-14 1.6.14. Input Capture Timer related pin ................................................................................................. 1-14 1.6.15. GPIO related pin ........................................................................................................................ 1-14 1.6.16. A/D converter related pin ........................................................................................................... 1-14 1.6.17. Audio D/A converter related pin ................................................................................................ 1-14 1.6.18. System related pin ...................................................................................................................... 1-15 1.6.19. JTAG / ICE related pin ............................................................................................................... 1-16 1.6.20. Power supply related pin ............................................................................................................ 1-16

1.7. Device handling ................................................................................................................................. 1-17

2. System configuration ...................................................................................... 2-1

2.1. Operating Modes .................................................................................................................................. 2-1 2.2. Note on system power up / down ......................................................................................................... 2-1

3. Memory map .................................................................................................... 3-1

3.1. Memory map of LSI ............................................................................................................................. 3-1 3.2. Register access ..................................................................................................................................... 3-2 3.3. Register map ........................................................................................................................................ 3-3

4. CPU (ARM946E-S core part) ........................................................................... 4-1

4.1. Outline .................................................................................................................................................. 4-1 4.2. Feature .................................................................................................................................................. 4-1 4.3. Block diagram ...................................................................................................................................... 4-1 4.4. ARM946E-S ......................................................................................................................................... 4-1

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5. Clock and reset generator (CRG) ................................................................... 5-1

5.1. Outline .................................................................................................................................................. 5-1 5.2. Feature .................................................................................................................................................. 5-1 5.3. Block diagram ...................................................................................................................................... 5-2 5.4. Register ................................................................................................................................................ 5-3

5.4.1. Register list .................................................................................................................................. 5-3 5.4.2. PLL control register (CRPR) ........................................................................................................ 5-5 5.4.3. Watchdog timer control register (CRWR) .................................................................................... 5-7 5.4.4. Reset/Standby control register (CRSR) ........................................................................................ 5-9 5.4.5. Clock divider control register A (CRDA) ................................................................................... 5-11 5.4.6. Clock divider control register B (CRDB) ................................................................................... 5-12 5.4.7. AHB (A) bus clock gate control register (CRHA) ..................................................................... 5-13 5.4.8. APB (A) bus clock gate control register (CRPA) ....................................................................... 5-14 5.4.9. APB (B) bus clock gate control register (CRPB) ....................................................................... 5-15 5.4.10. AHB (B) bus clock gate control register (CRHB) ...................................................................... 5-16 5.4.11. ARM core clock gate control register (CRAM) ......................................................................... 5-17

5.5. Operation ............................................................................................................................................ 5-18 5.5.1. Generation of reset ..................................................................................................................... 5-18 5.5.2. Clock generation ........................................................................................................................ 5-21

6. Audio Clock Generator (AUCLKG) ................................................................. 6-1

6.1. Outline .................................................................................................................................................. 6-1 6.2. Feature .................................................................................................................................................. 6-1 6.3. Block diagram ...................................................................................................................................... 6-2 6.4. Register ................................................................................................................................................ 6-3

6.4.1. Register list .................................................................................................................................. 6-3 6.4.2. PLL control register (AUCGPR) .................................................................................................. 6-5 6.4.3. Wait time reset register (AUCGWR) ........................................................................................... 6-7 6.4.4. Clock divider control register A (AUCGDA) ............................................................................... 6-8 6.4.5. Clock divider control register B (AUCGDB) ............................................................................... 6-9 6.4.6. Audio clock gate control register (AUCGGC) ........................................................................... 6-10

6.5. Operation ............................................................................................................................................ 6-11 6.5.1. Clock generation ........................................................................................................................ 6-11

7. Remap boot controller (RBC) ......................................................................... 7-1

7.1. Outline .................................................................................................................................................. 7-1 7.2. Feature .................................................................................................................................................. 7-1 7.3. Block diagram ...................................................................................................................................... 7-1 7.4. Supply clock ......................................................................................................................................... 7-2 7.5. Register ................................................................................................................................................ 7-2

7.5.1. Register list .................................................................................................................................. 7-2 7.5.2. Remap control register (RBREMAP) ........................................................................................... 7-4 7.5.3. VINITHI control register A (RBVIHA) ....................................................................................... 7-5 7.5.4. INITRAM control register A (RBITRA) ...................................................................................... 7-6

7.6. Operation .............................................................................................................................................. 7-7 7.6.1. RBC reset ..................................................................................................................................... 7-7 7.6.2. Remap control .............................................................................................................................. 7-7 7.6.3. VINITHI control .......................................................................................................................... 7-7

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7.6.4. INITRAM control ........................................................................................................................ 7-8

8. Interrupt controller (IRC) ................................................................................. 8-1

8.1. Outline .................................................................................................................................................. 8-1 8.2. Feature .................................................................................................................................................. 8-1 8.3. Supply clock ......................................................................................................................................... 8-2 8.4. Interrupt map ........................................................................................................................................ 8-2

8.4.1. Exception vector to ARM946E-S core ......................................................................................... 8-2 8.4.2. Extension IRQ interrupt vector of IRC0/IRC1 ............................................................................. 8-3

8.5. Register ................................................................................................................................................ 8-4 8.5.1. Register list .................................................................................................................................. 8-4 8.5.2. IRQ flag register (IR0IRQF/ IR1IRQF) ....................................................................................... 8-8 8.5.3. IRQ mask register (IR0IRQM/IR1IRQM) ................................................................................... 8-9 8.5.4. Interrupt level mask register (IR0ILM/IR1ILM) ........................................................................ 8-10 8.5.5. ICR monitoring register (IR0ICRMN/IR1ICRMN) ................................................................... 8-11 8.5.6. Delay interrupt control register 0 (IR0DICR0) .......................................................................... 8-12 8.5.7. Delay interrupt control register 1 (IR0DICR1) .......................................................................... 8-13 8.5.8. Table base register (IR0TBR/IR1TBR) ...................................................................................... 8-14 8.5.9. Interrupt vector register (IR0VCT/IR1VCT) ............................................................................. 8-15 8.5.10. Interrupt control register (IR0ICR31/IR1ICR31 – IR0ICR00/IR1ICR00) ................................. 8-16

8.6. Operation ............................................................................................................................................ 8-17 8.6.1. Outline ........................................................................................................................................ 8-17 8.6.2. Initialization ............................................................................................................................... 8-17 8.6.3. Multiple interrupt process .......................................................................................................... 8-18 8.6.4. Example of IRQ interrupt handler .............................................................................................. 8-18 8.6.5. Resume from Stop and standby modes ...................................................................................... 8-20 8.6.6. Notice for using IRC .................................................................................................................. 8-20

9. DMA controller (DMAC) ................................................................................... 9-1

9.1. Outline .................................................................................................................................................. 9-1 9.2. Feature .................................................................................................................................................. 9-1 9.3. DMA requests signals .......................................................................................................................... 9-2 9.4. Related pin ........................................................................................................................................... 9-2 9.5. Supply clock ......................................................................................................................................... 9-2 9.6. Register ................................................................................................................................................ 9-3

9.6.1. Register list .................................................................................................................................. 9-3 9.6.2. DMA configuration register (DMACR) ....................................................................................... 9-5 9.6.3. DMA configuration A register (DMACAx) ................................................................................. 9-7 9.6.4. DMA configuration B register (DMACBx) ............................................................................... 9-10 9.6.5. DMAC source address register (DMACSAx) ............................................................................ 9-13 9.6.6. DMAC destination address register (DMACDAx) .................................................................... 9-14

9.7. Operation ............................................................................................................................................ 9-15 9.7.1. Transfer mode ............................................................................................................................ 9-15 9.7.2. Beat transfer ............................................................................................................................... 9-27 9.7.3. Channel priority control ............................................................................................................. 9-29 9.7.4. Retry, split, and error .................................................................................................................. 9-31

9.8. Example of DMAC setting ................................................................................................................. 9-33 9.8.1. DMA start in single channel ....................................................................................................... 9-33 9.8.2. DMA start in all channels (in demand transfer mode) ................................................................ 9-34

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10. Timer (TIMER0/1) ........................................................................................... 10-1

10.1. Outline ................................................................................................................................................ 10-1 10.2. Features .............................................................................................................................................. 10-1 10.3. Supply clock ....................................................................................................................................... 10-1 10.4. Register .............................................................................................................................................. 10-2

10.4.1. Register list ................................................................................................................................ 10-2 10.4.2. Timer load register (TIMERxxLOAD) ...................................................................................... 10-4 10.4.3. Timer current value register (TIMERxxVALUE) ...................................................................... 10-4 10.4.4. Timer control register (TIMERxxCONTROL) .......................................................................... 10-5 10.4.5. Timer interrupt clear register (TIMERxxINTCLR) ................................................................... 10-6 10.4.6. Timer raw interrupt status register (TIMERxxRIS) ................................................................... 10-6 10.4.7. Timer masked interrupt status register (TIMERxxMIS) ............................................................ 10-7 10.4.8. Timer background load register (TIMERxxBGLOAD) ............................................................. 10-7

11. General-purpose input/output port (GPIO) .................................................. 11-1

11.1. Outline ................................................................................................................................................ 11-1 11.2. Feature ................................................................................................................................................ 11-1 11.3. Block diagram .................................................................................................................................... 11-1 11.4. Supply clock ....................................................................................................................................... 11-1 11.5. Register .............................................................................................................................................. 11-2

11.5.1. Register list ................................................................................................................................ 11-2 11.5.2. Port data registers (GPDRXX) ................................................................................................... 11-4 11.5.3. Data direction registers (GPDDRXX) ........................................................................................ 11-5

11.6. Operation ............................................................................................................................................ 11-6 11.6.1. Direction control ........................................................................................................................ 11-6 11.6.2. Data transfer ............................................................................................................................... 11-6

12. Chip Control Module (CCNT) ........................................................................ 12-1

12.1. Outline ................................................................................................................................................ 12-1 12.2. Feature ................................................................................................................................................ 12-1 12.3. Supply clock ....................................................................................................................................... 12-1 12.4. Register .............................................................................................................................................. 12-2

12.4.1. Register list ................................................................................................................................ 12-2 12.4.2. CHIP mode register (CMDR) ..................................................................................................... 12-4 12.4.3. Macro reset register (CSRST) .................................................................................................... 12-5 12.4.4. USB miscellanies control register (CUSBC) ............................................................................. 12-6 12.4.5. Port function select register (CPSEL) ........................................................................................ 12-7 12.4.6. NFRDY interrupt register (CNFR) ............................................................................................. 12-8 12.4.7. SD Card clock selection register (CSDMC) ............................................................................... 12-9 12.4.8. Peripheral data wrapper control register (CDWS) ................................................................... 12-10 12.4.9. CHIP ID register (CCID) ......................................................................................................... 12-11

13. External interrupt controller (EXIRC) ........................................................... 13-1

13.1. Outline ................................................................................................................................................ 13-1 13.2. Feature ................................................................................................................................................ 13-1 13.3. Usage limitation ................................................................................................................................. 13-1 13.4. Related Pin ......................................................................................................................................... 13-2

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13.5. Supply clock ....................................................................................................................................... 13-2 13.6. Register .............................................................................................................................................. 13-3

13.6.1. Register list ................................................................................................................................ 13-3 13.6.2. External interrupt enable register (EIENBx) .............................................................................. 13-5 13.6.3. External interrupt request register (EIREQx) ............................................................................. 13-6 13.6.4. External interrupt level register (EILVLx) ................................................................................. 13-7

13.7. Operation ............................................................................................................................................ 13-8 13.8. Operation procedure ........................................................................................................................... 13-8 13.9. Instruction for use .............................................................................................................................. 13-8

14. Pulse Width Modulator (PWM) ...................................................................... 14-1

14.1. Outline ................................................................................................................................................ 14-1 14.2. Feature ................................................................................................................................................ 14-1 14.3. Block diagram .................................................................................................................................... 14-1 14.4. Related pin ......................................................................................................................................... 14-1 14.5. Supply clock ....................................................................................................................................... 14-2 14.6. Interrupt .............................................................................................................................................. 14-2 14.7. Register .............................................................................................................................................. 14-2

14.7.1. Register list ................................................................................................................................ 14-2 14.7.2. PWMx base clock register (PWMxBCR) ................................................................................... 14-5 14.7.3. PWMx pulse width register (PWMxTPR) ................................................................................. 14-6 14.7.4. PWMx phase register (PWMxPR) ............................................................................................. 14-7 14.7.5. PWMx duty register (PWMxDR) ............................................................................................... 14-8 14.7.6. PWMx status register (PWMxCR) ............................................................................................. 14-9 14.7.7. PWMx start register (PWMxSR) ............................................................................................. 14-10 14.7.8. PWMx current count register (PWMxCCR) ............................................................................ 14-11 14.7.9. PWMx interrupt register (PWMxIR) ....................................................................................... 14-12

14.8. Example of setting register ............................................................................................................... 14-13

15. D/A converter ................................................................................................. 15-1

15.1. Outline ................................................................................................................................................ 15-1 15.2. Feature ................................................................................................................................................ 15-1 15.3. Block diagram .................................................................................................................................... 15-2 15.4. Related pin ......................................................................................................................................... 15-2 15.5. Supply clock ....................................................................................................................................... 15-2 15.6. Register .............................................................................................................................................. 15-3

15.6.1. Register list ................................................................................................................................ 15-3 15.6.2. Audio Output Data Buffer Register (AUFIFO) .......................................................................... 15-5 15.6.3. Audio Control and Status Register (AUCSR) ............................................................................ 15-7

15.7. Basic operation ................................................................................................................................. 15-11 15.7.1. Delta-Sigma DAC Initialization ............................................................................................... 15-11 15.7.2. Delta-Sigma D/A Converter (DAC) Sampling Frequency and Oversampling Ratio ............... 15-12 15.7.3. Data Transfer from Audio Output Data FIFO (AUFIFO) to Delta-Sigma D/A Converter (DAC)15-12

15.8. Application Notes............................................................................................................................. 15-13 15.9. Application Example ........................................................................................................................ 15-13

15.9.1. Basic Connection Diagram ....................................................................................................... 15-13 15.9.2. Post LPF/ Buffer ....................................................................................................................... 15-13

16. A/D converter ................................................................................................. 16-1

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16.6.1. Register list ................................................................................................................................ 16-3 16.6.2. ADC control register (ADCNT) ................................................................................................. 16-5 16.6.3. ADC mode register (ADMR) ..................................................................................................... 16-7 16.6.4. ADC Status register (ADST) ...................................................................................................... 16-9 16.6.5. ADCx data registers (ADDx) ................................................................................................... 16-11 16.6.6. ADC data lower limit compare register (ADCRL) .................................................................. 16-12 16.6.7. ADC data upper limit compare register (ADCRH) .................................................................. 16-12

16.7. Notes on Application ........................................................................................................................ 16-13

17. SIO interface .................................................................................................. 17-1


17.6.1. Register list ................................................................................................................................ 17-3 17.6.2. Serial Mode Control Status Register (SIOxSMCS) ................................................................... 17-5 17.6.3. Serial Data register (SIOxSDR) ................................................................................................. 17-6 17.6.4. Communication Pre-scalar (SIOxCDCR) .................................................................................. 17-7

17.7. Operation Description ........................................................................................................................ 17-8 17.7.1. Operating States of the SIO Interface ......................................................................................... 17-8 17.7.2. Interrupt ...................................................................................................................................... 17-9 17.7.3. Operating Timing of the SIO Interface ....................................................................................... 17-9

17.8. Notes on Application ........................................................................................................................ 17-11

18. UART interface ............................................................................................... 18-1


18.6.1. Register list ................................................................................................................................ 18-3 18.6.2. Reception FIFO register (URTxRFR) ........................................................................................ 18-6 18.6.3. Transmission FIFO register (URTxTFR) ................................................................................... 18-6 18.6.4. Interrupt enable register (URTxIER) .......................................................................................... 18-7 18.6.5. Interrupt ID register (URTxIIR) ................................................................................................. 18-8 18.6.6. FIFO control register (URTxFCR) ............................................................................................. 18-9 18.6.7. Line control register (URTxLCR) ............................................................................................ 18-10 18.6.8. Modem control register (URTxMCR) ...................................................................................... 18-11 18.6.9. Line status register (URTxLSR) ............................................................................................... 18-12 18.6.10. Modem status register (URTxMSR) ......................................................................................... 18-13 18.6.11. Divider latch register (URTxDLL&URTxDLM) ..................................................................... 18-14

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18.7. UART operation ............................................................................................................................... 18-16 18.7.1. Example of initial setting ......................................................................................................... 18-16 18.7.2. Example of transfer procedure ................................................................................................. 18-17 18.7.3. Example of reception procedure ............................................................................................... 18-18 18.7.4. Basic transmission operation .................................................................................................... 18-19 18.7.5. Basic reception operation ......................................................................................................... 18-20 18.7.6. Line status ................................................................................................................................ 18-21 18.7.7. Character time-out interrupt ..................................................................................................... 18-25

19. I2C bus interface ............................................................................................ 19-1


19.6.1. Register list ................................................................................................................................ 19-5 19.6.2. Bus status register (I2CxBSR) ................................................................................................... 19-7 19.6.3. Bus control register (I2CxBCR) ................................................................................................. 19-9 19.6.4. Clock control register (I2CxCCR) ........................................................................................... 19-12 19.6.5. Address register (I2CxADR) .................................................................................................... 19-15 19.6.6. Data register (I2CxDAR) ......................................................................................................... 19-16 19.6.7. Two bus control registers (I2CxBC2R) .................................................................................... 19-17 19.6.8. Expansion CS register (I2CxECSR) ......................................................................................... 19-18 19.6.9. Bus clock frequency register (I2CxBCFR) .............................................................................. 19-20

19.7. Operation .......................................................................................................................................... 19-21 19.7.1. Start condition .......................................................................................................................... 19-21 19.7.2. Stop condition .......................................................................................................................... 19-22 19.7.3. Addressing ............................................................................................................................... 19-23 19.7.4. Synchronous arbitration of SCL ............................................................................................... 19-24 19.7.5. Arbitration ................................................................................................................................ 19-25 19.7.6. Acknowledge/Negative acknowledge ...................................................................................... 19-26 19.7.7. Bus error ................................................................................................................................... 19-27 19.7.8. Initialization ............................................................................................................................. 19-28 19.7.9. One byte transfer from master to slave..................................................................................... 19-29 19.7.10. One byte transfer from slave to master..................................................................................... 19-30 19.7.11. Recover from bus error ............................................................................................................ 19-31 19.7.12. Interrupt process and wait request operation to master device ................................................. 19-32

19.8. Notice ............................................................................................................................................... 19-32

20. Serial peripheral interface (SPI) ................................................................... 20-1

20.1. Outline ................................................................................................................................................ 20-1 20.2. Feature ................................................................................................................................................ 20-1 20.3. Block diagram .................................................................................................................................... 20-2 20.4. Supply clock ....................................................................................................................................... 20-2 20.5. Transition state ................................................................................................................................... 20-3 20.6. Register .............................................................................................................................................. 20-4

20.6.1. Register list ................................................................................................................................ 20-4 20.6.2. SPI control register (SPIxCR) .................................................................................................... 20-6 20.6.3. SPI slave control register (SPIxSCR) ......................................................................................... 20-8

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20.6.4. SPI data register (SPIxDR) ...................................................................................................... 20-11 20.6.5. SPI status register (SPIxSR) ..................................................................................................... 20-12

20.7. Setup procedure flow ....................................................................................................................... 20-13

21. CAN interface (CAN) ...................................................................................... 21-1

21.1. Outline ................................................................................................................................................ 21-1 21.2. Related pin ......................................................................................................................................... 21-1 21.3. Supply clock ....................................................................................................................................... 21-1 21.4. Register .............................................................................................................................................. 21-1

22. Serial audio interface (I2S) ............................................................................ 22-1


22.6.1. Register list ................................................................................................................................ 22-4 22.6.2. I2SxRXFDAT register ................................................................................................................ 22-6 22.6.3. I2SxTXFDAT register ................................................................................................................ 22-7 22.6.4. I2SxCNTREG register ............................................................................................................... 22-8 22.6.5. I2SxMCR0REG register .......................................................................................................... 22-11 22.6.6. I2SxMCR1REG register .......................................................................................................... 22-12 22.6.7. I2SxMCR2REG register .......................................................................................................... 22-13 22.6.8. I2SxOPRREG register.............................................................................................................. 22-14 22.6.9. I2SxSRST register .................................................................................................................... 22-15 22.6.10. I2SxINTCNT register ............................................................................................................... 22-16 22.6.11. I2SxSTATUS register ............................................................................................................... 22-19 22.6.12. I2SxDMAACT register ............................................................................................................ 22-21

22.7. Operation .......................................................................................................................................... 22-22 22.7.1. Outline ...................................................................................................................................... 22-22 22.7.2. Transfer start, stop, and malfunction ........................................................................................ 22-23 22.7.3. Frame construction ................................................................................................................... 22-28 22.7.4. FIFO construction and description ........................................................................................... 22-32

23. NAND Flash interface .................................................................................... 23-1

23.1. Outline ................................................................................................................................................ 23-1 23.2. Spec limitation ................................................................................................................................... 23-1 23.3. Feature ................................................................................................................................................ 23-1 23.4. Related pin ......................................................................................................................................... 23-1 23.5. Supply clock ....................................................................................................................................... 23-1 23.6. Register .............................................................................................................................................. 23-2

23.6.1. Register list ................................................................................................................................ 23-2 23.6.2. Flash mode register (FMODE) ................................................................................................... 23-3 23.6.3. Flash timing register (FTIM) ...................................................................................................... 23-4 23.6.4. Flash area register (FAREA) ...................................................................................................... 23-5 23.6.5. ECC control register (ECCR) ..................................................................................................... 23-7 23.6.6. ECC0 Code Read Register (ECRR0) ....................................................................................... 23-10 23.6.7. ECC1 Code Read Register (ECRR1) ....................................................................................... 23-11

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23.6.8. ECC0 Code Write Register (ECWR0) ..................................................................................... 23-12 23.6.9. ECC1 Code Write Register (ECWR1) ..................................................................................... 23-12 23.6.10. ECC0 Error Position Register (ECCPOS0) .............................................................................. 23-13 23.6.11. ECC1 Error Position Register (ECCPOS1) .............................................................................. 23-14

23.7. Connection example ......................................................................................................................... 23-15 23.8. Example of access waveform ........................................................................................................... 23-16 23.9. Operation .......................................................................................................................................... 23-18

23.9.1. NAND Flash Access ................................................................................................................ 23-18

24. Real Time Clock Timer (RTC) ........................................................................ 24-1

24.1. Outline ................................................................................................................................................ 24-1 24.2. Feature ................................................................................................................................................ 24-1 24.3. Related pin ......................................................................................................................................... 24-1 24.4. Supply clock ....................................................................................................................................... 24-1 24.5. Register .............................................................................................................................................. 24-2

24.5.1. Register list ................................................................................................................................ 24-2 24.5.2. Power off status register (RTCROSR) ....................................................................................... 24-4 24.5.3. Second interval register (RTCPRSR) ......................................................................................... 24-4 24.5.4. Time register (RTCTIME) .......................................................................................................... 24-5 24.5.5. Date register (RTCDATE) .......................................................................................................... 24-6 24.5.6. Bus isolation control register (RTCRPON) ................................................................................ 24-7 24.5.7. Load control register (RTCLOAD) ............................................................................................ 24-7 24.5.8. Time compare register (RTCCOMP) ......................................................................................... 24-8 24.5.9. Interrupt control/status register (RTCINTR) .............................................................................. 24-8

24.6. Note on application .......................................................................................................................... 24-10

25. Input Capture Timer (INCP) ........................................................................... 25-1

25.1. Outline ................................................................................................................................................ 25-1 25.2. Feature ................................................................................................................................................ 25-1 25.3. Related pin ......................................................................................................................................... 25-1 25.4. Supply clock ....................................................................................................................................... 25-1 25.5. Register .............................................................................................................................................. 25-2

25.5.1. Register list ................................................................................................................................ 25-2 25.5.2. Input Capture data register (IPCPx) ........................................................................................... 25-4 25.5.3. Input capture control status register (IPCS) ............................................................................... 25-5 25.5.4. Timer compare register (IPCPCLR) ........................................................................................... 25-6 25.5.5. Timer data register (IPTDAT) .................................................................................................... 25-7 25.5.6. Timer control status register (IPTCSR) ...................................................................................... 25-8

26. USB Host controller ....................................................................................... 26-1

26.1. Outline ................................................................................................................................................ 26-1 26.2. Specification limitation ...................................................................................................................... 26-1 26.3. Feature ................................................................................................................................................ 26-2 26.4. Block diagram .................................................................................................................................... 26-3 26.5. Supply clock ....................................................................................................................................... 26-4 26.6. Register .............................................................................................................................................. 26-4

26.6.1. Register list ................................................................................................................................ 26-4 26.6.2. Capability Register (HCCAPBASE) .......................................................................................... 26-6 26.6.3. Structural Parameter Register (HCSPARAMS) ......................................................................... 26-7

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26.6.4. Capability Parameter Register (HCCPARAMS) ........................................................................ 26-8 26.6.5. USB Command Register (USBCMD) ........................................................................................ 26-9 26.6.6. USB Status Register (USBSTS) ............................................................................................... 26-11 26.6.7. USB Interrupt Enable Register (USBINTR) ............................................................................ 26-12 26.6.8. USB Frame Index Register (FRINDEX) .................................................................................. 26-13 26.6.9. 4G Segment Selector Register (CTRLDSSEGMENT) ............................................................ 26-13 26.6.10. Periodic Frame List Base Address Register (PERIODICLISTBASE) ..................................... 26-14 26.6.11. Asynchronous List Address Register (ASYNCLISTADDR) ................................................... 26-14 26.6.12. Configured Flag Register (CONFIGFLAG) ............................................................................ 26-15 26.6.13. Port Status/Control Register 1 (PORTSC_1) ............................................................................ 26-16 26.6.14. Programmable Microframe Base Value Register (INSNREG00) ............................................. 26-18 26.6.15. Programmable Packet Buffer OUT/IN Threshold Register (INSNREG01) ............................. 26-18 26.6.16. Programmable Packet Buffer Depth Register (INSNREG02) .................................................. 26-19 26.6.17. Time Available Offset Register (INSNREG03) ........................................................................ 26-19 26.6.18. Debug Register (INSNREG04) ................................................................................................ 26-20 26.6.19. UTMI Control Status Register (INSNREG05) ......................................................................... 26-20 26.6.20. Revision Register (HcRevision) ............................................................................................... 26-21 26.6.21. Control Register (HcControl) ................................................................................................... 26-22 26.6.22. Command/Status Register (HcCommandStatus) ...................................................................... 26-23 26.6.23. Interrupt Status Register (HcInterruptStatus) ........................................................................... 26-24 26.6.24. Interrupt Enable Register (HcInterruptEnable) ........................................................................ 26-25 26.6.25. Interrupt Disable Register (HcInterruptDisable) ...................................................................... 26-26 26.6.26. HCCA Register (HcHCCA) ..................................................................................................... 26-27 26.6.27. Periodic Current ED Register (HcPeriodCurrentED) ............................................................... 26-27 26.6.28. Control Head ED Register (HcControlHeadED) ...................................................................... 26-28 26.6.29. Control Current ED Register (HcControlCurrentED) .............................................................. 26-28 26.6.30. Bulk Head ED Register (HcBulkHeadED) .............................................................................. 26-29 26.6.31. Bulk Current ED Register (HcBulkCurrentED) ....................................................................... 26-29 26.6.32. Done Head Register (HcDoneHead) ........................................................................................ 26-30 26.6.33. Frame Interval Register (HcFmInterval) .................................................................................. 26-30 26.6.34. Frame Remaining Register (HcFmRemaining) ........................................................................ 26-31 26.6.35. Frame Number Register (HcFmNumber) ................................................................................. 26-31 26.6.36. Periodic Start Register (HcPeriodicStart) ................................................................................. 26-32 26.6.37. LS Threshold Register (HcLSThreshold) ................................................................................. 26-32 26.6.38. Root Hub Descriptor A Register (HcRhDescriptorA) .............................................................. 26-33 26.6.39. Root Hub Descriptor B Register (HcRhDescriptorB) .............................................................. 26-34 26.6.40. Root Hub Status Register (HcRhStatus) ................................................................................... 26-35 26.6.41. Root Hub Port Status/Control Register 1 (HcRhPortStatus[1]) ................................................ 26-36 26.6.42. Link Mode Setting Register (LinkModeSetting) ...................................................................... 26-37 26.6.43. PHY Mode Setting 1 Register (PHYModeSetting1) ................................................................ 26-38 26.6.44. PHY Mode Setting 2 Register (PHYModeSetting2) ................................................................ 26-38

27. SD memory controller (SDMC) ..................................................................... 27-1

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xx



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1. Overview This chapter describes feature, block diagram, and function of MB9G711.

1.1. Feature This LSI product is designed for car audio application using ARM Limited's CPU core ARM946ES. Varieties of on-chip peripherals make single chip solution of car audio application possible. MB9G711 has following features:

• CMOS 90nm technology • Package: FPT-144 • Power-supply voltage: (IO: 3.3 ± 0.3V, core: 1.2 ± 0.1V, RTC : 1.2 ± 0.1V) • Maximum operation frequency: 164MHz (CPU), 82MHz (AHB), 41MHz (APB) • CPU core

• ARM946ES • 16KB instruction cache/16KB data cache • 16KB ITCM/16KB DTCM • JTAG ICE interface

• Bus architecture • Multi-layer AHB bus architecture

• External Interrupt x 12ch • Total 288KB Built-in SRAM • Clock/Reset control function • Remap/Boot control function • USB 2.0 Host (HS/FS protocols) • Direct memory access controller (DMAC) having total 8 access channels • 32/16 bit re-load timer × 4ch • 10 bit A/D converter (0.294MS/s) with 6 analog input channels • 16-bit Audio D/A converter with 8 x 32bit output FIFO buffer

Option I/O (with pin multiplex) • 8/16 bit NandFlash Interface with 1-bit/256 Byte ECC unit • SD memory card controller (Support SDIO mode) • I2C (N-ch I/O) × 2ch • UART x 5ch • SIO x 5ch • CAN I/F (I/O voltage: 3.3V) × 1ch • SPI × 2ch • PWM × 4ch (2 PWM output and 2 for internal macro) • I2S x 2ch • GPIO x 69ch (max)

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1.2. Block diagram Figure 1-1 shows block diagram of MB9G711.

Figure 1-1 Block diagram of MB9G711

CPU core CPU core block of ARM946ES is connected to each I/O through AHB bus in this LSI. Instruction (I)/Data (D) share with single AHB bus master.


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AHB1 bus Following resources are connected.

• CPU core: ARM946ES CPU core It operates as bus masters at program control

• DMAC: General purpose DMA × 8ch It operates as bus master at data transfer

• USB 2.0 Host: It operates as USB 2.0 EHCI, USB 1.1 OHCI bus masters It operates as bus master at data transfer

• NandFlash I/F (connected ECC control) • SRAM0 :Internal SRAM 128KB • SRAM1/2: Internal SRAM 80KB • I2S0/1: Serial audio controller • AHB2 bus • APBBRG0/1/2: AHB-APB bridge circuit

AHB2 bus • USB 2.0 Host: USB 2.0 Host controller's register part • SDMC: SD memory controller

APB_TOP0 This block bridges between APBBRG0 bus and the AHB1 bus, and following low-speed peripheral resources are connected.

• IRC0/1 : Interrupt vector controller x 2 (able to handle up to 64 interrupt sources) • EXIRC0/1/2 : External interrupt controller x 3 (total 12 external interrupt inputs as interrupt source) • CRG : Clock and reset generator • UART0/1: UART controller × 2 • SIO0/1 : SIO controller x 2 • RBC : Remap boot controller • Timers0/1 : 32 bit general-purpose re-load timer module × 2 (2 timer channel per modoule) • GPIO0 : GPIO control (GPIO23 ~ GPIO00)

APB_TOP1 This block bridges between APBBRG1 bus and AHB1 bus, and following low-speed peripheral resources are connected.

• I2C0/1 : I2C controller × 2 • CCAN : C-CAN controller • UART2/3: UART controller × 2 • SIO2/3 : SIO controller x 2ch • ADC : A/D converter x 1 • DAC : Audio D/A converter • RTC : Real Time Clock • GPIO1 : GPIO control (GPIO47 ~ GPIO24 )

APB_TOP_2 This block bridges between APBBRG2 bus and AHB1 bus, and following low-speed peripheral resources are connected.

• PWM : PWM controller • SPI0/1 : SPI controller x 2 ch • CCNT : Chip control unit • UART4 : UART × 1ch • SIO4 : SIO x 1 ch • INCP : Input Capture Timer (2 input capture channels)


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Overview

1.3. Function list Function list of MB9G711 is shown below.

Table 1-1 MB9G711 function list Function Outline

CPU core • ARM946ESTM processor core • Core operation frequency: 164MHz • 16KB instruction cache • 16KB data cache • CM) Tightly-Coupled memory for 16KB instruction (IT

KB data (DTCM) • Tightly-Coupled memory for 16 • JTAG ICE debugging interface

Bus architecture • Multilayer AHB bus architecture Interrupt

h + built-in internal interrupt × 56ch) nel

• High-speed interrupt × 1ch (software interrupt) • Normal interrupt × 64ch (external interrupt × 12c• Up to 16 interrupt levels are settable by chan

Clock

) odule is stoppable)

• Input clock division: selectable from 8 ~ 16 • PLL multiplication: selectable from × 48 ~ 78 • Max Operation frequency: 164MHz (CPU), 82MHz (AHB), 41MHz (APB• Low power consumption mode (clock to ARM and m

Reset • Hardware reset, software reset, and watchdog reset Remap • 32KB ROM area is able to be mapping to built-in SRAM area NandFlash interface • Supported 8/16 bit width NandFlash connection with 1-bit ECC correction Built-in SRAM • Mounted total 3 pieces of general purpose SRAM (32 bit bus) on high speed AHB bus

so that maximum 3 bus masters are able to access internal memory in parallel DMAC nsfer channels

ed. Of which 13 are selectable and 4 are • AHB connection with 8 DMA tra• 17 hardware transfer request signal connect

fixed in particular DMA channel ck, burst, and demand • Transfer mode: Blo

Timer • 32/16 bit programmable re-load timer× 4 channels GPIO • Max. 69 is usable PWM • Built-in 4 channels

• Duty ratio and phase are configurable A/D converter A/D converter • 10 bit successive approximation type

• Sampling rate: 0.294MS/s (max. sampling rate) • Nonlinearity error: ± 2.0LSB (max.)

Audio D/A converter • 16-bit audio data • Dedicated PLL for Audio DAC sampling clock generation

ata • 8 x 32bit FIFO buffer for DAC output dI2S h (L/R)

d) and serial PCM data transfer interface ations are selectable

a clock generation

• Audio output × 2ch (L/R) /Audio input × 2c• Supported three-wire serial (I2S, MSB-Justifie• Master/Slave oper• Resolution capability: Max. 32 bit/sample • Dedicated PLL for I2S dat

UART

DMA transfer

• Max. 5 channels • 8 bit pre-scaler for baud rate clock generation • Supported

SIO • Max 5 channels Supported transfer operation: 8-bit, LSB first or MSB first, simultaneous se• nding and receiving

I2C

• 2 independent channels with true Nch I/O • Supported standard mode (max. 100kbps)/high-speed mode (max. 400kbps)

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Function Outline SPI • Max Transfer clock frequency 20.5MHz (APB bus clock / 2)

bit unit (max. 32 bit) (programmable setting) • Full duplex/Synchronous transmission • Transfer data length: 1

CAN • Mounted BOSCH C_CAN module × 1ch and B • Conformed to CAN protocol version 2.0 part A

• I/O voltage: 3.3V USB • USB 2.0 compliant Host controller

• HS/FS protocol support (supported VBus and isochronous transfer)

SD memorycontroller

Memory Card Specifications Part 1 Physical O Card Specifications Part E1 Secure Digital

ion version 2.0 is possible

PI mode, and CPRM

card • Interface with SD cards based on the SDLayer Specification version 2.0 and SDIInput/Output (SDIO) Card Specificat

• SDHC is supported • Equipped 1 channel • Support MMC, 1-bit and 4-bit SD mode • Unsupported S

CCNT rol

• Port resources multiplex control • Software reset cont

JTAG • Conformed to IEIEEE1149.1 (IEEE Standard Test Access Port and Boundary-Scan Architecture)

• Supported JTAG ICE connection • 12MHz JTAG I/F

INCP ction circuit for each triggering input

• 2 triggering inputs for capturing timer value • Equipped 16-bit free run timer and edge dete• Timer count clock: divided APB bus clock or PWM channel 3 output

RTC from the remaining of ssible

• Containing leap-year circuit for automatic leap-year adjustment • Alarm interrupt generation for pre-set time • 18-

• independent power pin (RVDD) which is isolated LSI circuit. Power cut off to the main supply except RVDD is poPowered by

bit internal prescaler circuit for 1 sec. timing by which wide range of RTC crystal can be used

• 16-bit internal register for checking RVDD power down or not

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1.4. Package dimension Package dimension of MB9G711 is shown below.

Figure 1-2 FPT-144P-M12/M08 package dimension


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Overview

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1.5. Pin assignment Pin assignment of MB9G711 is shown below.

JTC

KJT

DO

JTD

IJT

MS

JXTR

STJX

SRS

TJR

TCK

VDD

IVS

SVD

DE

GPI

O48

/ U

AR

T4U

O /

SIO

4SO

/ SP

I1C

K / N

FD15

GPI

O49

/ U

AR

T4U

I / S

IO4S

I / S

PI1D

O /

NFD

14G

PIO

50 /

SIO

4SC

K / S

PI1D

I / N

FD13

GPI

O51

/ S

PI1C

X / N

FD12

GPI

O52

/ U

AR

T3U

O /

SIO

3SO

/ N

FD11

GPI

O53

/ U

AR

T3U

I / S

IO3S

I / N

FD10

GPI

O54

/ S

IO3S

CK

/ NFD

09G

PIO

55 /

PTR

G /

NFD

08G

PIO

56 /

NFD

07G

PIO

57 /

NFD

06G

PIO

58 /

NFD

05G

PIO

59 /

NFD

04G

PIO

60 /

NFD

03G

PIO

61 /

NFD

02G

PIO

62 /

NFD

01G

PIO

63 /

NFD

00VS

SVD

DE

GPI

O64

/ S

PI0C

K / N

FRE

XG

PIO

65 /

SPI

0DO

/ N

FWEX

GPI

O66

/ S

PI0D

I / N

FCLE

GPI

O67

/ S

PI0C

X / N

FALE

GPI

O68

/ N

FCE

XG

PIO

47 /

NFR

DY

VSS

VDD

I

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

VSS 1 108 VSSVDDI 2 107 VDDE

UAVDF2 3 106 GPIO46 / INT11UAVSF2 4 105 GPIO45 / INT10

UAVSF1_2 5 104 GPIO44 / INT09UAVSF1_3 6 103 GPIO43 / INT08

USBHDM 7 102 GPIO42 / INT07USBHDP 8 101 GPIO41 / INT06UAVDF1 9 100 GPIO40 / INT05

UAVSF1_4 10 99 GPIO39 / INT04UAVSB 11 98 GPIO38 / INT03

UEXT12 12 97 GPIO37 / INT02UAVDB 13 96 GPIO36 / INT01UAVDP 14 95 GPIO35 / INT00UAVSP 15 94 VDDIUCK48 16 93 VSS

VSS 17 92 AULOVDDI 18 91 AULCP

UPRWR 19 90 AUVDLGPIO00 / SDDAT0 20 89 AUVSSGPIO01 / SDDAT1 21 88 AUVDDGPIO02 / SDDAT2 22 87 AURCPGPIO03 / SDDAT3 23 86 AUROGPIO04 / SDCMD 24 85 VSS

GPIO05 / SDXMCD 25 84 VDDIGPIO06 / SDWP 26 83 GPIO34 / SIO2SCK

VSS 27 82 GPIO33 / UART2UI / SIO2SIVDDE 28 81 GPIO32 / UART2UO / SIO2SO

GPIO07 / SDCLK 29 80 GPIO13 / I2S1ECK / CANTXGPIO15 / PWM1 30 79 GPIO12 / I2S0ECK / CANRX

GPIO08 / I2C0SL 31 78 GPIO19 / I2S0WSGPIO09 / I2C0SA 32 77 GPIO18 / I2S0DIGPIO10 / I2C1SL 33 76 GPIO17 / I2S0DOGPIO11 / I2C1SA 34 75 GPIO16 / I2S0CK

VSS 35 74 VDDEVDDI 36 73 VSS

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

ADVS

SAD

VDD

ADIN

0AD

IN1

ADIN

2AD

IN3

ADIN

4AD

IN5

PLLV

DD

IPL

LVSS

VSS

VDD

IG

PIO

24 /

UAR

T0U

O /

SIO

0SO

GP

IO25

/ U

ART0

UI /

SIO

0SI

GP

IO26

/ S

IO0S

CK

GP

IO27

/ U

ART1

UO

/ S

IO1S

OG

PIO

28 /

UAR

T1U

I / S

IO1S

IG

PIO

29 /

SIO

1SC

KG

PIO

30 /

IN0

GPI

O31

/ IN

1G

PIO

14 /

PW

M0

GP

IO23

/ I2

S1W

SG

PIO

22 /

I2S1

DI

GP

IO21

/ I2

S1D

OG

PIO

20 /

I2S1

CK

VDD

EVS

SVD

DI

MD

2M

D1

MD

0R

STX

RVD

DI

RXI

RVS

SR

XO

Top View (FPT-144P-M12)(FPT-144P-M08)

•

: Analog ground

: Independent 1.2V power I/O

: 3.3V for IO power

: Digital ground

: 3.3V analog power

: 1.2V analog power : 1.2V core power

Figure 1-3 MB9G711 pin assignment


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1.6. Pin function External pin function of MB9G711 is described below.

1.6.1. Pin Multiplex Some pins of this LSI have multiple functions. The function is determined by the setting of port function select register “CPSEL” Following is the pin multiplex table

Table 1-2 Multiplexed Pin function

Pin No.

After Reset

Pin state after Reset

Pin Function Register Setting

Pin Function

Register Setting

Pin Function

Register Setting

Pin Function

Register Setting

Others *1

16 UCK48 Input

19 UPRWR "L"

20 GPIO00 Input SDDAT0 CPSEL[30] = 1

21 GPIO01 Input SDDAT1 CPSEL[31:30] = 11



24 GPIO04 Input SDCMD CPSEL[30] = 1

25 GPIO05 Input SDXMCD CPSEL[30] = 1

26 GPIO06 Input SDWP CPSEL[30] = 1

29 GPIO07 Input SDCLK CPSEL[30] = 1

31 GPIO08 Input I2C0SL CPSEL[16] = 1

32 GPIO09 Input I2C0SA CPSEL[16] = 1

33 GPIO10 Input I2C1SL CPSEL[17] = 1

34 GPIO11 Input I2C1SA CPSEL[17] = 1

79 GPIO12 Input CANRX CPSEL[7] = 1 I2S0ECK

80 GPIO13 Input CANTX CPSEL[7] = 1 I2S1ECK

57 GPIO14 Input PWM0 CPSEL[28] = 1

30 GPIO15 Input PWM1 CPSEL[29] = 1

75 GPIO16 Input I2S0CK CPSEL[23] = 1

76 GPIO17 Input I2S0DO CPSEL[23] = 1

77 GPIO18 Input I2S0DI CPSEL[23] = 1

78 GPIO19 Input I2S0WS CPSEL[23] = 1

61 GPIO20 Input I2S1CK CPSEL[24] = 1

60 GPIO21 Input I2S1DO CPSEL[24] = 1

59 GPIO22 Input I2S1DI CPSEL[24] = 1

58 GPIO23 Input I2S1WS CPSEL[24] = 1

49 GPIO24 Input SIO0SO CPSEL[0] = 1 UART0UO CPSEL[16] = 1

50 GPIO25 Input SIO0SI CPSEL[0] = 1 UART0UI CPSEL[16] = 1

51 GPIO26 Input SIO0SCK CPSEL[0] = 1




55 GPIO30 Input IN0

56 GPIO31 Input IN1




95 GPIO35 Input INT00












111 GPIO47 Input NFRDY CPSEL[10] = 1

134 GPIO48 Input NFD15 CPSEL[9:8] = 11 SPI1CK CPSEL[6] = 1 SIO4SO CPSEL[4] = 1 UART4UO CPSEL[20] = 1

133 GPIO49 Input NFD14 CPSEL[9:8] = 11 SPI1DO CPSEL[6] = 1 SIO4SI CPSEL[4] = 1 UART4UI CPSEL[20] = 1

132 GPIO50 Input NFD13 CPSEL[9:8] = 11 SPI1DI CPSEL[6] = 1 SIO4SCK CPSEL[4] = 1

131 GPIO51 Input NFD12 CPSEL[9:8] = 11 SPI1CX CPSEL[6] = 1

130 GPIO52 Input NFD11 CPSEL[9:8] = 11 SIO3SO CPSEL[3] = 1 UART3UO CPSEL[19] = 1

129 GPIO53 Input NFD10 CPSEL[9:8] = 11 SIO3SI CPSEL[3] = 1 UART3UI CPSEL[19] = 1

128 GPIO54 Input NFD09 CPSEL[9:8] = 11 SIO3SCK CPSEL[3] = 1

127 GPIO55 Input NFD08 CPSEL[9:8] = 11 PTRG

126 GPIO56 Input NFD07 CPSEL[9:8] = 11

125 GPIO57 Input NFD06 CPSEL[8] = 1







116 GPIO64 Input NFREX CPSEL[8] = 1 SPI0CK CPSEL[5] = 1

113 GPIO65 Input NFWEX CPSEL[8] = 1 SPI0DO CPSEL[5] = 1

114 GPIO66 Input NFCLE CPSEL[8] = 1 SPI0DI CPSEL[5] = 1

115 GPIO67 Input NFALE CPSEL[8] = 1 SPI0CX CPSEL[5] = 1

112 GPIO68 Input NFCEX CPSEL[11] = 1

144 JTCK Pull-up

141 JTMS Pull-up

140 JXTRST Pull-up

142 JTDI Pull-up

143 JTDO Hi-z

138 JRTCK "H"

139 JXSRST Pull-up

*1 Resource input function should be disabled when corresponding pin is used by other resource

Resource Mux Priority

1st 2nd 3rd 4th


Overview

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1.6.2. Pin function description

Format Pin function list is shown in the following format.

Pin name I/O Polarity Analog /Digital Type Description

Meaning of item and sign Pin name

Name of external pin. I/O

Input/Output signal's distinction based on this LSI. • I: Pin that can be used as input • O: Pin that can be used as output • IO: Pin that can be used as input and output (interactive pin)

Polarity Active polarity of external pin's input/output signals

• P: "H" active pin (positive logic) • N: "L" active pin (negative logic) • PN: "H" and "L" active pins

Analog/Digital Signal type of external pin

• A: Analog signal • D: Digital signal

Type Input/Output circuit type of external pin.

• CLK • OD: Open Drain • PU: Pull Up • PD: Pull Down • ST: Schmitt Type • Tri: Tri-state • LVCMOS: 1.2V CMOS • LVXTAL: 1.2V Xtal

Description Outline of external pin function


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1.6.3. NandFlash interface related pin Table 1-3 External bus interface related pin's function

Pin name I/O Polarity Analog/Digital Type Description

NFCEX O N D - Chip enable NFCLE O P D - Command latch enable NFALE O P D - Address latch enable NFWEX O N D - Write enable NFREX O N D - Read enable NFRDY I P D - Ready input NFD[15:0] IO - D - Bi-directional data bus

1.6.4. SD memory controller related pin Table 1-4 SD memory controller related pin's function


SDCLK O - D - Media clock SDCMD IO - D - Media command SDDAT[3:0] IO - D - Media data SDWP I P D - Media write protection SDXMCD I N D - Media card detection

1.6.5. USB 2.0 Host related pin Table 1-5 USB 2.0 Host/Function related pin's function


USBHDP IO - A - D+ for HS/FS USBHDM IO - A - D- for HS/FS UCK48 I - D CLK Clock used for USB communication UPRWR O - D - USB port power control UEXT12K O - A - External resistance pin

This should be connected to UAVSB through 12kΩ resistance.

UAVSP I - A - Analog ground for internal PLL UAVDP I - A - 1.2V analog power for internal UAVSB I - A - Analog ground for internal power current UAVDB I - A - 3.3V analog power for internal power current UAVSF1-2 UAVSF1-3 UAVSF1-4

I - A - Analog ground for internal transceiver

UAVDF1 I - A - 3.3V analog power for internal transceiver UAVSF2 I - A - Analog ground for internal transceiver UAVDF2 I - A - 1.2V analog power for internal transceiver


Overview

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1.6.6. External interrupt controller related pin Table 1-6 External interrupt controller related pin's function


INT[11:0] I PN D - Asynchronous external interrupt requests

1.6.7. UART related pin Table 1-7 UART related pin's function

Pin name I/O Polarity Analog/Digital Type Explanation

UART0UI I P D - Input data signal UART0UO O P D - Output data signal UART1UI I P D - Input data signal UART1UO O P D - Output data signal UART2UI I P D - Input data signal UART2UO O P D - Output data signal UART2UI I P D - Input data signal UART2UO O P D - Output data signal UART3UI I P D - Input data signal UART3UO O P D - Output data signal UART4UI I P D - Input data signal UART4UO O P D - Output data signal

1.6.8. SIO related pin Table 1-8 SIO related pin's function


SIO0SI I P D - Input data signal SIO0SO O P D - Output data signal SIO0SCK IO - D Clock Clock signal SIO1SI I P D - Input data signal SIO1SO O P D - Output data signal SIO1SCK IO - D Clock Clock signal SIO2SI I P D - Input data signal SIO2SO O P D - Output data signal SIO2SCK IO - D Clock Clock signal SIO3SI I P D - Input data signal SIO3SO O P D - Output data signal SIO3SCK IO - D Clock Clock signal SIO4SI I P D - Input data signal SIO4SO O P D - Output data signal SIO4SCK IO - D Clock Clock signal


Overview

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1.6.9. CAN related pin Table 1-9 CAN related pin's function


CANTX O - D - Transmission CANRX I - D - Reception

1.6.10. I2S related pin Table 1-10 I2S related pin's function


I2S0ECK I - D - External clock I2S0CK IO - D - Clock I2S0WS IO PN D - Sync I2S0DI I P D - Input data signal I2S0DO O P D - Output data signal I2S1ECK I - D - External clock I2S1CK IO - D - Clock I2S1WS IO PN D - Sync I2S1DI I P D - Input data signal I2S1DO O P D - Output data signal

1.6.11. I2C related pin Table 1-11 I2C related pin's function


I2C0SL IO - D OD I2C clock I2C0SA IO - D OD I2C data I2C1SL IO - D OD I2C clock I2C1SA IO - D OD I2C data

1.6.12. SPI related pin Table 1-12 SPI related pin's function


SPI0DO O P D - Serial data output SPI0DI I P D - Serial data input SPI0CK O - D - Serial clock SPI0CX O PN D - Slave select SPI1DO O P D - Serial data output SPI1DI I P D - Serial data input SPI1CK O - D - Serial clock SPI1CX O PN D - Slave select


Overview

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1.6.13. PWM related pin Table 1-13 PWMrelated pin's function


PWM0 O - D - PWM out 0 PWM1 O - D - PWM out 1 PTRG I P D - PWM start trigger

1.6.14. Input Capture Timer related pin Table 1-14 GPIO related pin's function


IN0 I - D - Input Capture Timer input 0 IN1 I - D - Input Capture Timer input 1

1.6.15. GPIO related pin Table 1-15 GPIO related pin's function


GPIO[68:0] IO - D - General purpose I/O port

1.6.16. A/D converter related pin Table 1-16 A/D converter related pin's function


ADIN[5:0] I - A - A/D analog input ADVDD I - A - Analog power supply ADVSS I - A - Analog ground

1.6.17. Audio D/A converter related pin Table 1-17 A/D converter related pin's function


AULO O - A - Analog output for left channel AULCP O - A - Common voltage for left channel AURO O - A - Analog output for right channel AURCP O - A - Common voltage for right channel AUVDD I - A - Analog power supply 1 AUVDL I - A - Analog power supply 2 AUVSS I - A - Analog ground


Overview

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1.6.18. System related pin Table 1-18 System related pin's function


MD[2:0] I PN D ST Mode setting RSTX I N D LVCMOS System reset RXI I - D LVXTAL 32K Oscillator in RXO I - D LVXTAL 32K oscillator output


Overview

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1.6.19. JTAG / ICE related pin Table 1-19 JTAG related pin's function


JTCK I - D PU Test clock JXTRST I N D ST, PU Test reset JTMS I N D PU Test mode JTDI I - D PU Test data input JTDO O - D Tri Test data output JRTCK O - D - Return test clock JXSRST IO N D ST, PU System reset

1.6.20. Power supply related pin Table 1-20 Power supply related pin's function


VSS I - D - Ground VDDE I - D - 3.3V IO power supply VDDI I - D - 1.2V internal power supply PLLVDDI I - D - 1.2V internal power supply for PLL PLLVSS I - D - Ground for PLL power RVDDI I - D - 1.2V power supply for RTC RVSS I - D - Ground pin for RVDD


Overview

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1-17



Overview

1.7. Device handling 1. Preventing Latch-up

In a CMOS IC, latch-up may occur if a voltage higher than VDDE or lower than VSS is applied to the input or output pins, or supply voltage exceeded the absolute rating. Latch-up incurs excessive current drawn from power supply and results thermal damage to devices. Therefore, input and output pins should be used within maximum ratings

2. Pin Handling Unused pins :

Leaving unused input pins open may cause leakage and probably device malfunction. Therefore, unused input pins should be connected to either pull-up or pull-down resistor

Output pins : Short-circuit output pins with power supply pins or other output pins or connecting to a heavy load may cause excessive current flow. If such condition condition continues for a long time, the device will be damaged

Mode pins (MD2 ~ MD0) : Noise in Mode pins will cause device malfunction. These pins should be connected directly to VDDE or VSS with shortest wiring length and at low impedance

3. Sequence of Power on/off Following power on/off sequence is recommended :

At power on : VDDI (internal power) / RVDDI (RTC power) / PLLVDDI (PLL power) → VDDE (external I/O power) / Analog power → signal power

At power off : Signal power → VDDE (external I/O power) / Analog power → VDDI (internal power) / RVDDI (RTC power) / PLLVDDI (PLL power)

A dedicated power input (RVDDI) is used for internal Real Time Clock (RTC) module. Precautions for handling VDDE, VDDI and RSTX are required when power up/down. Details can refer to “Note on system power up / down” section

4. Power on Reset RSTX pin must be Low when power-on. It should keep in Low for at least 2μs (RTC is not used) to make sure all power source becomes stable before reset release. When using RTC, RSTX pin must be keep in Low for at least 65μs.

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2-1


2. System configuration Figure 2-1 shows system configuration for which this LSI is used to in-vehicle car audio.

Figure 2-1 Sample of system configuration

2.1. Operating Modes Three kinds of startup operation can be selected in this LSI. External pin MD[2:0] determines startup operation after deactivation of reset signal RSTX.

Table 1 Operating mode table MD[2:0] Operating Mode Function

000 Flash writer mode Write program to external Flash device 001 8-bit NandFlash boot mode Load program from external device by 8-bit

NandFlash interface 010 SPI Flash boot mode Load program from external device by SPI

interface (SPI0 is used) 011 Reserved Reserved 1xx Setting prohibited Reserved

2.2. Note on system power up / down This LSI has a dedicated power input (RVDD) for internal Real Time Clock (RTC) module. The main power of this LSI, (VDDE and VDDI), can be cut off for power saving while RVDD is still alive for RTC module running.

The reset input RSTX must keep “L” when main power VDDE/VDDI is cut off. Otherwise large current leakage will happen to RVDD power supply.

During power up, RSTX should not deactivated (go to “H”) until main power VDDE/VDDI stable. Before cut off external power (VDDE/VDDI), a register bit in RTC module must be written “0”.

Refer to RTC section for the details.

System Configuration FUJITSU SEMICONDUCTOR PROPRIETARY AND CONFIDENTIAL

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3-1



Memory map

3. Memory map This chapter shows memory map and register map of MB9G711.

3.1. Memory map of LSI

FFFF_FFFFH FFFF_FFFFH FFFF_FFFFH

IRC0/1 Mirror IRC0/1 Mirror IRC0/1 MirrorFFFF_FE00H FFFF_FE00H FFFF_FE00H

reserved reserved reservedFFFF_7FFFH FFFF_7FFFH FFFF_7FFFH

FFFF_0000H FFFF_0000H FFFF_0000H

FFFE_FFFFH FFFE_FFFFH FFFE_FFFFH

APB0 Resources APB0 Resources APB0 ResourcesFFFE_0000H FFFE_0000H FFFE_0000H

FFFD_FFFFH FFFD_FFFFH FFFD_FFFFH

HDMA HDMA HDMAFFFD_0000H FFFD_0000H FFFD_0000H

FFFC_FFFFH FFFC_FFFFH FFFC_FFFFH

MEMC MEMC MEMCFFFC_0000H FFFC_0000H FFFC_0000H

reserved reserved reservedFFF8_FFFFH FFF8_FFFFH FFF8_FFFFH

AHB2 Resources AHB2 Resources AHB2 ResourcesFFF6_0000H FFF6_0000H FFF6_0000H

FFF5_FFFFH FFF5_FFFFH FFF5_FFFFH

APB1 Resources APB1 Resources APB1 ResourcesFFF5_0000H FFF5_0000H FFF5_0000H


APB2 Resources APB2 Resources APB2 ResourcesFFF4_0000H FFF4_0000H FFF4_0000H


AHB2 Resources AHB2 Resources AHB2 ResourcesFFF0_0000H FFF0_0000H FFF0_0000H

FFEF_FFFFH FFEF_FFFFH FFEF_FFFFH

I2S1 I2S1 I2S1FFEF_0000H FFEF_0000H FFEF_0000H

FFEE_FFFFH FFEE_FFFFH FFEE_FFFFH

I2S0 I2S0 I2S0FFEE_0000H FFEE_0000H FFEE_0000H

reserved reserved reserved3001_FFFFH 3001_FFFFH 3001_FFFFH

reserved reserved reserved3000_0000H 3000_0000H 3000_0000H

reserved reserved reserved11FF_FFFFH 11FF_FFFFH 11FF_FFFFH

External Area External Area External Area(CSX0)

0200_0000H 0200_0000H 0200_0000H

reserved reserved reserved0104_8BFFH 0104_8BFFH 0104_8BFFH

0104_8000H 0104_8000H 0104_8000H

0104_7FFFH 0104_7FFFH 0104_7FFFH

80KB SRAM 2 80KB SRAM 2 80KB SRAM 20103_4000H 0103_4000H 0103_4000H

0103_3FFFH 0103_3FFFH 0103_3FFFH


0101_FFFFH 0101_FFFFH 0101_FFFFH


00FF_FFFFH 00FF_FFFFH 00FF_FFFFH

External Area External/128KB BROM External Area(CSX0)

0007_FFFFH

0000_8000H 0000_8000H

0000_7FFFH 0000_7FFFH 0000_3FFFH

0000_0000H 0000_0000H 0000_0000H

Internal Boot REMAP ITCM mode

16KB ITCM RAM

reserved reserved reserved

reserved

reserved 32K SRAM0 mirror reserved / SRAM0 mirror32K BROM

mirror

32K SRAM0

mirror

reserved reserved

Figure 3-1 Memory map

PRELIM

INARY

3-2



Memory map

3.2. Register access Basically, register in MB9G711 should be accessed by word length except some registers. Table 3-1 shows valid access data length of each register.

Table 3-1 Valid access data length of register Module Register name Valid data length

DMAC DMACR Byte (8 bit)

Address follows endian DMACA, DMACB, DMACSA, DMACDA Word (32 bit)/Half-word (16 bit)/Byte (8 bit)

UART RFR, TFR, DLL Word (32 bit)/Byte (8 bit) When these registers are accessed by byte long, address follows endian

GPIOx PDRx0, PDRx1, PDRx2 Word (32 bit)/Byte (8 bit). When these registers are accessed by byte long, address follows endian

SDMC All registers Half-word only CAN All registers Half-word only Others All registers other than the above Word (32 bit)

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INARY

3-3



Memory map

3.3. Register map The base address of each function module is listed in below. The details of each register can be found in the corresponding chapter

Table 3-2 MB9G711 register map Module name Address Register name Explanation

I2S_0 FFEE_0000H I2S0RXFDAT I2S_0 reception FIFO data register FFEE_0004H I2S0TXFDAT I2S_0 transmission FIFO data register FFEE_0008H I2S0CNTREG I2S_0 control register FFEE_000CH I2S0MCR0REG I2S_0 channel control register 0 FFEE_0010H I2S0MCR1REG I2S_0 channel control register 1 FFEE_0014H I2S0MCR2REG I2S_0 channel control register 2 FFEE_0018H I2S0OPRREG I2S_0 operation control register FFEE_001CH I2S0SRST I2S_0 software reset register FFEE_0020H I2S0INTCNT I2S_0 interrupt control register FFEE_0024H I2S0STATUS I2S_0 status register FFEE_0028H I2S0DMAACT I2S_0 DMA start register FFEE_002CH -

FFEE_0FFFH Reserved Access prohibited

No module FFEE_1000H - FFEE_FFFFH

Reserved Access prohibited

I2S_1 FFEF_0000H I2S1RXFDAT I2S_1 reception FIFO data register FFEF_0004H I2S1TXFDAT I2S_1 transmission FIFO data register FFEF_0008H I2S1CNTREG I2S_1 control register FFEF_000CH I2S1MCR0REG I2S_1 channel control register 0 FFEF_0010H I2S1MCR1REG I2S_1 channel control register 1 FFEF_0014H I2S1MCR2REG I2S_1 channel control register 2 FFEF_0018H I2S1OPRREG I2S_1 operation control register FFEF_001CH I2S1SRST I2S_1 software reset register FFEF_0020H I2S1INTCNT I2S_1 interrupt control register FFEF_0024H I2S1STATUS I2S_1 status register FFEF_0028H I2S1DMAACT I2S_1 DMA start register FFEF_002CH -

FFEF_0FFFH Reserved Access prohibited

No module FFEF_1000H - FFF0_FFFFH


SDMC FFF1_0000H - FFF1_0FFFH

Another specifications Another specifications

No module FFF1_1000H - FFF3_FFFFH


SPI0 FFF4_0000H SPI0CR SPI0 control register FFF4_0004H SPI0SCR SPI0 slave control register FFF4_0008H SPI0DR SPI0 data register FFF4_000CH SPI0SR SPI0 status register FFF4_0010H -

FFF4_07FFH Reserved Access prohibited

SPI1 FFF4_0800H SPI1CR SPI1 control register FFF4_0804H SPI1SCR SPI1 slave control register FFF4_0808H SPI1DR SPI1 data register FFF4_080CH SPI1SR SPI1 status register

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3-4



Memory map

Module name Address Register name Explanation FFF4_0010H -

FFF4_0FFFH Reserved Access prohibited

PWM FFF4_1000H PWM0BCR PWM ch0 base clock register FFF4_1004H PWM0TPR PWM ch0 pulse width register FFF4_1008H PWM0PR PWM ch0 phase register FFF4_100CH PWM0DR PWM ch0 duty register FFF4_1010H PWM0CR PWM ch0 status register FFF4_1014H PWM0SR PWM ch0 start register FFF4_1018H PWM0CCR PWM ch0 current count register FFF4_101CH PWM0IR PWM ch0 interrupt register FFF4_1020H -

FFF4_107FH Reserved Access prohibited

FFF4_1080H PWM1BCR PWM ch1 base clock register FFF4_1084H PWM1TPR PWM ch1 pulse width register FFF4_1088H PWM1PR PWM ch1 phase register FFF4_108CH PWM1DR PWM ch1 duty register FFF4_1090H PWM1CR PWM ch1 status register FFF4_1094H PWM1SR PWM ch1 start register FFF4_1098H PWM1CCR PWM ch1 current count register FFF4_109CH PWM1IR PWM ch1 interrupt register FFF4_10A0H -


FFF4_1100H PWM2BCR PWM ch2 base clock register FFF4_1104H PWM2TPR PWM ch2 pulse width register FFF4_1108H PWM2PR PWM ch2 phase register FFF4_110CH PWM2DR PWM ch2 duty register FFF4_1110H PWM2CR PWM ch2 status register FFF4_1114H PWM2SR PWM ch2 start register FFF4_1118H PWM2CCR PWM ch2 current count register FFF4_111CH PWM2IR PWM ch2 interrupt register FFF4_1120H -


FFF4_1180H PWM3BCR PWM ch3 base clock register FFF4_1184H PWM3TPR PWM ch3 pulse width register FFF4_1188H PWM3PR PWM ch3 phase register FFF4_118CH PWM3DR PWM ch3 duty register FFF4_1190H PWM3CR PWM ch3 status register FFF4_1194H PWM3SR PWM ch3 start register FFF4_1198H PWM3CCR PWM ch3 current count register FFF4_119CH PWM3IR PWM ch3 interrupt register FFF4_11A0H -


CCNT FFF4_2000H CMDR Chip mode register FFF4_2004H CSRST Software reset register FFF4_2008H Reserved Access prohibited FFF4_200CH CUSBC USB control register FFF4_2010H CPSEL Port function select register FFF4_2014H CNFR NF Ready interrupt register FFF4_2018H CSDMC SDIO clock selection register FFF4_201CH CDWS Peripheral data wrap control register FFF4_2020H CCID Chip ID register

PRELIM

INARY

3-5



Memory map

Module name Address Register name Explanation FFF4_2024H -


UART4 FFF4_3000H URT4RFR Transmission FIFO register (read only at DLAB = 0) When it accesses RFR by byte long in the big endian mode, address becomes FFF4_3003H.

FFF4_3000H URT4TFR Transmission FIFO register (write only at DLAB = 0) When it accesses TFR by byte long in the big endian mode, address becomes FFF4_3003H.

URT4DLL Dividing frequency value (lower byte at DLAB = 1) When it accesses DLL by byte long in the big endian mode, address becomes FFF4_3003H.

FFF4_3004H URT4IER DLAB = 0: Interrupt enable register URT4DLM DLAB = 1: Dividing frequency value (upper byte) FFF4_3008H URT4IIR Interrupt ID register (read only) URT4FCR FIFO control register (write only) FFF4_300CH URT4LCR Line control register FFF4_3010H URT4MCR Modem control register FFF4_3014H URT4LSR Line status register FFF4_3018H URT4MSR Modem status register FFF4_301CH -


SIO4 FFF4_3800H SIO4SMCS Serial Mode Control Status Register FFF4_3804H SIO4SDR Serial Data Register FFF4_3808H SIO4CDCR Communication Prescaler Register FFF4_380CH -


INCP FFF4_7000H IPCP0 Input capture data register 0 FFF4_7004H IPCP1 Input capture data register 1 FFF4_7008H IPCS Input capture control status register FFF4_700CH Reserved Access prohibited FFF4_7010H IPCPCLR Compare clear register FFF4_7014H IPTDAT Timer data register FFF4_7018H IPTCSR Timer control register FFF4_701CH -


GPIO2 FFF4_9000H GPDR20 Port data register 20 FFF4_9004H GPDR21 Port data register 21 FFF4_9008H GPDR22 Port data register 22 FFF4_900CH Reserved Access prohibited FFF4_9010H GPDDR20 Data direction register 20 FFF4_9014H GPDDR21 Data direction register 21 FFF4_9018H GPDDR22 Data direction register 22 FFF4_901CH -


No module FFF4_A000H - FFF4_FFFFH



URT2TFR Transmission FIFO register (write only at DLAB = 0) When it accesses TFR by byte long in the big endian mode, address becomes FFF5_0003H.

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Memory map

Module name Address Register name Explanation URT2DLL Dividing frequency value (lower byte at DLAB = 1)

When it accesses DLL by byte long in the big endian mode, address becomes FFF5_0003H.

FFF5_0004H URT2IER DLAB = 0: Interrupt enable register. URT2DLM DLAB = 1: Dividing frequency value (upper byte) FFF5_0008H URT2IIR Interrupt ID register (read only) URT2FCR FIFO control register (write only) FFF5_000CH URT2LCR Line control register FFF5_0010H URT2MCR Modem control register FFF5_0014H URT2LSR Line status register FFF5_0018H URT2MSR Modem status register FFF5_001CH -





URT3TFR Transmission FIFO register (write only at DLAB = 0) When it accesses TFR by byte long in the big endian mode, address becomes FFF5_1003H.

URT3DLL Dividing frequency value (lower byte at DLAB = 1) When it accesses DLL by byte long in the big endian mode, address becomes FFF5_1003H.

FFF5_1004H URT3IER DLAB = 0: Interrupt enable register. URT3DLM DLAB = 1: Dividing frequency value (upper byte) FFF5_1008H URT3IIR Interrupt ID register (read only) URT3FCR FIFO control register (write only) FFF5_100CH URT3LCR Line control register FFF5_1010H URT3MCR Modem control register FFF5_1014H URT3LSR Line status register FFF5_1018H URT3MSR Modem status register FFF5_101CH -




ADC FFF5_2000H ADCNT ADC control register FFF5_2004H ADMR ADC mode register FFF5_2008H ADST ADC Status register FFF5_200CH ADD0 ADC data register 0 FFF5_2010H ADD1 ADC data register 1 FFF5_2014H ADD2 ADC data register 2 FFF5_2018H ADD3 ADC data register 3 FFF5_201CH ADD4 ADC data register 4 FFF5_2020H ADD5 ADC data register 5 FFF5_2024H -

FFF5_2028H Reserved Access prohibited

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3-7



Memory map

Module name Address Register name Explanation FFF5_202CH ADCRL ADC lower limit compare register FFF5_2030H ADCRH ADC upper limit compare register FFF5_2034H -


DAC FFF5_3000H AUFIFO Audio Output Data Buffer Register FFF5_3004H AUCSR Audio Control and Status Register FFF5_3008H -


AUCLKG FFF5_3800H AUCGPR PLL control register FFF5_3804H Reserved Access prohibited FFF5_3808H AUCGWR Wait control register FFF5_380CH Reserved Access prohibited FFF5_3810H AUCGDA Clock frequency dividing control register A FFF5_3814H AUCGDB Clock frequency dividing control register B FFF5_3818H -


FFF5_3828H AUCGGC Audio clock gate control register FFF5_382CH -


CAN FFF5_4000H - FFF5_47FFH

Another specifications Another specifications

RTC FFF5_4800H RTCROSR Power off status register FFF5_4804H RTCPRSR Second interval register FFF5_4808H RTCTIME Time Register FFF5_480CH RTCDATE Date Register FFF5_4810H RTCRPON Bus isolation register FFF5_4814H RTCLOAD Load Register FFF5_4818H RTCCOMP Compare Register FFF5_481CH RTCINTR Interrupt control register FFF5_4820H -


I2C_0 FFF5_6000H I2C0BSR I2C bus status register ch0 FFF5_6004H I2C0BCR I2C bus control register ch0 FFF5_6008H I2C0CCR I2C clock control register ch0 FFF5_600CH I2C0ADR I2C address register ch0 FFF5_6010H I2C0DAR I2C data register ch0 FFF5_6014H I2C0ECSR I2C extension CS register ch0 FFF5_6018H I2C0BCFR I2C bus clock frequency register ch0 FFF5_601CH I2C0BC2R I2C bus control 2 registers ch0 FFF5_6020H -


I2C_1 FFF5_7000H I2C1BSR I2C bus status register ch1 FFF5_7004H I2C1BCR I2C bus control register ch1 FFF5_7008H I2C1CCR I2C clock control register ch1 FFF5_700CH I2C1ADR I2C address register ch1 FFF5_7010H I2C1DAR I2C data register ch1 FFF5_7014H I2C1ECSR I2C extension CS register ch1 FFF5_7018H I2C1BCFR I2C bus clock frequency register ch1 FFF5_701CH I2C1BC2R I2C bus control 2 registers ch1 FFF5_7020H -


PRELIM

INARY

3-8



Memory map

Module name Address Register name Explanation No module FFF5_8000H -


GPIO1 FFF5_9000H GPDR10 Port data register 10 FFF5_9004H GPDR11 Port data register 11 FFF5_9008H GPDR12 Port data register 12 FFF5_900CH Reserved Access prohibited FFF5_9010H GPDDR10 Data direction register 10 FFF5_9014H GPDDR11 Data direction register 11 FFF5_9018H GPDDR12 Data direction register 12 FFF5_901CH -


No module FFF5_A000H - FFF7_FFFFH


USB 2.0 EHCI Host

FFF8_0000H HCCAPBASE Capability register FFF8_0004H HCSPARAMS Structural parameter register

FFF8_0008H HCCPARAMS Capability parameter register FFF8_000CH Reserved Access prohibited FFF8_0010H USBCMD USB command register FFF8_0014H USBSTS USB status register FFF8_0018H USBINTR USB interrupt enable register FFF8_001CH FRINDEX USB frame index register FFF8_0020H CTRLDSSEGMENT 4G segment selector register FFF8_0024H PERIODICLISTBASE Periodic frame list base address register FFF8_0028H ASNCLISTADDR Asynchronous list address register FFF8_002CH -


FFF8_0050H CONFIGFLAG Configured flag register FFF8_0054H PORTSC_1 Port status/control register FFF8_0058H -


FFF8_0090H INSNREG00 Programmable Microframe base value register FFF8_0094H INSNREG01 Programmable packet buffer OUT/IN threshold register FFF8_0098H INSNREG02 Programmable packet buffer depth register FFF8_009CH INSNREG03 Break memory transfer register FFF8_00A0H INSNREG04 Debug register FFF8_00A4H INSNREG05 UTMI control status register USB 2.0 OHCI Host

FFF8_00A8H - FFF8_0FFFH


FFF8_1000H HcRevision HcRevision register FFF8_1004H HcControl Host HcControl register FFF8_1008H HcCommandStatus Command status register FFF8_100CH HcInterruptStatus Interrupt status register FFF8_1010H HcInterruptEnable Interrupt enable register FFF8_1014H HcInterruptDisable Interrupt disable register FFF8_1018H HcHCCA HCCA register FFF8_101CH HcPeriodCurrentED Period current ED register FFF8_1020H HcControlHeadED Control head ED register FFF8_1024H HcControlCurrentED Control current ED register FFF8_1028H HcBulkHeadED Bulk head ED register FFF8_102CH HcBulkCurrentED Bulk current ED register FFF8_1030H HcDoneHead Done head register

PRELIM

INARY

3-9



Memory map

Module name Address Register name Explanation FFF8_1034H HcFmInterval Frame interval register FFF8_1038H HcFmRemaining Frame remaining register FFF8_103CH HcFmNumber Frame number register FFF8_1040H HcPeriodicStart Periodic start register FFF8_1044H HcLSThreshold LS threshold register FFF8_1048H HcRhDescriptorA Root hub descriptor A register FFF8_104CH HcRhDescriptorB Root hub descriptor B register FFF8_1050H HcRhStatus Root hub status register FFF8_1054H HcRhPortStatus[1] Root hub port status/control register 1 FFF8_1058H -


USB 2.0 Host PHYCNT

FFF8_2000H LinkModeSetting Link mode setting register FFF8_2004H PHY Mode Setting1 PHY mode setting 1 register

FFF8_2008H PHY Mode Setting2 PHY mode setting 2 register FFF8_200CH -


No module FFF8_3000H - FFFB_FFFFH


NFIF FFFC_0000H FMODE Flash Mode Register FFFC_0004H -

FFFC_001CH Reserved Access prohibited

FFFC_0020H FTIM Flash Timing Register FFFC_0024H -

FFcF_003CH Reserved Access prohibited

FFFC_0040H FAREA Flash Area Register FFFC_0044H -

FFFC_005CH Reserved Access prohibited

FFFC_0060H ECCR ECC Control Register FFFC_0064H ECRR0 ECC Code Read Register 0 FFFC_0068H ECRR1 ECC Code Read Register 1 FFFC_006CH ECWR0 ECC0 Code Write Register FFFC_0070H ECWR1 ECC1 Code Write Register FFFC_0074H ECCPOS0 ECC0 Error Position Register FFFC_0078H ECCPOS1 ECC1 Error Position Register FFFC_007CH -

FFFC_7FFFH Reserved Access prohibited

DMAC FFFD_0000H DMACR DMAC configuration register FFFD_0004H -

FFFD_000FH Reserved Access prohibited

FFFD_0010H DMACA0 DMAC0 configuration A register FFFD_0014H DMACB0 DMAC0 configuration B register FFFD_0018H DMACSA0 DMAC0 source address register FFFD_001CH DMACDA0 DMAC0 destination address register FFFD_0020H DMACA1 DMAC1 configuration A register FFFD_0024H DMACB1 DMAC1 configuration B register FFFD_0028H DMACSA1 DMAC1 source address register FFFD_002CH DMACDA1 DMAC1 destination address register FFFD_0030H DMACA2 DMAC2 configuration A register FFFD_0034H DMACB2 DMAC2 configuration B register FFFD_0038H DMACSA2 DMAC2 source address register FFFD_003CH DMACDA2 DMAC2 destination address register FFFD_0040H DMACA3 DMAC3 configuration A register

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3-10



Memory map

Module name Address Register name Explanation FFFD_0044H DMACB3 DMAC3 configuration B register FFFD_0048H DMACSA3 DMAC3 source address register FFFD_004CH DMACDA3 DMAC3 destination address register FFFD_0050H DMACA4 DMAC4 configuration A register FFFD_0054H DMACB4 DMAC4 configuration B register FFFD_0058H DMACSA4 DMAC4 source address register FFFD_005CH DMACDA4 DMAC4 destination address register FFFD_0060H DMACA5 DMAC5 configuration A register FFFD_0064H DMACB5 DMAC5 configuration B register FFFD_0068H DMACSA5 DMAC5 source address register FFFD_006CH DMACDA5 DMAC5 destination address register FFFD_0070H DMACA6 DMAC6 configuration A register FFFD_0074H DMACB6 DMAC6 configuration B register FFFD_0078H DMACSA6 DMAC6 source address register FFFD_007CH DMACDA6 DMAC6 Destination address register FFFD_0080H DMACA7 DMAC7 configuration A register FFFD_0084H DMACB7 DMAC7 configuration B register FFFD_0088H DMACSA7 DMAC7 source address register FFFD_008CH DMACDA7 DMAC7 destination address register FFFD_0090H -

FFFD_FFFFH Reserved Access prohibited

Timer0 FFFE_0000H TIMER01LOAD Timer0 ch-1 load value FFFE_0004H TIMER01VALUE Timer0 ch-1 current value FFFE_0008H TIMER01CONTROL Timer0 ch-1 control register FFFE_000CH TIMER01INTCLR Timer0 ch-1 interrupt clear register FFFE_0010H TIMER01RIS Timer0 ch-1 interrupt status FFFE_0014H TIMER01MIS Interrupt status to which Timer0 ch-1 masks FFFE_0018H TIMER01BGLOAD Timer0 ch-1 background load value FFFE_001CH Reserved Access prohibited FFFE_0020H TIMER02LOAD Timer0 ch-2 load value FFFE_0024H TIMER02VALUE Timer0 ch-2 current value FFFE_0028H TIMER02CONTROL Timer0 ch-2 control registers FFFE_002CH TIMER02INTCLR Timer0 ch-2 interrupt clear register FFFE_0030H TIMER02RIS Timer0 ch-2 interrupt status FFFE_0034H TIMER02MIS Interrupt status to which Timer0 ch-2 masks FFFE_0038H TIMER02BGLOAD Timer0 ch-2 background load value FFFE_003CH -

FFFE_07FFH Reserved Access prohibited

Timer1 FFFE_0800H TIMER11LOAD Timer1 ch-1 load value FFFE_0804H TIMER11VALUE Timer1 ch-1 current value FFFE_0808H TIMER11CONTROL Timer1 ch-1 control register FFFE_080CH TIMER11INTCLR Timer1 ch-1 interrupt clear register FFFE_0810H TIMER11RIS Timer1 ch-1 interrupt status FFFE_0814H TIMER11MIS Interrupt status to which Timer1 ch-1 masks FFFE_0818H TIMER11BGLOAD Timer1 ch-1 background load value FFFE_081CH Reserved Access prohibited FFFE_0820H TIMER12LOAD Timer1 ch-2 load value FFFE_0824H TIMER12VALUE Timer1 ch-2 current value FFFE_0828H TIMER12CONTROL Timer1 ch-2 control registers FFFE_082CH TIMER12INTCLR Timer1 ch-2 interrupt clear register

PRELIM

INARY

3-11



Memory map

Module name Address Register name Explanation FFFE_0830H TIMER12RIS Timer1 ch-2 interrupt status FFFE_0834H TIMER12MIS Interrupt status to which Timer1 ch-2 masks FFFE_0838H TIMER12BGLOAD Timer1 ch-2 background load value FFFE_083CH -

FFFE_0FFFH Reserved Access prohibited

UART0 FFFE_1000H URT0RFR Reception FIFO register (read only at DLAB = 0) When it accesses RFR by byte long in the big endian mode, address becomes FFFE_1003H.

URT0TFR Transmission FIFO register (write only at DLAB = 0) When it accesses TFR by byte long in the big endian mode, address becomes FFFE_1003H.

URT0DLL Dividing frequency value (lower byte at DLAB = 1) When it accesses DLL by byte long in the big endian mode, address becomes FFFE_1003H.

FFFE_1004H URT0IER DLAB = 0: Interrupt enable register URT0DLM DLAB = 1: Dividing frequency value (upper byte) FFFE_1008H URT0IIR Interrupt ID register (read only) URT0FCR FIFO control register (write only) FFFE_100CH URT0LCR Line control register FFFE_1010H URT0MCR Modem control register FFFE_1014H URT0LSR Line status register FFFE_1018H URT0MSR Modem status register FFFE_101CH -


SIO0 FFFE_1800H SIO0SMCS Serial Mode Control Status Register FFFE_1804H SIO0SDR Serial Data Register FFFE_1808H SIO0CDCR Communication Prescaler Register FFFE_180CH -


UART1 FFFE_2000H URT1RFR Transmission FIFO register (read only at DLAB = 0) When it accesses RFR by byte long in the big endian mode, address becomes FFFE_2003H.

URT1TFR Transmission FIFO register (write only at DLAB = 0) When it accesses TFR by byte long in the big endian mode, address becomes FFFE_2003H.

URT1DLL Dividing frequency value (lower byte at DLAB = 1) When it accesses DLL by byte long in the big endian mode, address becomes FFFE_2003H.

FFFE_2004H URT1IER DLAB = 0: Interrupt enable register. URT1DLM DLAB = 1: Dividing frequency value (upper byte) FFFE_2008H URT1IIR Interrupt ID register (read only) URT1FCR FIFO control register (write only) FFFE_200CH URT1LCR Line control register FFFE_2010H URT1MCR Modem control register FFFE_2014H URT1LSR Line status register FFFE_2018H URT1MSR Modem status register FFFE_201CH -


SIO1 FFFE_2800H SIO1SMCS Serial Mode Control Status Register FFFE_2804H SIO1SDR Serial Data Register FFFE_2808H SIO1CDCR Communication Prescaler Register FFFE_280CH -


PRELIM

INARY

3-12



Memory map

Module name Address Register name Explanation External interrupt controller 0 (EXIRC0)

FFFE_3000H EIENB0 External interrupt enable register

FFFE_3004H EIREQ0 External interrupt request register FFFE_3008H EILVL0 External interrupt level register FFFE_301CH -


External interrupt controller 1 (EXIRC1)




External interrupt controller 2 (EXIRC2)




Interrupt controller 1 (IRC1)

FFFE_5000H IR1IRQF IRQ flag register FFFE_5004H IR1IRQM IRQ mask register FFFE_5008H IR1ILM Interrupt level mask register

FFFE_500CH IR1ICRMN ICR monitoring register FFFE_5010H -

FFFE_5018H Reserved Access prohibited

FFFE_501CH IR1TBR Table base register FFFE_5020H IR1VCT Interrupt vector register FFFE_5024H -

FFFE_502CH Reserved Access prohibited

FFFE_5030H IR1ICR0 Interrupt control register 00 FFFE_5034H IR1ICR1 Interrupt control register 01 FFFE_5038H IR1ICR2 Interrupt control register 02 FFFE_503CH IR1ICR3 Interrupt control register 03 FFFE_5040H IR1ICR4 Interrupt control register 04 FFFE_5044H IR1ICR5 Interrupt control register 05 FFFE_5048H IR1ICR6 Interrupt control register 06 FFFE_504CH IR1ICR7 Interrupt control register 07 FFFE_5050H IR1ICR8 Interrupt control register 08 FFFE_5054H IR1ICR9 Interrupt control register 09 FFFE_5058H IR1ICR10 Interrupt control register 10 FFFE_505CH IR1ICR11 Interrupt control register 11 FFFE_5060H IR1ICR12 Interrupt control register 12 FFFE_5064H IR1ICR13 Interrupt control register 13 FFFE_5068H IR1ICR14 Interrupt control register 14 FFFE_506CH IR1ICR15 Interrupt control register 15 FFFE_5070H IR1ICR16 Interrupt control register 16 FFFE_5074H IR1ICR17 Interrupt control register 17 FFFE_5078H IR1ICR18 Interrupt control register 18 FFFE_507CH IR1ICR19 Interrupt control register 19 FFFE_5080H IR1ICR20 Interrupt control register 20

PRELIM

INARY

3-13



Memory map

Module name Address Register name Explanation FFFE_5084H IR1ICR21 Interrupt control register 21 FFFE_5088H IR1ICR22 Interrupt control register 22 FFFE_508CH IR1ICR23 Interrupt control register 23 FFFE_5090H IR1ICR24 Interrupt control register 24 FFFE_5094H IR1ICR25 Interrupt control register 25 FFFE_5098H IR1ICR26 Interrupt control register 26 FFFE_509CH IR1ICR27 Interrupt control register 27 FFFE_50A0H IR1ICR28 Interrupt control register 28 FFFE_50A4H IR1ICR29 Interrupt control register 29 FFFE_50A8H IR1ICR30 Interrupt control register 30 FFFE_50ACH IR1ICR31 Interrupt control register 31 FFFE_50B0H -


Remap boot controller (RBC)

FFFE_6000H Reserved Access prohibited

FFFE_6004H RBREMAP Remap control register FFFE_6008H RBVIHA VINITHI control register A

FFFE_600CH RBITRA INITRAM control register A FFFE_6010H -


Clock reset generator (CRG)

FFFE_7000H CRPR PLL control register

FFFE_7004H Reserved Access prohibited FFFE_7008H CRWR Watchdog timer control register FFFE_700CH CRSR Reset/Standby control register FFFE_7010H CRDA Clock division control register A FFFE_7014H CRDB Clock division control register B FFFE_7018H CRHA AHB(A) bus clock gate control register FFFE_701CH CRPA APB(A) bus clock gate control register FFFE_7020H CRPB APB(B) bus clock gate control register FFFE_7024H CRHB AHB(B) bus clock gate control register FFFE_7028H CRAM ARM core clock gate control register FFFE_702CH -


Interrupt controller 0 (IRC0)

FFFE_8000H IR0IRQF IRQ flag register

FFFE_8004H IR0IRQM IRQ mask register FFFE_8008H IR0ILM Interrupt level mask register FFFE_800CH IR0ICRMN ICR monitoring register FFFE_8010H Reserved Access prohibited FFFE_8014H IR0DICR0 Delay interrupt control register 0 FFFE_8018H IR0DICR1 Delay interrupt control register 1 FFFE_801CH IR0TBR Table base register FFFE_8020H IR0VCT Interrupt vector register FFFE_8024H Reserved Access prohibited FFFE_8028H Reserved Access prohibited FFFE_802CH Reserved Access prohibited FFFE_8030H IR0ICR0 Interrupt control register 00 FFFE_8034H IR0ICR1 Interrupt control register 01

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3-14



Memory map

Module name Address Register name Explanation Interrupt controller 0 (IRC0)

FFFE_8038H IR0ICR2 Interrupt control register 02

FFFE_803CH IR0ICR3 Interrupt control register 03 FFFE_8040H IR0ICR4 Interrupt control register 04 FFFE_8044H IR0ICR5 Interrupt control register 05 FFFE_8048H IR0ICR6 Interrupt control register 06 FFFE_804CH IR0ICR7 Interrupt control register 07 FFFE_8050H IR0ICR8 Interrupt control register 08 FFFE_8054H IR0ICR9 Interrupt control register 09 FFFE_8058H IR0ICR10 Interrupt control register 10 FFFE_805CH IR0ICR11 Interrupt control register 11 FFFE_8060H IR0ICR12 Interrupt control register 12 FFFE_8064H IR0ICR13 Interrupt control register 13 FFFE_8068H IR0ICR14 Interrupt control register 14 FFFE_806CH IR0ICR15 Interrupt control register 15 FFFE_8070H IR0ICR16 Interrupt control register 16 FFFE_8074H IR0ICR17 Interrupt control register 17 FFFE_8078H IR0ICR18 Interrupt control register 18 FFFE_807CH IR0ICR19 Interrupt control register 19 FFFE_8080H IR0ICR20 Interrupt control register 20 FFFE_8084H IR0ICR21 Interrupt control register 21 FFFE_8088H IR0ICR22 Interrupt control register 22 FFFE_808CH IR0ICR23 Interrupt control register 23 FFFE_8090H IR0ICR24 Interrupt control register 24 FFFE_8094H IR0ICR25 Interrupt control register 25 FFFE_8098H IR0ICR26 Interrupt control register 26 FFFE_809CH IR0ICR27 Interrupt control register 27 FFFE_80A0H IR0ICR28 Interrupt control register 28 FFFE_80A4H IR0ICR29 Interrupt control register 29 FFFE_80A8H IR0ICR30 Interrupt control register 30 FFFE_80ACH IR0ICR31 Interrupt control register 31 FFFE_80B0H -


GPIO0 FFFE_9000H GPDR00 Port data register 00 FFFE_9004H GPDR01 Port data register 01 FFFE_9008H GPDR02 Port data register 02 FFFE_900CH Reserved Access prohibited FFFE_9010H GPDDR00 Data direction register 00 FFFE_9014H GPDDR01 Data direction register 01 FFFE_9018H GPDDR02 Data direction register 02 FFFE_901CH -


No module FFFE_A000H - FFFE_FFFFH


FFFF_0000H - FFFF_FDFFH

Not Register Area For external area.

Interrupt controller 0 (mirror) (IRC0 mirror)

FFFF_FE00H IR0IRQF IRQ flag register

FFFF_FE04H IR0IRQM IRQ mask register

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3-15



Memory map

Module name Address Register name Explanation FFFF_FE08H IR0ILM Interrupt level mask register FFFF_FE0CH IR0ICRMN ICR monitoring register FFFF_FE10H Reserved Access prohibited FFFF_FE14H IR0DICR0 Delay interrupt control register 0 FFFF_FE18H IR0DICR1 Delay interrupt control register 1 FFFF_FE1CH IR0TBR Table base register FFFF_FE20H IR0VCT Interrupt vector register FFFF_FE24H -

FFFF_FE2FH Reserved Access prohibited

FFFF_FE30H IR0ICR0 Interrupt control register 00 FFFF_FE34H IR0ICR1 Interrupt control register 01 FFFF_FE38H IR0ICR2 Interrupt control register 02 FFFF_FE3CH IR0ICR3 Interrupt control register 03 FFFF_FE40H IR0ICR4 Interrupt control register 04 FFFF_FE44H IR0ICR5 Interrupt control register 05 FFFF_FE48H IR0ICR6 Interrupt control register 06 FFFF_FE4CH IR0ICR7 Interrupt control register 07 FFFF_FE50H IR0ICR8 Interrupt control register 08 FFFF_FE54H IR0ICR9 Interrupt control register 09 FFFF_FE58H IR0ICR10 Interrupt control register 10 FFFF_FE5CH IR0ICR11 Interrupt control register 11 FFFF_FE60H IR0ICR12 Interrupt control register 12 FFFF_FE64H IR0ICR13 Interrupt control register 13 FFFF_FE68H IR0ICR14 Interrupt control register 14 FFFF_FE6CH IR0ICR15 Interrupt control register 15 FFFF_FE70H IR0ICR16 Interrupt control register 16 FFFF_FE74H IR0ICR17 Interrupt control register 17 FFFF_FE78H IR0ICR18 Interrupt control register 18 FFFF_FE7CH IR0ICR19 Interrupt control register 19 FFFF_FE80H IR0ICR20 Interrupt control register 20 FFFF_FE84H IR0ICR21 Interrupt control register 21 FFFF_FE88H IR0ICR22 Interrupt control register 22 FFFF_FE8CH IR0ICR23 Interrupt control register 23 FFFF_FE90H IR0ICR24 Interrupt control register 24 FFFF_FE94H IR0ICR25 Interrupt control register 25 FFFF_FE98H IR0ICR26 Interrupt control register 26 FFFF_FE9CH IR0ICR27 Interrupt control register 27 FFFF_FEA0H IR0ICR28 Interrupt control register 28 FFFF_FEA4H IR0ICR29 Interrupt control register 29 FFFF_FEA8H IR0ICR30 Interrupt control register 30 FFFF_FEACH IR0ICR31 Interrupt control register 31 FFFF_FEB0H -

FFFF_FEFFH Reserved Access prohibited

Interrupt controller 1 (mirror) (IRC1 mirror)

FFFF_FF00H IR1IRQF IRQ flag register

FFFE_FF04H IR1IRQM IRQ mask register FFFE_FF08H IR1ILM Interrupt level mask register FFFE_FF0CH IR1ICRMN ICR monitoring register

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3-16



Memory map

Module name Address Register name Explanation FFFF_FF10H -

FFFF_FF18H Reserved Access prohibited

FFFF_FF1CH IR1TBR Table base register FFFF_FF20H IR1VCT Interrupt vector register FFFF_FF24H -

FFFF_FF2CH Reserved Access prohibited

FFFF_FF30H IR1ICR0 Interrupt control register 00 FFFF_FF34H IR1ICR1 Interrupt control register 01 FFFF_FF38H IR1ICR2 Interrupt control register 02 FFFF_FF3CH IR1ICR3 Interrupt control register 03 FFFF_FF40H IR1ICR4 Interrupt control register 04 FFFF_FF44H IR1ICR5 Interrupt control register 05 FFFF_FF48H IR1ICR6 Interrupt control register 06 FFFF_FF4CH IR1ICR7 Interrupt control register 07 FFFF_FF50H IR1ICR8 Interrupt control register 08 FFFF_FF54H IR1ICR9 Interrupt control register 09 FFFF_FF58H IR1ICR10 Interrupt control register 10 FFFF_FF5CH IR1ICR11 Interrupt control register 11 FFFF_FF60H IR1ICR12 Interrupt control register 12 FFFF_FF64H IR1ICR13 Interrupt control register 13 FFFF_FF68H IR1ICR14 Interrupt control register 14 FFFF_FF6CH IR1ICR15 Interrupt control register 15 FFFF_FF70H IR1ICR16 Interrupt control register 16 FFFF_FF74H IR1ICR17 Interrupt control register 17 FFFF_FF78H IR1ICR18 Interrupt control register 18 FFFF_FF7CH IR1ICR19 Interrupt control register 19 FFFF_FF80H IR1ICR20 Interrupt control register 20 FFFF_FF84H IR1ICR21 Interrupt control register 21 FFFF_FF88H IR1ICR22 Interrupt control register 22 FFFF_FF8CH IR1ICR23 Interrupt control register 23 FFFF_FF90H IR1ICR24 Interrupt control register 24 FFFF_FF94H IR1ICR25 Interrupt control register 25 FFFF_FF98H IR1ICR26 Interrupt control register 26 FFFF_FF9CH IR1ICR27 Interrupt control register 27 FFFF_FFA0H IR1ICR28 Interrupt control register 28 FFFF_FFA4H IR1ICR29 Interrupt control register 29 FFFF_FFA8H IR1ICR30 Interrupt control register 30 FFFF_FFACH IR1ICR31 Interrupt control register 31 FFFF_50B0H -

FFFF_FFFFH Reserved Access prohibited

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4-1

4. CPU (ARM946E-S core part) This chapter describes CPU (ARM946E-S core part) of this LSI.

4.1. Outline ARM946E-S core part includes functional blocks such as ARM946ES, TCM (Tightly Coupled Memory)

4.2. Feature ARM946E-S core part has following features:

• Five stage pipeline (fetch, decode, execution, memory, and write) • 16KB instruction cache/16KB data cache • 16KB instruction TCM (ITCM) /16KB data TCM (DTCM) • Corresponded to little endian only

4.3. Block diagram Figure 4-1 shows ARM946E-S core part’s block diagram. ARM946ES core block

16kB Instruction

TCM

16kB data TCM

JTAG Sync. circuit

ARM946ES

16kB Data cache

16kB Instruction

cache

JTAG signal

AHB I/F

AHB

Figure 4-1 Block diagram of ARM946E-S core part

4.4. ARM946E-S ARM946E-S cache size, both instruction and data, is set to 16KB as well as DTCM. ITCM size is set to 512KB but only 16KB can be used Refer to related material of ARM Ltd. such as shown below for detailed specification of ARM946E-S

• ARM946E-S Product Overview (DVI0022A) • ARM946E-S (r1p1) Technical Reference Manual (DDI0201D) • ARM9E-S (r2p1) Core Technical Reference Manual DDI0240B)

They are found in the following URL. http://www.arm.com/documentation/ARMProcessor_Cores/index.html


CPU (ARM926E-S Core)

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http://www.arm.com/documentation/ARMProcessor_Cores/index.html


5. Clock and reset generator (CRG) This chapter describes function and operation of clock and reset generator (CRG.)

5.1. Outline CRG controls clock/reset of ARM946ES, AHB bus resources, and APB bus resources.

5.2. Feature CRG has the following features:

• Clock generator • Both PLL clock and external input clock (PLL by-pass mode) are operable • PLL control

a- Control of PLL oscillation and stop b- Control of PLL oscillation stabilization waiting time

• Clock gear control • Clock frequency of ARM core, AHB, and APB can be changed separately • Supply/Stop control of clock to ARM core, AHB, and APB module

• Reset generator

• Generation of internal reset from external reset • Generation of software reset • Input/Output control of JXSRST signal for JTAG ICE • Generation of JXTRST (TAP controller’s reset) signal

• Others

• Watchdog timer function • Corresponding to stop mode which halts all clocks of this device


Clock and reset generator (CRG)

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5.3. Block diagram

Figure 5-1 shows block diagram of clock reset generator (CRG.)

CRG

Clock divider (CR_DVS)


APB bus

APB I/F

(CR_REG)

AHB

control

Watch of ARM grant states (CR_GNT)

Time base timer (CR_TBT)

Controller of clock dividing

(CR_DIV)

Clock generator (CR_MCK)

PLL macro

Watchdog timer (CR_WDT)


Reset generator

(CR_RST)

Clock

ARM/ AHB/ APB clock

ARM/ AHB/ APB reset

Figure 5-1 Block diagram of clock reset generator (CRG)

Table 5-1 shows function of the block included in CRG.

Table 5-1 Individual block function Block Function

CR_RST Generation of reset signal CR_MCK PLL control/bypass CR_GNT ARM’s grant status watch CR_DIV Generation of clock frequency dividing and clock enable signal CR_DVS Selection of clock frequency dividing and non clock frequency dividing

CR_TBT

Count of following items: • PLL oscillation stabilization waiting time • PLL reset’s pulse width • Watchdog timer’s clear timing • Software reset’s pulse width

CR_REG Control register CR_WDT Watchdog timer



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5.4. Register This section describes CRG register.

5.4.1. Register list

Table 5-2 shows list of CRG register.

Table 5-2 CRG register list Address

Register name Abbreviation Explanation Base Offset

FFFE_7000H + 000H PLL control register CRPR To control PLL + 004H (Reserved) – Reserved area, access prohibited + 008H Watchdog timer control register CRWR To control watchdog timer + 00CH Reset/Standby control register CRSR To control reset/standby + 010H Clock frequency dividing control

register A CRDA To control clock divider

+ 014H Clock frequency dividing control register B

CRDB To control clock divider

+ 018H AHB(A) bus clock gate control register

CRHA To control clock gate of AHB(A) bus

+ 01CH APB(A) bus clock gate control register

CRPA To control clock gate of APB(A) bus

+ 020H APB(B) bus clock gate control register

CRPB To control clock gate of APB(B) bus

+ 024H AHB(B) bus clock gate control register

CRHB To control clock gate of AHB(B) bus

+ 028H ARM clock gate control register CRAM To control clock gate of ARM core + 02CH ~ + FFFH

(Reserved) – Reserved area, access prohibited



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Description format of register Following format is used for description of register’s each bit.

Address Base address + Offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name R/W

Initial value Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name R/W

Initial value

Meaning of item and sign Address

Address (base address + offset address) of the register Bit

Bit number of the register Name

Bit field name of the register R/W

Attribution of read/write of each bit field • R0:Read value is always "0" • R1: Read value is always "1" • W0: Write value is always "0", and write access of "1" is ignored • W1: Write value is always "1", and write access of "0" is ignored • R: Read • W: Write

Initial value Each bit field’s value after reset

• 0: Value is "0" • 1: Value is "1" • X: Value is undefined



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5.4.2. PLL control register (CRPR) This register controls PLL.

Address FFFE_7000H + 00H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name – – – – – – – – – – – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name (Reserved) XCLKMODE[2:0] PLLRDY *1 LUWMODE[1:0] PLLMODE[4:0] R/W R0 R0 R0 R0 R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 *1: PLLBYPASS

Bit field

Description No. Name

31-16 – Unused bits. Write access is ignored, and read value of these bits is undefined.

15-12 (Reserved) Reserved bits. Write access is ignored, and read value of these bits is always "0".

11-9 XCLKMODE PLL input clock dividing ratio Define the PLL input clock dividing ratio, K

K = 8 + XCLKMODE[2:0] PLL output clock frequency fCCLK = ( fCLK × N/K ) fCLK : Input clock frequency K : 8 + XCLKMODE[2:0] N : 48 + PLLMODE[4:0]

8 PLLRDY PLL READY monitoring This bit monitors internal signal, PLLREADY with external pin CLK clock. The PLLREADY signal shows overflow of the value selected at LUWMODE[1:0] bit by the timer which calculates PLL oscillation stabilization waiting time.

0 PLLREADY signal is "low" (initial value) 1 PLLREADY signal is "high"

Write access to this bit is ignored. Note: PLLRDY=1 does not guarantee that PLL is locked and clock supply is ready.

7 PLLBYPASS PLL bypass mode This bit bypasses PLL.

0 PLL clock is used.

1 PLL is bypassed (Initial value) When PLL clock is bypassed, direct input clock is used for system clock generation

Note: Do not change PLLBYPASS bit and PLLMODE[4:0] at the same time since clock switch

of both external pin CLK and PLL clocks needs to be changed. If they are changed at the same time, CRG detects PLL oscillation frequency change and state becomes PLL oscillation stabilization waiting before PLL bypass mode.



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Bit field Description

No. Name 6-5 LUWMODE[1:0] PLL lockup waiting mode

These bits are used to set PLL oscillation stabilization wait time.

00 TCLK × (2(n0+1) - 2m + 1) 01 TCLK × (2(n1+1) - 2m + 1) (initial value) 10 TCLK × (2(n3+1) - 2m + 1) 11 TCLK × (2(n3+1) - 2m + 1)

TCLK: Cycle time of external input CLK

n0 = 8 n1 = 12 n2 = 13 n3 = 14 m = 7

e.g When external input CLK = 48MHz 00 8.02 µS 01 168.02 µS 10 338.69 µS 11 680.02 µS

Note : The PLL lockup wait time must be set to exceed 100µS. If wait time last than 100µS, internal operating clock period is potentially unstable.

4-0 PLLMODE[4:0] PLL feedback clock dividing ratio, N

These bits are used to set PLL feedback clock dividing ratio. N = 48 + PLLMODE[4:0]

PLL output clock frequency fCCLK = ( fCLK × N/K ) fCLK : Input clock frequency K : 8 + XCLKMODE[2:0] N : 48 + PLLMODE[4:0] Note: Do not change PLLMODE[4:0] when PLLBYPASS bit is 0. PLLMODE[4:0] = “11111” stopped the PLL Operation of PLL output clock frequency (fCCLK ) from 250MHz (min) to 330MHz (max).

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5.4.3. Watchdog timer control register (CRWR) This register controls watchdog timer.




Name (Reserved) ERST (Reserved) TBR WDRST WDTSET/WDTCLR WDTMODE[1:0]

R/W R0 R0 R0 R0 R0 R0 R0 R0 R/W0 R0 R/W* R/W1 R/W0 R/W1 R/W R/WInitial value 0 0 0 0 0 0 0 0 1 0 0 0 X 0 0 0 *: Do not set "1" to bit 5

Bit field



15-8 (Reserved) Reserved bits. Write access is ignored, and read value of these bits is always "0".

7 ERST External reset of monitoring

0 External Reset is not asserted Write “0” to clear this bit

1 External Reset is asserted (initial value) The initial value of this bit is set to 1 by falling edge of external reset pin., and writing "1" is ignored.

6 (Reserved) Reserved bits. Write access is ignored, and read value of these bits is always "0".

5 (Reserved) Reserved bits. Always Writing “0” to this bit

4 TBR Time based timer reset request This bit resets the time based timer, and its reset signal is asserted during 1 cycle of APB clock.

0 Time based timer is not reset (initial value) 1 Reset the time based timer

Writing 0 is ignored.

3 WDRST Watchdog reset monitoring This bit monitors watchdog reset.

0 Watchdog reset is not asserted 1 Watchdog reset is asserted

The initial value of this bit is undefined, and writing 1 is ignored. When watchdog is reset, this bit is set to "1".



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No. Name 2 WDTSET

/WDTCLR Setting and clear of watchdog timer This bit sets and clears watchdog timer which starts count at writing "1" and clears at writing "1" from the second time.

0 The watchdog timer is not set (Initial value)

1 First time: The watchdog timer starts Second time or later: The watchdog timer is cleared


1-0 WDTMODE[1:0] These bits set timing to clear watchdog timer. Watchdog reset occurs at following period when "1" is written to WDTSET/WDTCLR bits at the end.

00 TCLK × 2(n0+1) ~ TCLK × 2(n0 + 2) (initial value) 01 TCLK × 2(n1+1) ~ TCLK × 2(n1 + 2) 10 TCLK × 2(n2+1) ~ TCLK × 2(n2 + 2) 11 TCLK × 2(n3+1) ~ TCLK × 2(n3 + 2)

TCLK: Cycle time of external input CLK n0 = 23 n1 = 24 n2 = 26 n3 = 27

e.g When external input CLK = 48MHz

00 0.3s ~ 0.7s 01 0.7s ~ 1.4s 10 2.8s ~ 5.6s 11 5.6s ~ 11.2s

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5.4.4. Reset/Standby control register (CRSR) This register controls reset and standby.

Address FFFE_7000H + 0CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name Reserved STOPEN Reserved Reserved Reserved SRST SWRST SWRSTREQ

SWRMODE

R/W R0 R0 R0 R0 R0 R0 R0 R0 R/W R/W R0 R/W R/W0 R/W0 R/W1 R/WInitial value 0 0 0 0 0 0 0 0 0 0 0 0 X X 0 0


No. Name 31-16 – Unused bits.

Write access is ignored, and read value of these bits is undefined. 15-8 (Reserved) Reserved bits.

Write access is ignored, and read value of these bits is always "0". 7 STOPEN Stop mode enable

This bit stops all bus clock operations when ARM core goes into the standby wait for interrupt.

0 Bus clock operation in the standby wait for interrupt does not stop (initial value) 1 All bus clock operations in the standby wait for interrupt is stopped

Note: When changing state to stop mode, write "1" to PLLBYPASS bit of CRPR.

6 (Reserved) Reserved bit. Always write "0" to write access.

5 (Reserved) Reserved bits. Write access is ignored, and read value of these bits is always "0".

4 (Reserved) Reserved bit. Always write "0" to write access.

3 SRST JXSRST monitoring This bit monitors JXSRST reset from ICE.

0 JXSRST is not asserted 1 JXSRST is asserted

Initial value of this bit is undefined. When JXSRST occurs, this bit is set to "1". This bit will be cleared by writing “0”. Writing “1” has no effect.

2 SWRST Software reset monitoring This bit monitors software reset.

0 Software reset is not asserted 1 Software reset is asserted

Initial value of this bit is undefined. When software reset occurs, this bit is set to "1". This bit will be cleared by writing “0”. Writing “1” has no effect.



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Bit field Description No. Name 1 SWRSTREQ Software reset request

This bit asserts software reset.

0 Software reset is not requested (initial value) 1 Software reset is requested

Writing 0 is ignored, and this bit is cleared with reset signal.

0 SWRMODE Pulse width mode of software reset This bit sets pulse width of software reset.

0 TCLK × (2n0+1) + TCCLK × 7 (initial value) 1 TCLK × (2n1+1) + TCCLK × 7

TCLK: Cycle time of external pin CLK TCCLK: Cycle time of PLL output n0 = 6 n1 = 11

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5.4.5. Clock divider control register A (CRDA) This register controls clock divider for ARM clock, AHB1 bus clock and AD converter operating clock.




Name Reserved Reserved ARMADM[2:0] ADDM[2:0] PADM[2:0] HADM[2:0] R/W R0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 15 (Reserved) Reserved bit.

Write access is ignored, and read value of these bits is always "0". 14-12 (Reserved) Reserved bit

Always Write “111” to these bits 11-9 ARMADM[2:0] CLK dividing ratio for ARM clock

These bits set clock frequency of ARM core operating clock, ARMCLK. Maximum clock frequency of ARM core is 165MHz

CRPR.PLLBYPASS = 0 fARMCLK = PLL output / 2ARMADM CRPR.PLLBYPASS = 1 fARMCLK = Input clock / 2ARMADM fARMCLK : Clock frequency of ARM core

8-6 ADDM[2:0] Clock dividing ratio for AD converter system Clock These bits set frequency dividing ratio of ADC operating clock ADCLK. Maximum clock frequency of ADC is 5MHz

CRPR.PLLBYPASS = 0 fADCLK = PLL output / 2ADDM CRPR.PLLBYPASS = 1 fADCLK = Input clock / 2ADDM fADCLK : Clock frequency of ADC operating clock

5-3 PADM[2:0] Clock dividing mode for APB bus clock These bits set frequency dividing ratio of APB bus clock, PACLK. Maximum clock frequency of APB bus is 41.25MHz

CRPR.PLLBYPASS = 0 fPACLK = PLL output / 2PADM CRPR.PLLBYPASS = 1 fPACLK = Input clock / 2PADM fPACLK : Clock frequency of APB bus clock

2-0 HADM[2:0] Clock dividing mode for AHB bus clock These bits set frequency dividing ratio of AHB1 bus block, HACLK. Maximum clock frequency of AHB bus is 82.5MHz

CRPR.PLLBYPASS = 0 fHACLK = PLL output / 2HADM CRPR.PLLBYPASS = 1 fHACLK = Input clock / 2HADM fHACLK : Clock frequency of AHB1 bus clock



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5.4.6. Clock divider control register B (CRDB) This register controls clock divider for AHB2 bus clock.




Name (Reserved) HBDM[2:0] R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 15-3 (Reserved) Reserved bits.

Write access is ignored, and read value of these bits is always "0". 2-0 HBDM[2:0] Clock dividing mode for AHB2 bus clock

These bits set frequency dividing ratio of AHB2 bus clock, HCLK2. AHB2 bus clock is used by SDMC, so the maximum frequency of AHB2 bus clock is 50MHz.

CRPR.PLLBYPASS = 0 fHBCLK = PLL output / 2HBDM CRPR.PLLBYPASS = 1 fHBCLK = Input clock / 2HBDM fHBCLK : Clock frequency of AHB2 bus clock

Note:

ARMCLK must not be slower than AHB1 bus clock (HCLK1); moreover, HCLK must not be slower than other clocks.

fARMCLK >= fHACLK, >= fADCLK, fPACLK, fHBCLK



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5.4.7. AHB (A) bus clock gate control register (CRHA) This register controls clock gating of AHB (A) bus.




Name HAGATE[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W0 R/W R/W R/W R/W

Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Always write “0” to bit4

Bit field



15-0 HAGATE[15:0] HACLK clock gate control These bits control HACLK clock gate.

HAGATE[n] Description 0 HACLKn stops 1 HACLKn does not stop (initial value)

HACLK0: AHB1 bus matrix, AHB2 bus matrix, APBBRG0, APBBRG1, APBBRG2 HACLK1: NAND I/F HACLK2: SRAM1, SRAM2 (Data RAM) HACLK3: HDMAC HACLK4: (Reserved) Always write “0” to this bit HACLK5: Boot ROM, SRRAM0 HACLK6: I2S_0 HACLK7: I2S_1 HACLK8: (Reserved) HACLK9: USB 2.0 host HACLK10: Boot ROM patch and IROM patch HACLK11: (Reserved) HACLK12: (Reserved) HACLK13: (Reserved) HACLK14: (Reserved) HACLK15: (Reserved)



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5.4.8. APB (A) bus clock gate control register (CRPA) This register controls clock gate of PACLK.

Address FFFE_7000H + 1CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name PAGATE[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1



Write access is ignored, and read value of these bits is undefined. 15-0 PAGATE[15:0] PACLK clock gate control

These bits control PACLK clock gate.

PAGATE[n] Description 0 PACLKn stops 1 PACLKn does not stop (initial value)

PACLK0: IRC x 2 ( IRC0, IRC1) PACLK1: EXIRC x 3 (EXIRC0, EXIRC1, EXIRC2) PACLK2: UART0, UART1 PACLK3: GPIO PACLK4: RBC PACLK5: 32 bit timer x 2 (Timers0, Timers1) PACLK6: I2C × 2 (I2C0, I2C1) PACLK7: CAN PACLK8: UART2, UART3 PACLK9: ADC registers PACLK10: PWM PACLK11: SPI0 PACLK12: CCNT PACLK13: UART4 PACLK14: SPI1 PACLK15: RTC control



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5.4.9. APB (B) bus clock gate control register (CRPB) This register controls clock gate of APB (B) bus.




Name PBGATE[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1



Write access is ignored, and read value of these bits is undefined. 15-0 PBGATE[15:0] These bits control PBCLK clock gate.

This LSI does not use them.

PBGATE[n] Description 0 PBCLKn stops 1 PBCLKn does not stop (initial value)

PBCLK0: SIO x 2 (SIO0, SIO1) PBCLK1: SIO x 2 (SIO2, SIO3) PBCLK2: SIO x 1 (SIO4) PBCLK3: DAC control PBCLK4: Input Capture timer PBCLK5: (Reserved) PBCLK6: (Reserved) PBCLK7: (Reserved) PBCLK8: ADC sample clock PBCLK9: (Reserved) PBCLK10: (Reserved) PBCLK11: (Reserved) PBCLK12: (Reserved) PBCLK13: (Reserved) PBCLK14: (Reserved) PBCLK15: (Reserved)



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5.4.10. AHB (B) bus clock gate control register (CRHB) This register controls clock gate of AHB (B) bus.




Name HBGATE[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1



Write access is ignored, and read value of these bits is undefined. 15-0 HBGATE[15:0] HBCLK clock gate control

These bits control HBCLK clock gate.

HBGATE[n] Description 0 HBCLKn stops 1 HBCLKn does not stop (initial value)

HBCLK0: SDMC HBCLK1: (Reserved) HBCLK2: (Reserved) HBCLK3: (Reserved) HBCLK4: (Reserved) HBCLK5: (Reserved) HBCLK6: (Reserved) HBCLK7: (Reserved) HBCLK8: (Reserved) HBCLK9: (Reserved) HBCLK10: (Reserved) HBCLK11: (Reserved) HBCLK12: (Reserved) HBCLK13: (Reserved) HBCLK14: (Reserved) HBCLK15: (Reserved)



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5.4.11. ARM core clock gate control register (CRAM) This register controls clock gate of ARM core.




Name (Reserved) (Reserved) (Reserved) ARMGATER/W R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R1 R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1



The write access is ignored, and read value of these bits is undefined. 15-4 (Reserved) Reserved bits.

Write access is ignored, and read value of these bits is always "1". 3-1 (Reserved) Reserved bits.

Write access is ignored, and read value of these bits is always "1". 0 ARMGATE ARMCLK clock gate control

These bits control ARMCLK clock gate.

0 ARMCLK stops 1 ARMCLK does not stop (initial value)

After stopping this clock, proceeds system reset to resume operation. If the watchdog timer is enabled, the chip returns to reset state when watchdog reset occurs.



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5.5. Operation This section describes CRG operation.

5.5.1. Generation of reset

Factor There are following five reset factors.

1. External reset (RSTX pin input) The entire chip is initialized by the reset input from external pin, RSTX. After external reset, PLLBYPASS is set to "H",.

2. Software reset (reset with register control) Software reset occurs with writing "1" to SWRSTREQ bit of reset/standby control register (CRSR). It does not change state to PLL oscillation stabilization even though PLLBYPASS bit of PLL control register (CRPR) is "0" (setting that uses PLL clock.) Moreover, this reset does not change CRG module register, VINITHI control register of remap/boot controller (RBC), and INITRAM control register. Clock source of the software reset is time based timer’s count value. It is cleared when software reset is asserted. This software reset generates the internal signal, which does not reset as CRSTn.

3. JXSRST (reset request from debugging tool) This signal is reset request from debugging tool (e.g. MultiICE), and internal reset request is able to transmit to the tool through JXSRST pin This module recognizes the reset signal to be the same reset request as external reset’s.

4. JXTRST (built-in ICE macro reset request from debugging tool) This signal is built-in ICE macro reset request from debugging tool (e.g. MultiICE), and the reset signal is to request reset to built-in ICE macro in ARM9. Although the reset signal is asserted, other peripherals are not initialized..



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5. Watchdog reset When the WDTSET/WDTCLR bits of watchdog timer control register (CRWR) are set to "1" after external reset, watchdog timer starts. Writing "1" to the WDTSET/WDTCLR bits at the second time or later clears the timer. Clock source of the watchdog timer is count value of the time based timer. Clear operation of time based timer affects on watchdog timer’s count value. When the timer is cleared, the watchdog timer is also cleared.

Selected time base timer bit

WDTCLR (max) WDTCLR (min)

Watchdog reset request

Tclk x 2n

Tclk x 2(n+1)

Figure 5-2 Timing of watchdog reset

As shown in Figure 5-2, watchdog reset occurs after second falling edge of selected time based timer

bit. During PLL oscillation stabilization waiting time and ARM9 debug mode (DBGACK = 1), CRG clears watchdog timer. Moreover, it monitors standby wait for interrupt (STANDBYWFI) of ARM9 and clears watchdog timer automatically in the stop or sleep mode.

Reset output signal Reset signal output from the reset generator based on the reset factor is as follows.

HRESETn (AHB/APB bus reset) This internal reset signal initializes ARM9 and AHB/APB peripherals, and it is output by external reset, software reset or JXSRST reset.

JXSRST (reset monitoring) This signal functions as reporting to external circuit of ARM’s internal reset source. This signal is asserted the same as HRESETn signal.

Internal XTRST (built-in ICE macro reset) This signal initializes built-in macro of ARM9. The macro must be reset at power-on so that this signal is output by external reset or external JXTRST reset.

CRSTn (internal reset) This signal is output by external reset or JXSRST reset.



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Table 5-3 shows correlation between reset factor and reset output signal.

Table 5-3 Correlation between reset factor and reset output signal

Reset output Reset factor

External reset Software reset Input JXSRST JXTRST Watchdog reset HRESETn Asserted Asserted Asserted Not asserted Asserted Output JXSRST Asserted Asserted Not asserted Not asserted Asserted Internal XTRST Asserted Not asserted Not asserted Asserted Not asserted CRSTn Asserted Not asserted Asserted Not asserted Asserted



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5.5.2. Clock generation

Figure 5-3 shows clock generation chart.

PLL CK FB

1

1/N

0

1/L4 Gate

ARMADM[2:0]

1/L1

Gate

HAGATE[n] | STOP

HADM[2:0]

1/L6 Gate

ARMACLK

HACLKcrg

HACLKn

HBCLKn

K = 8 ~ 15 N = 48 ~ 78 Ln = 1, 2, 4, 8, 16, 32, 64, 128

PLLBYPASS

CLK

PLLMODE[4:0]

HBGATE[0] | STOPHBDM[2:0]

1/L2

Gate

PAGATE[n] | STOP

PADM[2:0]

1/L3 Gate

PACLKcrg

PACLKn

ADCLK

PBGATE[8] | STOPADDM[2:0]

Gate

STOP

Gate

STOP

CCLK

ARMAGATE | STOP

AHB clock (A) AHB1 bus

APB clock (A) APB bus

ARM clock

AHB clock (B) (AHB2 bus)

CCLK

1/K

XCLKMODE[2:0]

Figure 5-3 Clock generation chart



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PLL control Oscillation stabilization waiting

The clock transmission source in oscillation stabilization waiting is count value of the time based timer. Clear operation of time based timer affects on its count value. When this module state is changed to PLL oscillation stabilization waiting state as shown below, the time based timer is cleared.

(1) PLL oscillation frequency is changed by PLL mode ("M" in Figure 5-5 and "m" of LUWMODE in the 5.4.2 PLL control register (CRPR))

RSTX PLL reset CLK 1/M PLL clock CCLK PLLREADY PLLBYPASS PLLMODE[4:0]

PLL oscillation stabilization waiting

a) Clock source change (write PLLBYPASS bit) b) Set the PLL oscillation mode (write PLLMODE bits) c) PLL reset de-asserted d) PLL ready (PLLREADY can be monitored by PLLRDY bit) e) Clock source change (write PLLBYPASS bit)

c) d) e) b)

a)

(m2 + 2) CLK cycles

Figure 5-4 PLL oscillation stabilization waiting state by PLL mode change

(2) Returning from stop mode by external interrupt (see Figure 5-9)

(3) Watchdog reset is asserted

Frequency change Oscillation frequency and frequency dividing ratio (M) of PLL (fCLK × N) are set by PLLMODE[4:0] bit of the PLL control register (CRPR), and the frequency is able to be changed during the operation. Do not change PLLMODE[4:0] and XCLKMODE[2:0] when PLLBYPASS bit of the PLL control register (CRPR) is 0.

PLLBYPASS Main clock (CCLK) of this module is able to be switched dynamically between PLL clock and external input clock (CLK) by PLLBYPASS bit of the PLL control register (CRPR.)



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CLK 1/M PLL clock CCLK PLLREADY PLLBYPASS

a) a) Clock source change (write PLLBYPASS bit (write 0)) b) Clock source change (write PLLBYPASS bit (write 1))

b)

Clock switching Clock switching

Figure 5-5 Clock switch between PLL clock and external clock



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Clock gear CRG corresponds to the clock gear function with clock enable signal.

CCLK ARAMDM ARMACLKEN ARMACLK HADM HACLKEN HACLKｎ

000

001

001

010

PADM PACLKEN PACLKｎ

010

Figure 5-6 Clock gear

Low power consumption states This chip comprises several low power consumption states to reduce power consumption. Depending on the application requirements, power saving ranges from high (stop mode) to low (clock gating). Maximum power saving is achieved by stopping all functions while individual module can be halted without sacrifice performance.

(1) SLEEP mode In sleep mode, ARM946ES core is putted into standby state with flexibility of operating individual AHB/APB modules. To stop individual AHB/APB module, corresponding bit of clock gate control register is set to “0” beforehand. ARM946ES core corresponds to standby state that is called "Interrupt waiting mode" using system coprocessor CP15. With register bit CRSR.STOPEN equal to “0”, the STANDBYWFI signal is asserted and internal clock gate is closed not to supply input clock to sub module during the standby state (refer to ARM946ES technical reference manual, "12.1.1 dynamic power management (interrupt mode waiting)".) To wake up ARM946ES from sleep mode, interrupt should be set properly in advance and the corresponding clock of the source including interrupt controller (IRC) must be in operation, refer to notes in (3) clock gating for details.

ARMCLK

Clock Reset

Generator

ARM946E-S

CLKclockgate

STANDBYWFI

Internal clock

Figure 5-7 STANDBYWFI signal (ARM946ES)



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5-25


(2) STOP mode When STANDBYWFI (ARM946ES) signal is set to "1" with register bit CRSR.STOPEN equal to “1”, the chip state changes to STOP mode. In this mode, CRG stops all clocks and PLL oscillation; moreover, the stop mode is released with external rest or external interrupt. Figure 5-9 shows STOP mode operation.

CLK

STOP mode

STOPEN STANDBYWFIPACLK0_STPSTOP WAKEUP CCLK ARMA(B)CLK HACLK PACLK PLLBYPASSPLLRDY PLL clock PLL reset


* STOP = CLK clock is able to stop while the value is "1”

Figure 5-9: STOP mode operation

Note: When the chip state is changed to the stop mode, "1" should be written to PLLBYPASS bit of the PLL control register (CRPR.) Although PLL proceeds oscillation stabilization waiting at STOP mode release, clock is not switched to PLL clock until PLLBYPASS bit becomes "0"; in addition, PLL stops when PLLMODE[4:0] is 5’b11111. Refer to section 13.9 for notices for using external interrupt from Stop mode.

(3) Clock gating To cope varies application requirements, each AHB/APB module can be halted by stopping the clock delivered to them. This is accomplished by setting corresponding register bit of clock gate control register to “0”. In other words, the chip can be set with arbitrary functions in operation saving unnecessary power consumption from the rest.

Note:

Depending on the user configuration, related modules need to be in operation for the chip to work properly.

i. The AHB1/2 bus matrix and APBBRG1/2/3 should be in operation (CRHA.HAGATE[0] = 1) in order to access AHB or APB modules.

ii. The SRAM1/2 should be in operation (CRHA.HAGATE[2] = 1) if user program accessing them.

iii. The SRAM0 should be in operation (CRHA.HAGATE[5] = 1) if user program storing inside.

iv. The IRC0/1 should be in operation (CRPA.PAGATE[0] = 1) if interrupt is used.

Clock and reset generator (CRG) FUJITSU SEMICONDUCTOR PROPRIETARY AND CONFIDENTIAL

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6. Audio Clock Generator (AUCLKG) This chapter describes function and operation of audio clock generator (AUCLKG)

6.1. Outline AUCLKG generates an operating clock of audio related macros i.e. I2S and Audio DAC

6.2. Feature AUCLKG has the following features:

• Clock generator • Dedicated PLL equipped with clock gear control • Clock frequency of module I2S0, I2S1 and Audio DAC can be changed separately • Supply/Stop control of clock to I2S and Audio DAC module


Audio Clock Generator (AUCLKG)

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6.3. Block diagram Figure 6-1 shows block diagram of audio clock generator (AUCLKG)

AUCLKG



APB bus

APB I/F

(CR_REG)

Time base timer (CR_TBT)

Controller of clock dividing

(CR_DIV)

Clock generator (CR_MCK)

PLL macro Clock divider

(CR_DVS)

Clock I2S0ECLKI2S1ECLKDACCLK

Figure 6-1 Block diagram of AUCLKG Table 6-1 shows function of the block included in CRG.

Table 6-1 Individual block function Block Function

CR_MCK PLL control/bypass CR_DIV Generation of clock frequency dividing and clock enable signal CR_DVS Selection of clock frequency dividing and non clock frequency dividing

CR_TBT Count of following items: • PLL oscillation stabilization waiting time • PLL reset’s pulse width

CR_REG Control register



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6.4. Register This section describes AUCLKG register.

6.4.1. Register list Table 6-2 shows list of AUCLKG register.

Table 6-2 AUCLKG register list Address

Register name Abbreviation Explanation Base Offset

FFF5_3800H + 000H PLL control register AUCGPR To control Audio PLL + 004H (Reserved) – Reserved area, access prohibited + 008H Wait control register AUCGWR To control Audio PLL wait time timer + 00CH (Reserved) – Reserved area, access prohibited + 010H Clock frequency dividing control

register A AUCGDA To control clock divider

+ 014H Clock frequency dividing control register B

AUCGDB To control clock divider

+ 018H (Reserved) – Reserved area, access prohibited + 01CH (Reserved) – Reserved area, access prohibited + 020H (Reserved) – Reserved area, access prohibited + 024H (Reserved) – Reserved area, access prohibited + 028H Audio clock gate control register AUCGGC To control clock gate of Audio clock + 02CH ~ + FFFH




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Description format of register Following format is used for description of register’s each bit in "6.4.2 Audio Clock Generator

(AUCLKG)" to "6.4.6 Audio clock gate control register (AUCGAM)".


Name R/W


Name R/W

Initial value










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6.4.2. PLL control register (AUCGPR) This register controls PLL.

Address FFF5_3800H + 00H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name PSBPS – PLSRC[1:0] XCKMODE[2:0] PLLRDY *1 LUWMODE[1:0] PLLMODE[4:0] R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 X 0 0 0 1 0 0 1 1 0 1 1 1 1 1 *1: PLLBYPASS

Bit field



15 PSBPS Input clock divider bypass This bit bypasses the input clock divider.

0 Input clock divider enable (initial value) 1 Input clock divider disable

14 – Unused bits. Write access is ignored, and read value of these bits is undefined.

13-12 PLSRC[1:0] PLL clock source These bits select clock source for Audio PLL

00 UCK48 (initial value) 01 External pin I2S0ECK 10 External pin I2S1ECK 11 Setting prohibited

Note: Clock source frequency should be less than or equal to 48 MHz.

11-9 XCKMODE[2:0] Input Clock dividing ratio Define the PLL input clock dividing ratio, K

K = 8 + XCKMODE[2:0] PLL output clock frequency fCCLK = ( fCLK × N/K ) fCLK : Input clock frequency K : 8 + XCKMODE[2:0] N : 48 + PLLMODE[4:0] Note: Maximum PLL output clock frequency (fCCLK) is 300MHz

8 PLLRDY PLL READY monitoring This bit monitors internal signal, PLLREADY with external pin CLK clock. The PLLREADY signal shows overflow of the value selected at LUWMODE[1:0] bit by the timer which calculates PLL oscillation stabilization waiting time.

0 PLLREADY signal is "low" (initial value) 1 PLLREADY signal is "high"

Write access to this bit is ignored. Note: PLLRDY=1 does not guarantee that PLL is locked and clock supply is ready.



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No. Name 7 PLLBYPASS PLL bypass mode

This bit bypasses PLL.

0 PLL clock is used. 1 PLL is bypassed

Note: Do not change PLLBYPASS bit and PLLMODE[4:0] at the same time since clock switch

of both external pin CLK and PLL clocks needs to be changed. If they are changed at the same time, AUCLKG detects PLL oscillation frequency change and state becomes PLL oscillation stabilization waiting before PLL bypass mode.

6-5 LUWMODE[1:0] PLL lockup waiting mode These bits are used to set PLL oscillation stabilization wait time.

00 TCLK × (2n0 - 2m + 1) 01 TCLK × (2n1 - 2m + 1) 10 TCLK × (2n2 - 2m + 1) (initial value) 11 TCLK × (2n3 - 2m + 1)

TCLK: Cycle time of external input CLK selected by PLSRC[1:0] n0 = 8 n1 = 12 n2 = 13 n3 = 14 m = 7

Note : The PLL lockup wait time must be set to exceed 100µS.

4-0 PLLMODE[4:0] PLL feedback clock dividing ratio, N These bits are used to set PLL feedback clock dividing ratio.

N = 48 + PLLMODE[4:0] PLL output clock frequency fCCLK = ( fCLK × N/K ) fCLK : Input clock frequency K : 8 + XCKMODE[2:0] N : 48 + PLLMODE[4:0] Note: 1. Do not change PLLMODE[4:0] when PLLBYPASS bit is 0. PLLMODE[4:0]=1Fh stops

the PLL. 2. Maximum PLL output clock frequency (fCCLK) is 300MHz

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6.4.3. Wait time reset register (AUCGWR) This register controls watchdog timer.




Name – – – – – – – – – – – TBR – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W1 R/W R/W R/W R/W

Initial value X X X X X X X X X X X 0 X X X X

Bit field

Description No. Name 31-5 – Unused bits.

Write access is ignored, and read value of these bits is undefined. 4 TBR Wait timer reset request

This bit resets the wait time timer, and its reset signal is asserted during 1 cycle of APB clock.

0 Wait Time timer is not reset (initial value) 1 Reset the Wait time timer





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6.4.4. Clock divider control register A (AUCGDA) This register controls clock divider.




Name I2S1DM[7:0] I2S0DM[7:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 15-8 I2S1DM[7:0] Clock dividing mode for I2S_1 clock

These bits set frequency dividing ratio of I2S1CK. I2S1DM[7]=0 fI2S1CK = CCLK / (I2S1DM[6:0] + 1) I2S1DM[7]=1 fI2S1CK = I2S1ECK / (I2S1DM[6:0] + 1)

7-0 I2S0DM[7:0] Clock dividing mode for I2S_0 clock These bits set frequency dividing ratio of I2S0CK. I2S0DM[7]=0 fI2S0CK = CCLK / (I2S0DM[6:0] + 1) I2S0DM[7]=1 fI2S0CK = I2S0ECK / (I2S0DM[6:0] + 1)



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6.4.5. Clock divider control register B (AUCGDB) This register controls clock divider.




Name – – – – – – – – DACDM[7:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W0 R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X X X 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 7-0 DACDM[7:0] Clock dividing mode for DAC oversampling clock

These bits set frequency dividing ratio of DACCLK. fDACCLK = CCLK / (DACDM[6:0] + 1) Note : DACDM[7] must be “0”



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6.4.6. Audio clock gate control register (AUCGGC) This register controls clock gating of audio clock.




Name – – – – – – – – – – – – – DACGATE

I2S1GATE

I2S0GATE

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial value X X X X X X X X X X X X X 1 1 1

Bit field


The write access is ignored, and read value of these bits is undefined. 3 DACGATE DACCLK clock gating control

These bits control DACCLK clock gate.

0 DACCLK stops 1 DACCLK does not stop (initial value)

1 I2S1GATE I2S_1 ECLK clock gating control These bits control I2S1ECLK clock gating.

0 I2S1ECLK stops 1 I2S1ECLK does not stop (initial value)

0 I2S0GATE I2S_0 ECLK clock gating control These bits control I2S0ECLK clock gating.

0 I2S0ECLK stops 1 I2S0ECLK does not stop (initial value)



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6.5. Operation This section descries AUCLKG operation.

6.5.1. Clock generation Figure 6-2 shows clock generation chart.

1

0

PSBPS

XCKMODE[2:0] PLLMODE[4:0]

PLLBYPASS

I2S1 clock

1/L1 Gate

DACDM[6:0]

1/L3 Gate

DACCLK

I2S1CK

I2S1GATE | STOPI2S1DM[6:0]

1/L2 Gate

I2S0DM[6:0]

I2S0CK

DACGATE | STOP

I2S0GATE | STOP

Audio DAC clock

I2S0 clock

K = 8 ~ 15 N = 48 ~ 78 L1-3 = 1 ~ 128

CCLK (Maximum 300MHz)

1

0

I2S0DM[7]

I2S1DM[7]

1

0

I2S0ECK

I2S1ECK

PLL CKFB

1/N

1

01/K

10

00 01 I2S0ECK

UCK48

I2S1ECK

PLSRC[1:0]

Figure 6-2 Clock generation chart



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PLL control Oscillation stabilization waiting

The clock transmission source in oscillation stabilization waiting is count value of the time based timer. Clear operation of time based timer affects on its count value. When this module state is changed to PLL oscillation stabilization waiting state as shown below, the time based timer is cleared.

(1) External reset is asserted ("M" in Figure 6-3 and "m" of LUWMODE in the 6.4.2 PLL control register (AUCGPR))

PLL oscillation

stabilization waiting

ERSTn PLL reset CLK 1/M PLL clock CCLK HRESETn PLLREADY PLLBYPASS

6 CLK cycles

a) External reset deasserted (XRST) b) ERSTn reset (CRG internal signal) c) PLL reset deasserted d) PLL ready e) HRESETn deasserted

a) b) c) d) e)

XRST

(m2 + 2) CLKcycles 21 or more CCLK cycles

Figure 6-3 PLL oscillation stabilization waiting state after external is reset

(2) PLL oscillation frequency is changed by PLL mode ("M" in Figure 6-4 and "m" of LUWMODE in the 6.4.2 PLL control register (AUCGPR))

XRST PLL reset CLK 1/M PLL clock CCLK PLLREADY PLLBYPASS PLLMODE[4:0]


a) Clock source change (write PLLBYPASS bit) b) Set the PLL oscillation mode (write PLLMODE bits) c) PLL reset de-asserted d) PLL ready (PLLREADY can be monitored by PLLRDY bit) e) Clock source change (write PLLBYPASS bit)

c) d) e) b)

a)

(m2 + 2) CLK cycles

Figure 6-4 PLL oscillation stabilization waiting state by PLL mode change



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6-13


Frequency change Oscillation frequency and frequency dividing ratio (M) of PLL (fCLK × N) are set by PLLMODE[4:0] bit of the PLL control register (AUCGPR), and the frequency is able to be changed during the operation. Do not change PLLMODE[4:0] and XCKMODE[2:0] when PLLBYPASS bit of the PLL control register (AUCGPR) is 0. The frequency of main clock (CCLK) should be set between 250 MHz to 330 MHz, otherwise proper operation is not guaranteed.

PLLBYPASS Main clock (CCLK) of this module is able to be switched dynamically between PLL clock and external input clock (CLK) by PLLBYPASS bit of the PLL control register (AUCGPR).

CLK 1/M PLL clock CCLK PLLREADY PLLBYPASS

a) a) Clock source change (write PLLBYPASS bit (write 0)) b) Clock source change (write PLLBYPASS bit (write 1))

b)

Clock switching Clock switching

Figure 6-5 Clock switch between PLL clock and external clock

Stop mode Before operating state changed to the stop mode, "1" should be written to PLLBYPASS bit of the PLL control register (AUCGPR), UCK48 is selected as external clock source (PLSRC[1:0] = 00B) and main clock (CCLK) should be used for all divided clocks (I2S0ECLK/ I2S1ECLK/ DACCLK) by setting DACDM[7:0] = 00H, I2S0DM[7:0] = 00H, I2S1DM[7:0] = 00H.

Audio Clock Generator (AUCLKG) FUJITSU SEMICONDUCTOR PROPRIETARY AND CONFIDENTIAL

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7. Remap boot controller (RBC) This chapter describes function and operation of remap boot controller (RBC.)

7.1. Outline RBC is APB slave module. It provides system boot operation control and controls remap sequence of the system, the VINITHI signal and INITRAM signal of ARM946E-STM. The VINITHI signal and INITRAM signal enable exception vector address change and ITCM reboot after power-on reset, respectively.

7.2. Feature RBC has following features:

• Remap control register • INITRAM signal control register • VINITHI signal control register

7.3. Block diagram Figure 6-1 shows RBC block diagram.

RBC

Remap control register

APB signals

REMAP

INITRAMcontrol register

INITRAM

VINITHIcontrol register

VINITHI (fixed “L”)

VINITHI

CRSTn(from CRG)

HRESETn(from CRG) (to BusMatrix)

(to ARM946E-S core)

(to ARM946E-S core)

Figure 7-1 RBC block diagram



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7.4. Supply clock APB clock is supplied to RBC. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.

7.5. Register This section describes RBC register.

7.5.1. Register list RBC is controlled by the register shown in Table 6-2.

Table 7-1 RBC register list Address

Register name Abbreviation Description Base Offset

FFFE_6000H + 00H (Reserved) – Reserved area (access prohibited) + 04H Remap control register RBREMAP Remap state control + 08H VINITHI control register A RBVIHA VINITHI output signal control + 0CH INITRAM control register A RBITRA INITRAM output signal control

+ 10H – + FFFH

(Reserved) – Reserved area (access prohibited)



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Description format of register Following format is used for description of register’s each bit in "7.5.2 Remap control register (RBREMAP)" to "7.5.4 INITRAM control register A (RBITRA)".


Name R/W


Name R/W

Initial value










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7.5.2. Remap control register (RBREMAP) Remap control register (RBREMAP) controls remap state. Once remap is carried out, its state kept until reset. Write operation to this register is valid only the first time after reset, and its second time or later is ignored. This register is reset by HRESETn input. This register should be accessed in word unit.

Address GPR0: FFFE_6000H + 04H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name (Reserved) REMAP

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field

Description No. Name 31-1 (Reserved) Reserved bit.

0 REMAP Remap state is controlled. When write operation to remap register is performed (both "0" and "1" of write data are available) REMAP output signal becomes high. BusMatrix is designed to remap memory map with REMAP output signal. REMAP = Low: Vector area is allocated to internal boot ROM REMAP = High: Vector area is allocated to internal SRAM_0



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7.5.3. VINITHI control register A (RBVIHA) VINITHI control register A (RBVIHA) controls VINITHI output signal. This register is reset by the CRSTn input, and its initial value is “0”. This register should be accessed in word unit.

Address GPR0: FFFE_6000H + 08H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) R/W R R R R R R R R R R R R R R R R


Name (Reserved) VIHAR/W R R R R R R R R R R R R R R R R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-1 (Reserved) Reserved bits.

Write access is ignored. Reading these bits enable reading the value set by VINITHI.

0 VIHA VINTHI output signal is controlled. The initial value of this bit is “0”.



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7.5.4. INITRAM control register A (RBITRA) INITRAM control register A (RBITRA) controls INITRAM output signal. This register is reset by the CRSTn input. It should be accessed in word unit.

Address GPR0: FFFE_6000H + 0CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name (Reserved) R/W R R R R R R R R R R R R R R R R


Name (Reserved) ITRAR/W R R R R R R R R R R R R R R R R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Write access is ignored. Read value of these bits is always "0". 0 ITRA INTRAM output signal is controlled.



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7.6. Operation This section describes RBC operation.

7.6.1. RBC reset RBC has two reset input ports. RBREMAP register is reset by HRESETn input, and RBVIHA and RBITRA registers are reset by CRSTn value. Table 7-3 shows correlation between these reset and register.

Table 6-2 Correlation between reset and register Reset input Register Description

HRESETn RBREMAP This port is reset by HRESETn. CRSTn RBVIHA This port is reset by CRSTn input. The initial value of VINITHI

output is “0” RBITRA This port is reset by CRSTn input.

7.6.2. Remap control Remap changes vector area (00000000H～00008000H) after power-on. Vector area is allocated to built-in boot ROM at power-on and the system starts up from it. With the remap control, the allocated area is changed to built-in SRAM_0; then vector table is able to be overwritten.

7.6.3. VINITHI control ARM946E-S has VINITHI signal which determines exception vector address. When it is low at reset, the exception vector is located in 00000000H. On the other hand, when the signal is high at reset, the exception vector is located in FFFF0000H. Refer to "Technical reference manual" of individual ARM9 provided by ARM Ltd. for detail of VINITHI signal. The initial value of RBVIHA register is “0”.



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7-8




7.6.4. INITRAM control ARM946E-S has INITRAM signal. When it is high at reset, instruction TCM automatically becomes valid which enables reboot operation from ITCM. Refer to "Technical reference manual" of individual ARM9 core provided by ARM Ltd. for detail of VINITHI signal. RBITRA register is initialized to "0" by CRSTn, however it is not reset by HRESETn. This means, reboot operation from ITCM is able to be proceeded at software reset when exception vector table is copied to ITCM before software reset

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8. Interrupt controller (IRC) This chapter describes function and operation of interrupt controller (IRC.)

8.1. Outline This LSI equipped with two IRC, IRC0 and IRC1 respectively, to determine up to 64 interrupt request. The interrupt request of highest priority will be sent to ARM as an IRQ.

Note: The IRQ interrupt determined by IRC1 is accepted as IRQ6 interrupt factor of IRC0. Therefore, priority of all IRQ sources allocated to IRC1 is determined according to IRC1 and IRC0’s IRQ6 settings.

The IRQ vector defined in ARM946ES is "0×18", but the vector table factor is extended to 32 by IRC. When IRQ interrupt is asserted to the ARM core, interrupt vector table address corresponding to the IRQ interrupt factor is generated and displayed during the register. IRQ interrupt handler must refer to the vector table extended further than "0×18". IRC, connected to APB bus has delay interrupt control circuit and interrupt wake-up circuit from stop/standby mode which is composed of clock control circuit.

8.2. Feature IRC has following features:

• 2 channels of IRC to correspond up to 32 factors of interrupt request • Determination of IRQ interrupt priority to transfer to ARM946ES • Enable/Mask of extension IRQ interrupt • Extension IRQ vector address display • Supply of returning signal from stop mode to CRG (clock/reset generator) • Capability of issuing software interrupt (IRC0_IRQ30/IRC0_FIQ) by register access


Interrupt controller (IRC)

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8.3. Supply clock APB clock is supplied to IRC. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.

8.4. Interrupt map This section describes interrupt map.

8.4.1. Exception vector to ARM946E-S core Table 8-1 shows exception vector defined in the ARM946E-S core. Each interrupt factor input to IRC is notified as final interrupt of either IRQ (0000_0018H/ FFFF_0018H) or FIQ (0000_001CH/ FFFF_001CH) to the core.

Table 8-1 Exception vector defined by ARM946E-S

Exception factor Mode Vector address At low vector/high vector

Reset SVC 0000_0000H/FFFF_0000H Undefined instruction UND 0000_0004H/FFFF_0004H Software interrupt SVC 0000_0008H/FFFF_0008H Prefetch abort (memory fault at instruction fetch)

Abort 0000_000CH/FFFF_000CH

Data abort (memory fault at data access)

Abort 0000_0010H/FFFF_0010H

Reserved – 0000_0014H/FFFF_0014H IRQ (normal) interrupt IRQ 0000_0018H/FFFF_0018H FIQ (high speed) interrupt FIQ 0000_001CH/FFFF_001CH



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8.4.2. Extension IRQ interrupt vector of IRC0/IRC1 Table 8-2 shows IRQ interrupt vector extended by IRC0/IRC1. Base address of the extension vector table is determined with IRC's TBR register.

Table 8-2 Extension IRQ interrupt vector of IRC0/1

Exception factor

Interrupt ControlRegister

(level setting)CorrectionValue

IRC0 IRQ00 Unused ICR00 20HIRQ01 Unused ICR01 24HIRQ02 Unused ICR02 28HIRQ03 Unused ICR03 2CHIRQ04 Unused ICR04 30HIRQ05 Unused ICR05 34HIRQ06 IRC1 interrupt ICR06 38HIRQ07 NF rdy interrupt ICR07 3CHIRQ08 ADC ICR08 40HIRQ09 MEMC ECC ICR09 44HIRQ10 External Interrupt 0 ICR10 48HIRQ11 External Interrupt 1 ICR11 4CHIRQ12 External Interrupt 2 ICR12 50HIRQ13 External Interrupt 3 ICR13 54HIRQ14 Timer0 ch0,ch1 ICR14 58HIRQ15 Timer1 ch0,ch1 ICR15 5CHIRQ16 DMAC ch0 ICR16 60HIRQ17 DMAC ch1 ICR17 64HIRQ18 DMAC ch2 ICR18 68HIRQ19 DMAC ch3 ICR19 6CHIRQ20 DMAC ch4 ICR20 70HIRQ21 DMAC ch5 ICR21 74HIRQ22 DMAC ch6 ICR22 78HIRQ23 DMAC ch7 ICR23 7CHIRQ24 UART/SIO ch0 ICR24 80HIRQ25 UART/SIO ch1 ICR25 84HIRQ26 Unused ICR26 88HIRQ27 Unused ICR27 8CHIRQ28 ARM946 COMMRX ICR28 90HIRQ29 ARM946 COMMTX ICR29 94HIRQ30 Delay Interrupt 0 ICR30 98HIRQ31 Unused ICR31 9CH

IRC1 IRQ00 Input Capture 0 ICR00 20HIRQ01 Input Capture 1 ICR01 24HIRQ02 Input capture free-run timer ICR02 28HIRQ03 CAN ICR03 2CHIRQ04 SDMC I/F ICR04 30HIRQ05 RTC ICR05 34HIRQ06 I2S ch0 ICR06 38HIRQ07 I2S ch1 ICR07 3CHIRQ08 Audio DAC ICR08 40HIRQ09 SPI 0 ICR09 44HIRQ10 SPI 1 ICR10 48HIRQ11 I2C ch0 ICR11 4CHIRQ12 I2C ch1 ICR12 50HIRQ13 PWM ch0 ICR13 54HIRQ14 PWM ch1 ICR14 58HIRQ15 UART/SIO ch2 ICR15 5CHIRQ16 UART/SIO ch3 ICR16 60HIRQ17 UART/SIO ch4 ICR17 64HIRQ18 Unused ICR18 68HIRQ19 Unused ICR19 6CHIRQ20 USB 2.0 EHCI Host ICR20 70HIRQ21 USB 2.0 OHCI Host ICR21 74HIRQ22 Unused ICR22 78HIRQ23 USB 2.0 dmac ICR23 7CHIRQ24 External Interrupt 4 ICR24 80HIRQ25 External Interrupt 5 ICR25 84HIRQ26 External Interrupt 6 ICR26 88HIRQ27 External Interrupt 7 ICR27 8CHIRQ28 External Interrupt 8 ICR28 90HIRQ29 External Interrupt 9 ICR29 94HIRQ30 External Interrupt 10 ICR30 98HIRQ31 External Interrupt 11 ICR31 9CH



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8.5. Register This section describes IRC register.

8.5.1. Register list Table 8-3 shows IRC0 register list and Table 8-4 shows IRC1 register list.



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Table 8-3 IRC0 register list Address


FFFF_FE00H or

FFFE_8000H

+ 00H IRQ flag register IR0IRQF IRQ interrupt flag control + 04H IRQ mask register IR0IRQM IRQ interrupt asserted mask control + 08H Interrupt level mask

register IR0ILM Valid interrupt level setting from ARM core

+ 0CH ICR monitoring register IR0ICRMN Current IRQ interrupt source’s interrupt level display + 10H (Reserved) – Reserved (access prohibited) + 14H Delay interrupt register 0 IR0DICR0 Delay interrupt control for task switch + 18H Delay interrupt register 1 IR0DICR1 Delay interrupt control

+ 1CH Table base register IR0TBR High order address (24 bit) setting of IRQ vector + 20H Interrupt vector register IR0VCT Interrupt vector table display + 24H (Reserved) – Reserved (access prohibited) + 28H (Reserved) – Reserved (access prohibited) + 2CH (Reserved) – Reserved (access prohibited) + 30H Interrupt control register 0 IR0ICR00 IRQ0 interrupt level setting (unused and access prohibited) + 34H Interrupt control register 1 IR0ICR01 IRQ1 interrupt level setting (unused and access prohibited) + 38H Interrupt control register 2 IR0ICR02 IRQ2 interrupt level setting (unused and access prohibited) + 3CH Interrupt control register 3 IR0ICR03 IRQ3 interrupt level setting (unused and access prohibited) + 40H Interrupt control register 4 IR0ICR04 IRQ4 interrupt level setting (unused and access prohibited) + 44H Interrupt control register 5 IR0ICR05 IRQ5 interrupt level setting (unused and access prohibited) + 48H Interrupt control register 6 IR0ICR06 IRQ6 interrupt level setting (IRC1 interrupt) + 4CH Interrupt control register 7 IR0ICR07 IRQ7 interrupt level setting (NF ready interrupt) + 50H Interrupt control register 8 IR0ICR08 IRQ8 interrupt level setting (ADC interrupt) + 54H Interrupt control register 9 IR0ICR09 IRQ9 interrupt level setting (MEMC ECC interrupt) + 58H Interrupt control register 10 IR0ICR10 IRQ10 interrupt level setting (external interrupt 0) + 5CH Interrupt control register 11 IR0ICR11 IRQ11 interrupt level setting (external interrupt 1) + 60H Interrupt control register 12 IR0ICR12 IRQ12 interrupt level setting (external interrupt 2) + 64H Interrupt control register 13 IR0ICR13 IRQ13 interrupt level setting (external interrupt 3) + 68H Interrupt control register 14 IR0ICR14 IRQ14 interrupt level setting (timer ch0 interrupt) + 6CH Interrupt control register 15 IR0ICR15 IRQ15 interrupt level setting (timer ch1 interrupt) + 70H Interrupt control register 16 IR0ICR16 IRQ16 interrupt level setting (DMAC ch0 interrupt) + 74H Interrupt control register 17 IR0ICR17 IRQ17 interrupt level setting (DMAC ch1 interrupt) + 78H Interrupt control register 18 IR0ICR18 IRQ18 interrupt level setting (DMAC ch2 interrupt) + 7CH Interrupt control register 19 IR0ICR19 IRQ19 interrupt level setting (DMAC ch3 interrupt) + 80H Interrupt control register 20 IR0ICR20 IRQ20 interrupt level setting (DMAC ch4 interrupt) + 84H Interrupt control register 21 IR0ICR21 IRQ21 interrupt level setting (DMAC ch5 interrupt) + 88H Interrupt control register 22 IR0ICR22 IRQ22 interrupt level setting (DMAC ch6 interrupt) + 8CH Interrupt control register 23 IR0ICR23 IRQ23 interrupt level setting (DMAC ch7 interrupt) + 90H Interrupt control register 24 IR0ICR24 IRQ24 interrupt level setting (UART/SIO ch0 interrupt) + 94H Interrupt control register 25 IR0ICR25 IRQ25 interrupt level setting (UART/SIO ch1 interrupt) + 98H Interrupt control register 26 IR0ICR26 IRQ26 interrupt level setting (unused and access prohibited) + 9CH Interrupt control register 27 IR0ICR27 IRQ27 interrupt level setting (unused and access prohibited) + A0H Interrupt control register 28 IR0ICR28 IRQ28 interrupt level setting (COMMRX interrupt) + A4H Interrupt control register 29 IR0ICR29 IRQ29 interrupt level setting (COMMTX interrupt) + A8H Interrupt control register 30 IR0ICR30 IRQ30 interrupt level setting (delay interrupt) + ACH Interrupt control register 31 IR0ICR31 IRQ31 interrupt level setting (unused and access prohibited)



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Table 8-4 IRC1 register list Address


FFFF_FF00 H or

FFFE_5000H

+ 00H IRQ flag register IR1IRQF IRQ interrupt flag control + 04H IRQ mask register IR1IRQM IRQ interrupt asserted mask control + 08H Interrupt level mask register IR1ILM Valid interrupt level setting from ARM core + 0CH ICR monitoring register IR1ICRMN Current IRQ interrupt source’s interrupt level display + 10H (Reserved) – Reserved (access prohibited) + 14H (Reserved) – Reserved (access prohibited) + 18H (Reserved) – Reserved (access prohibited)

+ 1CH Table base register IR1TBR IRQ vector’s high order address (24 bit) setting + 20H Interrupt vector register IR1VCT Interrupt vector table display。 + 24H (Reserved) – Reserved (access prohibited) + 28H (Reserved) – Reserved (access prohibited) + 2CH (Reserved) – Reserved (access prohibited) + 30H Interrupt control register 0 IR1ICR00 IRQ0 interrupt level setting (INCP, ch0 interrupt) + 34H Interrupt control register 1 IR1ICR01 IRQ1 interrupt level setting (INCP, ch1 interrupt)

+ 38H Interrupt control register 2 IR1ICR02 IRQ2 interrupt level setting (INCP free run timer interrupt) + 3CH Interrupt control register 3 IR1ICR03 IRQ3 interrupt level setting (CAN interrupt) + 40H Interrupt control register 4 IR1ICR04 IRQ4 interrupt level setting (SD I/F interrupt) + 44H Interrupt control register 5 IR1ICR05 IRQ5 interrupt level setting (RTC interrupt) + 48H Interrupt control register IR1ICR06 IRQ6 interrupt level setting (I2S ch0 interrupt) + 4CH Interrupt control register 7 IR1ICR07 IRQ7 interrupt level setting (I2S ch1 interrupt) + 50H Interrupt control register 8 IR1ICR08 IRQ8 interrupt level setting (Audio DAC interrupt) + 54H Interrupt control register 9 IR1ICR09 IRQ9 interrupt level setting (SPI 0 interrupt) + 58H Interrupt control register 10 IR1ICR10 IRQ10 interrupt level setting (SPI 1 interrupt) + 5CH Interrupt control register 11 IR1ICR11 IRQ11 interrupt level setting (I2C ch0 interrupt) + 60H Interrupt control register 12 IR1ICR12 IRQ12 interrupt level setting (I2C ch1 interrupt) + 64H Interrupt control register 13 IR1ICR13 IRQ13 interrupt level setting (PWM ch0 interrupt) + 68H Interrupt control register 14 IR1ICR14 IRQ14 interrupt level setting (PWM ch1 interrupt) + 6CH Interrupt control register 15 IR1ICR15 IRQ15 interrupt level setting (UART/SIO ch2 interrupt) + 70H Interrupt control register 16 IR1ICR16 IRQ16 interrupt level setting (UART/SIO ch3 interrupt) + 74H Interrupt control register 17 IR1ICR17 IRQ17 interrupt level setting (UART/SIO ch4 interrupt) + 78H Interrupt control register 18 IR1ICR18 IRQ18 interrupt level setting (Unused and access prohibited) + 7CH Interrupt control register 19 IR1ICR19 IRQ19 interrupt level setting (Unused and access prohibited) + 80H Interrupt control register 20 IR1ICR20 IRQ20 interrupt level setting (USB 2.0 EHCI Host interrupt) + 84H Interrupt control register 21 IR1ICR21 IRQ21 interrupt level setting (USB 1.1 OHCI Host interrupt) + 88H Interrupt control register 22 IR1ICR22 IRQ22 interrupt level setting (Unused and access prohibited) + 8CH Interrupt control register 23 IR1ICR23 IRQ23 interrupt level setting (USB 2.0 DMAC interrupt) + 90H Interrupt control register 24 IR1ICR24 IRQ24 interrupt level setting (External interrupt 4) + 94H Interrupt control register 25 IR1ICR25 IRQ25 interrupt level setting (External interrupt 5) + 98H Interrupt control register 26 IR1ICR26 IRQ26 interrupt level setting (External interrupt 6) + 9CH Interrupt control register 27 IR1ICR27 IRQ27 interrupt level setting (External interrupt 7) + A0H Interrupt control register 28 IR1ICR28 IRQ28 interrupt level setting (External interrupt 8) + A4H Interrupt control register 29 IR1ICR29 IRQ29 interrupt level setting (External interrupt 9) + A8H Interrupt control register 30 IR1ICR30 IRQ30 interrupt level setting (External interrupt 10) + ACH Interrupt control register 31 IR1ICR31 IRQ31 interrupt level setting (External interrupt 11)

`



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Description format of register Following format is used for description of register’s each bit in "8.5.2 IRQ flag register (IR0IRQF/ IR1IRQF)" to "8.5.10 Interrupt control register (IR0ICR31/IR1ICR31 – IR0ICR00/IR1ICR00)".


Name R/W


Name R/W

Initial value










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8.5.2. IRQ flag register (IR0IRQF/ IR1IRQF) IR0IRQF/IR1IRQF registers control IRQ interrupt flag. When interrupt level is higher than the one set in IR0ILM/IR1ILM registers as a result of determining IRQ interrupt source level, IRQF bit is set and IRQ interrupt is asserted to ARM core. The interruption to ARM core is negated with "0" writing to the IR0IRQF/IR1IRQF registers. When IRQF bit is set, interrupt vector is displayed to IR0VCT/IR1VCT registers but its address value is not changed until IRQF bit is set.

Address IRC0: FFFF_FE00H or FFFE_8000H + 00H

IRC1: FFFF_FF00 H or FFFE_5000H + 00H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name – – – – – – – – – – – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name – – – – – – – – – – – – – – – IRQFR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X X X X X X X X X X 0


No. Name 31-1 – Unused bit.

The write access is ignored. The read value of these bits is undefined. 0 IRQF IRQ interrupt flag.

When interrupt level is higher than the one set in IR0ILM/IR1ILM registers (interrupt level in IR0ICR/IR1ICR registers > interrupt level in IR0ILM/IR1ILM registers), IRQF bit is set to "1"and IRQX (interrupt request) is asserted to ARM core.

0 IRQ is not asserted. 1 IRQ is asserted.

This bit is cleared by writing "0", and writing "1" is invalid.



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8.5.3. IRQ mask register (IR0IRQM/IR1IRQM) IR0IRQM/IR1IRQM registers control masking asserted IRQ interrupt.


IRC1: FFFF_FF00H or FFFE_5000H + 04H



Name – – – – – – – – – – – – – – – IRQMR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W




The write access is ignored. The read value of these bits is undefined. 0 IRQM Asserted IRQ interrupt is masked.

0 Asserted IRQ is masked 1 Asserted IRQ is valid

This bit is initialized to "0" by reset.



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8.5.4. Interrupt level mask register (IR0ILM/IR1ILM) IR0ILM/IR1ILM registers set interrupt level enabled by the ARM core. When the IRQ interrupt source is larger than the setting value of this register, IRC notifies the ARM core of the IRQ interrupt.

"Interrupt level of IR0ICR/IR1ICR registers > Interrupt enable level of IR0ILM/IR1ILM registers" -> Generated IRQ interrupt





Name – – – – – – – – – – – – ILM3 ILM2 ILM1 ILM0R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X X X X X X X 1 1 1 1



The write access is ignored. The read value of these bits is undefined. 3-0 ILM3-0 These bits are used to set IRQ interrupt level ranging from max. 0000B to min. 1111B (IRQ

interrupt does not occur.) These bits are initialized to 1111B by reset.



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8.5.5. ICR monitoring register (IR0ICRMN/IR1ICRMN) IR0ICRMN/IR1ICRMN registers display interrupt level of the current IRQ interrupt source. If the IRQ interrupt requests from interrupt level in IR0ICRxx/IR1ICRxx are higher than the value of IR0ILM/IR1ILM register, the level of the highest-level interrupt request is displayed in these bits. When there is no interrupt request or the interrupt level in IR0ICRxx/IR1ICRxx is higher than the level set in IR0ILM/IR1ILM register, these bits indicate 1111B. These registers are updated with setting IRQF bit of IR0IRQF/IR1IRQF "1", and displayed interrupt level is not changed until IRQF bit is cleared. After it is cleared, interrupt level is set again and the display is updated with the source set the IRQF bit. Register value is not defined if the bit is not set to "1".

Address IRC0: FFFF_FE00H or FFFE_8000H + 0CH

IRC1: FFFF_FF00H or FFFE_5000H + 0CH



Name – – – – – – – – – – – – ICRMN3 ICRMN2 ICRMN1 ICRMN0R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X X X X X X X X X X X



The write access is ignored. The read value of these bits is undefined. 3-0 ILM3-0 When IRQ interrupt source is larger than the setting value of IR0ILM/IR1ILM registers, the

highest interrupt source level is displayed. The initial value of these bits is undefined.



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8.5.6. Delay interrupt control register 0 (IR0DICR0) IR0DICR0 register controls delay interrupt for the task switch. Writing to this register enables software to issue/cancel IRQ interrupt request. The delay interrupt is allocated into IRQ30 of IRC0.




Name – – – – – – – – – – – – – – – DLYI0R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W




The write access is ignored. The read value of these bits is undefined. 0 DLYI0 Delay interrupt is controlled.

It is cancelled by writing "0" to this bit.

0 Delay interrupt factor is cancelled and interrupt request does not occur. 1 Delay interrupt factor is generated and interrupt request occurs.

This bit is initialized to "0" by reset.



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8.5.7. Delay interrupt control register 1 (IR0DICR1) Writing to IR0DICR1 register enables software to issue/cancel FIQ interrupt request. The delay interrupt is allocated into FIQ of the ARM.




Name – – – – – – – – – – – – – – – DLYI1R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W




The write access is ignored. The read value of these bits is undefined. 0 DLYI1 Delay interrupt is controlled.

It is cancelled by writing "0" to this bit.

0 Delay interrupt factor is cancelled and interrupt request does not occur 1 Delay interrupt factor is generated and interrupt request occurs

This bit is initialized to "0" by reset. Note: FIQ is an individual interrupt to the ARM core and it is higher priority than normal IRQ. Once this bit is set, the FIQ will be served by ARM core without any masking. Setting the F bit in current program status register (CPSR) of ARM core under privileged mode can disable the FIQ request from IRC to ARM core even DLYI1 bit is set. Race condition is possible from re-enable interrupt after an interrupt exception. Special caution should be made in the interrupt service routine. Please refer to ARM9E-S Technical Reference Manual for more details.



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8.5.8. Table base register (IR0TBR/IR1TBR) IR0TBR/IR1TBR registers indicate upper address (24 bit) of IRQ vector. When IRC receives IRQ interrupt source, and IRQ is asserted to the ARM core, the address displayed in IR0VCT/IR1VCT registers are as follows.

(IR0TBR/IR1TBR setting value) + Individual IRQ interrupt source vector address

Address IRC0: FFFF_FE00H or FFFE_8000H + 1CH

IRC1: FFFF_FF00H or FFFE_5000H + 1CH

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name TBR31 TBR30 TBR29 TBR28 TBR27 TBR26 TBR25 TBR24 TBR23 TBR22 TBR21 TBR20 TBR19 TBR18 TBR17 TBR16R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name TBR15 TBR14 TBR13 TBR12 TBR11 TBR10 TBR9 TBR8 Zero Zero Zero Zero Zero Zero Zero Zero R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-8 TBR31-8 Set upper address (24 bit) of IRQ vector.

These bits are initialized to "0" by reset. 7-0 Zero "0" fixed bit.

Writing is invalid and "0" is always read in the read value. These bits are initialized to "0" by reset.



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8.5.9. Interrupt vector register (IR0VCT/IR1VCT) IR0VCT/IR1VCT registers display interrupt vector table to the interrupt source to be processed when IRQ is asserted to ARM core ("1" is set to IRQF bit of IR0IRQF/IR1IRQF registers.) The priority of vector address is as follows.

• The highest interrupt source vector level in the generated IRQ interrupt source has higher priority • When interrupt of same level and transmission source occurs at the same time, the one with less

address offset value is prioritized



Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name VCT31 VCT30 VCT29 VCT28 VCT27 VCT26 VCT25 VCT24 VCT23 VCT22 VCT21 VCT20 VCT19 VCT18 VCT17 VCT16R/W R R R R R R R R R R R R R R R R


Name VCT15 VCT14 VCT13 VCT12 VCT11 VCT10 VCT9 VCT8 VCT7 VCT6 VCT5 VCT4 VCT3 VCT2 VCT1 VCT0R/W R R R R R R R R R R R R R R R R



No. Name 31-0 VCT31-0 Interrupt vector table is displayed to the interrupt source to be processed.

The vector value is calculated by adding each interrupt vector’s offset value to the upper address value set by IR0TBR/IR1TBR register. Refer to "Table 8-2 Extension IRQ interrupt vector of IRC0/1" for correlation of interrupt source, interrupt level register, and vector address. The initial value of these bits is undefined.

After IRQF bit of IR0IRQF/IR1IRQF registers is set to "1", the displayed vector address value is not changed until the IRQF bit is cleared. When the bit is cleared, interrupt level is set again and the display is updated by the source that sets the IRQF bit. Register value is not defined if the bit is not set to "1". Firmware branches into the address specified by VCT register (branched to extension vector table) with the instruction in IRQ vector (0000_0018H). Then it branches into interrupt handler by the instruction on the address. If IRQF bit is cleared after the branch, asserting IRQ enables to observe whether new IRQ source is higher than the current one in the interrupt handler.



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8.5.10. Interrupt control register (IR0ICR31/IR1ICR31 – IR0ICR00/IR1ICR00)

IR0ICR31/IR1ICR31 – IR0ICR00/IR1ICR00 registers are supplied to each IRQ interrupt source, and are able to set interrupt level to the corresponding IRQ interrupt source. When IRQ interrupt source is smaller than the setting value of IR0ILM/IR1ILM registers (interrupt level of IR0ICRn/IR1ICRn registers <= interrupt level of IR0ILM/IR1ILM registers), it is masked.

Address

IRC0: FFFF_FE00H or FFFE_8000H + 30H | FFFF_FE00H or FFFE_8000H + ACH

IRC1: FFFF_FF00H or FFFE_5000H + 30H | FFFF_FF00H or FFFE_5000H + ACH



Name – – – – – – – – – – – – ICR3 ICR2 ICR1 ICR0R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W




The write access is ignored. The read value of these bits is undefined. 3-0 ICR3-0 These bits are used to set interrupt level value of each interrupt source in the range of max.

"0000B" to min. "1111B".

ICR3 ICR3 ICR1 ICR0 Interrupt level 0 0 0 0 Settable highest level 0 0 0 1 (highest) 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 (lowest) 1 1 1 1 Uninterruptible

These bits are initialized to "1111B" by reset.



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8.6. Operation This section describes IRC operation.

8.6.1. Outline Interrupt operation process is described with using IRQ24 interrupt as an example.

1. When IRQ interrupt is asserted to ARM core as a result of prioritization of IRQ24 interrupt source with interrupt controller, the ARM core refers instruction of vector address 0000_0018H.

2. Loading instruction, LDR PC, [PC, #_0×200] is written to vector table address 0000_0018H beforehand. Then extension interruption vector address of IRQ24 (VCT register value) is loaded into PC, and the ARM core refers IRQ24 vector address of extension interrupt vector table.

3. Branch instruction to the IRQ24 interrupt handler should be written to IRQ24 extension interrupt vector address. Then PC branches into the IRQ24 interrupt handler with the branch instruction. All interrupt handlers should be set within ±32MB of the extension interrupt vector table in order to use the branch instruction. If the handler is unable to be set in the range, use load instruction, LDR PC, [PC, #_0x200] instead.

LDR PC, [PC, #-0x200]

00000018H

IRQ24 interrupt handler

B IRQ24 handler

00000018H

FFFFE20H

IRQ vector

Reference

IR0VCT register

Extended interrupt vector table00000018H

Figure 8-1 IRQ24 interrupt process example

8.6.2. Initialization 1. Determine individual exception table after power-on. 2. Set extension interrupt vector table. 3. Store load instruction, LDR PC, [PC, #_0x200] to IRQ vector (00000018H) in the ARM core. 4. Set base address of the interrupt table to IR0TBR register. 5. Set interrupt level of each interrupt source to IR0ICR31 - 00 registers. 6. Set interrupt level that IRQ interrupt becomes valid to the IR0ILM register. 7. Set I flag of CPSRs register in the ARM core to "0" (to validate IRQ.) 8. Validate interrupt with IR0IRQM register in IRC.



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8.6.3. Multiple interrupt process Example of multiple interrupt process is shown below.

M a in rou tin e

IR Q re q u e s t 1 →

1 s t in te rru p t p ro ce s s (1 ) S a ve re g is te r va lu e to s ta ck (2 ) S a ve c u rre n t IR 0 IL M re g is te r va lu e a n d S P S R _ irq

( in th e co re ) re g is te r va lu e to s ta ck n o t to lo se th e m a t th e n e x t in te rru p t p ro ce ss

(3 ) S e t IR 0 IC R M N re g is te r va lu e to IR 0 IL M re g is te r, a n d va lid a te h ig h e r le ve l in te rru p t th a n th e firs t in te rru p t

(4 ) C le a r th e in te rru p t so u rc e cu rre n tly o ccu rre d (5 ) C le a r IR Q F fla g (th e n n IR Q is n e g a te d a n d

d e te rm in in g in te rru p t le ve l is re s ta rte d ) (6 ) C o n firm IR Q fla g is c le a re d (7 ) C le a r I b it to C P S R re g is te r o f th e A R M co re to b e

re a d y fo r in te rru p t re c e p tio n

IR Q re q u e s t 2 →

R e tu rn p ro ce ss o f 1s t in te rru p t p ro ce ssP ro ce e d th e s a m e re tu rn p ro c e ss a s th e 2 n d o n e

2 n d in te rru p t p ro ce ss P ro ce e d th e s a m e in te rru p t p ro ce ss a s th e 1 s t o n e

R e tu rn p ro ce ss o f 2 n d in te rru p t p ro c e ss (1 ) S e t I b it o f C P S R re g is te r a n d d isa b le

in te rru p t (2 ) R e s to re sa ve d S P S R _ irq va lu e to

S P S R _ irq re g is te r (3 ) R e s to re th e va lu e o n s ta ck to re g is te r (4 ) R e s to re P C va lu e to g o b a ck to th e

re g u la r ro u tin e , a n d re s to re th e re g is te r va lu e to C P S R a s w e ll

C P S R → S P S R _ irq

Figure 8-2 Example of multiple IRQ interrupt process

8.6.4. Example of IRQ interrupt handler

IRQ_Handler ROUT STMFD SP!, {R0-R12, R14} ;Save register value

MESSAGE "Enter Dummy IRQ Handler"

LDR R0, = IR0ILM

LDR R1, [R0]

MRS R2, SPSR

STMFD SP!, {R1, R2} ;IR0ILM and SPSR_irq register values are saved

LDR R2, = IR0ICRMN

LDR R1, [R2]

STR R1, [R0] ;IR0ICRMN register value is set to IR0ILM register



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Routine to clear interrupt factor MOV R1, #0

LDR R0, = IR0IRQF

STR R1, [R0]; ;Clear IRQF bit (bit 0) of IR0IRQF register

;Start the next interrupt level setting operation.

LOOP

LDR R1,[R0] ;Check IRQF flag clear

CMP R1,#0

BNE LOOP

;; Clear ARM IRQ Flag → Enable Interrupt

MRS R2, CPSR

BIC R2, R2, #I_Bit

MSR CPSR_c, R2; ;Clear I bit of CPSR register (included in the core) and validate IRQ interrupt (enable)

If the IRQ interrupt higher than the current IRQ source occurs, move to the corresponding interrupt handler.

Main routine for this interrupt factor MRS R2, CPSR

ORR R2, R2 #1_Bit

MSR CPSR_c, R2; ;Set I bit of CPSR register (included in the core) and invalidate IRQ interrupt (disable)

LDR R0, = IR0ILM

LDMFD SP!, {R1, R2}

MSR SPSR_cxsf, R2

STR R1, [R0]; ;Resume saved value in IR0ILM and SPSR_irq registers (included in the core)

LDMFD SP! {R0-R12, R14}; ;Resume register value

SUBS PC, R14, #4; ;CPSR < - SPSR_irq, PC < - R14 –4



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8-20




8.6.5. Resume from Stop and standby modes Resume from stop and standby modes is able to be instructed to CRG (Clock Reset Controller) with issuing IRQ interrupt from macro. The resume signal from stop and standby modes, asserted to ARM clock controller is generated by higher IRQ factor than the interrupt level set with IR0ILM register

8.6.6. Notice for using IRC Notice for using IRC is shown below.

Notice for IRQ clear timing As described in "8.5.2 IRQ flag register (IR0IRQF/ IR1IRQF)", "0" writing to IRQF bit of IR0IRQF/IR1IRQF registers negates IRQX (interrupt request) to the ARM core; however, IRQX is negated during 1 cycle of APB clock after writing "0". Therefore, the ARM core may wrongly goes into IRQ mode again by the IRQX before clear operation if the code (interrupt handler) which may validate ARM core interrupt again is written after "0" writing to the IRQF. This might occurs especially when ARM core’s clock frequency is faster than the IRC frequency. In order to prevent such problem, add dummy instruction which accesses to IRC interrupt register after clear instruction of IRQF. In this way, IRQX is cleared properly before interrupt of the ARM core becomes valid again.

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9. DMA controller (DMAC) This chapter describes function and operation of DMA controller.

9.1. Outline DMAC is 8 channel DMA controller.

9.2. Feature DMAC in the LSI has following features:

• Compliant with AMBA v2.0 • 8 DMA channels • DMA trigger

• External transfer request • 4ch of I2S transmission/reception DMA request

• Peripheral transfer request • 10ch of UART transmission/reception • 1ch of DAC transfer request • 2ch of SDIO transfer request

• Software request (start-up by register writing) • Beat transfer

16 word FIFO shared by all channels Corresponding to INCR, INCR 4/8/16, and WRAP 4/8/16.

• Transfer mode • Block transfer • Burst transfer • Demand transfer

• 4 bit block register and 16 bit count register are set by programming • Corresponding to 8, 16, and 32 bit transfer widths • Corresponding to increment and fixed addressing to source and destination • Reload count, source address, and destination address register • Issuing error interrupt and completion interrupt • Displaying end code of DMA transfer • Supporting source and destination protection • Corresponding to fixed priority and rotation priority by hardware.

In the fixed priority mode, channel 0 has the highest priority, and channel 7 has the lowest priority


DMA controller (DMAC)

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9.3. DMA requests signals Table 9-1 shows DMA request of each resources

Table 9-1 Individual block function Peripheral DMA request

IDREQ00 UART ch0 TX ready IDREQ01 UART ch0 RX ready IDREQ02 UART ch1 TX ready IDREQ03 UART ch1 RX ready IDREQ04 UART ch2 TX ready IDREQ05 UART ch2 RX ready IDREQ06 UART ch3 TX ready IDREQ07 UART ch3 RX ready IDREQ08 UART ch4 TX ready IDREQ09 UART ch4 RX ready IDREQ10 DAC FIFO status IDREQ11 SDMC WR request IDREQ12 SDMC RD request IDREQ13~IDREQ15 Unused

External DMA request DREQ0 I2S ch0 TX (TXDREQ0) DREQ1 I2S ch0 RX (RXDREQ0) DREQ2 I2S ch1 TX (TXDREQ1) DREQ3 I2S ch1 RX (RXDREQ1) DREQ4~DREQ7 Unused

9.4. Related pin This LSI has no external pin related to the DMAC.

9.5. Supply clock AHB clock is supplied to DMA controller. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.



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9.6. Register This section describes DMAC register.

9.6.1. Register list DMAC control related register is shown below.

Table 9-2 DMAC register list Module Address Register Function

DMAC common FFFD0000(h) DMACR DMAC configuration register FFFD0004(h)

FFFD000F(h) Reserved

DMAC ch0 FFFD0010(h) DMACA0 DMAC0 configuration A register FFFD0014(h) DMACB0 DMAC0 configuration B register FFFD0018(h) DMACSA0 DMAC0 source address register FFFD001C(h) DMACDA0 DMAC0 Destination address register










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Notice for register setting Note followings for DMAC register setting.

• DMACR, DMACA, DMACB, DMACSA, and DMACDA registers are accessible in byte, half-word, and word size.

• Do not set DMAC register address to DMACSA and DMACDA registers. • Do not change setting register's channel during DMA transfer except DE/DH bits of DMACR and

EB/PB bits of DMACA.

Description format of register Following format is used for description of register’s each bit in "9.6.2 DMA configuration register (DMACR)" to "9.6.6 DMAC destination address register (DMACDAx)".


Name R/W


Name R/W

Initial value










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9.6.2. DMA configuration register (DMACR) Address FFFD_0000 + 00(h)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name DE DS - PR DH[3:0] (Reserved) R/W R/W R R R/W R/W R/W R/W R/W R R R R R R R R



Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit field

Description No. Name 31 DE

(DMA Enable)

Transfer is controlled for all DMA channels.

0 All DMA channels are disabled and DMA transfer is not performed until "1" is set to this bit If the value is cleared to "0" during the transfer, DMA is stopped at transmission gap for the channel in transfer

1 DMA transfer starts according to the register setting of each channel [Transfer gap] The transfer gap is that DMAC de-asserts bus request (HBUSREQ) to the arbiter during DMA transfer (about 4 clocks) by DMAC. Its occurrence is different by transfer mode shown below.

• Block transfer: Transfer gap occurs at BC = 0 (after completing transfer in BC unit) • Burst transfer: There is no transfer gap. • Demand transfer: Transfer gap occurs at TC = TC - 1 (after completing 1 DMA transfer), or at

transfer request negotiation This bit can be used to reset all channels of Configuration register at a time during DMA transfer.

30 DS (DMA Stop)

This shows all channels of DMA transfer is stop.

0 Release of disable/halt setting 1 DMA transfer stop of all channels by disable/halt setting

This bit is set to "1" during DMA transfer by either of following operations:

• DMACR.DE bit is cleared to "0" (all channels are disabled) • Value other than 4'h0 is set to DMACR.DH bit (all channels are halt)

When the state of disable/halt is cleared, DMAC clears DS bit to "0". This bit is able to use for confirmation of transfer stop when DMAC stops transfer of all channels by disable/halt setting.

29 (Reserved) Reserved bits. Write access is ignoRead value of this bit is always "0".

red.

28 PR (Priority Rotation)

Prioritization procedure of DMA channel is controlled.

0 "Fixed" Priority order: Ch0 > Ch1 > Ch2 > Ch3 > Ch4 > Ch5 > Ch6 > Ch7

1 "Rotation" Priority order is rotated

gap. Channel switch occurs by the timing of transfer

Refer to DE bit description for the transfer gap.



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No. Name 27-24

DH[3:0] (DMA Halt)

All channels of DMA stop are controlled. When the value other than 4'b0000 is set to this bit, all DMA channels stop and DMA is not transferred until 4'b0000 is set. If the value other than 4'b0000 is set during DMA transfer, it is stopped at transfer gap. Refer to DE bit description for the transfer gap. These bits are used to stop DMA transfer without resetting each configuration register of all channels.

0000 Stop release Other than 0000 Stop of all channels

23-0 (Reserved) Reserved bits.

Write access is ignored. Read value of this bit is always "0".

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9.6.3. DMA configuration A register (DMACAx)

Address ch0：FFFD_0000+10 (h) ch1：FFFD_0000+20 (h) ch2：FFFD_0000+30 (h) ch3：FFFD_0000+40 (h)ch4：FFFD_0000+50 (h) ch5：FFFD_0000+60 (h) ch6：FFFD_0000+70 (h) ch7：FFFD_0000+80 (h)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name EB PB ST IS[4:0] BT[3:0] BC[3:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name TC[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31 EB

(Enable Bit) This bit is used to control DMA channel transfer. When "1" is set to this bit, channel waits for the trigger to start DMA transfer (DMACR/DE bits should be set to "1" beforehand.) DMAC sets "0" to this bit after DMA transfer, then this channel is disabled and DMA transfer is not performed until "1" is set to this bit. If "0" is set to this bit during DMA transfer, DMA stops at transfer gap which is regarded as forcible termination. Refer to DMACR/DE bits description for transfer gap. This bit is able to use for resetting each configuration register of the channel during DMA transfer.

0 This channel is disabled (initial value) 1 This channel is enabled

30 PB (Pause Bit)

This bit is used to discontinue DMA channel transfer. When "1" is set to this bit, this channel stops the transfer, and it is not performed until this bit is cleared. If "1" is set to this bit during DMA transfer, DMA stops at transfer gap. Refer to DMACR/DE bits description for transfer gap. When "1" is set to this bit before receiving transfer request to acquire bus right, DMAC is immediately paused; in this case, DMAC does not hold transfer request during the pause. When "0" is set to this bit during DMA transfer is in pause, it is cleared and DMAC waits for new transfer request. This bit is able to be used to stop DMA transfer without resetting each configuration register of the channel.

0 Initial value 1 This channel is stopped

29 ST (Software Trigger)

This bit is used to generate software trigger. When "1" is set to this bit, DMA transfer starts as software request is received. After the transfer, DMAC sets "0" to this bit. If "0" is set to this bit during DMA transfer by software request, it stops at transfer gap. 0 Initial value 1 Software request



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No. Name 28-24 IS[4:0]

(Input Select) This bit is used to select trigger for DMA transfer. DMA transfer trigger is software request (ST = 1): Set 5’b00000 to IS bit DMA transfer trigger is external request (DREQ): Set 5’b01110 or 5’b01111 to IS bit DMA transfer trigger is peripheral request (IDREQ[15:0]): Set 5’b1xxxx to IS bit External request (DREQ[7:0]) is allocated into each channel, and peripheral request (IDREQ[15:0]) is allocated into all channels. Thus, peripheral request can be selected from all channels.

IS[4:0] Function 0(h) Software request

1(h)-B(h) Invalid E(h) DREQ "H" active level or rising edge F(h) DREQ "L" active level or falling edge 10(h) IDREQ 0 "H" active level or rising edge 11(h) IDREQ 1 "H" active level or rising edge 12(h) IDREQ 2 "H" active level or rising edge 13(h) IDREQ 3 "H" active level or rising edge 14(h) IDREQ 4 "H" active level or rising edge 15(h) IDREQ 5 "H" active level or rising edge 16(h) IDREQ 6 "H" active level or rising edge 17(h) IDREQ 7 "H" active level or rising edge 18(h) IDREQ 8 "H" active level or rising edge 19(h) IDREQ 9 "H" active level or rising edge 1A(h) IDREQ 10 "H" active level or rising edge 1B(h) IDREQ 11 "H" active level or rising edge 1C(h) IDREQ 12 "H" active level or rising edge 1D(h) IDREQ 13 "H" active level or rising edge 1E(h) IDREQ 14 "H" active level or rising edge 1F(h) IDREQ 15 "H" active level or rising edge

Transfer mode is block transfer or burst transfer: Rising edge is selected. Transfer mode is demand transfer: "H" active level is selected. [Note] • These bits must not be the same as other channels’ • If these bits are changed at asserting DREQ/IDREQ, DMAC regards IS bit change as edge

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No. Name 23-20 BT[3:0]

(Beat Type) These bits are used to select beat transfer on AHB. When these bits are set to Normal or Single, single source access and single destination access are alternately performed. If these bits are set to INCR* or WRAP*, contiguous source access and contiguous destination access are alternately performed. DMAC has 64 byte of FIFO that is shared in all channels. FIFO is used for INCR* and WRAP*DMA transfer. Refer to the AMBA specifications (v2.0) for INCR* and WRAP*. When INCR (undefined length burst) is set, the burst length is specified by the BC bit.

BT[3:0] Function 0(h) Normal (same as Single)

(Initial value) 1(h)-7(h) Invalid

8(h) Single (same as Normal) 9(h) INCR A(h) WRAP4 B(h) INCR4 C(h) WRAP8 D(h) INCR8 E(h) WRAP16 F(h) INCR16

While DMACB/MS are set to block transfer and burst transfer, fixed length burst (INCR*, WRAP*) and undefined length burst (INCR) are valid. When DMACB/MS are set to demand transfer, BT should be set to Normal or Single.

19-16 BC[3:0] (Block Count)

These bits are used to specify number of block for block/burst transfer. When transfer mode is demand transfer, be sure to set 4'b0000 to BC. Max. block quantity is 16 (Fh.) These bits are valid when beat transfer type is Normal, Single, or INCR. When other types of beat (fixed length burst and lap) are set, these bits are ignored. In addition, they are able to be read during DMA transfer. After single source access and single destination access are properlycompleted, normally BC bit is decremented for 1. [Note] These bits are settable even beat type bit (BT[3:0]) is INCR, however, read data of BC after starting DMA transfer is always 4’h0 in INCR DMA transfer so that BC does not need to be monitored during the transfer. After DMA transfer is completed properly, DMAC sets 4’b0000 to these bits.

BC[3:0] Function x(h) Number of block (initial value: 4’b0000)

15-0 TC[15:0]

(Transfer Count) These bits are used to specify number of block/burst/demand transfer. Max. number of transfer is 65536 (FFFFh.) Any kind of bit type is valid for BT. These bits are readable during DMA transfer. After BC becomes "0" and DMA transfer is properly completed, normally TC bit is decremented for 1 in the Normal or Single mode (BT = Normal or Single.) In other beat transfer modes (INCR, INCR*, and WRAP*), TC bit is decremented for 1 after completing consecutive source/destination access operation (for example, when 4 consecutive source accesses and 4 consecutive destination accesses are completed, INCR4’s TC bit is decremented for 1.) After DMA transfer is completed properly, DMAC sets 16’h0000 to these bits.

TC[3:0] Function x(h) Number of transfer (initial value: 16’h0000)

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9.6.4. DMA configuration B register (DMACBx)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name TT[1:0] MS[1:0] TW[1:0] FS FD RC RS RD EI CI SS[2:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W0 R/W0 R/W0


Name SP[3:0] DP[3:0] (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-30 TT[1:0]

(Transfer Type) These bits are used to specify transfer type. Currently, only 2 cycle transfer mode is available for DMAC.

TT[1:0] Function 0(h) 2 cycle transfer (initial value)

Other than 0(h) Reserved

29-28 MS[1:0] (Mode Select)

These bits are used to select transfer mode.

MS[1:0] Function 0(h) Block transmission mode (initial value) 1(h) Burst transmission mode 2(h) Demand transmission mode 3(h) Reserved

27-26 TW[1:0] (Transfer Width)

These bits are used to specify transfer data width. HSIZE of DMAC issues this value on AHB.

TW[1:0] Function 0(h) Byte (initial value) 1(h) Half-word 2(h) Word 3(h) Reserved

25 FS

(Fixed Source) This bit is used to fix source address. When the address needs to be added after each transfer, "0" must be set to this bit.

FS Function 0(h) Source address is incremented (initial value) 1(h) Source address is fixed

24 FD

(Fixed Destination)

This bit is used to fix destination address. When the address needs to be added after each transfer, "0" must be set to this bit.

FD Function 0(h) Destination address is incremented (initial value) 1(h) The destination address is fixed



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No. Name 23 RC

(Reload Count) This bit is used to control reload function for number of block (DMACA/BC bits) and number of transfer (DMACA/TC bits.) When "1" is set to this bit, DMACA/BC and DMACA/TC are set to the initial value after DMA transfer.

RC Function 0(h) Reload function for number of transfer is disabled (initial value) 1(h) Reload function for number of transfer is enabled

22 RS

(Reload Source) This bit is used to control reload function of source address (DMACSA.) "1" is set to this bit: DMACSA is set to the initial value after DMA transfer "0" is set to this bit: DMAC sets the next source address to DMACSA after DMA transfer

RS Function 0(h) Reload function of source address is disabled (initial value) 1(h) Reload function of source address is enabled

21 RD

(Reload Destination)

This bit is used to control reload function of destination address (DMACDA.) "1" is set to this bit: DMACDA is set to the initial value after DMA transfer "0" is set to this bit: DMAC sets the next destination address to DMACDA after DMA transfer

RD Function 0(h) Reload function of destination address is disabled (initial value) 1(h) Reload function of destination address is enabled

20 EI

(Error Interrupt) This bit is used to control issuing interrupt (DIRQ) caused by error. When this bit is set to "1", error interrupt is issued by the following transfer errors. • Address overflow

• Transfer stop request from DSTP and IDSTP, or transfer disable with EB or DE bit • Source access error • Destination access error

EI Function 0(h) Error interrupt issue is disabled (initial value) 1(h) Error interrupt issue is enabled

19 CI

(Completion Interrupt)

This bit is used to control issuing interrupt (DIRQ) caused by completion of transfer. When this bit is set to "1", completion interrupt is issued after DMA is transferred properly.

CI Function 0(h) Completion interrupt is disabled (initial value) 1(h) Completion interrupt is enabled

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No. Name 18-16 SS[2:0]

(Stop Status) These bits are used to show end code of DMA transfer which is shown below. These bits are also used to release interrupt (DIRQ) which is performed by writing 3'b000 to these bits when interrupt becomes error or it is issued by normal termination.

SS Function Status type 0(h) Initial value None 1(h) Address overflow Error 2(h) Transfer stop request Error 3(h) Source access error Error 4(h) Destination access error Error 5(h) Normal termination End 6(h) Reserved 7(h) DMA discontinuance None

When various errors occur at the same time, end code is displayed by the following priority. High priority Reset Clear by 3'b000 writing Address overflow Demand stop Source access error Destination access error Low priority

15-12 SP[3:0] (Source

Protection)

These bits are used to control source protection. HPROT at source access issues this value to AHB; however, it is not performed if source target does not equip protection function.

SP Function x(h) Protection code (initial value: 4'b0000.)

Note: HPORT is not implemented in this LSI. Setting this field has no effect.

11-8 DP[3:0] (Destination Protection)

These bits are used to control destination protection. HPROT at destination access issues this value to AHB; however, it is not performed if source target does not equip protection function.

DP Function x(h) Protection code (initial value: 4'b0000.)

Note: HPORT is not implemented in this LSI. Setting this field has no effect.

7-0 (Reserved) Reserved bits. Write access is ignored. Read value of this bit is always "0".

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9.6.5. DMAC source address register (DMACSAx)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name DMACSA[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name DMACSA[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-0 DMACSA[31:0]

(DMAC Source Address)

These bits are used to specify source address to start DMA transfer, and they are able to be read during DMA transfer. When fixed address function (DMACB/FS) is disabled, these bits are incremented according to the transfer width (DMACB/TW) after completing source address properly. After the DMA transfer, DMAC sets the next source address to these bits. [Note] It is prohibited to set DMAC register address to DMACSA.

DMACSA Function x(h) Source address to start DMA transfer

(Initial value: 32'h00000000)



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9.6.6. DMAC destination address register (DMACDAx)

Address ch0：FFFD0000+1C (h) ch1：FFFD0000+2C (h) ch2：FFFD0000+3C (h) ch3：FFFD0000+4C (h) ch4：FFFD0000+5C (h) ch5：FFFD0000+6C (h) ch6：FFFD0000+7C (h) ch7：FFFD0000+8C (h)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name DMACDA[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name DMACDA[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-0 DMACDA[31:0]

(DMAC Destination Address)

These bits are used to specify destination address to start DMA transfer, and they are able to be read during DMA transfer. When fixed address function (DMACB/FD) is disabled, these bits are incremented according to the transfer width (DMACB/TB) after completing destination address properly. After DMA transfer, DMAC sets the next destination address to these bits. [Note] It is prohibited to set DMAC register address to DMACDA.

DMACDA Function x(h) Destination address to start DMA transfer

(Initial value: 32'h00000000)



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9.7. Operation This section describes operation of DMAC.

9.7.1. Transfer mode DMAC has 3 types of transfer modes, and they are set with DMACB.MS[1:0].

9.7.1.1. Block transfer

Operation In the block transfer mode, DMA transfer specified by number of block (DMACA/BC) is executed by 1 transfer request. When number of transfer (DMACA/TC) is set to other values than "0", TC is decremented for 1 after completing DMA transfer of BC. After the last transfer (BC is 4'h0 and TC is 16'h0000), DMA transfer is completed.

Transfer gap After completing BC transfer, DMAC negates bus request to arbiter for the moment in the block transfer mode. This operation prevents DMAC from occupying the bus. Transfer gap is able to be used to reflect register setting (e.g. disable/interruption setting) to DMAC during DMA transfer.

Transfer request Software requirement, external request (DREQ), and peripheral request (IDREQ) are valid in this mode.

• Software request Set "1" to DMACA/ST and set 5'b00000 to DMACA/IS

• External request Set "0" to DMACA/ST, and set 5'b01110 (rising edge of transfer request) or 5'b01111 (falling edge of transfer request) to DMACA/IS

• Peripheral request Set "0" to DMACA/ST, and set 5'b1**** (rising edge of transfer request) to DMACA/IS

When external request or peripheral request is selected, DMAC detects transfer request edge. When BC's DMA transfer is executed by either of those requests, DMAC is unable to detect the next transfer; however, it is able to detect the next transfer request after BC's DMA transfer is completed.



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Restrictions When DMA transfer is performed by external (DREQ) or peripheral (IDREQ) request, there are restrictions for external and peripheral signal pins.

1. DREQ/IDREQ

DREQ/IDREQ must be asserted at least 2 cycles of AHB clock (HCLK). There is no restriction for timing of negating DREQ/IDREQ. After asserting DACK/IDACK, DMAC is able to accept new transfer request (edge of DREQ/IDREQ) for the next DMA transfer.

2. DACK/IDACK

After DMAC transfers data to the destination address, DACK/IDACK are asserted during 1 cycle of AHB clock (HCLK). When access to the destination is proceeded properly, this signal is asserted. If destination issues error, retry, or split responses at AHB, it is not asserted. In the block transfer mode, these signals indicate DMAC properly performs destination access.

3. DEOP/IDEOP

Basically, DEOP/IDEOP asserted for 1 AHB clock (HCLK) cycle when DMAC terminates DMA transfer properly or abnormally. Abnormal DMA transfer includes following cases:

• Forced termination by DSTP/IDSTP • Forced termination by setting 1'b0 to DMACA/EB • Receiving error response from source/destination

4. DSTP/IDSTP

DSTP/IDSTP are used to forcibly terminate DMA transfer, and asserting them during the transfer is valid (it is also valid to assert DSTP/IDSTP while DMA is not transferred due to transfer gap and interruption function.) When these signals are used to forcibly terminate DMA transfer, they are not asserted until DEOP/IDEOP are asserted.

5. Exceptional operation of DEOP/IDEOP When DSTP/IDSTP is asserted immediately after asserting DREQ/DSTP, DMAC may request bus to execute IDLE transfer. In this case, DMAC may assert DEOP/IDEOP for 2 cycles or more of AHB clock (HCLK.) The asserting period of DEOP/IDEOP depends on number of previous master transfer cycle. Figure 9-1 shows example of this exceptional operation.



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DACK

DREQ

DEOP

DSTP

HCLK

HBUSREQM(HDMAC)

HGRANTM(HDMAC)

HMASTER

Control

HREADY

IDLE

HRESP

HDMAC

OK

Other Master

NONSEQ or SEQ READ or WRITE

Other Master

NONSEQ or SEQ READ or WRITE

Figure 9-1 Example of exceptional operation for DEOP/IDEOP

When DMA transfer is performed by software reset, DREQ/IDREQ, DACK/IDACK, DEOP/IDEOP, and DSTP/IDSTP are not valid.

Timing chart Figure 9-2 shows block transfer in timing chart.



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DREQ

DACK

DEOP

DSTP

HCLK

HADDR

HWRITE

Control

External trigger

Software trigger

DMACA[31:24]

HWDATA

HRDATA

HBUSREQ

HGRANT

HREADY

HRESP

HMASTER CPU HDMAC CPU HDMAC CPU

OK

SA DA SA DA SA DA SA DA

HTRANS N N N N N N N N I I

Data Data Data

Data Data Data Data

0x00 0xA0

DMACA[19:16] 0x0 0x1 BC

0x00

0x0 0x1 0x0

DMACA[15:0] 0x0 0x1 TC

0x0

DMACSA

DMACDA

SA0 SA1 SA2 SA3 SA4

DA0 DA1 DA2 DA3 DA4

Break of transfer

Data

Figure 9-2 Block transfer (for BC = 0x1 and TC = 0x1)



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9.7.1.2. Burst transfer

Operation In the burst transfer mode, DMA transfer is executed for number of block multiplied by number of transfer (DMACA/BC × DMACA/TC) with 1 request. When number of transfer (DMACA/TC) is set to other values than "0", TC is decremented for 1 after completing DMA transfer. After the last transfer (BC is 4'h0 and TC is 16'h0000), DMA transfer is completed.

Transfer gap After completing DMA transfer, DMAC negates bus request to arbiter that transfer gap does not occur in the burst transfer mode. Register setting change during DMA transfer (e.g. disable/interruption setting) is reflected after completing DMA transfer.

Transfer request Software request, external (DREQ), and peripheral (IDREQ) requests are valid in this mode.

• Software request Set "1" to DMACA/ST and set 5'b00000 to DMACA/IS

• External request Set "0" to DMACA/ST, and set 5'b01110 (rising edge of transfer request) or 5'b01111 (falling edge of transfer request) to DMACA/IS

• Peripheral request Set "0" to DMACA/ST, and set 5'b1**** (rising edge of transfer request) to DMACA/IS

When external request or peripheral request is selected, DMAC detects transfer request edge. When DMA transfer of BC × TC is executed by either of those requests, DMAC is unable to detect the next transfer; however, it is able to detect the next transfer request after DMA transfer of BC × TC is completed.



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Restrictions When DMA transfer is performed by external (DREQ) and peripheral (IDREQ) requests, there are some restrictions for external and peripheral signal pins.

1. DREQ/IDREQ DREQ/IDREQ must be asserted at least 2 cycles of AHB clock (HCLK.) There is no restriction for timing of negating DREQ/IDREQ. After completing DMA transfer in BC × TC and asserting DACK/IDACK and DEOP/IDEOP, new transfer request (edge of DREQ/IDREQ) is able to be accepted for the next DMA transfer.

2. DACK/IDACK

After DMAC transfers data to the destination address, DACK/IDACK are asserted for 1 cycle of AHB clock (HCLK.) When access to the destination is proceeded properly, this signal is asserted. If destination issues error, retry, or split responses at AHB, this signal is not asserted. In the burst transfer mode, these signals indicate that DMAC performs destination access properly.

3. DEOP/IDEOP

Basically, DEOP/IDEOP are asserted for 1 AHB clock (HCLK) cycle when DMAC ends DMA transfer properly or abnormally. Abnormal DMA transfer includes following cases:


4. DSTP/IDSTP

DSTP/IDSTP are used to forcibly terminate DMA transfer, and asserting them while the transfer is valid (it is also valid to assert DSTP/IDSTP while DMA is not transferred due to transfer gap and interruption function.) When these signals are used to forcibly terminate DMA transfer, they are not asserted until DEOP/IDEOP are asserted.

5. Exceptional operation of DEOP/IDEOP When DSTP/IDSTP are asserted immediately after DREQ/DSTP are asserted, DMAC may request bus to execute IDLE transfer. In this case, DMAC may assert DEOP/IDEOP for 2 cycles or more of AHB clock (HCLK.) The asserting period of DEOP/IDEOP depends on number of previous master transfer cycle. Figure 9-3 shows example of this exceptional operation.



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DACK

DREQ

DEOP

DSTP

HCLK

HBUSREQM(HDMAC)

HGRANTM(HDMAC)

HMASTER

Control

HREADY

IDLE READ

HRESP

NOSEQ or SEQ READ or WRITE

HDMAC

OK

Other Master Other Master


Figure 9-3 Example of exceptional operation of DEOP/IDEOP When DMA transfer is performed by software reset, DREQ/IDREQ, DACK/IDACK, DEOP/IDEOP, and DSTP/IDSTP are not valid.



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Timing chart Figure 9-4 shows burst transfer in timing chart.

DREQ

DACK

DEOP

DSTP

HCLK

HADDR

HWRITE

Control

External trigger

Software trigger

DMACA[31:24]

HWDATA

HRDATA

HBUSREQ

HGRANT

HREADY

HRESP

HMASTER CPU HDMAC CPU

OK

SA DA SA DA SA DA

HTRANS N N N N N I N

Data Data Data

Data Data Data

0x00 0xA0

DMACA[19:16] 0x0 0x1 BC

0x00

0x0 0x1 0x0

DMACA[15:0] 0x0 0x1 TC

0x0

SA DA

N N

Data

Data

Figure 9-4 Burst transmission (for BC = 0x1 and TC = 0x1)



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9.7.1.3. Demand transfer

Operation In the demand transfer mode, DMA transfer is executed for 1 time transfer when transfer request is asserted, and number of transfer is set to DMACA/TC registers. In this case, DMACA/BC is set to "0". In this mode, DMACA/BC values are ignored. DMACA/TC are decremented for 1 after completing DMA transfer. Therefore DMA transfer ends after the last transfer (TC is16’h0000) is completed.

Transfer gap After completing 1 transfer, DMAC negates bus request to arbiter for the moment even though transfer request is asserted. This operation prevents DMAC from occupying bus. Transfer gap is able to be used to reflect register setting (e.g. disable/interruption setting) to DMAC during DMA transfer.

Transfer request External (DREQ) and peripheral (IDREQ) requests are valid in the demand transfer mode; however, software request setting is prohibited in this mode.

• External request Set "0" to DMACA/ST, and set 5'b01110 (H level of transfer request) or 5'b01111 (L level of transfer request) to DMACA/IS

• Peripheral request Set "0" to DMACA/ST, and set 5'b1**** (H level of transfer request) to DMACA/IS

When external request or peripheral request is selected, DMAC detects transfer request level.



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Restrictions When DMA transfer is performed by external (DREQ) or peripheral (IDREQ) request, there are some restrictions for the external and peripheral signal pins.

1. DREQ/IDREQ

DREQ/IDREQ must be asserted until DACK/IDACK are asserted. After they are asserted, DREQ/IDREQ need to be negated within AHB clock (HCLK) cycle of "source access cycle + destination access cycle – 1". When negation timing of DREQ/IDREQ is sent against to the restrictions, DMAC may start the next transfer operation. After completing 1 DMATE transfer and DACK/IDACK are asserted, DMAC is able to receive new transfer request (DREQ/IDREQ level) for the next DMA transfer after the condition of negating time indicated above.

2. DACK/IDACK

After DMAC transfers control signal to the source address, DACK/IDACK are asserted during 1 cycle of AHB clock (HCLK.) In the demand transfer mode, these signals indicate that DMAC receives demand transfer request.

3. DEOP/IDEOP Basically, DEOP/IDEOP are asserted for 1 AHB clock (HCLK) cycle when DMAC ends DMA transfer properly or abnormally. Abnormal DMA transfer includes following cases:


4. DSTP/IDSPT

DSTP/IDSTP are used to forcibly terminate DMA transfer. Asserting them during DMA transfer is valid (it is also valid to assert DSTP/IDSTP while DMA is not transferred due to transfer gap and interrupt function.) When these signals are used to forcibly terminate DMA transfer, they are not asserted until DEOP/IDEOP are asserted.

5. Exceptional operation of DEOP/IDEOP When DSTP/IDSTP are asserted immediately after DREQ/DSTP are asserted, DMAC may request bus to execute IDLE transfer. In this case, DMAC may assert DEOP/IDEOP for 2 cycles or more of AHB clock (HCLK.) The asserting period of DEOP/IDEOP depends on number of previous master transfer cycle. Figure 9-5 shows example of this exceptional operation.



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DACK

DREQ

DEOP

DSTP

HCLK

HBUSREQM(HDMAC)

HGRANTM(HDMAC)

HMASTER

Control

HREADY

IDLE READ

HRESP


HDMAC

OK

Other Master Other Master


Figure 9-5 Example of exceptional operation of DEOP/IDEOP



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Timing chart Figure 9-6 shows demand transfer in timing chart.

DREQ

DACK

DEOP

DSTP

HCLK

HADDR

HWRITE

Control

External trigger

HWDATA

HRDATA

HBUSREQ

HGRANT

HREADY

HRESP


OK

SA DA

HTRANS N N I

Data

Data

DMACA[19:16]

0x2 BC

0x1 0x0 DMACA[15:0] 0x0 TC

0x0

HDMAC

SA DA

N N I

HDMAC

SA DA

N N I

Data

Data

Data

Data

Transfer gap Transfer gap

Figure 9-6 Demand transfer (for BC = 0x0 (should be 0) and TC = 0x2)



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9.7.2. Beat transfer DMAC supports beat transfer which means, in this case, increment/lap burst of the AMBA standard. DMAC has 64 byte FIFO shared in all channels, and enables sequential source access and destination access. The beat transfer type is set by DMACA/BT bits. Correlation to DMACA/BT and AHB of HBURST is shown below.

Table 9-3 DMACA/BT and HBURST DMACA/BT Beat transfer type HBURST DMACA/MS (mode select)

Block Burst Demand 4’b0000 Normal Single OK OK OK 4’b1000 Single Single OK OK OK 4’b1001 INCR INCR OK OK NG 4’b1010 WRAP4 WRAP4 OK OK NG 4’b1011 INCR4 INCR4 OK OK NG 4’b1100 WRAP8 WRAP8 OK OK NG 4’b1101 INCR8 INCR8 OK OK NG 4’b1110 WRAP16 WRAP16 OK OK NG 4’b1111 INCR16 INCR16 OK OK NG In the demand transfer, increment/lap burst (INCR* and WRAP*) is unsupported.

9.7.2.1. Normal and Single transfer Normal and Single transfer methods are the same. Single source access and single destination access are executed alternately as shown in Figure 9-1 and Figure 9-2.



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9.7.2.2. Increment and lap transfer When increment beat transfer (INCR, INCR4, INCR8 and INCR16) or lap beat transfer (WRAP4, WRAP8, and WRAP16) is set to DMACA/BT, sequential source access and destination access are executed by using 64 byte FIFO of DMAC. For the case of INCR4 (DMACA/BT = 4'b1011), DMAC performs 4 sequential source accesses. Output data from the source is stored in FIFO of DMAC, then the data is driven to destination in sequence.

HCLK

HADDR

HWRITE

Control

HWDATA

HRDATA

HBUSREQ

HGRANT

HREADY

HRESP


OK

SA SA SA SA DA DA

HTRANS N S S S S IN

D4D1

D1

DMACA[19:16] BC

0x0

DMACA[15:0] TC

DA DA

S S

INCR4 INCR4

D2 D3

D2 D3

D4

0x0

Figure 9-7 Increment/Lap beat transfer (example of INCR4 block transfer)



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9.7.3. Channel priority control DMAC controls priority of each channel by DMACR/PR bits.

9.7.3.1. Fixed priority When priority is set to DMACR/PR bits, priority order is fixed and bus is given to the lowest figure of channel. Priority controller of DMAC switches channel when active channel is in transfer gap. Thus, when all channels are active at the same time, the lowest figure of channel (ch0) is able to be selected by priority controller to start transfer. For instance, active channel (ch0) temporarily loses the bus at transfer gap. Then it is given to the second lowest figure of channel (ch1). If ch1 loses bus at transfer gap, it is given to ch0 again. As a result, those 2 channels are able to preferentially acquire bus in the fixed priority mode. Figure 9-8 shows defined channel in the fixed priority mode.

HBUSREQM

HGRANTM

HBUSREQM0 HBUSREQM1 HBUSREQM2 HBUSREQM3 HBUSREQM4 HBUSREQM5 HBUSREQM6 HBUSREQM7

Defined channel #0 #1 #0 #1 #0 #1 #0 #1 #2 #3 #2 #3 #2 #3 #2

HDMAC Internal

AHB

Figure 9-8 Defined channel in the fixed priority



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9.7.3.2. Rotate priority When priority is set to DMACR/PR bits, priority order rotates. After bus is given to the lowest figure of channel, priority controller of DMAC switches channel at transfer gap of active channel. Thus, when all channels become active at the same time, the lowest figure of channel (ch0) is selected by priority controller to enable transfer operation. In the rotate priority mode, all channels are able to acquire bus in rotation. For instance, active channel (ch0) temporarily loses the bus at transfer gap. Then it is given to the second lowest figure of channel (ch1). If ch1 loses bus at transfer gap, it is given to the third lowest figure of channel (ch2.) Figure 9-9 shows defined channel in the rotate priority mode.

HBUSREQM

HGRANTM

HBUSREQM0 HBUSREQM1 HBUSREQM2 HBUSREQM3 HBUSREQM4 HBUSREQM5 HBUSREQM6 HBUSREQM7

Defined channel #0 #1 #2 #3 #4 #5 #6 #7 #0 #1 #2 #3 #4 #5 #6

HDMAC Internal

AHB

Figure 9-9 Defined channel in the rotate priority



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9.7.4. Retry, split, and error DMAC supports retry and split responses of AHB slave.

9.7.4.1. Retry and split When DMAC receives retry or split responses from AHB slave during DMA transfer, DMAC negates bus temporarily to construct the contents to be retransmitted. Figure 9-10 shows example of receiving retry response at INCR4 DMA transfer.

HCLK

HADDR

HWRITE

Control

HWDATA

HRDATA

HBUSREQ

HGRANT

HREADY

HRESP


OK

SA SA SA SA DA DA

HTRANS N S S S S IN

D4D1

D1

DMACA[19:16] BC

0x0

DMACA[15:0] TC

DA DA

S S

INCR4 INCR4

D2 D3

D2 D3

D4

0x0

RETRY OK

HDMAC

DA

N I

D4

INCR

Figure 9-10 Increment/Lap beat transfer (example of INCR4 block transfer) When DMAC negates bus temporarily, the channel received retry/split responses is continuously selected by DMAC's priority controller that transfer operation is able to start even though higher priority channel requests the bus



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9.7.4.2. Error When DMAC receives error reply from AHB slave during DMA transfer, DMAC negates bus request and immediately stops the transfer even though it is not completed. In this case, neither Block/Transfer count register nor Source/Destination address register is updated.



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9.8. Example of DMAC setting

9.8.1. DMA start in single channel Example of block and burst transfer by software request (with DMAC ch0)

ー

(2) Set DMAC source address register DMACSA0 ← 0x0000_0000

(1) Set DMA configuration register DMACR ← 0x80 (byte writing)

Source address is set.

DMA transfer is enabled.

(3) Set DMAC destination address register DMACDA0 ← 0x0100_0000

(4) Set DMA configuration B register DMACB0 ← 0x0808_0000

Destination address is set.

Transfer mode, transfer data width, and completion interrupt are set. In this example, block transfer mode (MS[1:0] = 0H) is set as transfer mode. Burst transfer mode is able to be set by MS[1:0] = 1H.

DMA channel transfer control, software trigger, and number of block and transfer are set.

(5) Set DMA configuration A register DMACA0 ← 0xA00F_000F

Start DMA transfer

Remark: Setting order of step 1 ~ 4 is arbitrary; however, step 5 must be executed at the end of the setting procedure (as the 5th setting process).

Figure 9-11 Example of block and burst transfer by software request (with DMAC ch0)

Note: • DMA configuration register (DMACR) should be set by byte writing. • For block and burst transfer with software request, DMA configuration A register (DMACA)

should be set at the end.



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9-34

Example of demand transfer by software request (with DMAC ch0)

ー

(2) Set DMAC source address register DMACSA0 ← 0x0100_8000

(1) Set DMA configuration register DMACR ← 0x80 (byte writing)

Source address is set.

DMA transfer is enabled.

(3) Set DMAC destination address register DMACDA0 ← 0xFFFE_1000

(4) Set DMA configuration B register DMACB0 ← 0x2100_0000

Destination address is set.

Transfer mode, transfer data width, and completion interrupt is set.

DMA channel transfer control, software trigger, and number of block and transfer are set.

(5) Set DMA configuration A register DMACA0 ← 0x9000_000A

Start DMA transfer

Remark: Setting order of step 1 ~ 5 is arbitrary; however, the last setting should be step 1 or 5.

Figure 9-12 Example of demand transfer by software request (with DMAC ch0)

Note: • DMA configuration register (DMACR) should be set by byte writing.

9.8.2. DMA start in all channels (in demand transfer mode) All channels are able to start simultaneously by setting DMACR register after setting all DMA channels' register in the demand transfer mode. In this case, DMAC priority controller receives request of all channels at the same time, then transfer starts by selecting channel according to DMA channel priority, which is settable with PR bit of the DMACR.

DMA controller (DMAC) FUJITSU SEMICONDUCTOR PROPRIETARY AND CONFIDENTIAL

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10. Timer (TIMER0/1) This chapter describes function and specification of 32/16 bit timer.

10.1. Outline This LSI is equipped with two Timer modules (Timer0 / Timer1). Each Timer module includes 2 16/32 bit reload timer. A interrupt output of Timer1 channel 2 is used as hardware trigger signal for A/D conversion

10.2. Features Each Timer module has following features:

• 32/16 bit counter × 2 (bit width is controllable with register) • Supplying 2 interrupt request signals to interrupt controller • Timer clock prescaler unit • 3 operation modes:

• Free-run mode • Cycle timer mode • One-shot mode

• Using APB clock as base clock of the timer

10.3. Supply clock APB clock is supplied to timer0/1. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.


Timer (TIMER0/1)

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INARY


10.4. Register This section describes Timer0/1 register

10.4.1. Register list Table 10-1 Timer0/1 register list

Address Register name Abbreviation Description

Base Offset FFFE_0000H

+ 000H Timer0 ch 1 load register TIMER01LOAD Containing 32 bit reload value + 004H Timer0 ch 1 value register TIMER01VALUE Return current timer value + 008H Timer0 ch 1 control register TIMER01CONTROL Control Timer operation mode +00CH Timer0 ch 1 interrupt clear register TIMER01INTCLR Clears the interrupt output + 010H Timer0 ch 1 raw interrupt status register TIMER01RIS Indicates the raw interrupt status + 014H Timer0 ch1 interrupt status register TIMER01MIS Indicates the masked interrupt status + 018H Timer0 ch1 background load register TIMER01BGLOAD 32-bit reload value when Periodic

mode is enabled + 01CH (Reserved) + 020H Timer0 ch 2 load register TIMER02LOAD Containing 32 bit reload value + 024H Timer0 ch 2 value register TIMER02VALUE Return current timer value + 028H Timer0 ch 2 control register TIMER02CONTROL Control Timer operation mode + 02CH Timer0 ch 2 interrupt clear register TIMER02INTCLR Clears the interrupt output + 030H Timer0 ch 2 raw interrupt status register TIMER02RIS Indicates the raw interrupt status + 034H Timer0 ch2 interrupt status register TIMER02MIS Indicates the masked interrupt status + 038H Timer0 ch2 background load register TIMER02BGLOAD 32-bit reload value when Periodic

mode is enabled + 03CH ~ + 7FFH

(Reserved)

FFFE_0800H

+ 000H Timer1 ch 1 load register TIMER11LOAD Containing 32 bit reload value + 004H Timer1 ch 1 value register TIMER11VALUE Return current timer value + 008H Timer1 ch 1 control register TIMER11CONTROL Control Timer operation mode +00CH Timer1 ch 1 interrupt clear register TIMER11INTCLR Clears the interrupt output + 010H Timer1 ch 1 raw interrupt status register TIMER11RIS Indicates the raw interrupt status + 014H Timer1 ch1 interrupt status register TIMER11MIS Indicates the masked interrupt status + 018H Timer1 ch1 background load register TIMER11BGLOAD 32-bit reload value when Periodic

mode is enabled + 01CH (Reserved) + 020H Timer1 ch 2 load register TIMER12LOAD Containing 32 bit reload value + 024H Timer1 ch 2 value register TIMER12VALUE Return current timer value + 028H Timer1 ch 2 control register TIMER12CONTROL Control Timer operation mode + 02CH Timer1 ch 2 interrupt clear register TIMER12INTCLR Clears the interrupt output + 030H Timer1 ch 2 raw interrupt status register TIMER12RIS Indicates the raw interrupt status + 034H Timer1 ch2 interrupt status register TIMER12MIS Indicates the masked interrupt status + 038H Timer1 ch2 background load register TIMER12BGLOAD 32-bit reload value when Periodic

mode is enabled + 03CH ~ + 7FFH

(Reserved)


Timer (TIMER0/1)

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Description format of register Following format is used for description of register’s each bit


Name R/W


Name R/W

Initial value









Timer (TIMER0/1)

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10.4.2. Timer load register (TIMERxxLOAD) This register contains the value from which the counter is to decrement.

Address TIMER01LOAD : FFFE_0000H + 00H TIMER02LOAD : FFFE_0000H + 20H

TIMER11LOAD : FFFE_8000H + 00H TIMER12LOAD : FFFE_8000H + 20H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name LOAD[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name LOAD[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-0 LOAD[31:0] 32-bit timer reload value

When this register is written directly, the current count is immediately reset to the new value at the next rising edge of APB The value in this register is also overwritten if the corresponding background load register TIMERxxBGLOAD is written to, but the current count is not immediately affected If values are written to both TIMERxxLOAD and TIMERxxBGLOAD before an enabled rising edge on APB, the following occurs : 1. On the next enabled APB edge, the value written to the TIMERxxLOAD value replaces the

current count value 2. Then, each time the counter reaches zero, the current count value is reset tot the value written

to TIMERxxBGLOAD Reading from the TIMERxxLOAD register at any time after thw two writes have occurred retrieves the value written to TIMERxxBGLOAD. That is, the value read from TIMERxxLOAD is always the value that takes effect for Periodic mode after the next time the counter reaches zero

10.4.3. Timer current value register (TIMERxxVALUE) This register return the current value of the corresponding decrementing counter.

Address TIMER01VALUE : FFFE_0000H + 04H TIMER02VALUE : FFFE_0000H + 24H

TIMER11VALUE : FFFE_8000H + 04H TIMER12VALUE : FFFE_8000H + 24H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name LOAD[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name LOAD[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-0 VALUE[31:0] Current counter value


Timer (TIMER0/1)

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INARY


10.4.4. Timer control register (TIMERxxCONTROL) This register control the timer operation

Address TIMER01CONTROL : FFFE_0000H + 08H TIMER02CONTROL : FFFE_0000H + 28H

TIMER11CONTROL : FFFE_8000H + 08H TIMER12CONTROL : FFFE_8000H + 28H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Reserved R/W R R R R R R R R R R R R R R R R


Name Reserved TEN TPD INTE – PRE[1:0] X32 OSHTR/W R R R R R R R R R/W R/W R/W R R/W R/W R/W R/W

Initial value X X X X X X X X 0 0 0 X 0 0 0 0



Write access is ignored. Read value of these bits is undefined. 7 TEN Timer enable bit

0 Timer is disabled (Initial value) 1 Timer is enabled.

6 TPD Timer periodic mode bit

0 Timer is in free-running mode (Initial value) If timer is not in one-shot mode, counter reload its maximum value and continuous to decrement when reaching zero

1 Timer is in periodic mode If timer is not in one-shot mode, counter reload load register value and continuous to decrement when reaching zero

5 INTE Interrupt enable bit

0 Timer interrupt disable (Initial value) No interrupt output when timer raw interrupt flag is set TIMERxxRIS.RINT

1 Timer interrupt enable Interrupt output when timer raw interrupt flag is set TIMERxxRIS.RINT

4 – Unused bit. Write access is ignored. Read value of these bits is undefined.

3-2 PRE[1:0] Count clock prescaler

00 Count clock = APB clock (Initial value) 01 Count clock = APB clock / 16 10 Count clock = APB clock / 256 11 Setting prohitbited

1 X32 16/32-bit timer mode

0 16-bit counter is used (Initial value) 1 32-bit counter is used

0 OSHT One-shot mode enable

0 Wrapping mode (Initial value) Counter reload its maximum value or load register value when reaching zero

1 One-shot mode Counter halts until new load value is written to TIMERxxLOAD


Timer (TIMER0/1)

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10.4.5. Timer interrupt clear register (TIMERxxINTCLR) This register is to clear the raw interrupt flag.

Address TIMER01INTCLR : FFFE_0000H + 00CH TIMER02INTCLR : FFFE_0000H + 02CH

TIMER11INTCLR : FFFE_8000H + 00CH TIMER12INTCLR : FFFE_8000H + 02CH

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name TIMERxxINTCLR[31:16] R/W W W W W W W W W W W W W W W W W


Name TIMERxxINTCLR[15:0] R/W W W W W W W W W W W W W W W W W



No. Name 31-0 TIMERxxINTCLR Write of this register will clear zero flag (ZF) of register TIMERxxRIS

10.4.6. Timer raw interrupt status register (TIMERxxRIS) This register indicates the timer has reached zero value

Address TIMER01RIS : FFFE_0000H + 10H TIMER02RIS : FFFE_0000H + 30H

TIMER11RIS : FFFE_8000H + 10H TIMER12RIS : FFFE_8000H + 30H



Name Reserved ZF R/W R R R R R R R R R R R R R R R R




Write access is ignored. Read value of these bits is undefined. 0 ZF Zero flag

0 Counter not reached zero 1 Counter reached zero

This bit is cleared when written any value to TIMERxxINTCLR register


Timer (TIMER0/1)

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10-7



Timer (TIMER0/1)

10.4.7. Timer masked interrupt status register (TIMERxxMIS) This register indicates the timer has reached zero value

Address TIMER01RIS : FFFE_0000H + 14H TIMER02RIS : FFFE_0000H + 34H

TIMER11RIS : FFFE_8000H + 14H TIMER12RIS : FFFE_8000H + 34H



Name Reserved INT R/W R R R R R R R R R R R R R R R R




Write access is ignored. Read value of these bits is undefined. 0 INT Interrupt status flag

This bit is logical AND of the Zero Flag with the timer interrupt enable bit in Timer Control Register INT = TIMERxxRIS.ZF & TIMERxxCONTROL.INTE

10.4.8. Timer background load register (TIMERxxBGLOAD) This register provide an alternative method of accessing the TIMERxxLOAD register.

Address TIMER01LOAD : FFFE_0000H + 18H TIMER02LOAD : FFFE_0000H + 38H

TIMER11LOAD : FFFE_8000H + 18H TIMER12LOAD : FFFE_8000H + 38H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name BGLOAD[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name BGLOAD[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-0 BGLOAD[31:0] 32-bit timer reload value

The function of this register is same as TIMERxxLOAD. The difference is that writes this register do not cause the counter to immediately restart from the new value.

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11. General-purpose input/output port (GPIO) This chapter describes function and operation of general-purpose input/output port (GPIO.)

11.1. Outline This LSI has max. 69 bit of GPIO port which is in common with other peripheral ports. Refer to "1.6.1 Pin Multiplex" for shared peripherals. Direction control and data reading/writing of GPIO port is performed with using GPIO control register.

11.2. Feature GPIO has following features:

• Supplied 68 bit GPIO port • Composed of following 2 registers

• Port data register (GPDR) • Data direction register (GPDDR)

11.3. Block diagram Figure 11-1 shows block diagram of GPIO controller. In this LSI, 69 pcs. of these blocks are equipped. I/O cell GPIO module

APB GPDDR

GPDR(out)

External port 1 0

Read data of PDR

Write data

GPDR(in)

PI

PO

PC

Figure 11-1 Block diagram of GPIO module

11.4. Supply clock APB clock is supplied to GPIO. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.


General-purpose input/output port (GPIO)

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11.5. Register This section describes detail of register in GPIO.

11.5.1. Register list Table 11-1 shows list of GPIO register.

Table 11-1 GPIO register list Address

Register Abbreviation Description

Base Offset FFFE_9000H + 000H Port data register 00 GPDR00 Setting of input/output data of GPIO[7:0] pin

+ 004H Port data register 01 GPDR01 Setting of input/output data of GPIO[15:8] pin + 008H Port data register 02 GPDR02 Setting of input/output data of GPIO[23:16] pin + 00CH (Reserved) – Reserved area (access prohibited) + 010H Data direction register 00 GPDDR00 Control of input/output direction of GPIO [7:0] pin + 014H Data direction register 01 GPDDR01 Control of input/output direction of GPIO[15:8] pin + 018H Data direction register 02 GPDDR02 Control of input/output direction of GPIO[23:16] pin + 01CH ~ + 7FFH


FFF5_9000H + 000H Port data register 10 GPDR10 Setting of input/output data of GPIO[31:24] pin + 004H Port data register 11 GPDR11 Setting of input/output data of GPIO[39:32] pin + 008H Port data register 12 GPDR12 Setting of input/output data of GPIO[47:40] pin + 00CH (Reserved) – Reserved area (access prohibited) + 010H Data direction register 10 GPDDR10 Control of input/output direction of GPIO [31:24] pin + 014H Data direction register 11 GPDDR11 Control of input/output direction of GPIO[39:32] pin + 018H Data direction register 12 GPDDR12 Control of input/output direction of GPIO[47:40] pin + 01CH ~ + 7FFH


FFF4_9000H + 000H Port data register 20 GPDR20 Setting of input/output data of GPIO[55:48] pin + 004H Port data register 21 GPDR21 Setting of input/output data of GPIO[63:56] pin + 008H Port data register 22 GPDR22 Setting of input/output data of GPIO[68:64] pin + 00CH (Reserved) – Reserved area (access prohibited) + 010H Data direction register 20 GPDDR20 Control of input/output direction of GPIO [55:48] pin + 014H Data direction register 21 GPDDR21 Control of input/output direction of GPIO[63:56] pin + 018H Data direction register 22 GPDDR22 Control of input/output direction of GPIO[68:64] pin + 01CH ~ + 7FFH




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Description format of register Following format is used for description of register’s each bit in "11.5.2 Port data register 0-2 (GPDR0-2)" to "11.5.3 Data direction register 0-2 (GPDDR2-0)".


Name R/W


Name R/W

Initial value










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INARY


11.5.2. Port data registers (GPDRXX) GPDRXX registers are to set input/output data of GPIO port Input/Output directions of each GPIO are determined by the corresponding bit of GPDRXX registers.

Address GPDR00: FFFE_9000H + 00H GPDR01: FFFE_9000H + 04H GPDR02: FFFE_9000H + 08H

GPDR10: FFF5_9000H + 00H GPDR11: FFF5_9000H + 04H GPDR12: FFF5_9000H + 08H

GPDR20: FFF4_9000H + 00H GPDR21: FFF4_9000H + 04H GPDR22: FFF4_9000H + 08H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) R/W – – – – – – – – – – – – – – – –


Name (Reserved) PDR7 PDR6 PDR5 PDR4 PDR3 PDR2 PDR1 PDR0R/W – – – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W




Write access is ignored. Read value of these bits is undefined. 7-0 PDR[7:0] GPDR register's bit field.

The register is setting register of GPIOXX pin's input/output data, and each bit corresponds to GPIO pin as follows.

GPDR00 GPDR01 GPDR02 GPDR10 GPDR11 GPDR12 GPDR20 GPDR21 GPDR22 PDR7 GPIO7 GPIO15 GPIO23 GPIO31 GPIO39 GPIO47 GPIO55 GPIO63 – PDR6 GPIO6 GPIO14 GPIO22 GPIO30 GPIO38 GPIO46 GPIO54 GPIO62 – PDR5 GPIO5 GPIO13 GPIO21 GPIO29 GPIO37 GPIO45 GPIO53 GPIO61 – PDR4 GPIO4 GPIO12 GPIO20 GPIO28 GPIO36 GPIO44 GPIO52 GPIO60 GPIO68 PDR3 GPIO3 GPIO11 GPIO19 GPIO27 GPIO35 GPIO43 GPIO51 GPIO59 GPIO67 PDR2 GPIO2 GPIO10 GPIO18 GPIO26 GPIO34 GPIO42 GPIO50 GPIO58 GPIO66 PDR1 GPIO1 GPIO9 GPIO17 GPIO25 GPIO33 GPIO41 GPIO49 GPIO57 GPIO65 PDR0 GPIO0 GPIO8 GPIO16 GPIO24 GPIO32 GPIO40 GPIO48 GPIO56 GPIO64

Input/Output directions of GPIOXX pins are determined by the correspondence bit of GPDDRxx register. Initial value of these bits is undefined.



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11.5.3. Data direction registers (GPDDRXX) GPDDRXX registers are to control input/output directions of GPIO port

Address GPDDR00: FFFE_9000H + 10H GPDDR01: FFFE_9000H + 14H GPDDR02: FFFE_9000H + 18H

GPDDR10: FFF5_9000H + 10H GPDDR11: FFF5_9000H + 14H GPDDR12: FFF5_9000H + 18H

GPDDR20: FFF4_9000H + 10H GPDDR21: FFF4_9000H + 14H GPDDR22: FFF4_9000H + 18H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) R/W – – – – – – – – – – – – – – – –


Name (Reserved) DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 R/W – – – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W




Write access is ignored. Read value of these bits is undefined. 7-0 DDR[7:0] GPDR0 register's bit field.

This register controls input/output directions of GPIO pin.

0 GPIO becomes input port (initial) 1 GPIO becomes output port

GPIO pin corresponding to this register is as follows:

GPDR00 GPDR01 GPDR02 GPDR10 GPDR11 GPDR12 GPDR20 GPDR21 GPDR22 DDR7 GPIO7 GPIO15 GPIO23 GPIO31 GPIO39 GPIO47 GPIO55 GPIO63 – DDR6 GPIO6 GPIO14 GPIO22 GPIO30 GPIO38 GPIO46 GPIO54 GPIO62 – DDR5 GPIO5 GPIO13 GPIO21 GPIO29 GPIO37 GPIO45 GPIO53 GPIO61 – DDR4 GPIO4 GPIO12 GPIO20 GPIO28 GPIO36 GPIO44 GPIO52 GPIO60 GPIO68 DDR3 GPIO3 GPIO11 GPIO19 GPIO27 GPIO35 GPIO43 GPIO51 GPIO59 GPIO67 DDR2 GPIO2 GPIO10 GPIO18 GPIO26 GPIO34 GPIO42 GPIO50 GPIO58 GPIO66 DDR1 GPIO1 GPIO9 GPIO17 GPIO25 GPIO33 GPIO41 GPIO49 GPIO57 GPIO65 DDR0 GPIO0 GPIO8 GPIO16 GPIO24 GPIO32 GPIO40 GPIO48 GPIO56 GPIO64



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11-6




11.6. Operation This section describes GPIO operation.

11.6.1. Direction control Direction of GPIO port and its each bit is able to change by GPDDRxx register. Initial direction (DDRx bit's initial value of GPDDRxx register) after reset is "0" (input port.)

Note: Pay attention to bus confliction when changing GPIO port direction.

11.6.2. Data transfer When GPIO port is used as input port (DDRx = 0), the data signal input to the port input signal (PI) is stored to PDRx (in) at rising edge of APB clock (see Figure 11-1.) Reading GPDRxx register enables to observe input data. During the period, write access to the GPDRx register is valid that PDRx (out) is changeable except at DDRx = 0. When GPIO port is used as output port (DDR = 1), GPDRxx register value is output to the port output signal (PO); in that time, read data of the register becomes the same value as the port output signal's.

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12. Chip Control Module (CCNT) This chapter describes the function and the operation of Chip Control Module (CCNT.)

12.1. Outline Chip Control Module (hereafter called CCNT) performs pin multiplex control, software reset control others.

12.2. Feature • Multiplex pin interface:

Mode selection setting of pin multiplex groups 2 and 4 • Software reset interface:

Issuing software reset to each module in the register • Byte swap interface:

Setting byte swap of SDIO, I2S, and USB 2.0 Host • GPIO interface • USB 2.0 interface (host system):

USB 2.0 Host controller's stop control This is asserted when high order system detects error in AHB system or others

• USB 2.0 interface (host EHCI power): This asserts signal when overcurrent is detected, and it disables port

12.3. Supply clock APB clock is supplied to CCNT. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.


Chip Control Module (CCNT)

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12.4. Register This section describes CCNT module register.

12.4.1. Register list CCNT unit contains register shown in Table 12-1.

Table 12-1 CCNT register list Address

Register Abbreviation Description Base Offset

FFF4_2000H + 000H Chip mode register CMDR Return external pin MD2~MD0 status + 004H Module reset register CSRST Reset individual macro + 008H (Reserved) – Reserved area (access prohibited) + 00CH USB control register CUSBC USB general control + 010H Port function select register CPSEL Chip pin multiplex control + 014H NF Ready interrupt register CNFR NandFlash ready interrupt control + 018H SDIO clock selection register CSDMC SDMC clock selection + 01CH Peripheral data wrap control

register CDWS Peripheral data wrap control

+ 020H Chip ID register CCID Return chip ID information + 01FH ~ + 7FFH




PRELIM

INARY




Name R/W


Name R/W

Initial value










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INARY


12.4.2. CHIP mode register (CMDR)

Address FFF4_2000 + 00h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name – – – – – – – – – – – – – – – – R/W R R R R R R R R R R R R R R R R


Name – – – – – – – – – – – – – MD[2:0] R/W R R R R R R R R R R R R R R R R

Initial value X X X X X X X X X X X X X - - -

Bit field Function


Write access is ignored, and read value of these bits is undefined 3-0 MD[2:0] Current external pin MD[2:0] status



PRELIM

INARY




12.4.3. Macro reset register (CSRST)

Address FFF4_2000 + 04h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name PWMR CANR SPI1R SPI0R I2C1R I2C0R SIO4R SIO3R SIO2R SIO1R SIO0R URT4R URT3R URT2R URT1R URT0RR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name (Reserved) SDCR I2S1R I2S0R (Resv) USBHRR/W R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W R/W R/W R R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field Function

No. Name 15-5,

1 (Reserved) Reserved bit. Always write 0.

31-16, 4-2,

0

Various name Individual macro reset bit Writing "1" to enable the reset of corresponding macro Writing “0” to release the reset of corresponding macro

0 Not reset (initial value) 1 Reset

Following is the list of corresponding macro

Bit field Bit name Corresponding macro 31 PWMR PWM 30 CANR C-CAN I/F 29 SPI1R SPI interface 1 28 SPI0R SPI interface 0 27 I2C1R I2C interface 1 26 I2C0R I2C interface 0 25 SIO4R SIO interface 4 24 SIO3R SIO interface 3 23 SIO2R SIO interface 2 22 SIO1R SIO interface 1 21 SIO0R SIO interface 0 20 URT4R UART interface 4 19 URT3R UART interface 3 18 URT2R UART interface 2 17 URT1R UART interface 1 16 URT0R UART interface 0 4 SDCR SD Card inteface 3 I2S1R I2S interface 1 2 I2S0R I2S interface 0 0 USBHR USB host controller

CCNT

Macrosoftware

resetregister

AP

B

HRESETn

RST0

RST1

RSTx

to macro

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INARY


12.4.4. USB miscellanies control register (CUSBC)

Address FFF4_2000 + 0Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – – – – – – – (Resv) – – – OVCB – – – SYSERR/W R R R R R R R R/W0 R R R R/W R R R R/W

Initial value X X X X X X X 0 X X X 0 X X X 0

Bit field Function

No. Name 31-9, 7-5 3-1

– Unused bits. Write access is ignored, and read value of these bits is undefined

8

(Reserved) Reserved bit. Always write 0.

4 OVCB USB Host EHCI power control USB host controller uses this register value to disable the USB port power. Writing “1” to inform USB host controller that over current is detected or other circumstances that USB host controller need to disable the USB port power

0 SYSER USB Host system error indication bit USB host controller uses this register value to identify the AHB system encounter error condition or not Writing “1” to inform USB host controller that AHB system encounter error condition or other abnormal operation



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INARY


12.4.5. Port function select register (CPSEL) To select the function of each port pin.

Address FFF4_2000 + 10h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name SD4 SD PWM[1:0] Reserved Reserved Reserved I2S[1:0] I2C[1:0] UART[4:0] R/W R/W R/W R/W R/W R/W0 R/W0 R/W0 R/W R/W R R/W R/W R/W R/W R/W R


Name U0M[1:0] S1M[1:0] NFCEX NFRDY NF16 NFS CAN SPI[1:0] SIO[4:0] R/W R/W0 R/W0 R/W0 R/W0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Pin No.

After Reset


Pin Function

Register Setting



Others *1

20 GPIO00 SDDAT0 CPSEL[30] = 1

21 GPIO01 SDDAT1 CPSEL[31:30] = 11



24 GPIO04 SDCMD CPSEL[30] = 1

25 GPIO05 SDXMCD CPSEL[30] = 1

26 GPIO06 SDWP CPSEL[30] = 1

29 GPIO07 SDCLK CPSEL[30] = 1

31 GPIO08 I2C0SL CPSEL[21] = 1

32 GPIO09 I2C0SA CPSEL[21] = 1

33 GPIO10 I2C1SL CPSEL[22] = 1

34 GPIO11 I2C1SA CPSEL[22] = 1

79 GPIO12 CANRX CPSEL[7] = 1 I2S0ECK

80 GPIO13 CANTX CPSEL[7] = 1 I2S1ECK

57 GPIO14 PWM0 CPSEL[28] = 1

30 GPIO15 PWM1 CPSEL[29] = 1

75 GPIO16 I2S0CK CPSEL[23] = 1

76 GPIO17 I2S0DO CPSEL[23] = 1

77 GPIO18 I2S0DI CPSEL[23] = 1

78 GPIO19 I2S0WS CPSEL[23] = 1

61 GPIO20 I2S1CK CPSEL[24] = 1

60 GPIO21 I2S1DO CPSEL[24] = 1

59 GPIO22 I2S1DI CPSEL[24] = 1

58 GPIO23 I2S1WS CPSEL[24] = 1

49 GPIO24 SIO0SO CPSEL[0] = 1 UART0UO (CPSEL[16] = 1 && CPSEL[15] = 0) or (CPSEL[16] = 1 && CPSEL[15:14] = 11)

50 GPIO25 SIO0SI CPSEL[0] = 1 UART0UI (CPSEL[16] = 1 && CPSEL[15] = 0) or (CPSEL[16] = 1 && CPSEL[15:14] = 10)

51 GPIO26 SIO0SCK CPSEL[0] = 1

52 GPIO27 SIO1SO (CPSEL[1] = 1 && CPSEL[13] = 0) or (CPSEL[1] = 1 && CPSEL[13:12] = 11)

UART1UO CPSEL[17] = 1

53 GPIO28 SIO1SI (CPSEL[1] = 1 && CPSEL[13] = 0) or (CPSEL[1] = 1 && CPSEL[13:12] = 10)

UART1UI CPSEL[17] = 1


55 GPIO30 IN0

56 GPIO31 IN1

81 GPIO32 SIO2SO CPSEL[2] = 1 UART2UO CPSEL[18] = 1

82 GPIO33 SIO2SI CPSEL[2] = 1 UART2UI CPSEL[18] = 1


95 GPIO35 INT00

96 GPIO36 INT01

97 GPIO37 INT02

98 GPIO38 INT03

99 GPIO39 INT04

100 GPIO40 INT05

101 GPIO41 INT06

102 GPIO42 INT07

103 GPIO43 INT08

104 GPIO44 INT09

105 GPIO45 INT10

106 GPIO46 INT11

111 GPIO47 NFRDY CPSEL[10] = 1

134 GPIO48 NFD15 CPSEL[9:8] = 11 SPI1CK CPSEL[6] = 1 SIO4SO CPSEL[4] = 1 UART4UO CPSEL[20] = 1

133 GPIO49 NFD14 CPSEL[9:8] = 11 SPI1DO CPSEL[6] = 1 SIO4SI CPSEL[4] = 1 UART4UI CPSEL[20] = 1

132 GPIO50 NFD13 CPSEL[9:8] = 11 SPI1DI CPSEL[6] = 1 SIO4SCK CPSEL[4] = 1

131 GPIO51 NFD12 CPSEL[9:8] = 11 SPI1CX CPSEL[6] = 1

130 GPIO52 NFD11 CPSEL[9:8] = 11 SIO3SO CPSEL[3] = 1 UART3UO CPSEL[19] = 1

129 GPIO53 NFD10 CPSEL[9:8] = 11 SIO3SI CPSEL[3] = 1 UART3UI CPSEL[19] = 1

128 GPIO54 NFD09 CPSEL[9:8] = 11 SIO3SCK CPSEL[3] = 1

127 GPIO55 NFD08 CPSEL[9:8] = 11 PTRG

126 GPIO56 NFD07 CPSEL[9:8] = 11

125 GPIO57 NFD06 CPSEL[8] = 1







116 GPIO64 NFREX CPSEL[8] = 1 SPI0CK CPSEL[5] = 1

113 GPIO65 NFWEX CPSEL[8] = 1 SPI0DO CPSEL[5] = 1

114 GPIO66 NFCLE CPSEL[8] = 1 SPI0DI CPSEL[5] = 1

115 GPIO67 NFALE CPSEL[8] = 1 SPI0CX CPSEL[5] = 1

112 GPIO68 NFCEX CPSEL[11] = 1

*1 Resource input function should be disabled when corresponding pin is used by other resource

Resource Mux Priority

1st 2nd 3rd 4th



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INARY


12.4.6. NFRDY interrupt register (CNFR) This register is to indicate GPIO related interrupt status.

Address FFF4_2000 + 14h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – – – – – – – NFRE – – – – – – – NFRR/W R R R R R R R R/W R R R R R R R R/W

Initial value X X X X X X X 0 X X X X X X X 0

Bit field Function

No. Name 31-9, 7-1

– Unused bits. Write access is ignored, and read value of these bits is undefined

8 NFRE NFRDY interrupt output enable

0 Detection of interrupts at rising edge of NFRDY is disable (initial value)

1 Detection of interrupts at rising edge of NFRDY is enable

0 NFR NFRDY rising edge is detected This bit is effective only when NFRDY pin function is selected Writing “0” to clear this bit

0 No rising edge is detected at NFRDY pin 1 Rising edge is detected at NFRDY pin



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12.4.7. SD Card clock selection register (CSDMC)

Address FFF4_2000 + 18h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – – – – – – – – – – – – – – – SDCKSR/W R R R R R R R R R R R R R R R R/W


Bit field Function


Write access is ignored, and read value of these bits is undefined 0 SDCKS SD card transfer clock selection bit

To determine the source of SD card transfer clock

0 Divided clock from SD card macro is selected Refer to separated “SD Card controller manual” for details

1 System clock of SD card macro is selected (initial) Refer to “5 Clock and Reset (CRG)” for the details of SD card macro ‘s system clock setting



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INARY


12.4.8. Peripheral data wrapper control register (CDWS) This register is used to control the peripheral data format to accommodate different external data format.

Address FFF4_2000 + 1Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name (Reserved) SDCDWS[1:0] (Reserved) R/W R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W R/W R/W0 R/W0 R/W0 R/W0


Name (Reserved) I2S1DWS[1:0] (Reserved) I2S0DWS[1:0] (Reserved) USBDWS[1:0] (Reserved) R/W R/W0 R/W0 R/W R/W R/W0 R/W0 R/W R/W R/W0 R/W0 R/W R/W R/W0 R/W0 R/W0 R/W0

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field Function

No. Name 31-22 (Reserved) Reserved bit. Always write 0 21-20 SDCDWS[1:0] SD Card data wrap control bit

Half-word data access mode only. Setting “10” and “11” are prohibited 19-14 (Reserved) Reserved bit. Always write 0 13-12 I2S1DWS[1:0] I2S interface 1 data wrap control bit

Enable data wrapper function is effective for all register access of I2S1. 11-10 (Reserved) Reserved bit. Always write 0 9-8 I2S0DWS[1:0] I2S interface 0 data wrap control bit

Enable data wrapper function is effective for all register access of I2S0. 7-6 (Reserved) Reserved bit. Always write 0 5-4 USBDWS[1:0] USB host data wrap control bit

Enable data wrapper function is not effective for any register access in USB. This function is only effective for data access between USB Host and memory.

3-0 (Reserved) Reserved bit. Always write 0

XXXDWS[1:0] 00 Data wrap disabled

Bus master side Resources area (address) 31 - 24 23 -1 6 15 - 8 7 - 0 +3 +2 +1 + 0 Byte 3 Byte 2 Byte 1 Byte 0 ↔ Byte 3 Byte 2 Byte 1 Byte 0

01 Upper/lower byte swapped in each half-word Bus master side Resources area (address)

31 - 24 23 -16 15 - 8 7 - 0 +3 +2 +1 + 0 Byte 3 Byte 2 Byte 1 Byte 0 ↔ Byte 2 Byte 3 Byte 0 Byte 1

Note : Setting for word or half-word access mode only 10 Byte lane reversed

Bus master side Resources area (address) 31 - 24 23 -16 15 - 8 7 - 0 +3 +2 +1 + 0 Byte 3 Byte 2 Byte 1 Byte 0 ↔ Byte 0 Byte 1 Byte 2 Byte 3

Note : Setting for word access mode only 11 Upper / lower half-word swapped

Bus master side Resources area (address) 31 - 24 23 -16 15 - 8 7 - 0 +3 +2 +1 + 0 Byte 3 Byte 2 Byte 1 Byte 0 ↔ Byte 1 Byte 0 Byte 3 Byte 2

Note : Setting for word access mode only



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12-11




12.4.9. CHIP ID register (CCID)

Address FFF4_2000 + 20h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name YEAR[15:0] R/W R R R R R R R R R R R R R R R R


Name CHIPNAME[7:0] VERSION[7:0] R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 1 0 0 0 0 - - - - - - - -

Bit field Function

No. Name 31-16 YEAR[15:0] Date of LSI development is indicated in 4 digit dominical year.

In this LSI, 2009(d) is read. 15-8 CHIPNAME[7:0] LSI identification name is indicated in ID number.

In this LSI, 10(h) is read. 7-0 VERSION[7:0] LSI version is indicated.

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MB9G711 LSI Product Specification

13. External interrupt controller (EXIRC) This chapter describes function and operation of external interrupt controller (EXIRC.)

13.1. Outline An external interrupt controller controls maximum 4 external interrupt request pins. The request level can be selected among 4 settings: "H" level, "L" level, rising edge, and falling edge. In this LSI, three EXIRC are equipped so that total 12 external interrupt pins can be handled.

13.2. Feature EXIRC has following features:

• Operating as bus slave of AMBA (APB) • 4 channels of external interrupt control • 4 input request level selections

• "H" level • "L" level • Rising edge • Falling edge

• Utilization of external interrupt as returning factor from Stop mode

13.3. Usage limitation The external interrupt request pins are sharing with GPIO function. To use as external interrupt function, please set the GPIO as input pin before hand. To set the GPIO as input pin, please refer to the chapter of GPIO.


External Interrupt Controller (EXIRC)

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13.4. Related Pin Three external interrupt controllers use total 12 external pins in this LSI.

Table 13-1 External Interrupt related pin Pin Direction Qty. Description

INT[11:0] IN 12 External interrupt pins.

13.5. Supply clock APB clock is supplied to EXIRC. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.



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13.6. Register This section describes EXIRC register.

13.6.1. Register list Table 13-2 shows EXIRC0/1/2 registers list.

Table 13-2 EXIRC 0/1/2 register list Address


FFFE_3000H + 000H External interrupt enable registerfor pin INT[3:0]

EIENB0 Enable control of external interrupt request output

+ 004H External interrupt request registerfor pin INT[3:0]

EIREQ0 Clear function of external interrupt display and interrupt request

+ 008H External interrupt level register for pin INT[3:0]

EILVL0 Selection of input request level detection of external interrupt

+ 00CH ~

+ 7FFH

Reserved ( Access prohibited )







+ 00CH ~

+ 7FFH








+ 00CH ~

+ 7FFH




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Description format of register Following format is used for description of register’s each bit in "27.5.2 External interrupt enable register (EIENB)" to "27.5.4 External interrupt level register (EILVL)".


Name R/W


Name R/W

Initial value










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13.6.2. External interrupt enable register (EIENBx) This register is to control masking external interrupt request output.

Address EIENB0 : FFFE_3000H + 00H EIENB1 : FFFE_3800H + 00H

EIENB2 : FFFE_4000H + 00H



Name – – – – – – – – – – – – ENB3 ENB2 ENB1 ENB0R/W R/W R/W R/W R/W R/W R/W R/W R/W R0 R0 R0 R0 R/W R/W R/W R/W




Write access is ignored. Read value of these bits is undefined. 7-4 – Unused bit.

Write access is ignored. Read value of these bits is always "0". 3-0 ENB3-0 Masking external interrupt request output is controlled.

0 External interrupt request is disabled 1 External interrupt request is enabled.

When external interrupt request (INT[x]) corresponding to the bit is written “1”, the request (INT[x]) is output to the interrupt controller IRC0/1. For example, ENB0 bit enables input from INT[0] in EXIRC0. When the corresponding bit of external interrupt request is written “0”, the request is not output to the interrupt controller. These bits are initialized to "0000B" by reset.



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13.6.3. External interrupt request register (EIREQx) This register is to indicate and clear external interrupt request.

Address EIREQ0: FFFE_3000H + 04H EIREQ1: FFFE_3800H + 04H

EIREQ2: FFFE_4000H + 04H



Name – – – – – – – – – – – – REQ3 REQ2 REQ1 REQ0R/W R/W R/W R/W R/W R/W R/W R/W R/W R0 R0 R0 R0 R/W0 R/W0 R/W0 R/W0




Write access is ignored. Read value of these bits is undefined. 7-4 – Unused bit.

Write access is ignored. Read value of these bits is always "0". 3-0 REQ3-0 External interrupt request is indicated and cleared.

0 At reading: There is no external interrupt request At writing: External interrupt request is cleared

1 At reading: There is external interrupt request At writing: External interrupt request invalid

Read value of "1" shows external interrupt is requested. These bits correspond to external interrupt channel as follows. EXIRC0 : • REQ0: External interrupt 0 (INT[0] pin) • REQ1: External interrupt 1 (INT[1] pin) • REQ2: External interrupt 2 (INT[2] pin) • REQ3: External interrupt 3 (INT[3] pin) EXIRC1 : • REQ0: External interrupt 0 (INT[4] pin) • REQ1: External interrupt 1 (INT[5] pin) • REQ2: External interrupt 2 (INT[6] pin) • REQ3: External interrupt 3 (INT[7] pin) EXIRC2 : • REQ0: External interrupt 0 (INT[8] pin) • REQ1: External interrupt 1 (INT[9] pin) • REQ2: External interrupt 2 (INT[10] pin) • REQ3: External interrupt 3 (INT[11] pin) When "0" is written to these bits, external interrupt request is cleared. Writing "1" is invalid. These bits are initialized to "0000B" by reset.



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13.6.4. External interrupt level register (EILVLx) This register is to select input request level detection.

Address EILVL0: FFFE_3000H + 08H EILVL1: FFFE_3800H + 08H

EILVL2: FFFE_4000H + 08H



Name – – – – – – – – LVL3[1] LVL3[0] LVL2[1] LVL2[0] LVL1[1] LVL1[0] LVL0[1] LVL0[0]R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W




Write access is ignored. Read value of these bits is undefined. 7-0 LVL3[1:0] - LVL0[1:0] Input request level detection of external interrupt is selected.

2 bit is allocated to each external interrupt channel. This is initialized to "01B" by reset. EXIRC0 : • LVL0[1:0]: External interrupt 0 (INT[0] pin) • LVL1[1:0]: External interrupt 1 (INT[1] pin) • LVL2[1:0]: External interrupt 2 (INT[2] pin) • LVL3[1:0]: External interrupt 3 (INT[3] pin) EXIRC1 : • LVL0[1:0]: External interrupt 0 (INT[4] pin) • LVL1[1:0]: External interrupt 1 (INT[5] pin) • LVL2[1:0]: External interrupt 2 (INT[6] pin) • LVL3[1:0]: External interrupt 3 (INT[7] pin) EXIRC2 : • LVL0[1:0]: External interrupt 0 (INT[8] pin) • LVL1[1:0]: External interrupt 1 (INT[9] pin) • LVL2[1:0]: External interrupt 2 (INT[10] pin) • LVL3[1:0]: External interrupt 3 (INT[11] pin)

LVL3-0[1] LVL3-0[0] Input request level 0 0 "L" Level 0 1 "H" Level 1 0 Rising edge 1 1 Falling edge



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13-8


13.7. Operation External interrupt controller issues request signal to interrupt controller (IRC0/1) when input request level of external interrupt is input to corresponding channel after setting EIENBx and EILVLx registers. If interrupt from this module is higher than interrupt level set in ILM register and it is highest priority as a result of interrupt prioritization occurred in IRQ level decision circuit, IRQ interrupt request is issued to ARM core.

IRC0 (Interrupt Controller 0)

IRQyy

Compare interrupt level

ILM

IRQ External Interrupt Controller

From external pins

Figure 13-1 Operation of external interrupt

13.8. Operation procedure External interrupt register setting procedure is as followings.

1. Disable EIENBx register related bit 2. Set EILVLx register related bit 3. Clear EIREQx register related bit 4. Enable EIENBx register related bit

EIENBx register must be disabled to set register in the module; moreover, EIREQx register needs to be cleared before EIENBx register is enabled. This operation is to prevent accident caused by incidental interrupt source during register setting.

13.9. Instruction for use This section indicates notice for using external interrupt.

Notice for returning from Stop mode When external interrupt is used to return from Stop mode, where clock is stopped, set input request level to "H" since "L" level request may cause malfunction. Moreover, the edge request is not able to return from the Stop mode.

External Interrupt Controller (EXIRC) FUJITSU SEMICONDUCTOR PROPRIETARY AND CONFIDENTIAL

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14. Pulse Width Modulator (PWM) This chapter describes operation and function of PWM (Pulse Width Modulator.)

14.1. Outline This LSI has 4 channels of PWM which is able to output high-precision PWM wave pattern efficiently. Of them two PWM outputs are connected to external port and two are internally for ADC trigger.

14.2. Feature PWM has following features:

• Built-in 4 channels • Individually setting of duty ratio, phase, and polarity • Specifying one-shot output/continuous output of the pulse • External trigger input.

14.3. Block diagram

Tigger to ch0/1/2/3 Pin PTRG

PWM ch0 INT

CLKgenerator AP

B bu

s

PULSE generator

PWM module

AP

B I/F

IRC

Pin PWM0

Pin PWM1

PWM ch1 INT

ADC

PWM_O0

PWM_O3

PWM_O1

PWM_O2 trigger1

trigger2

INCP

Figure 14-1 PWM block diagram

14.4. Related pin PWM uses following pins.

Pin Direction Qty. Description PTRG IN 1 External trigger PWM0 PWM1

OUT 2 PWM0/1 output

PWM pins are common with other peripheral I/O functions. To use those pins as PWM output, set corresponding bits of CPSEL register as following

• Set CPSEL[28] = "1B" for PWM0 • Set CPSEL[29] = “1B" for PWM1


Pulse Width Modulator (PWM)

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14.5. Supply clock APB clock is supplied to PWM. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.

14.6. Interrupt When interrupt factor occurs, PWM notifies it to IRC. Refer to "7. Interrupt controller (IRC)" for more detail.

14.7. Register This section describes PWM register.

14.7.1. Register list This LSI equips 4 channels of PWM, and each of them has register shown in Table 14-1.

Table 14-1 PWM register list Address


FFF4_1000H + 00H PWM ch0 base clock register PWM0BCR Setting base clock of PWM cycle

+ 04H PWM ch0 pulse width register PWM0TPR Setting cycle length of 1 pulse

+ 08H PWM ch0 phase register PWM0PR Setting phase cycle of the pulse

+ 0CH PWM ch0 duty register PWM0DR Setting duty cycle of the pulse

+ 10H PWM ch0 status register PWM0CR Setting PWM such as pulse output format and polarity

+ 14H PWM ch0 start register PWM0SR Setting start/stop of PWM

+ 18H PWM ch0 current count register PWM0CCR Indicating current count value in the BASECLK base

+ 1CH PWM ch0 interrupt register PWM0IR Selecting cause of PWM interrupt factor

+ 20H ~ + 7FH

(Reserved)








+ 1CH PWM ch1 interrupt register PWM1IR Selecting cause of PWM interrupt factor + 20H ~ + 7FH

(Reserved)



+ 08H PWM ch2 place aspect register PWM2PR Setting phase cycle of the pulse





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Address Register Abbreviation Description

Base Offset




+ 20H ~ + 7FH

(Reserved)









+ 20H ~ + 7FH

(Reserved)

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Description format of register Following format is used for description of register’s each bit in "14.7.2 PWMx base clock register (PWMxBCR)" to "14.7.9 PWMx interrupt register (PWMxIR)".


Name R/W


Name R/W

Initial value










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14.7.2. PWMx base clock register (PWMxBCR) This register is to set base clock of PWM cycle.

Address ch0：FFF4_1000 + 00H ch1 : FFF4_1080 + 00H ch2：FFF4_1100 + 00H ch3：FFF4_1180 + 00H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name BCR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-16 - Unused bits.

Write access is ignored, and read value of these bits is undefined.. 15-0 BCR Base clock of the PWM cycle is set.

BCR[15:0] Base clock

0 0 APBCLK (Setting prohibited) 1 1 APBCLK | |

65535 65535 APBCLK



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14.7.3. PWMx pulse width register (PWMxTPR) This register is to set cycle length of 1 pulse.

Address ch0：FFF4_1000 + 04H ch1：FFF4_1080 + 04H ch2：FFF4_1100 + 04H ch3：FFF4_1180 + 04H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name TPR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 15-0 TPR Cycle length of 1 pulse shown in Figure 14-2 is set.

TPR[15:0] Pulse cycle length

0 0 BASECLK (Setting prohibited) 1 1 BASECLK (Setting prohibited) 2 2 BASECLK | |

65535 65535 BASECLK

APBCLK

BASECLK

PWM

Phase Duty

Next cycle (skippable)

Pulse width (1 cycle)

Figure 14-2 Setting parameter



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14.7.4. PWMx phase register (PWMxPR) This register is to set phase cycle of the pulse.




Name PR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 15-0 PR Phase cycle shown in Figure 14-3 is set.

PR[15:0] Phase cycle

0 0 BASECLK (Setting prohibited) 1 1 BASECLK | |

65535 65535 BASECLK

APBCLK

BASECLK

PWM

Phase Duty






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14.7.5. PWMx duty register (PWMxDR) This register is to set duty cycle of the pulse.

Address ch0：FFF4_1000 + 0CH ch1：FFF4_1080 + 0CH ch2：FFF4_1100 + 0CH ch3：FFF4_1180 + 0CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name DR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field Description No. Name 31-16 - Unused bits.

Write access is ignored, and read value of these bits is undefined. 15-0 DR Duty cycle shown in Figure 14-4 is set.

DR[15:0] Duty cycle

0 0 BASECLK (Setting prohibited) 1 1 BASECLK | |

65535 65535 BASECLK

APBCLK

BASECLK

PWM

Phase Duty






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14.7.6. PWMx status register (PWMxCR) This register is to set PWM such as pulse output format and polarity.




Name - ONESHOT EXEDG EXTRG POL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W




Write access is ignored, and read value of these bits is undefined. 3 ONESHOT Pulse output format, either continuous output or one-shot output is set.

0 Continuous output (initial value) 1 One-shot output

2 EXEDG External trigger edge selection bit

PWMxSR.START bit must be “1” to enable external trigger.

0 PWM trigged by falling edge of external trigger pin 1 PWM trigged by rising edge of external trigger pin

1 EXTRG External trigger enable bit. PWMxSR.START bit must be “1” to enable external trigger.

0 External trigger disabled 1 External trigger enabled

0 POL Polarity of the pulse is set.

0 Negative pulse (initial value) 1 Positive pulse



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14.7.7. PWMx start register (PWMxSR) This register is to set PWM start-up/stop.

Address ch0：FFF4_1000 + 14H ch1：FFF4_1080 + 14H ch2：FFF4_1100 + 14H ch3：FFF4_1180 + 14H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name - Reserved STARTR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X X X X X X X X X 0 0

Bit field Description No. Name 31-2 - Unused bits.

Write access is ignored, and read value of these bits is undefined. 1 Reserved Reserved bits

Always write “0” to this bit. Note: Writing “1” to this bit is prohibited.

0 START Start-up/Stop of PWM is set.

0 Stop (initial value)

1 Start-up After pulse cycle ends, this bit is cleared to "0" when ONSHOT bit = 1 of PWMxCR register.



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14.7.8. PWMx current count register (PWMxCCR) This register is to indicate current count value in BASECLK base.




Name CCR[15:0] R/W R R R R R R R R R R R R R R R R




Write access is ignored, and read value of these bits is undefined. 15-0 CCR Current count value in BASECLK base is indicated.

CCR[15:0] Duty cycle

0 0 BASECLK 1 1 BASECLK | |

65535 65535 BASECLK



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14.7.9. PWMx interrupt register (PWMxIR) This register is to select cause of PWM interrupt.

Address ch0：FFF4_1000 + 1CH ch1：FFF4_1080 + 1CH ch2：FFF4_1100 + 1CH ch3：FFF4_1180 + 1CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name - INTREP[1:0] - Reserved DONER/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W1 R/W1

Initial value X X X X X X 0 0 X X X X X X 0 0



Write access is ignored, and read value of these bits is undefined. 9-8 INTREP[1:0] The bit (DONE bit) which might be the cause of PWM interrupt is selected.

INTREP[1:0] Possible cause bit for PWM interrupt

00 DONE bit is not selected 01 DONE bit is selected as cause of interrupt factor 10 (Setting prohibited) 11 (Setting prohibited)

7-2 - Unused bits.

Write access is ignored, and read value of these bits is undefined. 1 (Reserved) Reserved bit.

Writing to this bit is prohibited. The read value of these bits is undefined.. 0 DONE This bit indicates end of 1 pulse cycle.

0 1 pulse is not output (initial value) 1 1 pulse is output

This bit is cleared to "0" by writing "1".



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14-13


14.8. Example of setting register This section describes example of register's initial setting.

Power-on

Set PWMx base clock register (PWMxBCR)

Set polarity (POL) and one-shot (ONESHOT) pulses

Set PWMx pulse width register (PWMxTPR)

Set PWMx phase register (PWMxPR)

Set PWMx duty register (PWMxDR)

Set PWMx status register (PWMxCR)

Set PWMx activation register (PWMxSR) PWM activates

PWMx interrupt register's INTREP bit

Output 1 pulse cycle

Yes

Interrupt occurs

No

PWMxSR start bit = 1Yes

No

End

PWM stops with negating start bit (PWMxSR START bit) at completing pulse cycle, not immediately after negating the start bit

Set each register in the following condition: • PWMx base clock register ≥ 1

• PWMx phase register ≥ 1

• PWMx duty register ≥ 1

• PWMx phase register + PWMx duty register ≤ PWMx pulse width register ≥ 2

(The next phase setting after duty operation is omitted)

Figure 14-5 PWM register initial setting example



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15. D/A converter This chapter describes function and operation of the audio D/A converter.

15.1. Outline This LSI has 1 audio D/A converter and interface.

15.2. Feature • Multi-bit Delta-Sigma D/A converter • Independent clock input for D/A converter’s operation • Stereo or Monaural audio data format supported • 8 x 32 bit FIFO buffer for audio output data (storing up to 8 stages of 16-bit stereo data ) • 2 types of interrupt : output FIFO data request and output FIFO underflow • DMA activate request for output FIFO data request • User defined FIFO usage condition for interrupt or DMA request generation • Mute function by which audio data “0x0000” is sent to Delta-Sigma D/A converter


D/A converter

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15.3. Block diagram

Output FIFO(8 x 32-bit)

32

Inte

rnal

Bus

AP

B

Delta-Sigma D/A Converter

AULOAULCP

AUROAURCP

Control Unit(AUCSR)

FIFO status

InterruptDMA

Data Transfer Unit

L-channel

R-channel

1/n

D/A converterclock (n x fs)

Audio samplingclock (fs)

DAC clock fromclock generation unit

32

CPU write

FIFO read

* n = 256 / 384 / 512

Figure 15-1 Block diagram of D/A converter and I/F

15.4. Related pin D/A converter uses following pins.

Table 1 DA converter related pin Pin Direction Qty. Description

AULO OUT 1 Analog output for left channel AULCP OUT 1 Common voltage for left channel AURO OUT 1 Analog output for right channel AURCP OUT 1 Common voltage for right channel AUVDD IN 1 Analog power supply 1 AUVDL IN 1 Analog power supply 2 AUVSS IN 1 Analog ground

15.5. Supply clock APB clock and DAC clock is supplied to D/A converter. Refer to "5. Clock reset generator (CRG)" and “6. Audio Clock Generator (AUCLKG)” for frequency setting and control specification of the clock.


D/A converter

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15.6. Register This section describes D/A converter register.

15.6.1. Register list This LSI has 1 D/A converter unit and has the register shown in Table 15-2.

Table 15-2 D/A converter register list Address


FFF5_3000H + 000H Audio Output Data Buffer Register AUFIFO A buffer to store the audio output data + 004H Audio Control and Status Register AUCSR To control the audio data output buffer

usage and return the buffer status + 008H

~ + 7FFH



D/A converter

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Name R/W


Name R/W

Initial value









D/A converter

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15.6.2. Audio Output Data Buffer Register (AUFIFO) This register is to store audio output data of Delta-Sigma D/A converted data.

Address FFF5_3000 + 00H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name AUFIFO[31:16] R/W W W W W W W W W W W W W W W W W


Name AUFIFO[15:0] R/W W W W W W W W W W W W W W W W W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-0 AUFIFO[31:0] Digital audio data written to the FIFO should be 2's complement sampled at frequency fs defined

in the register bits Sampling Frequency (AUCSR.FS[3:0]). The FIFO can store up to eight 32-bit data. When the FIFO is full, subsequence write access will not alter the data in the FIFO and extra data will be discarded. When the FIFO is empty, last data presented is transmitted to Delta-Sigma D/A Converter (DAC) until the FIFO is filled. Depending on the settings of Audio Control and Status Register bits (AUCSR: IDF, SEQ, RDF, ENDIAN, MONO), the data stored in the FIFO can be 24-bit audio data, 16-bit audio data, left-to-right channel, right-to-left channel, left justified, right justified, little endian, big endian, stereo or monaural. For details, please refer to the settings in the corresponding section. The following table shows the input data sequence written to the FIFO for both 24-bit audio data (AUCSR.IDF = 0) and 16-bit audio data (AUCSR.IDF = 1) at each setting. When the register bit Input Data Sequence (AUCSR.SEQ) is set to "0", the order of data written to the FIFO is left-to-right channel. When this bit is set to "1", the order of data written to the FIFO is right-to-left channel.

AUCSR register bit Order of data written to the FIFO SEQ IDF (1st data, 2nd data, 3rd data, …)

0 0 L, R , L, R,… 0 1 LR, LR, … 1 0 R, L, R, L,.. 1 1 RL, RL, …

* R: right channel, L: left channel * RL: FIFO bit 31 to 16 is right channel, FIFO bit 15 to 0 is left channel * LR: FIFO bit 31 to 16 is left channel, FIFO bit 15 to 0 is right channel

In case of monaural mode (AUCSR.MONO = 1), the data transfer to Delta-Sigma D/A Converter (DAC) is in first input first output basis for 24-bit audio data (AUCSR.IDF = 0). For 16-bit audio data (AUCSR.IDF = 1), the input data sequence is also determined by the register bit Endian (AUCSR.ENDIAN). The output sequence is lower address data followed by higher address data. The following table shows monaural mode input data sequence and the data transfer from the FIFO to the DAC is M1, M2, M3,.. in order.

AUCSR register bit Order of data written to FIFO ENDIAN IDF (1st data, 2nd data, 3rd data, …)

X 0 M1, M2, M3, … 0 1 M2M1, M4M3, … 1 1 M1M2, M3M4, …

* M2M1: FIFO bit 31 to 16 is 2nd output data, FIFO bit 15 to 0 is 1st output data


D/A converter

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D/A converter


No. Name

* M1M2: FIFO bit 31 to 16 is 1st output data, FIFO bit 15 to 0 is 2nd output data

The number of stages of audio samples stored in the FIFO depends on the audio data format defined in the Audio Control and Status Register (AUCSR: IDF, MONO). For 24-bit audio data, each FIFO register word (32-bit) can store one sample only. So, the FIFO can store 4 stages stereo or 8 stages monaural 24-bit audio samples. For 16-bit audio data, each FIFO register word (32-bit) can store two samples. So, the FIFO can store 8 stages stereo or 16 stages monaural 16-bit audio samples. Note: Since data transfer from the FIFO to the Delta-Sigma D/A converter is asynchronous, stack audio data to the FIFO is recommended. Since the FIFO is cleared by writing "1" to the register bit Initial (AUCSR.INIT), writing to the FIFO should be accomplished after initialization is started (read "1" from AUCSR.INIT). This ensures the data written to the FIFO is not cleared by initialization. For 16 bit mode, the DAC output voltage refer to value of AUFIFO[31:0] data is:

AUFIFO[31:0] DAC output voltage (V) 0x00007FFF AUVDD x 0.8075 0x00000000 AUVDD x 0.5 0x00008000 AUVDD x 0.1925

For 24 bit mode, the DAC output voltage refer to value of AUFIFO[31:0] data is:

AUFIFO[31:0] DAC output voltage (V) 0x007FFFFF AUVDD x 0.8075 0x00000000 AUVDD x 0.5 0x00800000 AUVDD x 0.1925

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15.6.3. Audio Control and Status Register (AUCSR) This register is to control D/A converter operation.

Address FFF5_3000 + 04H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name FFST[3:0] FFCH TSHD2 TSHD1 TSHD0 MUTE DMAE UFIE UF FFRQIE FFRQ – – R/W R R R R R R/W R/W R/W R/W R/W R/W R/W0 R/W R R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name MONO – – FS3 FS2 FS1 FS0 OSR2 OSR1 OSR0 ENDIAN RDF SEQ IDF INIT PDX R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 X X 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-28 FFST[3:0] Audio output data FIFO Status Bit

These bits indicate the usage status of the FIFO in word size. It is incremented by one for each CPU write access on AUFIFO register. Depending on audio data format, FFST[3:0] to be decremented varies: • Decremented by 2 for 24-bit stereo mode • Decremented by 1 for 24-bit monaural mode • Decremented by 1 for 16-bit stereo mode for each data transfer from FIFO to DAC • Decremented by 1 for 16-bit monaural mode for two data transfer from FIFO to DAC

FFST[3:0] FIFO usage (AUFIFO)

0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8

27 FFCH FIFO Current Channel in use

0 Left channel is selected to be written at next CPU write access 1 Right channel is selected to be written at next CPU write access

Note : This bit is valid for 24-bit audio data (AUCSR.IDF = 0) and stereo mode (AUCSR.MONO = 0)


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D/A converter


No. Name 26 - 24 TSHD[2:0] FIFO Data Request Threshold

These bits are used to define the usage of the FIFO at which a data request (AUCSR.FFRQ = 1) is generated. If the usage of the FIFO is less than the threshold setting (AUCSR.TSHD[2:0]), data request is generated

TSHD[2:0] Data request when FIFO usage less than 000 1 (FIFO empty) (initial value) 001 2 010 3 011 4 100 5 101 6 110 7 111 8 (FIFO not full)

Note : Change setting during the operation is prohibited

23 MUTE Mute audio output data

0 Audio data from FIFO is output to DAC (initial value) 1 Data “0” output to DAC and data transfer from the FIFO is stalled

22 DMAE FIFO Data DMA request enable This bit is used to enable DMA activate data request from the FIFO according to the defined FIFO Data Request Threshold (AUCSR.TSHD[2:0]).

0 DMA request not activate when FIFO usage is less that the threshold setting (initial value)

1 DMA request activate when FIFO usage is less than the threshold setting

21 UFIE Underflow Flag Interrupt Enable This bit is used to enable interrupt output when FIFO underflow flag is set

0 No Interrupt output when FIFO underflow occurs (initial value) 1 Interrupt output when FIFO underflow occurs

20 UF Underflow Flag This bit is set to "1" if the data transfer from the FIFO to the DAC occurs when the FIFO is empty. The last audio sample presented in the DAC is outputted again as long as the FIFO is empty. Writing "0" to this bit clears this flag. Writing "1" to this bit has no effect. Note: In 24-bit data stereo mode (AUCSR: IDF=0, MONO=0), if only left or right channel audio data available, the FIFO is considered to be empty and underflow occurs after the transfer. The last audio samples presented in the DAC is outputted again.

19 FFRQIE FIFO Data Request Interrupt Enable

0 No interrupt output when FIFO Data Request Flag is set (initial value) 1 Interrupt output when FIFO Data Request Flag is set

18 FFRQ FIFO Data Request Flag

0 FIFO usage is not less than the threshold setting 1 FIFO usage is less than the threshold setting (initial value)

Note: When the register bit Initial (AUCSR.INIT) is set to "1", FFRQ changes to "1" as the FIFO is cleared during initialization


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D/A converter


No. Name 15 MONO Monaural / Stereo Mode Set

0 Stereo mode is used (initial value) 1 Monaural is used


12-9 FS[3:0] Audio Data Sampling Frequency

FS[3:0] Audio Data Sampling Frequency (KHz) 0000 48 0001 44.1 0010 32 0011 24 0100 22.05 0101 16 0110 12 0111 11.025 1000 8

Others Setting prohibited 8-6 OSR[2:0] DAC Over Sampling Ratio

OSR[2:0] Over sampling ratio D/A converter clock required

000 128 384 x fs 001 128 256 x fs 010 192 384 x fs 011 256 256 x fs 100 384 384 x fs 101 512 512 x fs

Others Setting prohibited fs is Audio data sampling frequency set by FS[3:0]

Note : The D/A converter clock (DACCLK) is generated by other unit. The frequency required is listed here. Refer to “Audio clock Generator” section for the setting of DACCLK frequency generation

5 ENDIAN FIFO register data Endian

0

Audio data stored in FIFO buffer is little endian • The byte data from lower address (A0) to higher address (A3) are stored in FIFO

register as below Bit 31 - 24 23 - 16 15 - 8 7 - 0

Data at FIFO (A3) (A2) (A1) (A0)

1

Audio data stored in FIFO buffer is big endian • The byte data from low address (A0) to higher address (A3) are stored in FIFO

register as below Bit 31 - 24 23 - 16 15 - 8 7 - 0

Data at FIFO (A0) (A1) (A2) (A3)

4 RDF Register Data Alignment

0 Audio data stored in the FIFO buffer is right justified (initial value)

• Only bit 23-0 of FIFO register data is valid

1 Audio data stored in the FIFO buffer is left justified

• Only bit 31-8 of FIFO register data is valid Note: This bit is valid when 24-bit audio data format is used (i.e. AUCSR.IDF = 0)

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D/A converter


No. Name 3 SEQ Audio Data Sequence

0 Audio data sequence is left to right channel (initial value)

1 Audio data sequence is right to left channel

Note : The register bit Input Data Format (AUCSR.IDF) and this bit determines the order of data transmitted from the FIFO to the DAC, see Audio Output Data FIFO (AUFIFO) register for details. This bit is in effect at stereo mode only (register bit MONO = 0).

2 IDF Audio Data Format

0 24-bit audio data is used (initial value)

• Each FIFO stage (32-bit data) store one audio output data

1

16-bit audio data is used • In Stereo Mode, each FIFO stage store left channel and right channel audio

sampling data • In Monaural mode, each FIFO stage two audio sampling data

Bit 31 - 24 23 - 16 15 - 8 7 - 0 ENDIAN = 0 Audio sampling data 2 Audio sampling data 1 ENDIAN = 1 Audio sampling data 1 Audio sampling data 2

1 INIT DAC Initialization Bit

0 Data transfer from the FIFO to the DAC (initial value)

1

The FIFO data is cleared and data "0" is applied to the DAC Note :

The Delta-Sigma DAC requires 300 audio sampling data for initialization. After writing “1”, time duration of 300 audio sampling data (duration depends on the sampling frequency) should be wait before writing “0” (i.e. start data transfer)

Note: When audio Sampling Frequency (AUCSR.FS[3:0]) or Oversampling Ratio (AUCSR.OSR[2:0]) is changed, always write "1" to this bit to start initialization to avoid any abnormal sound output during Delta-Sigma modulator frequency switching Due to asynchronous timing between system bus (APB clock) and the DAC (DAC clock), INIT bit is used to monitor current status in addition to start (write "1") and stop (write "0") initialization. During read, this bit shows whether internal state is in initialization (read "1") or operation (read "0"). Reading "0" after writing "1" to this bit means initialization is not yet started while reading "1" after writing "0" means initialization in progress.

0 PDX DAC Power Down

0 DAC is putted into low power consumption mode (initial value) 1 DAC enable

Note: It is recommended to initialization DAC by writing "1" to register bit “INIT” at the time this bit is set to "1". This guarantees the DAC is initialized properly. If abnormal sound is outputted as a result of uncorrelated audio data is written to the FIFO, writing "0" to this bit is the way to exit abnormal state immediately.

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15.7. Basic operation The basic operation is described in below

15.7.1. Delta-Sigma DAC Initialization In order to avoid abnormal sound output during DAC turn on, changing audio sampling frequency and over-sampling ratio, proper initialization procedure should be followed. Register bit Initial (AUCSR.INIT) is provided to setup the initialization during these scenarios. 1. Turning On Delta-Sigma D/A Converter (DAC)

Enable the DAC clock from clock generation unit with frequency according to the settings of Sampling Frequency (AUCSR.FS[3:0]) and Oversampling Ratio (AUCSR.OSR[2:0]).

Turn on the DAC (AUCSR.PDX: "0" -> "1"), writing "1" to the register bit Initial (AUCSR.INIT) to start initialization procedure along with the settings of Sampling Frequency (AUCSR.FS[3:0]) and Oversampling Ratio (AUCSR.OSR[2:0]) at the same time.

Wait 300 or more sampling cycle (1/fs). During initialization (AUCSR.INIT = 1), data "0" is applied to the DAC.

Write "0" to the register bit Initial (AUCSR.INIT) to stop initialization. Data transfer from the FIFO to the DAC occurs at next sampling cycle.

2. Changing Audio Sampling Frequency and Oversampling Ratio

Write "1" to the register bit Initial (AUCSR.INIT) to start initialization with current Sampling Frequency (AUCSR.FS[3:0]) and Oversampling Ratio (AUCSR.OSR[2:0]) settings.


Change the DAC clock from clock generation unit with frequency according to the new settings of Sampling Frequency (AUCSR.FS[3:0]) and Oversampling Ratio (AUCSR.OSR[2:0]).

Write new settings of Sampling Frequency (AUCSR.FS[3:0]) and Oversampling Ratio (AUCSR.OSR[2:0]) while initialization (AUCSR.INIT = 1).


Write "0" to the register bit Initial (AUCSR.INIT) to stop initialization. Data transfer from the FIFO to the DAC occurs at next sampling cycle.


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15.7.2. Delta-Sigma D/A Converter (DAC) Sampling Frequency and Oversampling Ratio

The DAC reconstructs the digital audio samples based on the settings of register bits Sampling Frequency (AUCSR.FS[3:0]) and Oversampling Ratio (AUCSR.OSR[2:0]). Whenever these settings are changed, write "1" to register bit Initial (AUCSR.INIT) to start initialization. Table 3 shows all possible combinations, other setting is not supported.

Sampling frequency (fs/KHz)

Over-sampling ratio

D/A converter clock*

Register bits settings OSR[2:0] FS[3:0]

48 128 256 x fs

001 0000 24 256 011 0011 44.1 128

384 x fs

000 0001 32 0010 22.05 192 010 0100 16 0101 8 384 100 1000 12 512 512 x fs 101 0110 11.025 0111 * DAC clock from “Audio Clock Generator” unit

Table 2 D/A converter sampling frequency setting

15.7.3. Data Transfer from Audio Output Data FIFO (AUFIFO) to Delta-Sigma D/A Converter (DAC)

The data transfer from the FIFO to the DAC is carried out at a rate defined in the register bits Sampling Frequency (AUCSR.FS[3:0]). Since the CPU writing to the FIFO and the transfer is asynchronous, stack audio data in the FIFO is recommended. Otherwise, FIFO underflow (AUCSR.UF = 1) will occur and abnormal sound will come out. The register bits FIFO Data Request Threshold (TSHD[2:0]) can be used to signal the CPU write as required, adjusting the threshold to balance between the frequency of data request and the buffer size before underflow. Interrupt or DMA can be used for FIFO data request generation.

L1R1 L1R1, L2R2 L2R2 L2R2, L3R3 L3R3

CPU write

Data in FIFO buffer

Sampling cycle

L1R1 L2R2Data to DAC Undefined

Empty

L1, R1Empty1

2345

EmptyEmptyEmptyEmpty

6 Empty7 Empty

0FIFO

L1, R1L2, R21

2345


6 Empty7 Empty

0FIFO

L2, R2Empty1

2345


6 Empty7 Empty

0FIFO

L2, R2L3, R31

2345


6 Empty7 Empty

0FIFO

L3, R3Empty1

2345


6 Empty7 Empty

0FIFO

1 2

3

4

5

1 2 3 4 5 DMA demand transfer is not supported, use block / burst transfer with proper number of transfer count according to the vacancies in the FIFO. The FIFO data request is automatically cleared by CPU write access, and retriggering occurs at around the data transfer from the FIFO to the DAC.


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15-13


15.8. Application Notes Out-of-Band noise should be removed to avoid any unexpected operation of connected analog

amplifier section such as inter-modulated noise in audio band. This DAC has built-in passive LPF, but the attenuation may not be enough for general applications. The use of post LPF is recommended. Second order active filter or higher may be required in some applications.

Pop noise is generated when the power supply turns on/off, and during power-down sequence (AUCSR.PDX: H -> L, L -> H). If the noise is problem, the external mute circuit should be used.

Changing the settings of audio data format (AUCSR: IDF, SEQ, RDF, ENDIAN, MONO) should be performed when the DAC is stopped (AUCSR.PDX = 0) or initialization in progress (AUCSR.INIT = 1).

Due to asynchronous timing between system bus (APB clock) and the DAC (DAC clock), register bit Initial (AUCSR.INIT) is used to monitor current status in addition to start (write "1") and stop (write "0") initialization. During read, this bit shows whether internal state is in initialization (read "1") or operation (read "0"). Reading "0" after writing "1" to this bit means initialization is not yet started while reading "1" after writing "0" means initialization in progress.

15.9. Application Example

15.9.1. Basic Connection Diagram

AUVDL

AUVDD

AUVSS

AULCPAURCP

C6C5

AULO

AURO Post LPF/ Buffer Right channel

Post LPF/ Buffer Left channel

C4 C3

C2 C1

C1,C3: more than 10 F low ESR aluminum electrolytic capacitorsC2,C4: 0.1 F ceramic capacitorsC5,C6: 10 F low ESR tantalum capacitorsImpedance of each power line must be less than 0.5 .

Low noise power supply

15.9.2. Post LPF/ Buffer

AULO or AURO

C1:1nF

+-

OUTPUT

Cut off frequency fc = 1/{2 (R1+Ro)C1} = 1/(2 3200 1 10-9) = 49.7 [kHz]Ro: output resistance of DAC, 200 typical conditionR2 may be required to stabilize the capacitive load.

R2 C2R1:3K


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16. A/D converter This chapter describes function and operation of A/D converter.

16.1. Outline This LSI has 1 A/D converter with total 6 analog input channels.

16.2. Feature • Successive approximation A/D converter. • Minimum conversion time at 5 MHz: 3.4 μs /1 ch (= 0.294 MS/s) • Resolution: 10 bits • Selection of analog input from 6 channels by the program • Converted data storage registers available for six channels • A/D converter can be started by software, timer or PWM output • The clock for A/D converter operation is generated from the “Clock and Reset Unit” independently • There is a function that generates an interrupt when the conversion result of current channel is larger

or smaller than the value set in the AD comparison register

16.3. Block diagram

A/D Converter

Pin ADVIN0 ~ ADVIN6

ADC I/F A/D Converter

AP

B I/F

PWM

PWM_O1

PWM_O3

Timer1

TIMER12MIS.INT

Edge detector

TGS[1:0]

APB bus

CRGADCCLK

Figure 16-1 Block diagram of A/D converter


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16.4. Related pin A/D converter uses following pins.

Table 16-1 A/D converter related pin Pin Direction Qty. Description

ADVIN0~5 IN 6 A/D analog input pin ADVDD IN 1 Analog power supply pin ADVSS IN 1 Analog GND

16.5. Supply clock APB clock and ADCLK are supplied to A/D converter. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.


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16.6. Register This section describes A/D converter register.

16.6.1. Register list This LSI has 1 A/D converter unit and the register are shown in Table 16-2.

Table 16-2 ADC register list Address


FFF5_2000H + 000H ADC control register ADCNT To control the operation ADC + 004H ADC mode register ADMR To control the ADC interrupt, sampling

time and operating mode + 008H ADC Status register ADST Return ADC status + 00CH ADC data register 0 ADD0 ADC data for input channel 0 + 010H ADC data register 1 ADD1 ADC data for input channel 1 + 014H ADC data register 2 ADD2 ADC data for input channel 2 + 018H ADC data register 3 ADD3 ADC data for input channel 3 + 01CH ADC data register 4 ADD4 ADC data for input channel 4 + 020H ADC data register 5 ADD5 ADC data for input channel 5 + 024H (Reserved) + 028H (Reserved) + 02CH ADC lower limit

compare register ADCRL Lower limit of ADC data comparison

+ 030H ADC upper limit compare register

ADCRH Upper limit of ADC data comparison

+ 034H ~ +7FF H

(Reserved)

Note:

Access ADC areas with 32 bit (word.)


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Name R/W


Name R/W

Initial value









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16.6.2. ADC control register (ADCNT) This register is to enable the ADC and control the method of ADC triggering.

Address FFF5_2000 + 00H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name Reserved APDC STG[1:0] TGS[1:0] XPD STRG Reserved Reserved ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0R/W R/W0 R/W R/W R/W R/W R/W R/W R0/W R/W0 R/W0 R/W R/W R/W R/W R/W R/W

Initial value 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 15 (Reserved) It is a reserved bit.

Always write “0” to this bit. 14 APDC Automatic ADC power down control

It is used to control the ADC whether automatic power down in single conversion mode

0 Enable automatic power down (initial value) • XPD clear to “0” on completion of single conversion mode (ADMR.MD = 00)

1 Disable automatic power down • XPD not change on completion of single conversion mode (ADMR.MD = 00)

13-12 STG[1:0] ADC start trigger select It is used to determine how ADC starts

STG[1:0] ADC start method 00 No AD conversion start 01 Start AD conversion by timer trigger 10 Start AD conversion by software (initial value) 11 Start AD conversion by the timer trigger or software

11-10 TGS[1:0] ADC timer trigger select To determine which timer trigger starts AD conversion if timer trigger method is selected bySTG[1:0]

TGS[1:0] Timer trigger selected 00 No AD conversion start 01 Timer 1 ch-2 interrupt output triggers AD conversion 10 PWM ch-2 output triggers AD conversion 11 PWM ch-3 output triggers AD conversion

Note: If TGS[1:0] is “10” or “11”, the PWM pulse width must be at least 2 x ADCLK to trigger AD conversion.

9 XPD ADC power down To power down the ADC

0 ADC power down (initial value) 1 ADC power on

Note: • 1us should be waited after ADC power on before starting AD conversion


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A/D converter


No. Name 8 STRG Software Trigger bit

To start AD conversion by writing “1” to this bit if software trigger start method is selected by STG[1:0] (STG = 10 or 11). If "0" is written to it, the operation stops.

7-6 Reserved Reserved bit Always write “0” to these bit

5 ADCS5 AD channel 5 conversion enable AD conversion on analog input ADVIN5 is allowed

0 ADVIN5 AD conversion not allow (initial value) 1 ADVIN5 AD conversion allow











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16.6.3. ADC mode register (ADMR) This register is to control A/D interrupt, operating mode and sampling and hold time.

Address FFF5_2000 + 04H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – INTE INTEH INTEL MD[1:0] STS[7:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X X 0 0 0 0 0 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 12 INTE Interrupt output for INTF flag

To control interrupt output when ADST.INTF is set to “1”

0 No Interrupt output when ADST.INTF is set “1” (initial value) 1 Interrupt output when ADST.INTF is set to“1”

11 INTEH Interrupt output for INTH flag To control interrupt output when ADST.INTH is set to “1”

0 No interrupt output when ADST.INTH is set to “1”(initial value) 1 Interrupt output when ADST.INTH is set to “1”

10 INTEL Interrupt output for INTL flag To control interrupt output when ADST.INTL is set to “1”

0 No interrupt output when ADST.INTL is set to “1”(initial value) 1 Interrupt output when ADST.INTL is set to “1”


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No. Name 9-8 MD[1:0] Conversion mode select

To select ADC conversion mode

00

Single conversion mode (initial value) • AD channels enable by register bit ADCNT.ADCS5~0 are sampled and

converted in turn in ascending order. Conversion will be stopped and register bit ADST.INTF is set when completion of all enabled channel conversion. e.g. when ADCS0~5 = 111111 ch0 -> ch1 -> ch2 -> ch3 -> ch4.-> ch5 -> stop)

• ADC will power down on completion if ADCNT.APDC = 0 • Another conversion will started when selected trigger event (selected by

ADCNT.STG) happen if ADC not power down (i.e. ADCNT.XPD = 0)

01

Continuous conversion mode • 1 AD channel enabled by ADCNT.ADCS5~0 is sampled and converted

continuously • Reading AD data of corresponding AD channel (i.e. register ADDn) is

reading the last conversion data • If more than 1 AD channel are enabled in ADCNT.ADCS5~0, following

AD channel priority will be applied ch5 > ch4 > ch3 > ch2 > ch1 > ch0

• Register bit ADST.INTF does not change

10

Continuous conversion with lower limit comparison mode • Operation same as Mode “01” • Register bit ADST.INTL is set to “1” if AD conversion data (ADDx) is less

than the value of register ADCRL

11

Continuous conversion with upper limit comparison mode • Operation same as Mode “01” • Register bit ADST.INTH is set to “1” if AD conversion data (ADDx) is

larger than the value of register ADCRH

7-0 STS[7:0] ADC Sampling timing setting To set the sampling and hold time for AD converter operation Sampling time = 1/fADCCLK x (STS[7:0] + 1) Note: • Sampling time must large than 1μs • fADCCLK must not higher than 5MHz

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16.6.4. ADC Status register (ADST) This register is to return the ADC status.

Address FFF5_2000 + 08H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – RWB – CS[2:0] INTF INTH INTL BUSY R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R R R/W0 R/W0 R/W0 R

Initial value X X X X X X X 0 X X X X 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 8 RWB Register write busy

Indicate register update in progress 0 No register update in progress (initial value) 1 Register update in progress, further write access is prohibited.

7 – Unused bits. Write access is ignored, and read value of these bits is undefined.

6-4 CS[2:0] Current conversion channel Indicate which AD channel which is being converted

000B Channel 0 001B Channel 1 010B Channel 2 011B Channel 3 100B Channel 4 101B Channel 5 110B Undefined 111B Undefined

3 INTF End of conversion interrupt request flag To indicate the completion of conversion in single conversion mode (ADMR.MD = 00) Note : • Write “0” to clear the bit • Write “1” has no effect

2 INTH Upper limit detected interrupt request flag To indicate AD conversion data exceed the value of register ADCRH in continuous conversion mode (ADMR.MD = 10) Note : • Write “0” to clear the bit • Write “1” has no effect

1 INTL Lower limit detected interrupt request flag To indicate AD conversion data exceed the value of register ADCRL in continuous conversion mode (ADMR.MD = 11) Note : • Write “0” to clear the bit • Write “1” has no effect

0 BUSY ADC converter busy flag To indicate AD conversion is in progress

0B No AD conversion started 1B AD conversion in progress


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16.6.5. ADCx data registers (ADDx) These registers return the AD conversion result of corresponding channels.

Address FFF5_2000 + 0CH ~ 20H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – ADDT[9:0] R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R




Write access is ignored, and read value of these bits is undefined. 9-0 ADDT[9:0] ADCx conversion data


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16.6.6. ADC data lower limit compare register (ADCRL) This registers set the lower limit of ADC data for interrupt generation.

Address FFF5_2000 + 2CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – ADCL[9:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X 0 0 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 9-0 ADCL[9:0] Lower limit value of ADC data

16.6.7. ADC data upper limit compare register (ADCRH) This registers set the upper limit of ADC data for interrupt generation.

Address FFF5_2000 + 30H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – ADCH[9:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X 0 0 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 9-0 ADCH[9:0] Upper limit value of ADC data


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16-12



A/D converter

16.7. Notes on Application 1. ADC operating clock ADCLK should not exceed 5MHz although CRG able to generate a clock of

higher frequency 2. Do not change register bit ADCNT.ADCS5~0, ADMR.MD[1:0] during AD conversion 3. Timer trigger signal is generated from other module. Refer to corresponding section for the details of

setting. 4. Check register bit ADST.RWB = 0 before writing to ADC registers as internal register is updated at

ADCLK which is different from APB bus I/F clock

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17. SIO interface This chapter describes function and operation of SIO.

17.1. Outline SIO is synchronous transmission/reception serial interface which is controllable by the program. This LSI equips 5 channels of SIO.

17.2. Feature SIO has following features:

• The length of transfer data is fixed at 8 bits. • The LSB first format or MSB first format can be selected as the data transfer format. • Receiving and sending take place simultaneously. (A decision to send or receive is required on the

part of the user.) • An interrupt request can be generated at the end of a transfer

17.3. Block diagram

MD - - - DIV3 DIV2 DIV1 DIV0

SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT - - - - BDS -MODE

Communication

prescaler

Control circuitShift clock

counter(SIOCK)

Serial data register

(SDR)

ReadWrite(PORT)

(SIOOUT)

(SIOIN)

Interrupt request

Clock for

peripheral macro

APB Bus

(MSB First)D7-D0

D0-D7(LSB first)

Transfer direction

selection

Serial mode control

status regiser (SMCS)

Communication prescaler register (CDCR)

SCOE

(PORT)

(PORT)

Figure 17-1 Block diagram of SIO interface


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17.4. Related pin SIO uses the following pins.

Table 17-1 SIO related pin Pin Direction Qty. Description

SIOIN0 SIOIN1 SIOIN2 SIOIN3 SIOIN4

IN 5 Input pin of serial data. The number at the end of pin shows channel number of SIO.

SIOOUT0 SIOOUT1 SIOOUT2 SIOOUT3 SIOOUT4

OUT 5 Output pin of serial data. The number at the end of pin shows channel number of SIO.

SIOCK0 SIOCK1 SIOCK2 SIOCK3 SIOCK4

IO 5 Serial data shift clock The number at the end of pin shows channel number of SIO

17.5. Supply clock APB clock is supplied to SIO. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.


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17.6. Register This section describes SIO interface module's register.

17.6.1. Register list The LSI has 5 channels of SIO interface unit, and each module has the register shown in Table 17-2 SIO register list.

Table 17-2 SIO register list Channel Address Register Abbreviation Description

Base Offset SIO ch0 FFFE_1800H + 000H Serial Mode Control

Status Register SIO0SMCS To control the operating mode

and interrupt of SIO + 004H Serial Data Register SIO0SDR SIO transmit and receive data + 008H Communication Prescaler

Register SIO0CDCR To enable the SIO shift clock

prescaler + 00CH

~ +7FF H

(Reserved)

SIO ch1 FFFE_2800H + 000H Serial Mode Control Status Register

SIO1SMCS To control the operating mode and interrupt of SIO

+ 004H Serial Data Register SIO1SDR SIO transmit and receive data + 008H Communication Prescaler


prescaler + 00CH

~ +7FF H

(Reserved)

SIO ch2 FFF5_0800H + 000H Serial Mode Control Status Register




prescaler + 00CH

~ +7FF H

(Reserved)





prescaler + 00CH

~ +7FF H

(Reserved)





prescaler + 00CH

~ +7FF H

(Reserved)

Note:

SIO's registers are able accessed in 32 bit.


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Description format of register Following format is used for description of register’s each bit in "17.6.2 Serial Mode Control Status Register (SIOxSMCS)" to "17.6.4 Communication Pre-scalar (SIOxCDCR)".


Name R/W


Name R/W

Initial value









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17.6.2. Serial Mode Control Status Register (SIOxSMCS)

Address

ch0 FFFE_1800 + 00h ch1 FFFE_2800 + 00h ch2 FFF5_0800 + 00h ch3 FFF5_1800 + 00h ch4 FFF4_3800 + 00h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name SMD[2:0] SIE SIR BUSY STOP STRT – MODE BDS Reserved SCOER/W R/W R/W R/W R/W R/W R R/W R0/W R/W R/W R/W R/W R/W R/W W0 R/W

Initial value 0 0 0 0 0 X 1 0 X X X X 0 0 0 0

Bit No. Bit name Function 31-16 – Unused bits.

Write access is ignored, and read value of these bits is undefined. 15-13 SMD[2:0] Shift clock selection bit

To determine the SIO shift clock frequency (fsck)

000 fsck = Internal shift clock / 2 (initial value) 001 fsck = Internal shift clock / 4 010 fsck = Internal shift clock / 16 011 fsck = Internal shift clock / 32 100 fsck = Internal shift clock / 64 101 fsck = External pin SIOCKx

Others Setting prohibited Note : Internal shift clock is defined by “Communication Prescaler Register CDCR”

12 SIE Interrupt enable Bit To enable the SIO interrupt output

0 Disable SIO interrupt output when SIR is set (initial value) 1 Enable SIO interrupt output when SIR is set

11 SIR SIO transmission and reception end flag To indicate the end of SIO transmission or reception

0 SIO is either stopped or sending / receiving data (initial value) 1 End of sending / receiving data

Note : If the MODE bit of the SMCS register is set to "0", writing "0" to this bit clears it. If the MODE bit of the SMCS register is set to "1", this bit is cleared to "0" when the serial data register is either read or written.

10 BUSY Transmission and reception status bit To indicate the status of transmission and reception.

0 Transmission and reception is not in progress (initial value) 1 Transmission and reception is in progress

9 STOP Stop bit To terminate the transmission and reception process. SIO enters into Stop state

0 Enable transmission and reception


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SIO interface

Bit No. Bit name Function

1 Terminate transmission and reception (initial value)

8 STRT Start bit To start the transmission and reception process if register bit MODE = “0”

0 Invalid (initial value)

1 Starts transmission and reception • Writing “1” when SIO is in transmission and reception process

has no effect


3 MODE SIO start mode To determine the method of starting SIO

0 SIO start transmission and reception if SMCS:STRT is written “1” (initial value)

1 SIO starts transmission and reception if SDR is read or written

2 BDS Transmission and reception data format select bit To determine format of serial data register SDR

0 LSB is sending and receiving first 1 MSB is sending and receiving first

1 Reserved Reserved bit Write value is always "0".

0 SCOE Shift clock output enable bit To control the shift clock output to external SIOCKx pin

0 External pin SIOCKx is used shift clock input (initial value) 1 External pin SIOCKx is used as shift clock output

17.6.3. Serial Data register (SIOxSDR)

Address




Name – DATA[7:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W



Write access is ignored, and read value of these bits is undefined. 7-0 DATA[7:0] Serial data register

To store the data of transmission and reception • When the register is read, SDR returns the serial data received • When the register is written, SDR holds output data and transmission to SIOOUTx pin

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17.6.4. Communication Pre-scalar (SIOxCDCR)

Address




Name – MD – DIV[3:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X X X 0 X X X 1 1 1 1


Write access is ignored, and read value of these bits is undefined. 7 MD Communication Pre-scalar Enable

To enable the internal pre-scalar

0 Disable Communication clock pre-scalar (initial value) 1 Enable Communication clock pre-scalar

Note: SIO macro may behave abnormally when the AC timing requirement (minimum clock width) is not meet.


3-0 DIV[3:0] Internal communication clock division ration To set the clock division ratio of the communication pre-scalar Pre-scalar clock frequency fpsck = APB clock frequency / ( 15 – DIV[3:0] + 1 ) Note : Setting DIV[3:0] = “1111” is prohibited SIO macro may behave abnormally when the AC timing requirement (minimum clock width) is not meet.


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17.7. Operation Description

17.7.1. Operating States of the SIO Interface The SIO interface has four operating states: STOP state, HALT state, SDR reading/writing state, and transmission and reception state.

Figure 17-2 Operation state SIO interface

BUSY=0

STRT=0

STOP=0

BUSY=0

BUSY=1

STRT=0

STOP=0

BUSY=0

STRT=1

STOP=0

BUSY=0

STOP state

SDR reading/

writing standby

state

MODE=0

STOP=1

STOP=0STOP=0 &

STRT=1

SDR reading/writing

(BUSY=0)

STOP=1

STOP=0

STRT=1(BUSY=0)

STOP=1

Reset

HALT state

STOP state End of receiving

and transmission

MO

DE

=1

MO

DE

=1

MO

DE

=0

MO

DE

=0

End of receiving

and transmission Reception andtransmission state

STOP=0 &

STRT=1

STOP=0STRT=0

STRT=1

STOP=0

STOP State After the peripheral macro is reset, the SIO interface enters the STOP state. If the stop bit of the serial mode control status register (SMCS: STOP) is set to "1", the SIO interface also enters the STOP state. If the SIO interface enters the STOP state, the shift clock counter is initialized, the SIO transmission and reception end flag bit of the serial mode control status register (SMCS: SIR) is cleared to "0". The SIO interface returns from the STOP state to the transmission and reception state according to the setting of the starting state select bit of the serial mode control status register (SMCS: MODE) as shown below. When MODE is set to "0", set the stop bit and start bit of the serial mode control status register (SMCS: STOP, STRT) to "0" and "1" respectively. When MODE is set to "1", set the stop bit and start bit of the serial mode control status register (SMCS: STOP, STRT) to "0" and "1" respectively. Then the serial data register (SDR) is read or data are written to it. As the stop bit (SMCS: STOP) has priority over the start bit, if the stop bit is set to "1", no data transmission and reception is executed even the start bit is set to "1"

HALT State


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With the starting state select bit (SMCS: MODE) set to "0", which means the SIO interface is started by the setting of the start bit, when data transmission and reception ends, the SIO interface enters the HALT state. When data transmission and reception ends, the transmission and reception state bit (SMCS: BUSY) is cleared to "0", the SIO transmission and reception end flag bit (SMCS: SIR) is set to "1", the shift clock counter is initialized, and the SIO interface enters the HALT state. If SIO interrupts are enabled (SMCS: SIE="1"), interrupts will be generated. To recover the SIO interface from the HALT state to the transmission and reception state, set the start bit (SMCS: STRT) to "1".

SDR Read/Write Standby State With the starting state select bit (SMCS: MODE) set to "1", which means the SIO interface is started by the reading/writing to the serial data register (SDR), when data receiving and writing ends, the SIO interface enters the SDR reading/writing standby state. When data transmission and reception ends, the transmission and reception state bit (SMCS: BUSY) is cleared to "0", the SIO transmission and reception end flag bit (SMCS: SIR) is set to "1", and the SIO interface enters the SDR reading/writing standby state. If SIO interrupts are enabled (SMCS: SIE="1"), interrupts will be generated. To recover the SIO interface from the SDR reading/writing standby state to the transmission and reception state, read or write data to the serial data register (SDR).

Transmission and Reception State When data transmission and reception ends, the SIO interface enters the HALT state or the SDR reading/writing standby state according to the setting of the starting state select bit.

17.7.2. Interrupt In the SIO interface, after the end of data transmission and reception, interrupt requests can be made.

Generation of interrupt After data transmission and reception ends, the SIO transmission and reception end flag bit (SMCS: SIR) of the serial mode control status register is set to "1", and interrupt requests are made if interrupts are enabled (SMCS: SIE="1").

Clearing of interrupt An interrupt is cleared under the following conditions.

The starting state select bit (SMCS: MODE) and the SIO transmission and reception end flag bit (SMCS: SIR) are both set to "0".

The starting state select bit is set to "1"; the serial data register (SDR) is read or data are written to it. The peripheral macro is reset or the stop bit (SMCS: STOP) is set to "1".

17.7.3. Operating Timing of the SIO Interface The transmission and reception state bit (SMCS: BUSY) of the serial mode control status register is set to "1" during the transmission and reception of data, and to "0" when the SIO interface is in the HALT state or the SDR reading/writing standby state. To check the state of data transmission and reception, read the transmission and reception state bit (SMCS: BUSY) of the serial mode control status register. The starting and ending timings of data transmission and reception in each mode


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Internal shift clock mode (LSB first)

SIOCK pin

(This bit always

reads "0".)

"1" is output

Data receiving and

transmission starts

Data receiving and

transmission ends

When MODE="0"

D07 (data retained)DO0 ...SIOOUT pin

BUSY bit

STRT bit"1" is written

DO7~DO0: Indicate output data bits

External shift clock mode (LSB first)

SIOCK pin

STRT bit

BUSY bit

SIOOUT pin


D07 (data retained)...DO0

(This bit alwaysreads "0".)

Data receiving and

transmission starts

Data receiving and

transmission ends

When MODE="0""1" is written

External shift clock mode with a shift clock supplied by the program SIOCK pin

STRT bit

BUSY bit

SIOOUT pin

DO7~DO0: Indicate output data bit

D07 (data retained)... DO6

SIOCK bit of PDR "0"SIOCK bit of PDR "1"

SIOCK bit of PDR "0"


Data receiving and

transmission ends

When MODE="0"

Forced stop with stop bit

SIOCK pin

STRT bit

BUSY bit

STOP bit

SIOOUT bit


... D05 (data retained)DO3 DO4


"1" is output

Data receiving and

transmission starts Forced stop

When MODE="0""1" is written


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17-11


Timing of Serial Data I/O

During the transfer of serial data, data are output from the serial data output pin (SIOOUT) at a falling edge of the shift clock, and are input from the serial data input (SIOIN) at a rising edge of the shift clock.

SIOCK pin

SIOOUT output

at the falling edge

SIOIN pin

SIOOUT pin

SIOIN input

at the rising edge

DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7

DI7~DI0: Indicate input data bits


17.8. Notes on Application Note the following points when using the SIO interface.

Discrepancy at the start of data transmission and reception Since the shift clock and the start of data transmission and reception by the start bit (SMCS: STRT="1") are not synchronous, there will be a delay of up to one cycle in the shift clock set before the first serial data are input/output.

Malfunction due to noise If unwanted pulses (pulses which exceed the hysteresis width) are introduced into the shift clock due to noise from the external during the transmission and reception of data, proper operations of the SIO interface cannot be guaranteed.

Notes on program setting When stop bit of serial mode control status register (SMCS: STOP) is “0”, only the serial data register (SDR), start bit (STRT) and stop bit (STOP) of serial mode control status register (SMCS) can be written. Other bit and registers can only be written when stop bit of serial mode control status register (SMCS:STOP) is “1”. If the forced stop of data transmission and reception (SMCS: STOP="1") and the end of data transmission and reception occur at the same time, the SIO transmission and reception end flag bit (SMCS: SIR) is not set. The SIO interface does not have an error detection function. Try to use the SIO interface with a timer or check data whenever necessary. The SIO interface does not have any data buffer. If the shift clock operates at high speed or multiple interrupts are used, the interrupt of the SIO interface must be given priority.

Idle state of the shift clock In external shift clock mode (SMCS: SMD[2:0]="101"), set the external shift clock for the transfer of 8-bit data and the waiting time during the data transfer (idle state) to "H" level. In internal shift clock mode (SMCS: SMD[2:0]="000", "001", "010", "011", "100"’), if the output of the shift clock is set at the port, "H" level is output in the idle state.


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18. UART interface This chapter describes function and operation of UART.

18.1. Outline UART is asynchronous transmission/reception serial interface which is controllable by the program. This LSI equips 5 channels of UART.

18.2. Feature UART has following features:

• Programmable baud rate (baud rate is selectable arbitrarily based on APB clock) • 16 byte transmission FIFO and 16 byte reception FIFO

18.3. Block diagram Figure 18-1 shows block diagram of UART.

IRC0/1

DMAC

Baud rate generator

Register

Transmitter FIFO shift

Modem I/F CPU I/F

Receiver FIFO shift

INTR

XTXRDY

XRXRDY

UART_SOUT0

UART_SIN0

APB bus

UART ch4

UART ch0

UART_SOUT4

UART_SIN4

This LSI

UART ch1 UART_SOUT1

UART_SIN1

Figure 18-1 Block diagram of UART


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18.4. Related pin UART uses the following pins.

Table 18-1 UART related pin Pin Direction Qty. Description

UART_SIN0 UART_SIN1 UART_SIN2 UART_SIN3 UART_SIN4

IN 5 Input pin of serial data. The umber at the end of pin shows channel number of UART.

UART_SOUT0 UART_SOUT1 UART_SOUT2 UART_SOUT3 UART_SOUT4

OUT 5 Output pin of serial data. The number at the end of pin shows channel number of UART.

18.5. Supply clock APB clock is supplied to UART. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.


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18.6. Register This section describes UART interface module's register.

18.6.1. Register list The LSI has 5 channels of UART interface unit, and each module has the register shown in Table 18-2.

Table 18-2 UART register list Channel Address Register Description

UART ch0 FFFE1000h URT0RFR Reception FIFO register (read only) that is valid in DLAB = 0

URT0TFR Transmission FIFO register (write only) that is valid in DLAB = 0

URT0DLL Divider latch (low order byte) register that is valid in DLAB = 1 FFFE1004h URT0IER Interrupt enable that is valid in DLAB = 0.

URT0DLM Divider latch (high order byte) register that is valid in DLAB = 1 FFFE1008h URT0IIR Interrupt ID register (read only)

URT0FCR FIFO control (write only) FFFE100Ch URT0LCR Line control register FFFE1010h URT0MCR Modem control register FFFE1014h URT0LSR Line status register (read only) FFFE1018h URT0MSR Modem status register (read only)

UART ch1 FFFE2000h URT1RFR Reception FIFO register (read only) that is valid in DLAB = 0


URT1DLL Divider latch register (low order byte) that is valid in DLAB = 1 FFFE2004h URT1IER Interrupt enable that is valid in DLAB = 0.

URT1DLM Divider latch (high order byte) register that is valid in DLAB = 1 FFFE2008h URT1IIR Interrupt ID register (read only)

URT1FCR FIFO control (write only) FFFE200Ch URT1LCR Line control register FFFE2010h URT1MCR Modem control register FFFE2014h URT1LSR Line status register (read only) FFFE2018h URT1MSR Modem status register (read only)

UART ch2 FFF50000h URT2RFR Reception FIFO register (read only) that is valid in DLAB = 0


URT2DLL Divider latch (low order byte) register that is valid in DLAB = 1

FFF50004h URT2IER Interrupt enable that is valid in DLAB = 0.

URT2DLM Divider latch (high order byte) register that is valid in DLAB = 1 FFF50008h URT2IIR Interrupt ID register (read only)

URT2FCR FIFO control (write only)

FFF5000Ch URT2LCR Line control register

FFF50010h URT2MCR Modem control register

FFF50014h URT2LSR Line status register (read only)

FFF50018h URT2MSR Modem status register (read only) UART ch3 FFF51000h URT3RFR Reception FIFO register (read only) that is valid in DLAB = 0


URT3DLL Divider latch (low order byte) register that is valid in DLAB = 1


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UART interface

Channel Address Register Description FFF51004h URT3IER Interrupt enable that is valid in DLAB = 0.


URT3FCR FIFO control (write only)

FFF5100Ch URT3LCR Line control register

FFF51010h URT3MCR Modem control register

FFF51014h URT3LSR Line status register (read only)

FFF51018h URT3MSR Modem status register (read only) UART ch4 FFF43000h URT4RFR Reception FIFO register (read only) that is valid in DLAB = 0


URT4DLL Divider latch (low order byte) register that is valid in DLAB = 1 FFF43004h URT4IER Interrupt enable that is valid in DLAB = 0.


URT4FCR FIFO control (write only) FFF4300Ch URT4LCR Line control register FFF43010h URT4MCR Modem control register FFF43014h URT4LSR Line status register (read only) FFF43018h URT4MSR Modem status register (read only)

DLAB: Bit7 of Line control register (LCR)

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Note: Although UART's register length is 8 bit, each register except RFR, TFR, and DLL should be accessed in 32 bit. PER, TFR, and DLL are able to be accessed in both 32 bit and 8bit lengths; however, note that 8 bit length access is different since register address is endian dependent.

Description format of register Following format is used for description of register’s each bit in "18.6.2 Reception FIFO register (URTxRFR)" to "18.6.11 Divider latch register (URTxDLL&URTxDLM)".


Name R/W


Name R/W

Initial value









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18.6.2. Reception FIFO register (URTxRFR)

Address ch0：FFFE_1000 + 00h ch1：FFFE_2000 + 00h ch2：FFF5_0000 + 00h

ch3：FFF5_1000 + 00h ch4：FFF4_3000 + 00h (Reading is enabled only at DLAB = 0)



Name (Reserved) RFR[7:0] R/W R R R R R R R R R R R R R R R R


Bit No. Bit name Function 31:8 Unused Reserved bit

7-0 RFR[7:0]

This is FIFO register that is able to maintain up to 16 byte. Reception data is acquired and maintained at the end of reception sequence. This register can be reset by system reset and FCR bit 1 (RxF RST). After reset, this field becomes 00h. RFR register becomes valid at DLAB = 0, and DLL register is assigned at DLAB = 1. RFR register becomes valid only at reading register, and data is written to TFR register (at DLAB =0) or DLL register (at DLAB = 1) according to the setting value of DLAB when writing.

18.6.3. Transmission FIFO register (URTxTFR)


ch3：FFF5_1000 + 00h ch4：FFF4_3000 + 00h (Writing is enabled only at DLAB = 0)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) R/W W W W W W W W W W W W W W W W W


Name (Reserved) TFR[7:0] R/W W W W W W W W W W W W W W W W W


Bit No. Bit name Function 31:8 Unused Reserved bit (input "0" at writing)

7:0 TFR[7:0]

This is FIFO register that is able to maintain up to 16 byte. Data is maintained in this register until being transmitted to the Transmission shift register. This register can be reset by system reset and FCR bit 2 (RxF RST). After reset, this field becomes 00h. This register is write only; however, reading operation reads RFR register (at DLAB = 0) or DLL register (at DLAB = 1) according to setting value of DLAB.


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18.6.4. Interrupt enable register (URTxIER)


ch3：FFF5_1000 + 04h ch4：FFF4_3000 + 04h (Accessing is enabled only at DLAB = 0)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name (Reserved) (Reserved) EDSSI ELSI ETBEI ERBFIR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W



3 EDSSI Enable Modem Status Interrupt When EDSSI is set to "1" and bit3:0 of the Modem status register is set, interrupt occurs.

2 ELSI Enable Receiver Status Interrupt When ELSI is set to "1" and bit4:1 of the Line status register is set, interrupt occurs.

1 ETBEI Enable Transmitter FIFO Register Empty Interrupt After ELSI is set to "1", interrupt occurs when Transfer FIFO register becomes empty.

0 ERBFI Enable Receiver FIFO Register When ERBFI is set to "1" and reception FIFO reaches to the trigger level, interrupt occurs. (Interrupt also occurs when character time-out occurs.)

Interrupt can be disabled by setting "0" to all bits of bit3:0. All interrupt factors of the bit set "1" in bit3:0 become valid.


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18.6.5. Interrupt ID register (URTxIIR)

Address ch0：FFFE_1000 + 08h ch1：FFFE_2000 + 08h ch2：FFF5_0000 + 08h ch3：FFF5_1000 + 08h ch4：FFF4_3000 + 08h



Name (Reserved) FIFO ST1

FIFO ST0 (Reserved) ID2 ID1 ID0 NINT

R/W R R R R R R R R R R R R R R R R Initial value X X X X X X X X 1 1 0 0 0 0 0 1


31:8 Unused Reserved bit (input "0" at writing)

7:6 FIFO1:0 FIFO status Fixed to "11"

5:4 "00"

3:0 ID2:0, NINT

Interrupt setting 0001: No interrupt 0110: Reception line status (1) Top priority 0100: Reception data equal to trigger level (2) 1100: Time-out (2) 0010: Transmission FIFO is empty (3) 0000: Modem status (4)

* Bit7:0 = C1h, after the reset * Numerical value in ( ) is priority level When character time-out interrupt occurs with having received data, ID2:0, NINT is changed from 0100 to 1100. Interrupt signal (INTR) is cleared by the following operation. Priority level:

(1) Read Line status register (LSR) (2) Read reception FIFO (3) Read Interrupt ID register (IIR) or write to transmission FIFO (4) Read Modem status register (MSR)


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18.6.6. FIFO control register (URTxFCR)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) R/W W W W W W W W W W W W W W W W W


Name (Reserved) RCVR1 RCVR0 (Reserved) DMA MODE

TxF RST

RxF RST

(Reserved)

R/W W W W W W W W W W W W W W W W W Initial value X X X X X X X X 0 0 0 0 0 0 0 0


31:8 Unused Reserved bit (input "0" at writing)

7:6 RCVR1:0

Reception FIFO's trigger level 00: 1 byte 01: 4 byte 10: 8 byte 11: 14 byte

5:4 Unused Reserved bit

3 DMA MODEDMA transfer mode (mode of XTXRDY and XRXRDY pins) 0: Single transfer mode 1: Demand transfer mode

2 TxF RST Transmission FIFO reset 1: Reset

1 RxF RST Reception FIFO reset 1: Reset

0 Unused Reserved bit * Bit7:0 = 00h, after reset


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18.6.7. Line control register (URTxLCR)

Address ch0：FFFE_1000 + 0Ch ch1：FFFE_2000 + 0Ch ch2：FFF5_0000 + 0Ch ch3：FFF5_1000 + 0Ch ch4：FFF4_3000 + 0Ch



Name (Reserved) DLAB SB SP EPS PEN STB WLS1 WLS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W



7 DLAB

Divisor Latch Access Bit (divider latch access bit) 0: Disable

Reception FIFO register reads with address 0 Transmission FIFO register writes with address 0 IER register reads and writes with address 1

1: Enable DLL register reads and writes with address 0 DLM register reads and writes with address 1 TST register writes with address 7

6 SB Set Break (break transmission) 1: The SOUT signal forcibly becomes "0"

5 SP

Stick Parity (fixed parity) 0: Parity bit is determined by EPS and PEN 1: Parity bit is fixed as follows depending on the status of EPS and PEN (checked at

transmission, generation, and reception) Parity is "1" at PEN = 1 and EPS = 0 Parity is "0" at PEN = 1 and EPS = 1

4 EPS Even Parity Select (parity selection) 0: Odd parity 1: Even parity

3 PEN

Parity Enable (parity enable) 0: Parity is not sent nor checked 1: Parity is sent and checked Parity bit is added to end of data area, and stop bit comes last

2 STB

Number of Stop Bit (stop bit length) 0: 1 bit 1: 1.5 bit (data length: 5)

2 bit (data length: 6 ~ 8)

1:0 WLS1:0

Word Length Select (transmission/reception data length) 00: 5 bit 01: 6 bit 10: 7 bit 11: 8 bit

* Bit7:0 = 00h, after reset


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18.6.8. Modem control register (URTxMCR)




Name (Reserved) (Reserved) LOOP OUT2 OUT1 RTS DTR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Bit No. Bit name Function 31:8 Unused Reserved bit (input "0" at writing) 7:5 Unused Reserved bit (input "0" at writing)

4 LOOP

Loop Back Mode (self-diagnostic mode) When loop is set to "1", following is performed. 1. SOUT becomes "1" 2. SIN is separated from input Shift register of reception 3. Transmission shift register output is connected to input of the Reception shift register 4. Modem status is separated (CTS, DSR, DCD, and RI) 5. Modem status signal is connected to modem status input

CTS bit of URTxMSR is connected to DDSR bit of URTxMCR DSR bit of URTxMSR is connected to DCTS bit of URTxMCR RI bit of URTxMSR is connected to TERI bit of URTxMCR DCD bit of URTxMSR is connected to DDCD bit of URTxMCR

3 OUT2 When this bit is set to “1” and LOOP bit is “1”. The DDCD bit of URTxMSR is looping back into DCD bit of URTxMSR. Otherwise, it has no effect to this LSI.

2 OUT1 When this bit is set to “1” and LOOP bit is “1”. The TERI bit of URTxMSR is looping back into RI bit of URTxMSR. Otherwise, it has no effect to this LSI.

1 RTS When this bit is set to “1” and LOOP bit is “1”. The DDSR bit of URTxMSR is looping back into CTS bit of URTxMSR. Otherwise, it has no effect to this LSI.

0 DTR When this bit is set to “1” and LOOP bit is “1”. The DCTS bit of URTxMSR is looping back into DSR bit of URTxMSR. Otherwise, it has no effect to this LSI.



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18.6.9. Line status register (URTxLSR)




Name (Reserved) ERRF TEMT THRE BI FE PE OE DR R/W R R R R R R R R R R R R R R R R



7 ERRF

Error in RCVR FIFO (error in reception FIFO) When data in receiver FIFO has either one of parity, or framing or break detect error, this bit is set. If there is no error in data of reception FIFO (except ERRF flag set), this bit is reset whenURTxLSR register is read.

6 TEMT Transmitter Empty (transmission shift register empty) When both Transmission shift register and Transmission FIFO register become empty, TEMT is set to "1".

5 THRE Transmitter FIFO Register Empty (transmission register empty) When Transmission FIFO register is empty and ready to accept new data, THRE is set to "1". This bit is cleared at sending data to Transmission shift register.

4 BI Break Interrupt (break reception) This bit is set when SIN holds in "0" more than transmission time (start bit + data bit + parity + stop bit.) BI is reset when CPU reads this register.

3 FE Framing Error (flaming error) This bit is set when reception data does not have valid stop bit. FE is reset by CPU reading this register.

2 PE Parity Error (parity error) This bit is set when reception data does not have valid parity bit. PE is reset when CPU reads this register.

1 OE Overrun Error (overrunning error) This bit is set when reception FIFO is full and receives the next reception data. OE is reset when CPU reads this register.

0 DR Data Ready (reception data existed) This bit shows 1 byte or more of data is in FIFO. This bit is set when data is in FIFO and reset after reading all data in FIFO.



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18.6.10. Modem status register (URTxMSR)




Name (Reserved) DCD RI DSR CTS DDCD TERI DDSR DCTS R/W R R R R R R R R R R R R R R R R



7 DCD

Data Carrier Detect Loop = 0: Inversed input signal, XDCD is indicated Loop = 1: It is equal to OUT2 of MCR. Note: In this LSI, DCD field is always be “1” when Loop = 0. OUT2 is the DDCD bit of URTxMSR when OUT2 bit and LOOP bit of URTxMCR is set to “1”.

6 RI

Ring Indicator Loop = 0: Inversed input signal, XRI is indicated Loop = 1: It is equal to OUT1 of MCR Note: In this LSI, RI is always be “1” when Loop = 0. OUT1 is the TERI bit of URTxMSR when OUT1 bit and LOOP bit of URTxMCR is set to “1”.

5 DSR

Data Set Ready Loop = 0: Inversed input signal, XDSR is indicated Loop = 1: It is equal to DTR of MCR Note: In this LSI, DSR is always be “1” when Loop = 0. DTR is the DCTS bit of URTxMSR when DTR bit and LOOP bit of URTxMCR is set to “1”.

4 CTS

Clear To Send Loop = 0: Inversed input signal, XCTS is indicated Loop = 1: It is equal to RTS of MCR Note: In this LSI, CTS is always be ”0” when Loop = 0. RTS is the DDSR bit of URTxMSR when RTS bit and LOOP bit of URTxMCR is set to “1”.

3 DDCD Delta Data Carrier Detect This bit is set when DCD signal changes after the last reading by CPU. The bit is reset by reading this register.

2 TERI Traling Edge of Ring Indicator This bit is set when RI signal changes from 1 to 0 after the last reading by CPU. The bit isreset by reading this register.

1 DDSR Delta Data Set Ready This bit is set when DSR signal changes after the last reading by CPU. The bit is reset by reading this register.

0 DCTS Delta Clear To Send This bit is set when CTS signal changes after the last reading by CPU. The bit is reset by reading this register.

* Bit7:0 = x0h, after reset Bit7:4 is monitor bit of external pin


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18.6.11. Divider latch register (URTxDLL&URTxDLM) This register is frequency dividing latch to generate necessary baud rate from clock input. Frequency diving latch consists of 16 bit, DLM (high order byte) and DLL (low order byte.)

[DLL]


ch3：FFF5_1000 + 00h ch4：FFF4_3000 + 00h (Accessing is enabled only at DLAB = 1)



Name (Reserved) DL[7:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


[DLM]

Address ch0：FFFE_1000 + 04h ch1：FFFE_2000 + 04h ch2：FFF5_0000 + 04h ch3：FFF5_1000 + 04h ch4：FFF4_3000 + 04h ch5：FFF4_4000 + 04h

(Accessing is enabled only at DLAB = 1)) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name (Reserved) DL[15:8] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X X X 0 0 0 0 0 0 0 0 DLL and DLM are read/written when DLAB bit of LCR is set to "1".

• After the reset, DLL and DLM are 00h • DLL and DLM values are loaded by writing to either DLL or DLM • Baud rate in the range from FFFFh to 0001h can be set in DLM and DLL


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To calculate transfer baud rate

Transfer baud rate (bps) = (APB clock frequency (Hz)/Frequency dividing value)/16

Example of frequency dividing value (DLM and DLL values) and baud rate is shown in Table 18-3.

Table 18-3 Example of frequency dividing value (DLM and DLL values) and baud rate

DLL value (decimal)

(DLM = 0)

Baud rate The other party's baud rate

(error range) APB clock = 41.663(MHz)

(external input condition: CLK = 33.33MHz, CRG.CRPR.PLLMODE[3:0] = 0011)

2170 1200 1200 (100%) 1085 2400 2400 (100%) 542 4804 4800 (99.9%) 271 9609 9600 (99.9%) 181 14386 14400 (100.1%) 136 19147 19200 (100.3%) 90 28933 28800 (99.5%) 68 38293 38400 (100.3%) 45 57865 57600 (99.5%) 23 113215 115200 (101.8%)

If transmitting baud rate of a communication partner and baud rate of this UART module are within the allowable range, it can receive data normally. If they exceed the allowable range, receive error occurs. The allowable range is shown below.

104.1% > Macro baud rate (100%) > 95.3%

When baud rate used by macro is within the reception baud rate's permissible error range of the other party, data is able to be received. Out of the range causes error on the other party side. After the reset (MR = 1), it takes 1/4 bit of time from setting DLL and DLM to enable start bit detection. Although start bit (SIN = 0) is received in the period, proper start bit detection is not performed.


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18.7. UART operation

18.7.1. Example of initial setting

Set DLAB bit of line control register

Set low order frequency dividing latch

Set high order frequency dividing latch

1.

2.

3.

4. Reset DLAB bit of line control register

Set transmission/reception format in line control register

Set interrupt enable register

5.

6.

Reset

End

Figure 18-2 Example of initial setting

1. After the power-on, macro's each output pin is undefined. Each output pin level becomes the one shown in the table of chapter 5 by inputting "L" to reset (MR) pin.

2. Divider latch is able to be accessed by setting "1" to DLAB bit in the Line control register (LCR register.)

3. Set baud rate clock (refer to "18.6.11 Divider latch register (URTxDLL&URTxDLM)".) 4. Set "0" to DLAB bit in the Line control register. 5. Set transmission/reception format by setting the Line control register. 6. Control each interrupt by setting the Interrupt enable register (IER register.)


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18.7.2. Example of transfer procedure

Set transmission data to transmission FIFO

N o

1 .

2 .

Yes

Transmission procedure

End

Transmission FIFO is empty

Figure 18-3 Example of transfer procedure 1. Check transmission FIFO is empty with following method:

a. Polling process of THRE bit in the Line status register (LSR) THRE bit shows transmission FIFO status. When the FIFO is empty, the bit becomes "1".

b. Polling process of TEMT bit in the Line status register (LSR) TEMT bit shows transmission FIFO and Transmission shift register statuses that data in transmission process and empty transmission FIFO are able to be confirmed. When they are empty, TEMT becomes "1".

c. Transmission FIFO empty interrupt process When all data in transmission FIFO is moved to the Transmission shift register, this interrupt occurs. It is able to control approval/prohibition in the Interrupt enable register (URTxIER.)

Note: During transmission FIFO empty interrupt process, check THRE bit of the LSR is "1" before writing data to transmission FIFO.

• THRE = 1: Transmission FIFO is empty that data is able to be written • THRE = 0: Transmission FIFO is not empty. Retry from interrupt process to be FIFO

empty interrupt status without writing data to transmission FIFO.

2. Set transmission data to transmission FIFO. Up to 16 byte is able to be set in the FIFO at a time. In this case, THRE bit of the LSR becomes "0".

Note:

The last written data is deleted when writing data to transmission FIFO while it is full.


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18.7.3. Example of reception procedure

Interrupt occurs

Data ready or line status interrupt? R e c ep t io n d a ta re a dy in t er r up t

1 .

2 .

3 . 4 .

L i n e s ta t us in t er r up t

Interrupt factor check (reception error factor) Reading reception FIFO

Reception procedure

End

Figure 18-4 Example of reception procedure

1. When certain interrupt is permitted, interrupt occurrence is able to be confirmed with interrupt (INTR) pin (at INTR = "H".) Moreover, it is confirmed by polling NINT bit in the Interrupt ID register (IIR register) (at NINT = "0".)

2. Type of interrupt is able to be observed by confirming ID0, ID1 and ID2 bit in the Interrupt ID register.

3. After interrupt type is judged as reception line status interrupt with the process in item 2, reception error information is able to be acquired by reading the Line status register which also releases the interrupt (INTR= "L".)

4. After interrupt type is judged as reception data ready interrupt with the process in item 2, read number of character corresponding to the trigger level to acquire reception character. Reception data ready status is also able to be confirmed by referring DR bit in the Line status register. The interrupt is released when data in FIFO becomes less than the trigger level (INTR= "L".)


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18.7.4. Basic transmission operation

1 character

Mark state Start bit Parity bit

Data bit Stop bit

UART_SOUTx

(THRE)

D0 D1 D2 D3 D4 D5 PT D0 PT

(TEMT)

INTR

XTXRDY

This is example of the case, data bit length is 6 bit and stop bit length is 2 bit, and parity

APB CLK

Figure 18-5 Basic transmission operation After initial reset is completed and transmission data is not written to the transmission shift register in the transmission control part (mark state), serial transfer (SOUT) pin is maintained as "H" level. The data is output from serial transmission (SOUT) pin with adding start bit, parity bit, and stop bit in the transmission control part as shown in Figure 18-5 when transmission data is written from CPU to transmission FIFO. 1 ~ 16 byte of transmission data is able to be consecutively written to transmission FIFO at a time. Transmission FIFO state is able to be confirmed with THRE bit of the LSR register. When transmission data is written to transmission FIFO though it is full, the last written data is deleted. The data that is already stored in the transmission FIFO is properly transmitted. THRE bit becomes "0" by writing to transmission FIFO. When the writing data is transferred to the transmission shift register and FIFO becomes empty, the value becomes "1". If transmission data buffer interrupt is permitted in that time, interrupt (INTR) pin becomes "H" and interrupt occurs. This interrupt is released by writing data to the transmission FIFO again or reading the Interrupt confirmation register. TEMT bit becomes "0" at the same timing of THRE bit, and the value becomes "1" after transmission of all written data is completed. XTXRDY is data ready signal that indicates transmit enable against DMA controller when DMA controller is used. Single transfer mode is supported when bit 3 of the FCR register is "0" and the demand transfer mode is supported when the bit is "1". When transmission baud rate used by macro is within the reception baud rate permissible error range, the other party is able to receive data. Out of the range causes reception error on the other party side.


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18.7.5. Basic reception operation

1 character


Data bit Stop bit

UART_SINx

(DR)


INTR

XRXRDY

This is example of the case, data bit length is 6 bit and stop bit length is 2 bit, and parity

APB CLK

Figure 18-6 Basic reception operation After detecting received start bit ("L" level) from serial input (SIN) pin, the bit receiving next is regarded as start bit of reception data. Then, received data is sampled with reception clock, and stop bit is detected after receiving data bit and parity bit. When transmission error occurs during that time, its factor (break detection, flaming error, parity error, and overrunning error) is applied to each data in FIFO, and the status is maintained. Status can be confirmed by CPU at the first data of FIFO. When reception data ready interrupt is permitted, interrupt (INTR) pin becomes "H" and interrupt occurs by reaching the data in reception FIFO to the trigger level. This interrupt is released when the data in the FIFO becomes less than the trigger level, and interrupt (INTR) pin becomes "L". XRXRDY is data ready signal that shows possible reception to DMA controller at using the controller. Single transfer mode is supported when bit 3 of the FCR register is "0" and the demand transfer mode is supported when the bit is "1". If transmitting baud rate of a communication partner and baud rate of this UART module are within the allowable range, it can receive data normally. If they exceed the allowable range, receive error occurs. The allowable range is shown below.

104.1% > Macro baud rate (100%) > 95.3%

After the reset (MR = 1), it takes 1/4 bit of time from setting DLL and DLM to enable start bit detection. Although start bit (SIN = 0) is received in the period, proper start bit detection is not performed.


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18.7.6. Line status

THRE flag and TEMT flag Operation example of THRE flag and TEMT flag of bit 5 and 6 in the Line status register (LSR) is shown in Figure 18-7.

SOUT

(THRE)

DATA1 DATA2 DATA3 DATA4 DATA5

DATA2 DATA4 DATA5

Mark state

(TEMT)

Transmission buffer

Write Transmission

buffer DATA3

CLK

Figure 18-7 Example of operation of THRE flag and TEMT flag THRE flag = "1" indicates that there is no data in the Transmission FIFO buffer register, and transmission character is able to be written. TEMT flag becomes "1" when there is no data in the register and Transmission shift register in the transmission control part. Both flags become "0" at writing "0" to transmission FIFO buffer.


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FE flag and BI flag Operation example of BI flag and of bit 4 and 3 and FE flag in the Line status register (LSR) is shown in Figure 18-8.

1 character

UART_SINx

(FE)

D0 D1 D2 D3 D4 SPPT

(BI)

UART_SINx

(note)

URTxLSR

Register reading URTxRFR

Register reading

1 character

D0 D1 D2 D3 D4 SP PT

D0 D1 D2 D3 D4 SPPT

Figure 18-8 Operation example of FE flag and BI flag

If "L" level is received at the stop bit during reception operation, flaming error occurs and FE flag becomes "1". The error flag is reset by reading Line status register. When "L" level continues during transmission time (start bit, data bit, parity bit, and stop bit) for 1 character, break code is detected. These errors are applied to each data in FIFO, and they are able to be confirmed when CPU reads the first data of FIFO. FE and BI flags are able to be confirmed by reading the Line status register if first data of FIFO includes framing or break detection error. Both flags become "0" by reading Status register. For the case of break detection error, reception data is stored to FIFO as 0. When break error is detected, macro stops receiving process, and it restarts the process by detecting SIN's falling edge.


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PE flag Operation example of PE flag of bit 2 in the line status register (LSR) is shown in Figure 18-9.

1 character


Data bits Stop bit

UART_SINx

Normal completion

1 0 1 0 1 0 1 D0 PT

(PE-FIFO)

URTxLSR

register reading Abnormal completion

D0 D1 D2 D3 D4 D5 PT

UART_SINx 1 0 0 0 1 0 1 D0 PT D0 D1 D2 D3 D4 D5 PT

(PE)

Figure 18-9 Operation example of PE flag (setting even parity) Parity bit is set to "1" or "0" depending on the number of "1" level bit in each of the data bits. When even parity is set by EPS bit in line control register, if the number of “1” in the data bits is odd number, the parity bit is set to “1”. Then the total number of data bits and parity bit becomes even number. When the number of “1” in the data bits is even number, the parity bit is set to “0”. Likewise, when odd parity is set in EPS bit in line control register, the polarity of parity bit is adjusted so that the total number of data bits and parity bit becomes odd number. Receiver compares count results and polarity of parity set in EPS bit in line control register by counting number of “1” level in data bits and input parity bit. If the polarity of the parity set in the EPS bit of the line control register is not consistent with the number of "1" level bits, it is considered as an error and "1" is set in the PE flag of the register. This error is applied to each data in FIFO, and is able to be confirmed when CPU reads first data of FIFO.


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OE flag Operation example of OE flag of bit 1 in the Line status register (LSR) is shown in Figure 18-10.

UART_SINx

(DR)

D14 D15 D16

Line status D1 D15 D16

D17

(OE)

APB reading

FIFO FULL

D2

Figure 18-10 Operation example of OE flag When next character is received completely to the Reception shift register in the status that reception FIFO is full, overrun error occurs. In this case, OE flag of the Line status register is set immediately and interrupt occurs (if it is permitted.)

DR flag Operation example of DR flag of bit 0 in the Line status register (LSR) is shown in Figure 18-11.

1 character


Data bit Stop bit

UART_SINx

(DR)


URTxRFR

register reading

Figure 18-11 Operation example of DR flag When reception data is received and 1 byte or more of data is stored in reception FIFO, DR flag of the Line status register becomes "1". The flag becomes "0" by reading reception FIFO data and FIFO becomes empty.

ERRF flag When error (parity, break detection, and flaming) is included in the data stored in reception FIFO, ERRF flag of bit 7 of the Line status register (LSR) is set to "1" during reception operation. If there is no error in data of reception FIFO except ERRF flag set, this bit is reset when CPU reads line status register.


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18-25



UART interface

18.7.7. Character time-out interrupt Character time-out interrupt occurs in the following cases:

• 1 or more data is stored in reception FIFO and the next serial data is still not received after 4 characters of time

• 1 or more data is stored in reception FIFO and CPU still does not read the data after 4 characters of time

When time-out interrupt occurs, INTR pin becomes "H". Moreover, XRXRDY signal becomes "L", showing DMA controller that reception is ready, and requests to read data. Timer and time-out interrupt are reset by CPU (or DMA controller) reading 1 byte from reception FIFO. If time-out does not occur, it is reset after timer receives new data or CPU (or DMA controller) reads data from reception FIFO.

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19. I2C bus interface This chapter describes function and operation of I2C bus interface.

19.1. Outline I2C bus is serial bus advocated by Philips Semiconductors (now NXP) that supports data transfer between multiple devices with 2 signals. MB9G711 equips 2 channels of interface corresponding to I2C standard mode (max. 100Kbps)/high-speed mode (max. 400KBps.) External pin, I2C_SDA0, I2C_SDA1, I2C_SCL0, and I2C_SCL1 uses 3.3V exclusive I/O, so that it is able to be used in 3.3V I2C. I2C_SDA0/I2C_SDA1 are indicated as SDA line, and I2C_SCL0/I2C_SCL1 are indicated as SCL line in this document.

19.2. Feature I2C has following features:

• Master transmission/reception function • Slave transmission/reception function • Arbitration function • Clock synchronization function • Slave address detecting function • General call address detecting function • Transfer direction detecting function • Repeat occurrence and detecting function of start condition • Bus error detecting function • Corresponding to standard mode (max. 100KBps)/high-speed mode (max. 400KBps)


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19.3. Block diagram

Start condition/Stop condition

detector

Arbitration lost detector

Start condition/Stop condition detector

Shift Clock generator

I2C_SDA0 I2C_SCL0

Noise filter

I2C×ADR

APB bus

I2C module 0

I2C module 1

I2C_SDA1 I2C_SCL1

Comparator

I2C×DAR

I2C×BSR

I2C×BCR

I2C×CCR

I2C×BC2R

I2C×ECSR

I2C×BCFR

Figure 19-1 Block diagram of I2C


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Block function Each block function is described below.

Table 19-1 I2C block function Block Description

Start condition/Stop condition detector

Start condition and Stop condition are detected from transition state of SDA and SCL lines.

Start condition/Stop condition generator

Start condition and Stop condition are issued from transition state of SDA and SCL lines.

Arbitration lost detector Output data to SDA line and input data from SDA line are compared at data transmission. If they are unmatched, arbitration lost occurs.

Shift clock generator Timing count of serial data t transfer clock occurrence and output control of SCL line clock are performed with clock control register setting.

Comparator Received address and self-address specified to address register, or received address and global address are compared.

I2CxADR 7 bit register that specifies slave address. I2CxDAR 8 bit register used for serial data transfer. I2CxBSR 8 bit register with following functions to show I2C bus status and others.

• Repeated start condition detection • Arbitration lost detection • Acknowledge bit storage • Direction of data transfer • Addressing detection • General call address detection • First byte detection

I2CxBCR 8 bit register that performs I2C bus control and interrupt control has following functions. • Interrupt request/permission • Start condition occurrence • Master/Slave selection • Acknowledge occurrence permission

I2CxCCR 7 bit register that sets clock frequency of serial data transfer. • Operation permission • Frequency setting of serial clock • Standard/High-speed mode selection

Noise filter This is noise filter composed of 3 stage shift register circuit. When all 3 values consecutively sampled SCL/SDA line input signals are "1", the filter output becomes "1". When those values are "0", the filter output becomes "0". For other sampling, the state 1 clock before is maintained.

I2CxBC2R This is the register to drive "L" forcibly and to confirm the line status after noise filter is passed.

I2CxECSR This is the register to enhance CS bit in I2CxCCR register. I2CxBCFR This is the register that specifies frequency range of bus clock to be used.


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19.4. Related pin I2C uses following pins.

Table 19-2 I2C related pin Pin Direction Qty. Description

I2C0SL I2C1SL

IN/OUT 2 Clock pin of I2C bus interface. Corresponding to I2C_SCLx output Output of this pin is open drain.

I2C0SA I2C1SA

IN/OUT 2 Data pin of I2C bus interface. Corresponding to I2C_SDAx output Output of this pin is open drain.

I2C pins are common with other GPIO functions. To use those pins as I2C output, set corresponding bit of CPSEL register as following

• Set CPSEL[16] = "1B" for I2C0SA and I2C0SL • Set CPSEL[17] = “1B" for I2C1SA and I2C1SL

19.5. Supply clock APB clock is supplied to I2C. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.


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19.6. Register This section describes I2C bus interface register.

19.6.1. Register list This LSI equips 2 channels of I2C bus interface, and each module has the register shown in Table 19-3.

Table 19-3 I2C register list Channel Address Register Description

I2C ch0 FFF56000h I2C0BSR Bus status register

FFF56004h I2C0BCR Bus control register

FFF56008h I2C0CCR Clock control register

FFF5600Ch I2C0ADR Address register

FFF56010h I2C0DAR Data register

FFF56014h I2C0ECSR Extension CS register

FFF56018h I2C0BCFR Bus clock frequency register

FFF5601Ch I2C0BC2R Bus control 2 register

I2C ch1 FFF57000h I2C1BSR Bus status register FFF57004h I2C1BCR Bus control register FFF57008h I2C1CCR Clock control register FFF5700Ch I2C1ADR Address register FFF57010h I2C1DAR Data register FFF57014h I2C1ECSR Extension CS register FFF57018h I2C1BCFR Bus clock frequency register FFF5701Ch I2C1BC2R Bus control 2 register

Note:

Access the area of I2C ch0 and I2C ch1 in 32 bit (word)


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Description format of register Following format is used for description of register’s each bit in "19.6.2 Bus status register (I2CxBSR)" to "19.6.9 Bus clock frequency register (I2CxBCFR)".


Name R/W


Name R/W

Initial value









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19.6.2. Bus status register (I2CxBSR)

Address ch0：FFF5_6000 + 00h ch1：FFF5_7000 + 00h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name (Reserved) BB RSC AL LRB TRX AAS GCA FBT R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All bit of this register is cleared during EN bit of I2CxCCR is "0".

Bit 7: BB (bus busy) This bit shows I2C bus state.

BB Status 0 Stop condition is detected 1 Start condition is detected (but is in use)

Bit 6: RSC (Repeated Start Condition)

Repeated start condition detecting bit. RSC State

0 Repeated start condition is not detected 1 Start condition is detected again during bus is in use

This bit is cleared by writing "0" to INT bit, start condition detection at bus stop, and stop condition detection as well as addressing is not performed at slave.

Bit 5: AL (Arbitration Lost) Arbitration lost detecting bit

AL State 0 Arbitration lost is not detected

1 Arbitration lost occurs during master transmission, or "1" is written to MSS bit while other systems are using bus

This bit is cleared by writing "0" to INT bit.

Restrictions: In the multi master environment, it is prohibited that other masters transmit general call address simultaneously with this module. Moreover, use of arbitration lost by this module at the second byte or later is also prohibited.


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Bit 4: LRB (LAST Received Bit) This bit is to store 9th bit of the data indicating acknowledge (ACK)/negative acknowledge (NACK).

LRB State 0 Acknowledge (ACK) is detected 1 Negative acknowledge (NACK) is detected

This bit is cleared at start condition detection or stop condition detection.

Bit 3: TRX (Transfer/Receive) This bit is to indicate transmission/reception state of data transfer.

TRX State 0 Reception state 1 Transmission state

Bit 2: AAS (Address As Slave)

This is addressing detection bit. AAS State

0 Addressing is not performed at slave 1 Addressing is performed at slave

This is cleared at start condition detection or stop condition detection.

Bit 1: GCA (General Call Address) This is general call address (00h) detecting bit.

GCA State 0 General call address is not received at slave 1 General call address is received at slave

This bit is cleared at start condition detection or stop condition detection.

Bit 0: FBT (First Byte Transfer) This is first byte detecting bit.

FBT State 0 Reception data is not first byte 1 Reception data is the first byte (address data)

Although this is set to "1" at start condition detection, it is cleared if "0" is written to INT bit and addressing is not performed at the salve.


I2C bus interface

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19.6.3. Bus control register (I2CxBCR)




Name (Reserved) BER BEIE SCC MSS ACK GCAA INTE INT R/W R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This is cleared during EN bit of I2CxCCR is "0", except bit 7 and 6 of this register.

Bit 7: BER (Bus ERror) This is bus error interrupt request flag bit.

At writing

BER State 0 Bus error interrupt request flag is cleared 1 N/A

At reading

BER State 0 Bus error is not detected 1 Incorrect start and stop conditions are detected during data transfer

When this bit is set, EN bit of I2CxCCR resister is cleared, this module becomes in halt state, and the data transfer is discontinued.

Bit 6: BEIE (Bus Error Interrupt Enable) This is buss error interrupt permission bit. At reading/writing

BEIE State 0 Bus error interrupt is prohibited 1 Bus error interrupt is permitted

When this bit is "1" and BER bit is "1", interrupt occurs.

Bit 5: SCC (Start Condition Continue) This is start condition generation bit. At writing

SCC State 0 N/A 1 Start condition is generated again at master transfer

This bit is automatically cleared after setting "1".


I2C bus interface

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Bit 4: MSS (Master Slave Select) This is master/slave selection bit. At writing

MSS State 0 Stop condition is generated, and state becomes slave mode after the transfer 1 State becomes master mode, and start condition is generated to start transfer

This bit is cleared when arbitration lost occurs during master transmission, and state becomes slave mode.

Restrictions: In the multi master environment, prohibit other masters to transmit general call address simultaneously with this module and to use arbitration lost by this module at the second byte or later.

Bit 3: ACK (ACKnowledge) This is acknowledge permission bit at receiving data. At reading/writing

ACK State 0 Acknowledge is not occurred. 1 Acknowledge is occurred.

This bit is disabled at address data reception in the slave mode.

Bit 2: GCAA (General Call Address Acknowledge) This is acknowledge permission bit at receiving general call address. At reading/writing

GCAA State 0 Acknowledge is not occurred. 1 Acknowledge is occurred.

Bit 1: INTE (INTerrupt Enable)

This is interrupt permission bit. At reading/writing

INTE State 0 Interrupt is prohibited 1 Interrupt is enabled

When this bit is "1" and INT bit is "1", interrupt occurs.


I2C bus interface

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Bit 0: INT (INTerrupt) This is transfer end interrupt request flag bit. At writing

INT State 0 Transfer end interrupt flag is cleared 1 N/A

At reading

INT State 0 Transfer is not completed

1

This is set when following conditions are applied at completion of 1 byte transfer which includes acknowledge bit. • Bus master • Addressed slave • General call address is received (only at GCAA ＝ "1") • Arbitration lost occurs (only at bus acquisition state) • Start condition is attempted while other systems use bus

When this bit is "1", SCL line is maintained in "L" level. This is cleared by writing "0" to this bit, then SCL line opens and the next byte is transferred. Moreover, this is cleared to "0" by occurrence of start condition or stop condition at the master mode.

Competition of SCC, MSS, and INT bits Competition of the next byte transfer, start condition, and stop condition occurs by writing SCC, MSS, and INT bits simultaneously. Priority order in this case is as follows.

1. Occurrence of the next byte transfer and stop condition When writing "0" to INT bit and MSS bit simultaneously, MSS bit is prioritized and stop condition occurs.

2. Occurrence of the next byte transfer and start condition When writing "0" to INT bit and "1" to SCC bit simultaneously, SCC bit is prioritized and start condition occurs.

3. Occurrence of start condition and stop condition Writing "1" to SCC bit and "0" to MSS bit simultaneously is prohibited.


I2C bus interface

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19.6.4. Clock control register (I2CxCCR)




Name (Reserved) (Reserved) HSM EN CS[4:0] R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 1 0 0 X X X X X

Bit 7: Reserved The value is always "1" at reading.

Bit 6: HSM (High Speed Mode) This is standard/high-speed setting bit. At reading/writing

HSM State 0 Standard mode 1 High-speed mode

Bit 5: EN (ENable)

This is operation permission bit. At reading/writing

EN State 0 Operation is prohibited 1 Operation is permitted

When this bit is "0", each bit of I2CxBSR register and I2CxBCR register (excluding BER and BEIE bits) is cleared. When BER bit is set, this bit is cleared.


I2C bus interface

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Bit 4-0: CS4-0 (Clock Period Select 4-0) This bit is to set frequency of serial transfer clock. Upper bound of the bus clock frequency is able to be extended by setting I2CxECSR register. Refer to "19.6.8 Expansion CS register (I2CxECSR)" for details. When I2CxECSR register is not used (using I2CxECSR register in initial state), frequency fscl of serial transfer clock can be calculated by expressions shown below.

At standard mode

clockAPBm

fscl _ 2)2(

:φφ

+×=

At high-speed mode

tpoindecimalafteroffRound

clockAPBm

fscl

:) int(

_ 2)5.1int(

:φφ

+×=

Be sure to set fscl not to exceed the following values at the master operation.

• At standard mode: 100KHz. • At high-speed mode: 400KHz.

APB clock φ of this module should be used within the range shown below. When it is less than the range, transmission by max. transfer rate is not guaranteed. When it exceeds the range, upper bound of the bus clock frequency is able to be extended by setting I2CxECSR register.

• At the master operation: 14MHz ~ 18MHz. • At the slave operation: 14MHz ~ 18MHz. • At the register access operation: 14MHz ~ 41MHz

Note:

+2 cycle is min. overhead for checking output level change of SCL line. When rising edge delay of SCL line is large or the clock is enlarged with slave device, the value is lager than the above. The value of m to CS4 ~ 0 is shown in the next page


I2C bus interface

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CS4 CS3 CS2 CS1 CS0 m

Standard High speed 0 0 0 0 0 65 Setting prohibited 0 0 0 0 1 66 Setting prohibited 0 0 0 1 0 67 Setting prohibited 0 0 0 1 1 68 Setting prohibited 0 0 1 0 0 69 Setting prohibited 0 0 1 0 1 70 Setting prohibited 0 0 1 1 0 71 Setting prohibited 0 0 1 1 1 72 Setting prohibited 0 1 0 0 0 73 9 0 1 0 0 1 74 10 0 1 0 1 0 75 11 0 1 0 1 1 76 12 0 1 1 0 0 77 13 0 1 1 0 1 78 14 0 1 1 1 0 79 15 0 1 1 1 1 80 16 1 0 0 0 0 81 17 1 0 0 0 1 82 18 1 0 0 1 0 83 19 1 0 0 1 1 84 20 1 0 1 0 0 85 21 1 0 1 0 1 86 22 1 0 1 1 0 87 23 1 0 1 1 1 88 24 1 1 0 0 0 89 25 1 1 0 0 1 90 26 1 1 0 1 0 91 27 1 1 0 1 1 92 28 1 1 1 0 0 93 29 1 1 1 0 1 94 30 1 1 1 1 0 95 31 1 1 1 1 1 96 32


I2C bus interface

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19.6.5. Address register (I2CxADR)

Address ch0：FFF5_6000 + 0Ch ch1：FFF5_7000 + 0Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name (Reserved) (Reserved) A[6:0] R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 1 X X X X X X X

Bit 7: Reserved The value is always "1" at reading.

Bit 6-0: A6-0 (Address 6-0) This is slave address storage bit. The comparison with I2CxDAR register is performed after address data reception at slave. If they are matched, acknowledge is transmitted to master.


I2C bus interface

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19.6.6. Data register (I2CxDAR)




Name (Reserved) D[7:0] R/W R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 X X X X X X X X

Bit 7-0: D7-0 (Data 7-0) This is serial data storage bit. This data register is used for serial transfer transmitted from MSB. When data is received (TRX = 0), the data output becomes "1". This register's writing side is double buffer that writing data is loaded to serial transfer register at transmission of each byte if bus (BB = 1) is in use. Since serial transfer register is directly read at reading, received data is valid only when INT bit is set. Refer to Figure 19-4 for the format of the D[7:0] for address transmission. D[0] is the R/W bit of the Slave address.


I2C bus interface

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19.6.7. Two bus control registers (I2CxBC2R)

Address ch0：FFF5_6000 + 1Ch ch1：FFF5_7000 + 1Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name (Reserved) (Reserved) SDAS SCLS (Reserved) SDAL SCLL R/W R R R R R R R R R R R R R R R/W R/W

Initial value 0 0 0 0 0 0 0 0 ００ X X ００ 0 0

Bit 7 and 6: Reserved The value is always "00" at reading.

Bit 5: SDAS (SDA status)

Signal level of SDA line after passed noise filter is indicated. Only reading is valid.

SDAS State 0 The SDA line is "0" 1 The SDA line is "1"

Bit 4: SCLS (SCL status)

Signal level of SCL line after passed noise filter is indicated. Only reading is valid.

SCLS State 0 SCL line is "0" 1 SCL line is "1"

Bit 3 and 2: Reserved

The value is always "00" at reading.

Bit 1: SDAL (SDA low drive) SDAO output is forcibly become "L". Both reading/writing are valid.

SDAL State 0 SDAL output is in normal operation 1 SDAL output is forcibly become "L"

Bit 0: SCLL (SCL Low drive)

SCLO output is forcibly become "L". Both reading/writing are valid.

SCLL State 0 SCLO output is in normal operation 1 SCLO output is forcibly become "L"


I2C bus interface

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19.6.8. Expansion CS register (I2CxECSR)




Name (Reserved) (Reserved) CS[10:5] R/W R R R R R R R R R R R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 5-0: CS10-5 (Clock Period Select 10-5) This is set to expand upper bound of bus clock frequency with extending CS4 ~ 0 in the I2CxCCR register. Initial value of CS10 ~ 5 is "000000", and setting other values goes into frequency upper bound expansion mode.

CS10~5 State

000000 No upper bound expansion of bus clock frequency (only CS4 ~ 0 is used)

Other than 000000 There is upper bound expansion of bus clock frequency


I2C bus interface

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Standard mode:

10)10(:

:

_ 2)2(

＋～

φφ

CSofValuem

clockAPBm

fscl+×

=

High-speed mode:

tpoindecimalafteroffRound

mm

fscl

CSofValue

APBclock

:) int(

2)5.1int(

10)10(:

:

＋～

φφ

+×=

Set fscl not to exceed the following values at master operation.

• Standard mode: 100kHz • High-speed mode: 400kHz

Use system clock φ of this module within the range shown below. When it is less than the range, transfer in max. transfer rate is not guaranteed. When it exceeds the range, the operation is not guaranteed.

• Master operation: 14MHz ~ 41MHz • Slave operation: 14MHz ~ 41MHz • Register access operation: 14MHz ~ 41MHz

Note:

+2 cycle is min. overhead for checking output level change of SCL line. When rising edge delay of SCL pin is large or the clock is enlarged with slave device, the value is lager than the above.

When extension CS register is used, m value becomes CS10 ~ 0 + 1.


I2C bus interface

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19.6.9. Bus clock frequency register (I2CxBCFR)


Name (Reserved) R/W ＲＲＲＲＲＲＲＲＲＲＲＲＲＲＲＲ


Name (Reserved) (Reserved) FS[3:0] R/W ＲＲＲＲＲＲＲＲ R R R R R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit 7 and 4: Reserved The value is always "0000" at reading.

Bit 3-0: FS3-0 (Bus Clock Frequency Select 3-0) Select frequency of the bus clock to be used. Characteristics such as noise filters are set with this register's setting. A standard setting value is shown below; however, adjustment might be required depending on I2C buffer characteristics and noise state on I2C bus.

FS3 FS2 FS1 FS0 Frequency [MHz] 0 0 0 0 Setting prohibited 0 0 0 1 14 or more ~ Less than 20 0 0 1 0 20 or more ~ Less than 40 0 0 1 1 40 or more ~ Less than 60 0 1 0 0 – 0 1 0 1 – 0 1 1 0 – 0 1 1 1 – 1 0 0 0 – 1 0 0 1 – 1 0 1 0 – 1 0 1 1 – 1 1 0 0 – 1 1 0 1 – 1 1 1 0 – 1 1 1 1 –


I2C bus interface

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19.7. Operation I2C bus communicates with 2 interactive bus lines, serial data line (SDA) and serial clock line (SCL.) This module is connected to SDA and SCL lines through open drain IO cell by wired logic.

19.7.1. Start condition When "1" is written to MSS bit with bus open (BB = 0), this module becomes master mode, and start condition occurs at the same time. In the master mode, the start condition can be occurred again by writing "1" to SCC bit even if the bus is in use (BB = 1). There are 2 ways of condition to engender start condition.

1. Writing "1" to MSS bit in status (MSS = 0 & BB = 0 & INT = 0 & AL = 0) that bus is not used 2. Writing "1" to SCC bit in interrupt status (MSS = 1 & BB = 1 & INT = 1 & AL = 0) at bus master

When "1" is written to MSS bit at idling, AL bit is set to "1". Writing "1" to MSS bit and SCC bit in other states than the above is ignored.

Start condition on I2C bus Changing SDA line from "1" to "0" while SCL line is "1" calls start condition.

I2C_SDAx

I2C_SCLx

Start condition

Figure 19-2 Start condition on I2C bus


I2C bus interface

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INARY


19.7.2. Stop condition When "0" is written to MSS bit at master operation (MSS = 1), stop condition occurs and mode becomes slave. Following is condition to engender stop condition.

1. Writing "0" to MSS bit in interrupt status (MSS = 1 & BB = 1 & INT = 1 & AL = 0) at bus master Writing "1" to MSS bit in other states than the above is ignored.

Stop condition on I2C bus Changing SDA line from "0" to "1" while SCL line is "1" is called stop condition.

I2C_SDAx

I2C_SCLx

Stop condition

Figure 19-3 Stop condition on I2C bus


I2C bus interface

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19.7.3. Addressing In the master mode, status is set to BB = "1" and TRX = "1" after start condition occurs, and contents of I2CxDAR register is output from MSB. When acknowledge is received from the slave after sending address data, bit 0 of its data (I2CxDAR register’s bit 0 after transmission) is reversed and stored to TRX bit. In the salve mode, status is set to BB = "1" and TRX = "0" after start condition occurs, and transmission data from the master is received to I2CxDAR register. After receiving address data, I2CxDAR register and I2CxADR register are compared. When they are matched, status is set to AAS = "1" and acknowledge is sent to the master, then bit 0 of the reception data (I2CxDAR register’s bit 0 after reception) is stored to TRX bit.

Transfer format of slave address Transfer format of the slave address is shown below.

MSB LSB

Slave address

R/ＷA6 A0A5 A1 A4 A2 A3 ACK

Figure 19-4 Slave address's transfer format

Map of slave address Slave address map is shown below.

Slave address R/W Description 0000 000 0 General call address 0000 000 1 Start byte 0000 001 X CBUS address 0000 010 X Reserved 0000 011 X

Reserved 0000 1XX X 0001 XXX

1110 XXX

X Available slave address

1111 0XX X 10 bit slave address (*1) 1111 1XX X Reserved

*1: This module does not support 10 bit slave address


I2C bus interface

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19.7.4. Synchronous arbitration of SCL When multiple I2C devices become master device almost the same time to operate SCL line, each device detects SCL line status and automatically adjusts the line’s operation timing with keeping the pace to slow device.

I2C_SCLx

SCL output (before arbitration)

Macro A

Macro B

Take timing from when SCL line becomes "H" to the next SCL output = "L"

Take timing from when SCL line becomes "H" to the next SCL output = "L"

SCL output (after arbitration)

SCL output (before arbitration)

SCL output (after arbitration)

Figure 19-5 SCL output's synchronous arbitration


I2C bus interface

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19.7.5. Arbitration Arbitration occurs when other masters also transmit data at the same time.

• When own transfer data is "1" and data on SDA line is "0", AL = "1" is set regarding that arbitration is lost.

• When start condition is attempted during other masters are using bus, AL = "1" is set regarding that arbitration is lost.

• When other masters' start condition is detected before starting condition occurs though unused bus is confirmed and MSS = "1" is set, AL = "1" is set regarding that arbitration is lost.

When AL bit is set to "1", status becomes MSS = "0" and TRX = "0" that state becomes slave reception mode. When arbitration is lost (the right to use the bus is lost.), master discontinues drive of SDA. However, drive of SCL is not discontinued until 1 byte of transmission ends and the interrupt is cleared.

I2C_SDAx

I2C_SCLx

SDA input

SDA output

SDA input

SDA output

Macro A

Macro B

Since input and output are matched, right to use bus is acquired.

Since input and output are unmatched, right to use bus is lost.

Figure 19-6 Arbitration


I2C bus interface

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19.7.6. Acknowledge/Negative acknowledge 9th bit of data shows acknowledge (ACK)/negative acknowledge (NACK), status of "0" is acknowledge and "1" is negative acknowledge. The reception side transmits acknowledge/negative acknowledge to transmission side, and they are stored to LRB bit at data reception. If acknowledge is not received from master reception side at slave transmission (when negative acknowledge is received), the state becomes TRX = "0" and mode becomes slave reception mode. As a result, master is able to generate stop condition when slave opens SCL.

I2C_SDAx

I2C_SCLx

SDA output

Macro A (transmission)

Macro B (reception) Reception side returns ACK/NACK to transmission side

Transmission side opens bus for ACK/NACK output on reception side

1 2 3 4 5 6 7 8 9

ACK

ACK

SCL output

SDA output

SCL output

Master generates clock

Figure 19-7 Acknowledge/Negative acknowledge


I2C bus interface

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19.7.7. Bus error When following conditions meet, state is judged as bus error and this module stops.

a. Detection of basic rule violation on I2C bus in data transmission (including ACK bit) b. Detection of stop condition at master c. Detection of basic rule violation on I2C bus at bus idle

I2C_SDAx

1 Start 3 I2C_SCLx 2

D7 D5 D6

I2C_SDAx is changed in I2C_SCLx = H during data transfer which leads to bus error

Figure 19-8 Bus error


I2C bus interface

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19.7.8. Initialization

Start

Slave address setting

Clock frequency settingMacro enable setting

Interrupt setting

End

I2CxADR (offset + 0Ch): Write

I2CxCCR (offset + 08h): Write CS[4:0]: Write EN: 1 write

I2CxBCR (offset + 04h): Write BER: 0 write BEIE: 1 write INT: 0 write INTE: 1 write

Figure 19-9 I2C initialization


I2C bus interface

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19.7.9. One byte transfer from master to slave

Start

Start condition

Address data transfer

Acknowledge

Interrupt

Data transfer

Acknowledge

Interrupt

Stop condition

End

Master

I2CxDAR (offset + 10h): Write MSS: 1 write

BB set and TRX set

LRB reset

Slave

INT set and TRX set DAR: write INT: 0 write

INT set

LRB reset

INT set and TRX reset ACK: 1 write INT: 0 write

MSS: 0 write INT reset BB reset and TRX reset

AAS set

BB set and TRX reset

INT setI2CxDAR (offset + 10h): Read INT: 0 write

BB reset and TRX reset AAS reset

Figure 19-10 1 byte transfer example from master to slave


I2C bus interface

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19.7.10. One byte transfer from slave to master

Start

Start condition

Address data transfer

Acknowledge

Interrupt

Data transfer

Negative acknowledge

Interrupt

Stop condition

End

Master

I2CxDAR (offset + 10h): Write MSS: 1 write

BB set and TRX set

LRB reset

Slave

INT set and TRX reset ACK: 0 write INT: 0 write

INT set I2CxDAR: Read

LRB set and TRX set

INT set and TRX set I2CxDAR(offset+10h): Write INT: 0 write

MSS: 0 write INT reset BB reset and TRX reset

AAS set

BB set and TRX reset

INT set INT: 0 write

BB reset and TRX reset AAS reset

Figure 19-11 1 byte transfer example from slave to master


I2C bus interface

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19.7.11. Recover from bus error

Start

Error flag release

Clock frequency settingMacro enable setting

Interrupt setting

End

I2CxBCR (offset + 04h): Write BER: 0 write BEIE: 1 write

I2CxCCR (offset + 08h): Write CS[4:0]: Write EN: 1 Write

I2CxBCR (offset + 04h): Write BER: 0 write BEIE: 1 write INT: 0 write INTE: 1 write

Figure 19-12 Setting example for recovering from bus error


I2C bus interface

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19.7.12. Interrupt process and wait request operation to master device

When INT flag of I2CxBCR register is "H" (during this module engenders interrupt and CPU proceeds interrupt operation), "L" is output to SCL line. While slave side sets "L" to SCL line, master side is unable to generate the next transfer since slave side puts wait on master side.

19.8. Notice System clock and fscl of this module

Supply system clock to this module within the following range. The communication with system clock of 18MHz or more needs I2CxCSR setting.

• Master operation: 14MHz ~ 41MHz Set I2CxECSR not to exceed the following limits on fscl. If it exceeds the upper bound of each mode, normal transfer is not proceeded since it is timing violation on I2C bus.

Standard: 100kHz High-speed: 400kHz

• Slave operation: 14MHz ~ 41MHz • Register access: 14MHz ~ 41MHz

10 bit slave address This module does not support 10 bit slave address; therefore, do not specify slave address from 78H to 7bH for the module. When wrong address is specified, acknowledge is returned at receiving 1byte; however, normal transfer is not proceeded.

Competition of SCC, MSS, and INT bit Simultaneous writing of SCC, MSS, and INT bits causes competition of start and stop conditions at the next byte transfer. The priority of this case is as follows.

1. Occurrence of the next byte transfer and stop condition When "0" is written to INT bit and MSS bit simultaneously, MSS bit is prioritized and stop condition occurs.

2. Occurrence of the next byte transfer and start condition When "0" is written to INT bit and "1" is written to SCC bit simultaneously, SCC bit is prioritized and start condition occurs.

3. Occurrence of start condition and stop condition Writing "1" to SCC bit and "0" to MSS bit simultaneously is prohibited.

Serial transfer clock setting When rising edge delay of SCL line is large or clock is expanded at the slave device, the value may be smaller than the setting value (calculated value) since overhead occurs.


I2C bus interface

PRELIM

INARY

19-33



I2C bus interface

Restrictions in global call address transmission at using multi master When this module is used at multi master, it is prohibited that other masters send global call address at the same time of this module and it loses arbitration at the 2nd byte or later. This restriction is not applied to the following usage:

• This module is used in the single master environment. • This module is used in the multi mater environment; however, it does not send general call address. • This module is used in the multi master environment; however, other modules do not use general call

address transmission. • Although this module is used in the multi master environment and other masters send general call

address simultaneously with this module, it does not lose arbitration at the 2nd byte or later.* *: Because the larger transmission data causes arbitration lost, the data of the 2nd byte or later must

always be smaller than the value of other masters' data.

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MB9G711LSI Product Specifications


Serial peripheral interface (SPI)

20. Serial peripheral interface (SPI) This chapter describes function and operation of serial peripheral interface (SPI.)

20.1. Outline SPI is a serial interface to perform synchronous communication.

20.2. Feature SPI has following features:

• Serial synchronous transmission of the full duplex • Transfer format is programmable

a) Bit rate b) Data length (1 ~ 32 bit) c) Clock polarity d) Phase

• Supporting 2 types of slave select signals • Only 1 slave is connectable

Example of SPI connection Figure 20-1 shows SPI connection example.

Figure 20-1 Example of SPI connection

Note: When slave is active, SPIxDI pin may be floating.

SPI master (MB9G711) SPI slave

SPIxCK

SPIxDO

SPIxDI

SPIxCX

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20.3. Block diagram Figure 20-2 shows block diagram of SPI.

APB CLK

(Bus clock) SPI CRG

Stat

e m

achi

ne

Control logic

32bi

t shi

ft

regi

ster

Dat

a re

gist

er

AP

B B

US

32

bit/4

1.5M

Hz

SIRQ

SPIxCK

SPIxDO

SPIxDI

SPIxCX IRC

Figure 20-2 Block diagram of SPI

20.4. Supply clock APB clock is supplied to SPI. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.



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20.5. Transition state Figure 20-3 shows SPI transition state chart.

RESET

SLEEP

SENB = 0 SBSY = 0 SERR = 0

ERROR


SETUP


BUSY


HRESETn = 1

SPE = 1

SPE = 0

Write data

Normal end

Error

SPE = 0

Figure 20-3 SPI state transition chart Detail of each state shown in Figure 20-3 is as follows. SPI moves to reset state with hardware reset (HRESETn = 0) from all conditions (broken line in the chart.)

SPI state Description Sleep (SLEEP) Initial state of SPI.

Clock is not supplied except to state machine. While setup or transition from error state, internal logic is initialized except certain part.

Setup (SETUP) Stand-by state of communication between master and slave. SPI changes state in the following cases. • SPE bit of SPI slave control register (SPIxSCR) is set to "1" in the sleep state • Communication completes properly in the busy state Received data should be read in the setup state.

Busy (BUSY) Communicating state with SPI slave. Writing SPI data register (SPIxDR) in the setup state moves to this state; in that time, transmission/reception of the data are performed simultaneously. When 1 bit is output to SPIxDO pin, 1 bit is input from SPIxDI pin. Set SIRQ at the normal termination of the communication.

Error (ERROR) Performing prohibited register access in the busy state moves to this state. Clearing SPE bit of SPI slave control register (SPIxSCR) returns to sleep (SLEEP) state.



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20.6. Register This section describes SPI register.

20.6.1. Register list SPI is controlled by the register shown in Table 20-1.

Table 20-1 SPI register list Address


FFF4_0000H + 000H SPI0 control register SPI0CR Common setting of SPI0 + 004H SPI0 slave control register SPI0SCR SPI0 slave setting + 008H SPI0 data register SPI0DR SPI0 data register for data to be transmitted/received+ 00CH SPI0 status register SPI0SR This register contains SPI0 status + 010H ~ + 7FFH

(Reserved) – Access prohibited

FFF4_0800H + 00H SPI1 control register SPI1CR Common setting of SPI1 + 04H SPI1 slave control register SPI1SCR SPI1 slave setting + 08H SPI1 data register SPI1DR SPI1 data register for data to be transmitted/received+ 0CH SPI1 status register SPI1SR This register contains SPI1 status + 010H ~ + FFFH

(Reserved) – Access prohibited

Description format of register Following format is used for description of register’s each bit in "20.6.2 SPI control register (SPIxCR)" to "20.6.5 SPI status register (SPIxSR)".


Name R/W


Name R/W

Initial value





Attribution of read/write of each bit field • R0:Read value is always "0" • R1: Read value is always "1" • W0: Write value is always "0", and write access of "1" is ignored



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• W1: Write value is always "1", and write access of "0" is ignored • R: Read • W: Write





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20.6.2. SPI control register (SPIxCR) This register is to set common setting of SPI. SPIxCR setting should be carried out in the sleep or setup states, and do not write to this register in the busy state. Each bit of SPIxCR is not cleared even the state is changed to sleep by SPE = 0 of SPI slave control register (SPIxSCR.)

Address SPI0: FFF4_0000H + 00H SPI1: FFF4_0800H + 00H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name – – – – – – – – – – – – – – – SPL0R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R/W R/W R/W

Initial value X X X X X X X X X X X X X 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name – – – – – CDV2 CDV1 CDV0 – – – – – – CPOL CPHAR/W R0 R0 R0 R0 R0 R/W R/W R/W R0 R0 R0 R0 R0 R0 R/W R/W

Initial value X X X X X 0 0 0 X X X X X X 0 0 (Note) This register should be accessed in 32 bit unit.

Bit field


31-19 – Unused bits. The write access is ignored. The read value of these bits is always "0".

18-17 – Unused bits. The write access is ignored.

16 SPL0 Polarity of SPIxCX pin (slave selection pin) is specified.

0 Active-high (initial value) 1 Active-low

15-11 – Unused bits.

The write access is ignored. The read value of these bits is always "0". 10-8 CDV2-0 Frequency dividing ratio of serial clock (CK) to bus clock (PCLK) is specified.

CDV2 CDV1 CDV0 Frequency dividing ratio

0 0 0 PCLK × 1/2 (initial value) 0 0 1 PCLK × 1/4 0 1 0 PCLK × 1/8 0 1 1 PCLK × 1/16 1 0 0 PCLK × 1/32 1 0 1 PCLK × 1/64 1 1 0 PCLK × 1/128 1 1 1 PCLK × 1/256


The write access is ignored. The read value of these bits is always "0". 1 CPOL Polarity of serial clock (CK) is selected.

0 Positive pulse (initial value) 1 Negative pulse

0 CPHA Timing of I/O serial data (DI/DO) and serial clock (CK) are specified.

Timing at CPHA = 0 or 1, and CPOL = 0 is shown in Figure 20-4 Timing at CPHA = 0 or 1, and CPOL = 1 is shown in Figure 20-5



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SPIxCK (CPHA=0)

SPIxCK (CPHA=1)

SPIxDI Shift in

SPIxDI Shift out

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Figure 20-4 Timing of serial data and serial clock (at CPOL = 0)

SPIxCK (CPHA=0)

SPIxCK (CPHA=1)

SPIxDI Shift in

SPIxDI Shift out

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Figure 20-5 Timing of serial data and serial clock (at CPOL = 1)



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20.6.3. SPI slave control register (SPIxSCR) This register maintains unique setting of SPI slave. All bits are cleared by moving state to sleep. Set this register at sleep or setup state.


Name – – – SPE – – – DRVS – – – – STL3 STL2 STL1 STL0R/W R0 R0 R0 R/W R0 R0 R0 R/W R0 R0 R0 R0 R/W R/W R/W R/W

Initial value X X X 0 X X X 0 X X X X 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name – – – DLN4 DLN3 DLN2 DLN1 DLN0 – – SMOD SAUT – – SSP1 SSP0R/W R0 R0 R0 R/W R/W R/W R/W R/W R0 R0 R/W R/W R0 R0 R/W R/W

Initial value X X X 0 0 0 0 0 X X 0 0 X X 0 0 (Note) This register should be accessed in 32 bit unit.

Bit field



28 SPE SPI's clock supply is controlled.

0 Clock supply to internal logic stops except certain part (initial value) 1 Clock is supplied to all the circuits

Write "1" to operate SPI. Its state changes from sleep to setup by setting SPE bit. It changes to sleep by clear; at the same time, internal logic is reset except certain part.


24 DRVS Transfer order of serial data is specified.

0 MSB --> LSB (initial value) 1 LSB --> MSB


The write access is ignored. The read value of these bits is always "0". 19-16 STL3-0 Strobe width is specified at pulse mode selection (SMOD = 1) in the range of CK 1 ~ 16 cycles.

0000 CK 1cycle (initial value) 0001 CK 2cycles

: : 1110 CK 15cycles 1111 CK 16cycles


The write access is ignored. The read value of these bits is always "0".



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No. Name 12-8 DLN4-0 Data length of transmission/reception serial data is specified in the range of 1 ~ 32 bit.

00000 1 bit (initial value) 00001 2 bit 00010 3 bit

: : 11101 30 bit 11110 31 bit 11111 32 bit


The write access is ignored. The read value of these bits is always "0". 5 SMOD Operation mode of slave selection is specified. Slave selection signal is output to SPIxCX pin.

0 Selection mode (always active while communication) (initial value) 1 Pulse mode (after communicating, this becomes active)

4 SAUT Operation timing of slave selection is specified according to the combination of SMOD bit.

0 Slave selection synchronizes with SSP bit's setting value regardless of SMOD (see Figure 20-6) (initial value)

1 1CK of wait is added from SPI data register (SPIxDR) writing to serial data transmission, and from the last data transmission to asserting/negating salve selection (see Figure 20-7)


The write access is ignored. The read value of these bits is always "0". 1-0 SSP1-0 Slave selection pin to be active is specified.

00 Slave selection pin becomes non-active (initial value) 01 SPIxCX pin becomes active 10 Reserved (setting prohibited) 11 Reserved (setting prohibited)

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First Last

SIRQ

SPIxCK

SPIxDO

SSP Assert

SPIDR Write SSP

Negate

SPISR Read

BUSY

Figure 20-6 Timing chart of SPIxCX pin (at SAUT = 0)

First Last

SIRQ

SPIxCX SMOD=0

DPI_DO

SPIDR Write

BUSY

1SCK 1SCK

SIRQ

SPIxCX SMOD=1

STL

BUSY

Figure 20-7 Timing chart of SPIxCX pin (at SAUT = 1)



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20.6.4. SPI data register (SPIxDR) This register is used to write/read data to be transmitted to/received from SPI slave.


Name D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Note) This register should be accessed in 32 bit unit. Do not operate this register in the busy state.

Bit field

Description No. Name 31-0 D31-0 Transmission/Reception data to SPI slave is stored.

SPIxDR is reset at moving to the sleep state. Writing to this register in the setup state starts transmission/reception of the data length specified in DLN[4:0] bit of SPI slave control register (SPIxSCR), and LSB is fixed regardless of the data length.



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20.6.5. SPI status register (SPIxSR) This register is to maintain SPI state, and it is not able to be written.

Address SPI0: FFF4_0000H + 0CH SPI1: FFF4_0800H + 0CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name – – – – – – – – – – – – – – – – R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0


Name – – – – – – – – SIRQ – – – – SERR SBSY SENBR/W R0 R0 R0 R0 R0 R0 R0 R0 R R R R R R R R

Initial value X X X X X X X X 0 X X X X 0 0 0 (Note) This register should be accessed in 32 bit unit

Bit field


The write access is ignored. The read value of these bits is always "0". 7 SIRQ Proper completion of communication between master and slaves is indicated.

0 It is under the communication or stand-by (initial value) 1 Communication is completed

SIRQ pin outputs this bit. It is cleared by reading SPIxSR register. Figure 20-6 and Figure 20-7 show timing chart.


2 SERR Operation error is indicated.

0 Normal operation is in process (initial value)

1 Prohibited operation occurs Clear SPE bit of SPI slave control register (SPIxSCR)

SERR bit is set to "1" by processing other operations than reading SPIxCR, SPIxSCR, and SPIxSR in the busy state. Moreover, this bit is cleared by changing state to sleep with clearing SPE bit of SPIxSCR.

1 SBSY Communication with SPI slave is in process.

0 It is standing-by (initial value) 1 It is communicating

SBSY is set to "1" by writing to SPI data register (SPIxDR.) Do not clear SPE bit of SPIxSCR in the busy state. This bit is released by either of followings: • SIRQ bit setting • SERR bit setting

0 SENB SPI circuit is active.

0 Clock supply to internal logic is stop except to certain part (initial value) 1 Clock is supplied to all the circuits



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20-13


20.7. Setup procedure flow Figure 20-8 shows SPI setup procedure flow.

START STATE = SLEEP

Yes

No

START STATE = SLEEP

STATE = ERROR ?

Write SPIxSCR (SPE set/clear)

Write SPIxCR

STATE = SETUP ?

DATA communication

No

Yes

Yes

No

STATE = BUSY ?

Read SPIxSR (SIRQ clear)

Write SPIxDR (TxRx start)

STATE = SETUP ?

No

Yes

DATA Communication

start

Delete received data?

Read SPIxDR

Continue data communication without

setting change?

DATA

communication end

Yes

No

Yes

No

Figure 20-8 SPI setup flow chart



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21-1



CAN interface

21. CAN interface (CAN) This chapter describes CAN interface. Refer following website for CAN module specification. URL: http://www.semiconductors.bosch.de/en/20/can/products/ccan.asp

21.1. Outline This LSI equips 1 CAN interface which is in compliance with CAN protocol version 2.0 part A and B.

21.2. Related pin CAN uses following pins.

Pin Direction Qty. Description CANTX OUT 1 CAN I/F transmit CANRX IN 1 CAN Received

CAN related pin is common with other peripheral I/O functions. To use those pins as CAN interface terminal set corresponding bit of CPSEL register as following

• Set CPSEL[7] = "1B"

21.3. Supply clock APB clock is supplied to CAN interface. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.

21.4. Register This LSI use byte address (8 bit) for register mapping. 16-bit length register is allocated in a unit of word address (32 bit) for local address of CAN; therefore, only 16 bits data of APB Bus (32-bit width) is valid.

Table 21-1 CAN 0ch register map Register address CAN 0ch register address APB Bus data[31:0]

FFF5_4000h 00h {0x0000, 16 bit data} FFF5_4004h 02h {0x0000, 16 bit data} FFF5_4008h 04h {0x0000, 16 bit data}

… … …

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http://www.semiconductors.bosch.de/en/20/can/products/ccan.asp

MB9G711 LSI Product specifications

22. Serial audio interface (I2S) This chapter describes function and operation of serial audio interface (hereafter called, I2S.)

22.1. Outline This LSI equips audio I/O interface in I2S format, and up to 2 channels are able to be used.

Note: I2S is Inter-IC Sound bus advocated by Philips Semiconductors (now NXP).

22.2. Feature I2S interface in MB9G711 has following features:

• Selecting master/slave operations by programmable • Supporting state of transmission only, reception only, and simultaneous transmission/reception • Selecting 1 sub frame and 2 sub frame constructions • Setting up to 32 channels to each sub frame • Individually setting number of channel in each sub frame • Individually setting channel length of each sub frame (number channel bit) • Individually setting word length in channel of each sub frame (corresponding to MSB-Justified) • Setting valid/invalid of each channel in each sub frame (Note 1) • Setting word length from 7 to 32 bit • Programming frequency of frame synchronous signal • Setting up to 3071 bit in 1 frame • Programming width of frame synchronous signal (1 bit or 1 channel length) • Programming phase of frame synchronous signal (0 bits or 1 bit delay) • Setting polarity of frame synchronous signal • Setting polarity of serial bit clock • Programming sampling point of received data • Selecting clock frequency dividing source of serial bit clock in the master mode (internal and external

clock.) • Setting clock frequency dividing ratio in the master mode

Frequency of I2S_SCLK = frequency of AHB clock (or external clock)/2 × CKRT[5:0] Frequency dividing ratio is settable within 0 – 126 in multiple of 2 (when the ratio is 0, frequency dividing source is by-passed)

• Data transfer to system memory by DMA, interrupt, and polling

Note 1: Data is not sent or received to invalid channel


Serial audio interface (I2S)

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22.3. Block diagram Figure 22-1 shows block diagram of I2S. As shown below, MB9G711 has 2 channels of I2S module.

I2S0 Module

I2S0CK

I2S0WS

I2S0SDO

AHB Bus

HDMAC

I2S0SDI

I2S1 Module

I2S1CK

I2S1WS

I2S1DO

I2S1DI

AUCLKGEN

I2S1ECLKI2S0ECLK

ECLK

ECLK

Figure 22-1 Block diagram of I2S



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22.4. Related pin I2S interface uses following pins which are common with other functions. To use this pin as Serial audio interface (I2S), make setting to use I2S function for external pin by using the Chip port function select register CPSEL of CCNT module.

Table 22-1 I2S related pin Pin Direction Qty. Description

I2S0CK I2S1CK

IO 2 Bit clock input/output signal In the master mode: Clock output In the slave mode: Clock input

I2S0WS I2S1WS

IO 2 Input/Output signals of frame synchronization Polarity is settable in the register In the master mode: Frame synch. signal output In the slave mode: Frame synch. signal input

I2S0DI I2S1DI

I 2 Serial reception data input signal

I2S0DO I2S1DO

O 2 Serial transmission data output signal

22.5. Supply clock AHB clock and I2SxECLK are supplied to I2S interface unit. Refer to "5. Clock reset generator (CRG)" and “6. Audio clock generator” for frequency setting and control specification of the clock.



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22.6. Register This section describes I2S register.

22.6.1. Register list Register relating to I2S control is shown below.

Table 22-2 I2S register list Module Address Register Function

I2S ch0 FFEE_0000 I2S0RXFDAT Reception FIFO data register FFEE_0004 I2S0TXFDAT Transmission FIFO data register FFEE_0008 I2S0CNTREG Control register FFEE_000C I2S0MCR0REG Channel control register 0 FFEE_0010 I2S0MCR1REG Channel control register 1 FFEE_0014 I2S0MCR2REG Channel control register 2 FFEE_0018 I2S0OPRREG Operation control register FFEE_001C I2S0SRST Software reset register FFEE_0020 I2S0INTCNT Interrupt control register FFEE_0024 I2S0STATUS STATUS register FFEE_0028 I2S0DMAACT DMA start-up register

I2S ch1 FFEF_0000 I2S1RXFDAT Reception FIFO data register FFEF_0004 I2S1TXFDAT Transmission FIFO data register FFEF_0008 I2S1CNTREG Control register FFEF_000C I2S1MCR0REG Channel control register 0 FFEF_0010 I2S1MCR1REG Channel control register 1 FFEF_0014 I2S1MCR2REG Channel control register 2 FFEF_0018 I2S1OPRREG Operation control register FFEF_001C I2S1SRST Software reset register FFEF_0020 I2S1INTCNT Interrupt control register FFEF_0024 I2S1STATUS STATUS register FFEF_0028 I2S1DMAACT DMA start-up register

All registers of I2S correspond to access in byte (8 bit), half word (16 bit), and word (32 bit.)



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Description format of register Following format is used for description of register’s each bit in "22.6.2 I2SxRXFDAT register" to "22.6.12 I2SxDMAACT register".


Name R/W


Name R/W

Initial value










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22.6.2. I2SxRXFDAT register This register is reception FIFO register that is able to maintain up to 66 words (simultaneous transfer mode) or 132 words (reception only mode.)

Address ch0：FFEE_0000 (h) ch1：FFEF_0000 (h) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name RXDATA R/W R R R R R R R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name RXDATA R/W R R R R R R R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field

Description No. Name 31-0 RXDATA[31:0] The word received from serial bus is written to reception FIFO.

When frame is 1 sub frame construction and word length set to S0WDLN of MCR0REG register is 32 bit or less (16 bit when RHLL of CNTREG register is "1"), it is written to reception FIFO after higher order bit is extended. When frame is 2 sub frame construction and word length set to S0WDLN of MCR0REG register is 32 bit or less (16 bit when RHLL of CNTREG register is "1"), reception data of sub frame 0 is written to reception FIFO after higher order bit is extended. For the case that word length set to S1WDL of MCR0REG register is 32 bit or less, receptiondata of sub frame 1 is written to reception FIFO after higher order bit is extended. When BEXT of CNTREG register is "1", it is extended with MSB of reception word (sign extension). For the case that the value is "0", it is enhanced by "0". Top of the data (First In) of reception FIFO is able to be read by read access (First Out). After read the top of the data, it is automataically updated to next reception FIFO data . It is able to be accessed regardless of shift register's operation status. When RXNUM of STATUS register is "0", data read from RXDATA is invalid. Writing to RXDATA is ignored.



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22.6.3. I2SxTXFDAT register This register is transmission FIFO register that is able to maintain up to 66 words (simultaneous transfer mode) or 132 words (transmission only mode.)


Name TXDATA R/W W W W W W W W W W W W W W W W W Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name TXDATA R/W W W W W W W W W W W W W W W W W Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field

Description No. Name 31-0 TXDATA[31:0] Word to be transmitted is able to be written as long as transmission FIFO is not full.

Write access is able to be performed regardless of shift register's operation status. The word written to full transmission FIFO is actually not written. Although writing data is accessed in word, half-word, and byte access, actual number of bit to be transmitted is determined by S0WDL and S1WDL (when frame is 2 sub frame) of MCR0REG register. The data read from TXDATA is invalid. (last written data after right justified )



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22.6.4. I2SxCNTREG register


Name CKRT OVHD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name (Res) MSKB MSMD SBFN RHLL ECKM BEXT FRUN MLSB TXDIS RXDIS SMPL CPOL FSPH FSLN FSPL R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0

Bit field


31-26 CKRT[5:0] This sets output clock frequency dividing ratio at master operation. AHB clock is divided at ECKM = 0, and external clock is divided at ECKM = 1. Only even number of the ratio is supported and output clock's DUTY becomes 50%. CKRT [5:0] × 2 becomes number of AHB clock or external clock cycle included in 1 cycle (I2S_SCKx.) Setting examples are shown below.

External clock mode and external clock are 24.576MHz:

CKRT Dividing ratio I2S_SCKx

0x00 By pass 24.576MHz (external clock is output as it is)

0x01 1/2 12.288MHz 0x02 1/4 6.144MHz 0x03 1/6 4.096MHz 0x04 1/8 3.072MHz 0x05 1/10 2.458MHz

: : :

Internal clock mode and AHB clock are 80MHz: CKRT Dividing ratio I2S_SCKx

: : : 0x04 1/8 10MHz 0x05 1/10 8MHz 0x06 1/12 6.67MHz 0x07 1/14 5,71MHz 0x08 1/16 5MHz 0x09 1/18 4.44MHz

: : :

25-16 OVHD[9:0] Frame rate is able to be adjusted by inserting OVHD bit following to valid data of the frame. OVHD section of the transmission frame becomes in high impedance. The number of OVHD bit which can be inserted in the end of the frame is from 0 to 1023 bits. The value set to OVHD becomes the number of insertion bit. The relationship between OVHD and frame synchronous signal is explained in the following: 1 sub frame construction:

OVHD = Frame synchronous signal cycle/I2S_SCKx cycle – (S0CHL + 1) × (S0CHN + 1) 2 sub frame construction:

OVHD = Frame synchronous signal cycle/I2S_SCKx cycle – (S0CHL + 1) × (S0CHN + 1) – (S1CHL + 1) × (S1CHN + 1)

Note: It is recommended to use the same frame rate in both I2S master and slave.

15 (Reserved) Reserved bits. The write access is ignored. The read value of these bits is always "0".



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No. Name 14 MSKB Serial output data of invalid transmission frame is set.

For master operation (MSMD = 1), free-running mode (FRUN = 0), and TXENB = 1: When transmission FIFO is empty at frame synchronous signal output, MSKB is output to all

valid channels of its transmission frame. For slave operation (MSMD = 0) and TXENB = 1: When transmission FIFO is empty at frame synchronous signal reception, MSKB is output to

all valid channels of its transmission frame. For the case that transmission word length is shorter than the channel length, MSKB is driven to the rest of bit in transmission channel (channel length -word length.)

13 MSMD Master and slave modes are set.

0 Slave operation 1 Master operation

12 SBFN Sub frame construction (number of sub frame) of the frame is specified.

0 1 sub frame construction (only sub frame 0) 1 2 sub frame construction (sub frame 0 and sub frame 1)

Frame starts from the 0th sub frame

11 RHLL Number of word construction of FIFO (1 word or 2 words) is set.

0 32 bit FIFO word is handled as 1 word 1 In serial bus transmission, 32 bit FIFO word is seperated into 2 parts, upper 16 bit

and lower 16 bit, and this 32 bit FIFO word is treated as 2 words. Each word is transferred by the serial bus and the order of the word trasfer is as follows: Lower bit → Higher bit → Lower bit → Higher bit. In reception, two successive 16 bit data is treated as upper 16 bit and lower 16 bit. Then the upper and lower bit are combined into 32 bit, and written into reception FIFO.

10 ECKM Clock frequency dividing is selected in the master mode.

0 Internal clock (AHB clock) is divided and output 1 External clock (I2S_ECLKx pin input) is divided and output

9 BEXT When reception word length is shorter than the word length of FIFO (32 bit when RHLL is "0",

and 16 bit when RHLL is "1"), extension mode of upper bit (word length of FIFO - reception word length) should be set.

0 Extended by 0 1 Extended by sign bit (When MSB of word is "1", it is extended using "1" and when

MSB of word is "0", it is extended using "0")

8 FRUN Output mode of frame synchronous signal is set.

0 Burst mode When start bit of OPRREG register is "1", frame synchronous signal is outputaccording to TXENB, RXENB, and transmission/reception FIFO conditions

1 Free-running mode When start bit of OPRREG register is "1", frame synchronous signal proceeds free-running with the set frame rate When start bit is "0", frame synchronous signal is not output.

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No. Name 7 MLSB Word bit's shift order is set.

0 Shift starts from MSB of the word 1 Shift starts from LSB of the word

6 TXDIS Transmitting function is enabled or disabled.

0 Transmitting function is enabled 1 Transmitting function is disabled

5 RXDIS Receiving function is enabled or disabled.

0 Receiving function is enabled 1 Receiving function is disabled

4 SMPL Sampling point of the data is specified.

0 Sampling at the center of reception data

If CPOL bit setting is “0”, the sampling time of the reception data is rising edge of I2S_SCKx. If CPOL bit setting is “1”, the sampling time of the reception data is falling edge of I2S_SCKx.

1 Sampling at the end of reception data If CPOL bit setting is “0”, the sampling time of the reception data is falling edge of I2S_SCKx If CPOL bit setting is “1”, the sampling time of the reception data is rising edge of I2S_SCKx

3 CPOL I2S_SCKx polarity which drives/samples serial data is specified.

0 Data is driven at rising edge of I2S_SCKx. 1 Data is driven at falling edge of I2S_SCKx.

Note: Sampling of reception data is based on SMPL setting.

2 FSPH Phase is specified to I2S_WSx frame data.

0 I2S_WSx becomes valid 1 clock before the first bit of frame data 1 I2S_WSx becomes valid at the same time as the first bit of frame data

1 FSLN Pulse width of I2S_WSx is specified.

0 Pulse width is 1 cycle/I2S_SCKx long (1 bit) 1 Pulse width is 1 channel long (1 channel)

Setting "1" is prohibited when frame length is 1 channel long.

0 FSPL Polarity of I2S_WSx pin is set.

0 Frame synchronous signal becomes valid with I2S_WSx is "1" The value is "0" at idle

1 Frame synchronous signal becomes valid with I2S_WSx is "0" The value is "1" at idle

Note: Do not overwrite CNTREG register when start bit of OPRREG register is "1".

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22.6.5. I2SxMCR0REG register

Address ch0：FFEE_000C (h) ch1：FFEF_000C (h) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name (Res) S1CHN S1CHL S1WDL R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name (Res) S0CHN S0CHL S0WDL R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field

Description No. Name 31 (Reserved) Reserved bits.

The write access is ignored. The read value of these bits is always "0". 30-26 S1CHN[4:0] Number of channel of sub frame 1 is set.

This is valid only when the frame is 2 sub frame construction (SBFN of CNTREG is "1"), and is invalid when the frame is 1 sub frame construction (SBFN of CNTREG is "0".) Up to 32 channels are able to be specified, and S1CHN needs to be set to "number of channel –1". Example 1 S1CHN = "00011": Sub frame 1 becomes 4 channel construction Example 2 S1CHN = "11111": Sub frame 1 becomes 32 channel construction S1WDL is valid only in 2 sub frame construction (SBFN of CNTREG is "1") and is invalid in 1 sub frame construction (SBFN of CNTREG is "0".)

25-21 S1CHL[4:0] Channel length of the channel constructing sub frame 1 (bit length of channel) is set. 7 - 32 bit of channel length are available but 1 - 6 bit are prohibited. S1CHN needs to be set to "number of channel – 1". Example 1 S1CHL = "00110": Channel length becomes 7 bit Example 2 S1CHL = "11111": Channel length becomes 32 bit Channel length is able to be set to 32 or less regardless of RHLL value of CNTREG register. S1WDL is valid only in 2 sub frame construction (SBFN of CNTREG is "1") and is invalid in 1 sub frame construction (SBFN of CNTREG is "0".)

20-16 S1WDL[4:0] Word length of the channel constructing sub frame 1 (bit length of channel) is set. 7 - 32 bit of word length are available but 1 - 6 bit are prohibited. S1WDL needs to be set to "word length – 1". Example 1 S1WDL = "00110": Word length becomes 7 bit Example 2 S1WDL = "11111": Word length becomes 32 bit RHLL of CNTREG register is "1": Set word length to 16 or less and channel length to shorter than the one set to S1CHL RHLL of CNTREG register is "0": Set word length to 32 or less and channel length to shorter than the one set to S1CHL S1WDL is valid only in 2 sub frame construction (SBFN of CNTREG is "1") and is invalid in 1 sub frame construction (SBFN of CNTREG is "0".)

15 (Reserved) Reserved bits. The write access is ignored. The read value of these bits is always "0".

14-10 S0CHN[4:0] Number of channel of sub frame 0 is set up to 32 channels. S0CHN needs to be set to "number of channel – 1". Example 1 S0CHN = "00011": Sub frame 0 becomes 4 channel construction Example 2 S0CHN = "11111": Sub frame 0 becomes 32 channel construction



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No. Name 9-5 S0CHL[4:0] Channel length of the channel constructing sub frame 0 (bit length of channel) is set.

7 - 32 bit of channel length are available but 1 - 6 bit are prohibited. S0CHN needs to be set to "channel length – 1". Example 1 S0CHL = "00110": Channel length becomes 7 bit Example 2 S0CHL = "11111": Channel length becomes 32 bit The channel length can be set to 32 or less regardless of RHLL value of CNTREG register.

4-0 S0WDL[4:0] Word length of the channel constructing sub frame 0 (number of bit in channel) is set. 7 - 32 bit of word length are available but 1-6 bit are prohibited. S0WDL needs to be set to "word length – 1". Example 1 S0WDL = "00110": Word length becomes 7 bit Example 2 S0WDL = "11111": Word length becomes 32 bit RHLL of CNTREG register is "1": Set word length to 16 or less and channel length to shorter than the one set to S0CHL RHLL of CNTREG register is "0": Set word length to 32 or less and channel length to shorter than the one set to S0CHL

22.6.6. I2SxMCR1REG register This register controls enable and disable functions to each channel of sub frame 0.


Name S0CH31

S0CH30

S0CH29

S0CH28

S0CH27

S0CH26

S0CH25

S0CH24

S0CH23

S0CH22

S0CH21

S0CH20

S0CH19

S0CH18

S0CH17

S0CH16

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name S0CH15

S0CH14

S0CH13

S0CH12

S0CH11

S0CH10

S0CH09

S0CH08

S0CH07

S0CH06

S0CH05

S0CH04

S0CH03

S0CH02

S0CH01

S0CH00


Bit field

Description No. Name 31-0 S0CH31-S0CH00 The number at the end of each bit name (example: S0CHxx) indicates channel number of sub

frame 0 (e.g. S0CH00 bit controls 0th channel of sub frame 0.) Thus, S0CH31 bit controls 31st channel of sub frame 0.

0 The corresponding channel is disabled Transmission/Reception are not performed to the disabled channel

1 The corresponding channel is enabled Transmission/Reception are performed to the enabled channel

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22.6.7. I2SxMCR2REG register This register is to control enable and disable functions to each channel of sub frame 1.


Name S1CH31

S1CH30

S1CH29

S1CH28

S1CH27

S1CH26

S1CH25

S1CH24

S1CH23

S1CH22

S1CH21

S1CH20

S1CH19

S1CH18

S1CH17

S1CH16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name S1CH15

S1CH14

S1CH13

S1CH12

S1CH11

S1CH10

S1CH09

S1CH08

S1CH07

S1CH06

S1CH05

S1CH04

S1CH03

S1CH02

S1CH01

S1CH00


Bit field

Description No. Name 31-0 S1CH31-S1CH00 Name (S1CHxx) of each bit indicates channel number xx of sub frame 1 (e.g. S1CH00 bit

controls 0th channel of sub frame 1.) Thus, S1CH31 bit controls 31st channel of sub frame 1. When frame is 1 sub frame construction (SBFN of CNTREG is "0"), this is invalid.

0 The corresponding channel is disabled Transmission/Reception are not performed to the disabled channel

1 The corresponding channel is enabled Transmission/Reception are performed to the enabled channel



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22.6.8. I2SxOPRREG register


Name (Reserved) RXENB (Reserved) TXENBR/W R R R R R R R R/W R R R R R R R R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name (Reserved) start R/W R R R R R R R R R R R R R R R R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field


31-25 (Reserved) Reserved bits. The write access is ignored. The read value of these bits is always "0".

24 RXENB Enable/Disable functions of receiving operation is set.

0 Receiving operation is disabled Reception FIFO becomes empty with writing "0" to this bit When RXENB is "0", the data received from serial reception bus is not written to reception FIFO DMA reception channel stops during DMA transfer

1 Receiving operation is enabled


16 TXENB Enable/Disable functions of transmitting operation is set.

0 Transmitting operation is disabled Reception FIFO becomes empty with writing "0" to this bit When TXENB is "0", the data written to TXFDAT register from CPU or DMA isnot written to transmission FIFO DMA reception channel stops during DMA transfer

1 Transmitting operation is enabled


0 start I2S is enabled/disabled.

0 I2S is stopped, and internal transmission/reception FIFO becomes empty by writing "0" to this bit

1 I2S is operable Prohibit overwriting CNTREG, MCR0REG, MCR1REG, and MCR2REG registers when Start is "1".



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22.6.9. I2SxSRST register This register is to control I2S software reset.

Address ch0：FFEE_001C (h) ch1：FFEF_001C (h) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name (Reserved) SRSTR/W R R R R R R R R R R R R R R R R/W

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



The write access is ignored. The read value of these bits is always "0". 0 SRST Software reset is performed by writing "1".

STATUS register and each internal state machine become initial state by software reset, and transmission/reception FIFO becomes empty. There is no influence in registers other than STATUS, INTCNT, and DMAACT registers. When read value is "0" after writing "1", it indicates software reset is completed. "1" indicates software reset is in process.



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22.6.10. I2SxINTCNT register


Name (Res) TXUD1M TBERM FERRM TXUD0M TXOVM TXFDM TXFIM (Reserved) RBERM RXUDM RXOVM EOPM RXFDM RXFIM R/W R R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W

Initial 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name (Reserved) TFTH (Reserved) RPTMR RFTH R/W R R R R R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31 (Reserved) Reserved bits.

The write access is ignored. The read value of these bits is always "0". 30 TXUD1M This is transmission FIFO underflow interrupt mask bit.

It becomes "1" by software reset.

0 Interrupt to CPU by TXUDR1 of STATUS register is not masked 1 Interrupt to CPU by TXUDR1 of STATUS register is masked

29 TBERM This is interrupt mask bit of block size error of transmission channel.


0 Interrupt to CPU by TBERR of STATUS register is not masked 1 Interrupt to CPU by TBERR of STATUS register is masked

28 FERRM This is frame error interrupt mask bit.


0 Interrupt to CPU by FERR of STATUS register is not masked 1 Interrupt to CPU by FERR of STATUS register is masked.

27 TXUD0M This is transmission FIFO underflow interrupt mask bit.


0 Interrupt to CPU by TXUDR0 of STATUS register is not masked. 1 Interrupt to CPU by TXUDR0 of STATUS register is masked.

26 TXOVM This is transmission FIFO overflow interrupt mask bit.


0 Interrupt to CPU by TXOVR of STATUS register is not masked. 1 Interrupt to CPU by TXOVR of STATUS register is masked.

25 TXFDM This is DMA request mask register bit.


0 DMA transfer is requested when reception data written to transmission FIFO is threshold value or more

1 DMA transfer is not requested even reception data written to transmission FIFO is threshold value or more



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No. Name 24 TXFIM This is transmission FIFO interrupt mask bit.


0 Interrupt to CPU by TXFI of STATUS register is not masked 1 Interrupt to CPU by TXFI of STATUS register is masked


The write access is ignored. The read value of these bits is always "0". 21 RBERM This is interrupt mask bit of reception channel block size error.


0 Interrupt to CPU by RBERR of STATUS register is not masked 1 Interrupt to CPU by RBERR of STATUS register is masked

20 RXUDM This is reception underflow interrupt mask bit.


0 Interrupt to CPU by RXUDR of STATUS register is not masked 1 Interrupt to CPU by RXUDR of STATUS register is masked

19 RXOVM This is interrupt mask bit of reception FIFO overflow.


0 Interrupt to CPU by RXOVR of STATUS register is not masked 1 Interrupt to CPU by RXOVR of STATUS register is masked

18 EOPM This is interrupt mask bit by EOPI of STATUS register.


0 Interrupt to CPU by EOPI of STATUS register is not masked 1 Interrupt to CPU by EOPI of STATUS register is masked

17 RXFDM This is reception DMA request mask bit.


0 DMA transfer is requested when reception data written to reception FIFO is threshold value or more

1 DMA transfer is not requested though reception data written to reception FIFO is threshold value or more

16 RXFIM This is reception FIFO interrupt mask bit. It becomes "1" by software reset.

0 Interrupt to CPU by RXFI of STATUS register is not masked 1 Interrupt to CPU by RXFI of STATUS register is masked


The write access is ignored. The read value of these bits is always "0".

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No. Name 11-8 TFTH[3:0] Threshold value of transmission FIFO is set.

Empty space of transmission FIFO is threshold value or more and TXFIM is "0": Interrupt to CPU occurs Empty space of transmission FIFO is threshold value or more and TXFDM is "0": DMA is requested to DMA controller TFTH is set according to the following expressions.

TFTH = Transmission FIFO threshold – 1

Note: In this LSI, if DMA is used (only block/burst mode supported in I2S), the TFTH setting should be equal to the Block Count (BC) value (TFTH[3:0] = BC[3:0]) of the DMA channel. The minimum value for TFTH is 1 (Transmission FIFO threshold = 2) for DMA transfer. No restriction for Transfer Count (TC) setting in DMA transmission channel.


5-4 RPTMR[1:0] This is packet reception completion timer setting bit which sets time-out value of the internal reception completion timer. Reception FIFO is not empty and number of its data is smaller than threshold value: The timer always counts up Reception FIFO is empty or the data value is threshold value or more: The timer is cleared. When the timer becomes time-out, EOPI bit of STATUS register is set to "1". The timer becomes "00" by software reset.

00 0 (the timer is not in operation) 01 54000 AHB clock cycles 10 108000 AHB clock cycles 11 216000 AHB clock cycles

3-0 RFTH[3:0] Threshold value of reception FIFO is set.

Number of reception word written to reception FIFO is threshold value or more and RXFIM is "0": Interrupt to CPU occurs Number of reception word written to reception FIFO is threshold value or more and RXFDM is "0": DMA is requested to DMA controller RFTH is set according to the following expressions.

RFTH = Reception FIFO threshold – 1

Note: In this LSI, if DMA is used (only block/burst mode supported in I2S), the RFTH setting should be equal to the Block Count (BC) value (RFTH[3:0] = BC[3:0]) of the DMA channel. The minimum value for RFTH is 1 (Reception FIFO threshold = 2) for DMA transfer. No restriction for Transfer Count (TC) setting in DMA receiption channel.

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22.6.11. I2SxSTATUS register


Name TBERR RBERR FERR TXUDR1 TXUDR0 TXOVR RXUDR RXOVR (Reserved) EOPI BSY TXFI RXFI R/W R R R/W R/W R/W R/W R/W R/W R R R R R/W R R R

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name TXNUM RXNUM R/W R R R R R R R R R R R R R R R R

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31 TBERR If the block count (BC) setting for DMA transmission channel is not equal to the I2S transmission

FIFO threshold (TFTH), this bit is set to “1” when DMA transfer encounter errors. When TBERR is "1" and TBERM of INTCNT register is "0", interrupt to CPU occurs. This becomes "0" by software reset.

30 RBERR If the block count (BC) setting for DMA reception channel is not equal to the I2S transmission FIFO threshold (RFTH), this bit is set to “1” when DMA transfer encounter errors. When RBERR is "1" and RBERM of INTCNT register is "0", interrupt to CPU occurs. This becomes "0" by software reset.

29 FERR Occurrence of frame error is indicated. This bit is set to "1" in the following cases: • Frame synchronous signal is not able to be received with the set frame rate in the free-running

mode (FRUN = 0 of CNTREG) and the slave mode (MSMD = 0 of CNTREG) • The next frame synchronous signal is received during frame transmission/reception in the slave

mode (MSMD = 0 of CNTREG), not free-running mode (FRUN = 1 of CNTREG) When FERR is "1" and FERRM of INTCNT register is "0", interrupt to CPU occurs. Writing "1" from CPU clears the value to "0". This becomes "0" by software reset.

28 TXUDR1 When transmission FIFO underflows at the top of frame, the value is set to "1". Writing "1" from CPU clears the value to "0". This becomes "0" by software reset.

27 TXUDR0 When transmission FIFO underflows during frame transmission (from 2nd bit word to the last frame of the word), the value is set to "1". Writing "1" from CPU clears the value to "0". This becomes "0" by software reset.

26 TXOVR When transmission FIFO overflows, the value is set to "1" indicating transmission data is written in the condition that transmission FIFO is full. The value "1" indicates 1 word or more of transmission data is deleted. When TXOVR is "1" and TXOVM of INTCNT register is "0", interrupt to CPU occurs. Writing "1" from CPU clears the value to "0". This becomes "0" by software reset.

25 RXUDR When reception FIFO underflows, the value is set to "1" indicating read access is carried out to reception FIFO in the condition that reception FIFO is empty. Writing "1" from CPU clears the value to "0". This becomes "0" by software reset.

24 RXOVR When reception FIFO overflows, the value is set to "1" indicating reception is carried out in the condition that reception FIFO is full. The value "1" indicates 1 word or more of reception data is deleted. When RXOVR is "1" and RXOVM of INTCNT register is "0", interrupt to CPU occurs. Writing "1" from CPU clears the value to "0". This becomes "0" by software reset.




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No. Name 19 EOPI This is interrupt flag containing reception timer. The timer is enabled when following conditions

are met at the same time, otherwise the timer value is automatically cleared: • RXDIS of CNTREG register is set to "0" • start bit of OPRREG register is set to "1" and RXENB = "1" • RPTMR of INTCNT register is not set to “00” • RX FIFO is not empty • The number of data in RX FIFO (RXNUM) is fewer than RX FIFO RFTH threshold

After the chip reset RSTX or SRST reset in I2SxSRST register, operation starts with the 1st word reception. When reception FIFO is not empty at the time set to RPTMR of INTCNT register, the value is set to "1". When EOPI is "1" and EOPM of INTCNT register is "0", interrupt to CPU occurs. The value is automatically cleared if reception FIFO data is threshold or more, or it becomes empty. Writing "1" from CPU clears the value to "0". This becomes "0" by software reset.

18 BSY Serial transmission control part is busy state. This bit is not affected by software reset.

0 Serial transmission control part is in idle 1 Serial transmission control part is in busy

17 TXFI When empty slot of transmission FIFO is larger than the threshold set in TFTH of INTCNT register,

this bit is set to "1". This bit is "1" and TXFIM bit of INTCNT register is "0": Interrupt to CPU occurs This bit is "1" and TXFDM bit of INTCNT register is "0": DMA is requested When number of empty slot of reception FIFO becomes smaller than the threshold by writing to TXFDAT register from CPU or DMAC, this bit is cleared automatically to "0". The value is also become "0" when start bit of OPRREG register is "0" and TXENB bit of OPRREG register is "0". If software reset is performed at start bit = "1" and TXENB bit = "1", the value becomes "0" during software reset then changes to "1" after the process.

16 RXFI When number of reception FIFO data is larger than the threshold set in RFTF of INTCNT register, this bit is set to "1". This bit is "1" and RXFIM bit of INTCNT register is "0": Interrupt to CPU occurs This bit is "1" and RXFDM bit of INTCNT register is "0": DMA is requested When number of data in reception FIFO becomes smaller than the threshold by reading RXFDAT register from CPU or DMAC, this bit is automatically cleared to "0". When start bit of OPRREG register is "0" or RXENB bit of OPRREG register is "0", this bit becomes "0". This becomes "0" by software reset.

15-8 TXNUM[7:0] The number of data in transmission FIFO is indicated. This bit is incremented by write access to TXFDAT register and decremented by serial word transfer. In the simultaneous transfer mode, the maximum value of TXNUM is 66. In transmission only mode, the maximum value of TXNUM is 132. This becomes "0" by software reset.

7-0 RXNUM[7:0] The number of data in reception FIFO is indicated. This bit is incremented by word reception from serial bus and decremented by read access to RXFDAT register. In the simultaneous transfer mode, the maximum value of TXNUM is 66. In transmission only mode, the maximum value of TXNUM is 132. This becomes "0" by software reset.

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22.6.12. I2SxDMAACT register


Name (Reserved) TDMACTR/W R R R R R R R R R R R R R R R R/W

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name (Reserved) RDMACTR/W R R R R R R R R R R R R R R R R/W

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



The write access is ignored. The read value of these bits is always "0". 16 TDMACT Transmission channel of DMAC (DMA controller) is activated.

After transfer channel starts, software should write "1" to TDMACT to teach I2S that the transfer channel is active. When TDMACT is "0", transfer request of transmission channel block is not sent to DMAC. I2S automatically clears TDMACT every time DMA packet transmission completes (DEOP from DMA controller is “1”). Writing "0" from CPU clears the value to "0". This becomes "0" by software reset.

0 Transmission channel of DMAC is stop that TXDREQ is unable to be detected 1 Transmission channel of DMAC is activated that TXDREQ is able to be detected

Only Block and Burst mode is supported for I2S DMA transfer in this LSI. Refer to section 9.3 for DMA request connection from I2S in this LSI. The DMA request is also affected by the DMA request mask setting (I2SxINTCNT.TXFDM). If TXFDM is “1”, there is no DMA request even TDMACT is “1”.


0 RDMACT The reception channel of DMAC (DMA controller) is activated. After reception channel starts, software should write "1" to RDMACT to teach I2S that thechannel is active. When RDMACT is "0", transfer request of reception channel block is not sent to DMAC. I2S automatically clears RDMACT every time DMA packet reception completes (DEOP from DMA controller is “1”). Writing "0" from CPU clears the value to "0". This becomes "0" by software reset.

0 Reception channel of DMAC is stop that RXDREQ is unable to be detected 1 Reception channel of DMAC is active that RXDREQ is able to be detected

Only Block and Burst mode is supported for I2S DMA transfer in this LSI. Refer to section 9.3 for DMA request connection from I2S in this LSI. The DMA request is also affected by the DMA request mask setting (I2SxINTCNT.RXFDM). If RXFDM is “1”, there is no DMA request even RDMACT is “1”.



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22.7. Operation

22.7.1. Outline This module is synchronous serial interface which enables full duplex and multiplexer channel. It is also able to correspond to various frame formats by register setting. (Refer to "22.7.3 Frame construction" for detail.) This module is also able to operate as master and slave. In the master mode, clock (I2S_SCKx) and frame synchronous signal (I2S_WSx) are output to the external slave. In the slave mode, they are input from the external master. During the master mode, I2S_SCKx clock can be output by dividing external clock (I2S_external clock x) or internal clock (it is selectable at register). Frame synchronous signal can be generated by free-running or burst mode (generated only when there is transmission data.) This module equips transmission/reception FIFO, and its depth varies depending on mode: transmission only mode is 132 word × 32 bit constructive transmission FIFO and reception only mode is 66 word × 32 bit constructive reception FIFO. Refer to "22.7.3 Frame construction" for more detail. Internal transfer between transmission and reception FIFO and internal system memory is able to be performed by DMA, interrupt, and polling.



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22.7.2. Transfer start, stop, and malfunction Transmission only mode

Transfer setting

Operation Master mode (MSMD = 1) Slave mode (MSMD = 0)

Transmission only TXDIS = 0 RXDIS = 1

Start Free-running mode (FRUN = 1): After start bit becomes "1" and TXENB bit is "1", frame synchronous signal starts to output when transmission FIFO is not empty. From the 2nd time, it outputs frame synchronous signal with the frame rate determined by the register setting. If transfer FIFO is empty, empty frame is output at the same time of frame synchronous signal output. Serial data of the empty frame is able to be set to "0" or "1" by the register setting.

Burst mode (FRUN = 0):

When start bit is "1" and TXENB bit is "1", frame synchronous signal is output if transfer FIFO is not empty. Always confirm transmission FIFO status at the end of 1 frame output or at idle to output the signal if transfer FIFO is not empty.

Free-running mode (FRUN = 1): The frame rate determined by the register setting inputs frame synchronous signal. If transmission FIFO is empty at inputting frame synchronous signal with start bit is "1" and TXENB bit is "1", empty frame is output. Serial data of the empty frame is able to be set to "0" or "1" by the register setting.

Burst mode (FRUN=0):

When start bit is "1" and TXENB bit is "1", 1 frame is output every time frame synchronous signal is input. When transmission FIFO is empty at the time of frame synchronous signal input, empty frame is output.

Stop At the time of stop, transmission FIFO becomes empty with having no data transfer from internal memory to I2S transmission FIFO. To maintain start bit to "1"

TXENB = "1": Keep outputting frame synchronous signal in the free-running mode. When transmission FIFO becomes empty, empty frame is output; however, do not output frame synchronous signal in the burst mode. Output empty frame bit to serial data bus.

TXENB = "0": When "0" is written to TXENB, transmission FIFO becomes empty that the data in the FIFO at writing "0" is not sent. Although frame synchronous signal continues outputting in the free-running mode, serial bus becomes in high impedance state. In the burst mode, frame synchronous signal is not output and serial data bus becomes in high impedance state.

To make start bit "0"

Write "0" to start bit, then transmission FIFO becomes empty. Stop clock supply to the serial control part regardless of TXENB setting, and do not output clock to external part. Frame synchronous signal output should also be stopped.

Serial data bus becomes in high impedance state.

To maintain start bit to "1" TXENB = "1":

Output empty frame data to serial bus. TXENB = "0": Write "0" to TXENB, then transmission FIFO becomes empty that the data in the FIFO at writing "0" is not sent. Data writing to transmission FIFO and transmission frame detection are stop. Serial data bus becomes in high impedance state.


Write "0" to start bit, then transmission FIFO becomes empty. Writing to transmission FIFO and detection of transmission frame synchronous signal are stop regardless of TXENB setting.



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Transfer setting


Abnormality When reading to transmission FIFO occurs with having it empty, empty frame is output. When writing to transmission FIFO occurs with having it full, set TXOVR to "1".

When reading to transmission FIFO occurs with having it empty, empty frame is output. However do not set TXUDR to "1" for the 1st output frame after bit becomes Start = "1" and TXENB = "1". When writing to transmission FIFO occurs with having it full, set TXOVR to "1". If it is not input with the frame rate defined frame synchronous signal in the free-running mode, set FERR bit of the register to "1". If the next frame synchronous signal is input before completing 1 frame transmission in the burst mode, set FERR bit of the register to "1"

Note: 1. TXDIS and RXDIS are for setting to enable and disable transmission/reception of CNTREG register. 2. Start, TXENB, and RXENB are operation control bits of OPRREG register. 3. Empty frame bit is determined by MSKB of CNTREG register.

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Reception only mode Transfer setting


Reception only TXDIS = 1 RXDIS = 0

Start Free-running mode (FRUN = 1): Frame synchronous signal starts to output after start bit becomes "1" and TXENB bit is "1" when transmission FIFO is not empty. From the 2nd time, output frame synchronous signal with the frame rate determined by the register setting.


When start bit is "1" and RXENB bit is "1", output frame synchronous signal to receive frame if reception FIFO is not full. If the FIFO is full, the signal does not output.

Free-running mode (FRUN = 1): When start bit is "1" and RXENB bit is "1", input frame synchronous signal with the frame rate determined by the register setting. Frame should be received every time the signal is input.


When start bit is "1" and RXENB bit is "1", perform frame reception every time frame synchronous signal is input. The signal is input with less speed than the frame rate in the free-running mode.

Stop At the time of stop, frame is not imported from serial bus even though reception FIFO is empty in the condition that data transfer from I2S reception FIFO to internal memory is not required. To maintain start bit to "1"

Write "0" to RXENB and empty reception FIFO. Although frame synchronous signal is kept outputting in the free-running mode, frame is not received. In the burst mode, frame is not received and the signal is not output.


Write "0" to start bit, then reception FIFO becomes empty. Clock supply to the serial control part stops regardless of RXENB setting, and I2S_SCKx supply to the external part is stop as well.

To maintain start bit to "1" Reception FIFO becomes empty by "0" writing to RXENB. Ignore the input frame synchronous signal, and do not receive the frame.

To make the start bit "0"

Write "0" to the start bit, then reception FIFO becomes empty. Ignore the input frame synchronous signal regardless of RXENB setting, and do not receive the frame.

Abnormality When writing to reception FIFO occurs with having it full, set RXOVR to "1". The bit also should be set to "1" when read access to reception FIFO occurs with having it empty.

When writing to reception FIFO occurs with having it full, set RXOVR of the STATUS register to "1". When read access to reception FIFO occurs with having it empty, set RXUDR of the register to "1".

Free-running mode: If frame synchronous signal is not input with the frame rate defined by the register setting, set FERR bit of the register to "1".

Burst mode:

Set the bit also to "1" if the next frame synchronous signal is input during 1 frame reception.

Note: 1. TXDIS and RXDIS are for setting to enable and disable transmission/reception of CNTREG register. 2. Start, TXENB, and RXENB are operation control bits of OPRREG register.



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Simultaneous transfer mode Transfer setting


Simultaneous transfer TXDIS = 0 RXDIS = 0

Start Free-running mode (FRUN = 1): Status of Start = 1, TXENB = 1, and RXENB = 1:

The same operation as transmission only mode. Status of Start = 1, TXENB = 0, and RXENB = 1:

The same operation as reception only mode. Status of Start = 1, TXENB = 1, and RXENB = 1:

Frame synchronous signal is output from the state that transmission FIFO is not empty and reception FIFO is not full. Then output frame synchronous signal with the frame rate defined by the register setting; at the same time, output empty frame if reception FIFO is empty. Empty frame's serial data is able to be set to "0" or "1" at the register setting. Every time frame synchronous signal is output, receive frame.


Status of Start = 1, TXENB = 1, and RXENB = 0:

The same operation as transmission only mode. Status of Start = 1, TXENB = 0, and RXENB = 1:

The same operation as reception only mode. Status of Start = 1, TXENB = 1, and RXENB = 1:

Frame synchronous signal is output from the state that transmission FIFO is not empty and reception FIFO is not full. After completion of 1 frame output or at idle state, always confirm transmission/reception FIFO status. If transmission FIFO is not empty and reception FIFO is not full, output frame synchronous signal to perform frame transmission/reception.

Free-running mode (FRUN = 1): Status of Start = 1, TXENB = 1, and RXENB= 0:

The same operation as transmission only mode. Status of Start = 1, TXENB = 0, and RXENB= 1:

The same operation as reception only mode. Status of Start = 1, TXENB = 1, and RXENB= 1:

Frame synchronous signal is input with the frame rate defined by the register setting; at the same time, output empty frame if transmission FIFO is empty. Its serial data is able to be set to "0" or "1" at the register setting. Every time frame synchronous signal is input, receive frame.


Every time frame synchronous signal is input with start bit is "1", transmission and reception for 1 frame is performed. When the signal is input, output empty frame if transmission FIFO is empty.



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Transfer setting


Stop Stop operation has following states: Transmission stop:

Transmission FIFO becomes empty without sending data from internal memory to I2S transmission FIFO.

Reception stop: Data does not need to be transferred from I2S reception FIFO to internal memory.

To maintain start bit to "1"

Keep outputting frame synchronous signal in the free-running mode. In the burst mode, do not output the signal when transmission FIFO becomes empty. Transmission stop:

TXENB = 1: Keep outputting empty frame bit when transmission FIFO becomes empty. TXENB = 0: Transmission FIFO becomes empty and transmission serial data bus becomes in high impedance. Do not send the data in transmission FIFO at writing "0" to TXENB. Writing to transmission FIFO stops.

Reception stop: Write "0" to RXENB, then reception FIFO becomes empty and frame reception operation stops.


Write "0" to start bit, then transmission/reception FIFO becomes empty. The clock supply to the internal serial control part stops regardless of TXENB and RXENB statuses as well as I2S_SCKXoutput to the external part and frame synchronous signal output.

To maintain start bit to "1" Transmission stop:

Keep outputting empty frame bit after transmission FIFO becomes empty in order to maintain this bit to TXENB = 1. When the value is changed to "0", transmission FIFO becomes empty and transmission serial data bus becomes in high impedance. Do not send the data in transmission FIFO at writing "0" to TXENB. Stop writing to transmission FIFO.

Reception stop: Write "0" to RXENB, then reception FIFO becomes empty and frame reception operation stops.


Write "0" to start bit, then transmission/reception FIFO becomes empty.Stop transmission/ reception regardless of TXENB and RXENB statuses.

Abnormality When reading to transmission FIFO occurs with having it empty, output empty frame bit. When writing to transmission FIFO occurs with having it full, set TXOVR to "1". If read access to reception FIFO occurs while it is empty, set RXUDR of STATUS register to "1". If writing to reception FIFO occurs with having it full, set RXOVR of the register to "1".

When reading to transmission FIFO occurs with having it empty, output empty frame bit. When writing to transmission FIFO occurs with having it full, set TXOVR to "1". When read access occurs to reception FIFO with having it empty, set RXUDR of STATUS register to "1". When writing to reception FIFO occurs with having it full, set RXOVR of the register to "1". If it is not input with the frame rate defined frame synchronous signal in the free-running mode, set FERR bit of the register to "1". If the next frame synchronous signal is input before completing 1 frame transmission in the burst mode, set FERR bit of the register to "1".

Note: 1. TXDIS and RXDIS are for setting to enable and disable transmission/reception of CNTREG register. 2. Start, TXENB, and RXENB are operation control bits of OPRREG register. 3. Empty frame bit is determined by MSKB of CNTREG register.

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22.7.3. Frame construction This module supports frame format of multiplexer channel construction. Frame is able to be set to 1 or 2 sub frames; moreover, number of each frame’s channel and word length are able to be set individually.

22.7.3.1. 1 sub frame construction

Figure 22-2 1 sub frame composite frame

Description 1. When SBFN bit of CNTREG register is "0", frame becomes 1 sub frame composite. 2. Number of channel of 1 sub frame is determined by S0CHN of MC0REG register.

Up to 32 channels are settable. 3. Each channel bit length (word length) is determined by S0WDL of MC0REG register. 4. Sub frame channel starts from 0th, and each channel is settable to valid/invalid with the corresponding bit of

MC1REG register. Transmission/Reception of data is not performed to invalid channel. 5 Dummy bit can be inserted behind sub frame by setting OVHD of CNTREG register.

0-1023 bit are insertable. 6. Polarity of I2S_WSx is set with FSPL bit of CNTREG register. 7. Pulse width of I2S_WSx can be set to 1 bit or 1 word length by setting FSLN bit of CNTREG register. 8. When I2S_WSx is active from rising edge, the first bit of frame (before channel 0 data) is configurable to "0" or "1".9. In this construction, setting of S1CHN of MC0REG register, S1WDL register and MC2REG register are ignored.



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22.7.3.2. 2 sub frame construction

Figure 22-3 2 sub frame composite frame

Description 1. When SBFN bit of CNTREG register is "1", frame becomes 2 sub frame composite that first sub frame is 0 and

the next one is 1. 2. Set number of channel of sub frame 0 to S0CHN of MC0REG register, and set number of sub frame 1 channel

to S1CHN of the register. Those numbers of channel are individual that they do not need to have the same channel. Up to 32 channels are settable.

3. Channel bit length (word length) of sub frame 0 is determined by S0WDL of MC0REG register. For sub frame 1, they are determined by S1WDL of MC0REG register. Since channel bit length of the sub frame is individual, those channels (word length) do not need to be the same.

4. Sub frame channel starts from 0th. Each channel of sub frame 0 is settable to valid/invalid with the corresponding bit of MC1REG register, and corresponding bit of MC2REG register for sub frame 1. Transmission/Reception of data is not performed to invalid channel.

5 Dummy bit can be inserted behind sub frame 1 by setting OVHD of CNTREG. 0-1023 bit are insertable.

6. Polarity of I2S_WSx is set to FSPL bit of CNTREG register. 7. Pulse width of I2S_WSx can be set to 1 bit or 1 channel length by setting FSLN bit of CNTREG register.

Channel length setting of 1 channel is determined by the channel length of sub frame 0. 8. Timing from the edge I2S_WSx becomes valid to the first bit of frame is settable to "0" or "1" bit.



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22.7.3.3. Bit alignment (1) Transmission word alignment

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AB0 MSB LSB

AB1 MSB LSB

AB2 MSB LSB

AB3 MSB LSB

AH0 MSB LSB

AH1 MSB LSB

AW MSB LSB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FB0 MSB LSB

FB1 MSB LSB

FB2 MSB LSB

FB3 MSB LSB

FH0 MSB LSB

FH1 MSB LSB

FW MSB LSB

S0WDL and S1WDL counts to the left from this bitWhen S0WDL and S1WDL are 3,

M L

M LS0WDL and S1WDL are 7,…

Image of CPU written to TXFDAT register

Image of TXFDAT written to FIFO

Transmission word

Transmission word

The data written to TXFDAT register from CPU or DMA is written to transmission FIFO after right adjusted.

Figure 22-4 Transmission word line chart

When transmission is performed with serial bus, word is sent from M bit when CNTREG register's MLSB is "0" and from L bit when the value is "1". When channel length (set to S0CHL and S1CHL) is longer than the word length (set to S0WDL and S1WDL), remaining bit in the channel becomes CNTREG[MSKB]. If channel length is shorter than the word's, setting is prohibited.

Note:

AB0, AB1, AB2, AB3, AH0, AH1, and AW on the above chart indicate byte 0, byte 1, byte 2, byte 3, half word 0, half word 1, and word at write accessing to TXFDAT on AHB bus. Each FB0, FB1, FB2, FB3, FH0, FH1, and FW indicate AB0, AB1, AB2, AB3, AH0, AH1, and AW are written to transmission FIFO after they are right justified.

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(2) Reception word alignment

MSB First LSB FirstSerial data input pin's shifting direction

B0 B1 B2 B3 B4 B5 B6 B7 B7 B6 B5 B4 B3 B2 B1 B0

B7 B6 B5 B4 B3 B2 B1 B0

0 1MLSB

Bit extension and right justificationBEXT = 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LSB

BEXT = 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB

BEXT = 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 LSB

BEXT = 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB

Write to reception FIFO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RXFDAT

Figure 22-5 Reception word line chart This chart shows word line example of when word length is 8. The word received from serial bus is always written to reception FIFO after right-justified. Therefore, read access should be performed from AHB bus to RXFDAT in order to read as follows:

Word length • 8 or less: Byte 0 • 9 – 16: Half word 0 • 17 – 32: Full word



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22.7.4. FIFO construction and description

Simultaneous transfer mode (TXDIS = 0 and RXDIS = 0)

Figure 22-6 Simultaneous transfer mode data flow With setting TXDIS = 0 and RXDIS = 0 of CNTREG register, the mode becomes simultaneous transfer mode which operates in 66 word × 32 bit transmission FIFO and reception FIFO.



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Transmission only mode (TXDIS = 0 and RXDIS = 1)

Figure 22-7 Transmission only mode data flow With setting TXDIS = 0 and RXDIS = 1 of CNTREG register, the mode becomes transmission only mode which operates in 132 word × 32 bit transmission FIFO, and reception is not performed.



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22-34


Reception only mode (TXDIS = 1 and RXDIS = 0)

SWITCHFIFO

W R

R W

TXDIS = 1 and RXDIS = 0

To RXFDAT register

From TXFDAT register

From reception pin

To transmission pin

18 word x 32 bit

18 word x 32 bit

Figure 22-8 Reception only mode data flow With setting TXDIS = 1 and RXDIS = 0 of CNTREG register, the mode becomes reception only mode which operates in 36 word × 32 bit reception FIFO, and transmission is not performed.



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23. NAND Flash interface This chapter describes NAND Flash interface of MB9G711.

23.1. Outline MB9G711 has external bus interface for accessing to external NAND Flash device.

23.2. Spec limitation NAND Flash interface provides the external area for NAND Flash access, address area are allocated in LSI during initialization. The base address for NAND flash is set via Flash Area Register (FAREA).

23.3. Feature External bus interface of MB9G711 has the following features.

• Supporting 8/16 bit width of NAND Flash • Parameter setting by selection NAND Flash • Support little endian • ECC supports to detect 2 bit errors (max) for every 512 bytes of data

23.4. Related pin Table 23-1 External interface related pin

Pin I/O No. of pin Function NFD[15:8] IO 8 Upper 8 bits of data bus. Use in x16 device NFD[7:0] IO 8 Data bus NFCEX O 1 Chip select (active low) NFCLE O 1 Command Latch Enable NFALE O 1 Address Latch Enable NFREX O 1 Read Enable (active low) NFWEX O 1 Write Enable (active low) NFRDY I 1 Ready Enable (active low)

23.5. Supply clock AHB clock is supplied to external bus interface. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.


NAND Flash interface

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23.6. Register This section describes 32 bit width NAND Flash interface register. Be sure to access to it in word (32 bit.)

23.6.1. Register list Table 23-2 NAND Flash Interface register list

Address Register Abbreviation Description

Base Offset FFFC_0000H + 00H Flash Mode Register FMODE This sets the bus width and enable of NAND Flash

+ 20H Flash Timing Register FTIM This sets flash timing parameters + 40H Flash Area Register FAREA This sets the address accessing flash

+ 60H ECC Control Register ECCR This sets the configuration settings for ECC. ECC result can also read from this register

+ 64H ECC Code Read Register 0 ECRR0 This register stores the ECC code generated in ECC0 macro

+ 68H ECC Code Read Register 1 ECRR1 This register stores the ECC code generated in ECC1 macro

+ 6CH ECC0 Code Write Register ECWR0 This register is to write the ECC code read from NAND flash spare area for ECC comparison in ECC0 macro

+ 70H ECC1 Code Write Register ECWR1 This register is to write the ECC code read from NAND flash spare area for ECC comparison in ECC1 macro

+ 74H ECC0 Error Position Register ECCPOS0 This register provides 1-bit correctable error location and bit position for ECC0 macro

+ 78H ECC1 Error Position Register ECCPOS1 This register provides 1-bit correctable error location and bit position for ECC1 macro

Description format of register

Following format is used for description of register’s each bit


Name R/W


Name R/W

Initial value





Attribution of read/write of each bit field • R0:Read value is always "0" • R1: Read value is always "1" • W0: Write value is always "0", and write access of "1" is ignored



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• W1: Write value is always "1", and write access of "0" is ignored • R: Read • W: Write



23.6.2. Flash mode register (FMODE) Address FFFC_0000H + 00H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name – – – – – – – – – – – – – – – – R/W R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0


Name – – – – – – – – – Reserved NAND Reserved WDTH R/W R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W R/W0 R/W0 R/W R/W

Initial value X X X X X X X X X 0 0 0 0 0 0 0



Write "0" to these bits. Their read value is undefined.

6-5 Reserved Reserved bits. Write “0” to these bits. Their read value is “0”

4 NAND NAND flash mode This bit controls the mode to connect NAND Flash. To enable the access to NAND Flash, this bit must be set to “1”. In NAND Flash mode, the external pin NFCEX is fixed to “L”, and NAND Flash dedicated pin is used in accesses after this. Reset this bit to “0” when NAND Flash is not used, and the NFCEX is fixed to “H”, and the NAND Flash is kept in power-saving state.

0 NAND flash mode OFF (initial value) 1 NAND flash mode ON

3-2 Reserved Reserved bits. Write “0” to these bits. Their read value is “0”

1-0 WDTH NAND Flash data width These bits specify data bit width of the connected device.

00 8 bit (initial value) 01 16 bit 10 Reserved 11 Reserved



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23.6.3. Flash timing register (FTIM) Address FFFC_0000H + 20H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Reserved WWEC WADC WACC R/W R/W0 R/W0 R/W0 R/W0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name RIDLC Reserved RADC RACC R/W R/W R/W R/W R/W R/W0 R/W0 R/W0 R/W0 R/W R/W R/W R/W R/W1 R/W1 R/W1 R/W1

Initial value 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1


No. Name 31-28 Reserved Reserved bits.

Write “0” to these bits. Their read value is all “0” 27-24 WWEC Write Enable Cycle

These bits set the number of write enable assertion cycle.

0000 1 cycle : :

0101 6 cycles (initial value) : :

1110 15 cycles 1111 Reserved

23-20 WADC Write Address Setup Cycle These bits set number of write access setup cycle. Address is output to the cycle; however, write enable is not asserted.

0000 1 cycle : :


1110 15 cycles 1111 Reserved

19-16 WACC Write Access Cycle These bits specify number of cycle required for write access. The address does not change during the cycle specified in these bits. This value should be larger than the sum of Address Setup Cycle (WADC) and Write Enable Cycle (WWEC) by 1 cycle. WACC – WADC – WWEC >= 1 cycle

0000 Reserved 0001 Reserved 0010 3 cycles

: : 1111 16 cycles (initial value)

15-12 RIDLC Read Idle Cycle These bits set number of idle cycle after read access. They are used to prevent data collision that occurs by write access immediately after the read access.

0000 Reserved 0001 Reserved 0010 3 cycles

: : 1111 16 cycles (initial value)



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Write “0” to these bits. Their read value is all “0” 7-4 RADC Read Address Setup Cycle

These bits set number of read address setup cycle which asserts NFCEX and its address but not NFREX. When 0 is selected, NFREX and NFCEX are asserted simultaneously. The specifying value should be within number of the read access setup cycle.


1111 15 cycles

3-0 RACC Read Access Cycle These bits set necessary cycles for read access. The address is not changed during the cycles specified in these bits, and data is fetched in the final cycle. Specify 15 to use a low-speed device with Ready function.

0000 1 cycles : :

1111 16 cycles (initial value)

23.6.4. Flash area register (FAREA) Address FFFC_0000H + 40H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Reserved MASK R/W R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W R/W R/W R/W R/W R/W R/W

Initial value X X X X X X X X X 0 0 0 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Reserved ADDR R/W R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W1 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0




Write “0” to these bits. Their read value is undefined

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No. Name 22-16 MASK Mask (Address Mask)

These bits set mask value of the one set to ADDR. According to the specified MASK, this interface masks ADDR (masked with setting “1”) and the masked ADDR will compare with the internal bus mask address. If they are matched, the interface accesses to the flash. [22:16] masks each address [26:20].

(Example)

ADDR = 00001000 (b) MASK = 0000011 (b)

<When the device is selected>

Internal bus address (external interface address): AD = 0x10900000

Masking ADDR & (!MASK) = 00001000 (b) AD [27:20] & (!MASK) = 00001000 (b) ….. Matched, and this device is selected

<When the device is not selected>

Internal bus address (external interface address): AD = 0x10c00000 Masking ADDR & (!MASK) = 00001000 (b) AD [27:20] & (!MASK) = 00001100 (b) ….. Unmatched, and device is not selected

The masking selects area size; in this example, 0x10800000 - 0x10b00000 (4MB) areselected. The bit specified "1" with masking is lost during mask processing. These bits are invalid even if they are set to ADDR. When LSB in the example is 1 (ADDR= 00001001 (b)), the same address field is selected since it is invalid in masking. The correlation of the size in mask setting and address field is shown below.

0000000 (b) → 1MB 0001111 (b) → 16MB 0000001 (b) → 2MB 0011111 (b) → 32MB

Recommended setting: MASK = 0000000(b)

15-8 Reserved Reserved bits. Write “0” to these bits. Their read value is undefined

7-0 ADDR (Reserved) Address These bits specify setting address in the corresponding chip select area. Define corresponding value to [27:20] part of the address. Fix base address (ADDR = 0x04) is allocated for flash interface. Therefore, flash base address is 0x0400_0000 after system boot up. Do not try to change the value in ADDR field.

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23.6.5. ECC control register (ECCR) Address FFFC_0000H + 60H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name – – – – – – – – DCERR1

DUCER1

DECER1 – DCE

RR0 DUCER0

DECER0 –

R/W R0 R0 R0 R0 R0 R0 R0 R0 R/W0 R/W0 R/W0 R0 R/W0 R/W0 R/W0 R0 Initial value X X X X X X X X 0 0 0 X 0 0 0 X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name – – – – – – – – ECC1INTE

ECC0INTE – ECC

CHK

ECCMOD

E X16 DEC

CENECCINT

R/W R0 R0 R0 R0 R0 R0 R0 R0 R/W R/W R0 R/W R/W R/W R/W R/WInitial value X X X X X X X X 0 0 X 0 0 0 0 0

Bit field


31-24 – Unused bits. All bits are read as “0”. Write to these bits has no effect.

23 DCERR1 ECC1 Correctable Error This bit is used to indicate the 1 bit error status of ECC1 macro, it fixed at "0" when ECCMODE (ECCR:bit3) bit is "0". Update this bit by writing ECCCHK (ECCR:bit4), it will be cleared by writing "0". Writing "1" has no effect

0 No 1 bit error (initial value) 1 1 bit error exists

22 DUCERR1 ECC1 Un-Correctable Error This bit is used to indicate the 2 bit error status of ECC1 macro, it is fixed at “0” when ECCMODE bit is “0”. Update this bit by writing ECCCHK (ECCR:bit 4). it is cleared by writing “0”. Writing “1” has no effect.

0 No 2 bits error (initial value) 1 2 bits error exists

21 DECERR1 ECC1 ECC Code Error This bit is used to indicate the ECC code error status of ECC1 macro, it is fixed at “0” when ECCMODE bit is “0”. Update this bit by writing ECCCHK (ECCR:bit 4). This bit is cleared by writing “0”. Writing “1” has no effect.

0 No ECC code error (initial value) 1 ECC code error exists

20 – Unused bits. All bits are read as “0”. Write to these bits has no effect.

19 DCERR0 ECC0 Correctable Error This bit is used to indicate the 1 bit error status of ECC0 macro, it fixed at "0" when ECCMODE (ECCR:bit3) bit is "0". Update this bit by writing ECCCHK (ECCR:bit4), it will be cleared by writing "0". Writing "1" has no effect

0 No 1 bit error (initial value) 1 1 bit error exists

18 DUCERR0 ECC0 Un-Correctable Error This bit is used to indicate the 2 bit error status of ECC0 macro, it is fixed at “0” when ECCMODE bit is “0”. Update this bit by writing ECCCHK (ECCR:bit 4). it is cleared by writing “0”. Writing “1” has no effect.

0 No 2 bits error (initial value) 1 2 bits error exists



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No. Name 17 DECERR0 ECC0 ECC Code Error

This bit is used to indicate the ECC code error status of ECC0 macro, it is fixed at “0” when ECCMODE bit is “0”. Update this bit by writing ECCCHK (ECCR:bit 4). This bit is cleared by writing “0”. Writing “1” has no effect.

0 No ECC code error (initial value) 1 ECC code error exists


7 ECC1INTE ECC1 Interrupt Enable When 1 bit error (DCERR1) or 2 bit error (DUCERR1) or ECC code error (DECERR1) of ECC1 macro is occurred and interrupt is enabled, interrupt request is generated. To clear the interrupt, clear the corresponding interrupt flag bit.

0 Disable (initial value) 1 Enable

6 ECC0INTE ECC0 Interrupt Enable When 1 bit error (DCERR1) or 2 bit error (DUCERR1) or ECC code error (DECERR1) of ECC0 macro is occurred and interrupt is enabled, interrupt request is generated. To clear the interrupt, clear the corresponding interrupt flag bit.

0 Disable (initial value) 1 Enable

5 – Unused bits. All bits are read as “0”. Write to these bits has no effect.

4 ECCCHK Trigger ECC Code Checking After the page reading to flash, if writing the ECC data (for comparison) to ECWR0/1 register, write “1” to this bit. This bit will be automatically clear after set. Writing “1” to this bit confirms the error status of ECC macro (DCERR0/1 bit, DUCERR0/1 bit and DECERR0/1 bit), 1 bit error correction address (ECAR0/1 register) and 1 bit error correction bit (ECBR0/1 register). Read value is always “0”

0 No effect (initial value) 1 Trigger ECC code checking

3 ECCMODE ECC Mode Select This bit is used to select how many ECC unit(s) is being used to generate ECC code. When this bit set to "0", only one ECC macro (ECC0) is used, and one 24 bit or 26 bit ECC is generated at every 512 byte (word) access. When this bit set to "1", two ECC macros (ECC0 for 1st half page, ECC1 for 2nd half page) are used, and one 22-bit ECC is generated at every 256 byte access. Since two ECC codes (ECCR0, ECCR1) can be stored, 512 bytes continuous access is possible. In addition, the function of DCERR1 bit, DUCERR1 bit, DECERR1 bit, ECWR1 register, ECAR1 register and ECBR1 register are effective.

0 One ECC macro (ECC0) is used (initial value) 1 Two ECC macros (ECC0 for 1st half page, ECC1 for 2nd half page) are used

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No. Name 2 X16 16 bit Device Select

For this product, 512 byte/page is supported for both x8 and x16 device, therefore 512 entries per page for x8 device; 256 entries per page for x16 device. If page size is more than 512 bytes, ECC code(s) is generated for every 512 bytes of data.

0 x8 bit flash is connected. (initial value) 1 x16 bit flash is connected.

1 DECCEN ECC0/1 Enable This bit is used to enable ECC code generation in ECC macro(s). Both ECC units (ECC0/ECC1) share this enable signal. Setting ECCINT bit (ECCR:bit0) to “1” before enable ECC unit(s) to initial internal ECC code. Make sure to clear ECCINT bit after enable ECC unit(s)

0 Freeze generated ECC code in ECC0/1 macro (initial value) 1 Enable ECC0/1 ECC code generation

0 ECCINT ECC0/1 Unit Initialization

0 Reset ECC0/1 is released (initial value) 1 Reset ECC0/1 unit

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23.6.6. ECC0 Code Read Register (ECRR0) Address FFFC_0000H + 64H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name – – – – – – ECRR0[25:16] R/W R1 R1 R1 R1 R1 R1 R R R R R R R R R R

Initial value X X X X X X 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name ECRR0[15:0] R/W R R R R R R R R R R R R R R R R

Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1



All bits are read as “1”. Write to these bits has no effect. 25-0 ECRR0[25:0] ECC0 ECC Code

This register contains the ECC code generated from corresponding data in ECC0 macro. Make sure to write "1" to ECCINIT (ECCR:bit0) to reset ECC units before enable and generates ECC code in the ECC units.

ECCMODE X16 ECC Code [31:16]

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0/1 0 1 1 1 1 1 1 1 1 CP[5:0] LP[17:16]0/1 1 1 1 1 1 1 1 CP[7:0] LP[17:16]


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0/1 0/1 LP[15:0]

Table 23-3 ECC code format in ECRR0 (CP: Column Parity, LP: Line Parity)



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23.6.7. ECC1 Code Read Register (ECRR1) Address FFFC_0000H + 68H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name – – – – – – ECRR1[25:16] R/W R1 R1 R1 R1 R1 R1 R R R R R R R R R R


Name ECRR1[15:0] R/W R R R R R R R R R R R R R R R R

Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1



All bits are read as “1”. Write to these bits has no effect. 25-0 ECRR1[25:0] ECC1 ECC Code

This register contains the generated ECC code from corresponding data in ECC1 macro. Make sure to write "1" to ECCINIT (ECCR:bit0) to reset ECC units before enable and generates ECC code in the ECC units. ECRR1 register will be fixed at "0xFFFF_FFFF" when ECCMODE bit (ECCR:bit3) is "0".


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 1 1 1 1 1 1 1 1 CP[5:0] LP[17:16]1 1 1 1 1 1 1 1 CP[7:0] LP[17:16]0 0/1 All “1”


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0/1 LP[15:0] 0 0/1 All “1”

Table 23-4 ECC code format in ECRR1 (CP: Column Parity, LP: Line Parity)



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23.6.8. ECC0 Code Write Register (ECWR0) Address FFFC_0000H + 6CH

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name – – – – – – ECWR0[25:16] R/W R1 R1 R1 R1 R1 R1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name ECWR0[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1



All bits are read as “1”. Write to these bits has no effect. 25-0 ECWR0[25:0] ECC0 ECC Code Write Location

This register is used to compare the ECC code read from NAND flash spare area with the generated ECC code inside ECC0 unit. After read the data from NAND flash, start the comparison by writing ECC code in flash spare area to this register. Then write ECCCHK bit (ECCR:bit4) to "1" to update the result in related registers. When X16 bit is “0”, writing to ECWR0[25:24] has no effect, and reading is fixed at “11”. Format of ECC code can refer to section Table 23-3.

23.6.9. ECC1 Code Write Register (ECWR1) Address FFFC_0000H + 70H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name – – – – – – ECWR1[25:16] R/W R1 R1 R1 R1 R1 R1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name ECWR1[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1



All bits are read as “1”. Write to these bits has no effect. 25-0 ECWR1[25:0] ECC1 ECC Code Write Location

This register is used to compare the ECC code read from NAND flash spare area with the generated ECC code inside ECC1 unit. After read the data from NAND flash, start the comparison by writing ECC code in flash spare area to this register. Then write ECCCHK bit (ECCR:bit4) to "1" to update the result in related registers. When X16 bit is “0”, writing to ECWR1[25:24] has no effect, and reading is fixed at “11”. ECC code format can refer to Table 23-4. When ECCMODE bit is "0", writing ECWR1[25:0] has no effect, and reading is fixed at all "1".

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23.6.10. ECC0 Error Position Register (ECCPOS0) Address FFFC_0000H + 74H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name – – – – – – – ECAR0[8:0] R/W R0 R0 R0 R0 R0 R0 R0 R R R R R R R R R

Initial value X X X X X X X 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name ECBR0[15:0] R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field



24-16 ECAR0[8:0] ECC0 1 bit Error Correction Address Writing “1” to ECCCHK bit (ECCR:bit 4) to renew the correction address. X16 (ECCR:bit2) = '0' : When ECCMODE bit (ECCR:bit3) is “1”, the correction address range is “0_0000_0000~0_1111_1111” (0~255). When ECCMODE bit (ECCR:bit3) is “0”, the correction address range is “0_0000_0000~1_1111_1111” (0~511). X16 (ECCR:bit2) = '1' : When ECCMODE bit (ECCR:bit3) is “1”, the correction address range is “0_0000_0000~0_0111_1111” (0~127). When ECCMODE bit (ECCR:bit3) is “0”, the correction address range is “0_0000_0000~0_1111_1111” (0~255).

15-0 ECBR0[15:0] ECC0 1 bit Error Correction Bit Position 1 bit error can be corrected by EXOR error data to this register value. When X16 bit (ECCR:bit2) is “0”, the data of ECBR0[15:8] is same as ECBR0[7:0]. This bit confirms the writing of “1” to ECCCHK bit (ECCR:bit4). ECBR0[7:0] : 00000001 : error bit position at bit 0 00000010 : error bit position at bit 1 … 10000000 : error bit position at bit 7 ECBR0[15:8] (X16 = 1): 00000001 : error bit position at bit 8 00000010 : error bit position at bit 9 … 10000000 : error bit position at bit 15



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23.6.11. ECC1 Error Position Register (ECCPOS1) Address FFFC_0000H + 78H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name – – – – – – – ECAR1[8:0] R/W R0 R0 R0 R0 R0 R0 R0 R R R R R R R R R

Initial value X X X X X X X 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name ECBR1[15:0] R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field



24-16 ECAR1[8:0] ECC1 1 bit Error Correction Address Writing “1” to ECCCHK bit (ECCR:bit 4) to renew the correction address. When X16 bit (ECCR:bit2) is “0” and ECCMODE bit (ECCR:bit3) is “1”, the correction address range is “1_0000_0000~1_1111_1111” (256~511). When X16 bit (ECCR:bit2) is “1” and ECCMODE bit (ECCR:bit3) is “1”, the correction address range is “0_1000_0000~0_1111_1111” (128~255). When ECCMODE bit (ECCR:bit3) is “0”, these bits are fixed at “0_0000_0000”.

15-0 ECBR1[15:0] ECC1 1 bit Error Correction Bit Position 1 bit error can be corrected by EXOR error data to this register value. When X16 bit (ECCR:bit2) is “0”, the data of ECBR1[15:8] is same as ECBR1[7:0]. When ECCMODE bit (ECCR:bit3) is “0”, these bits are fixed at “0000_0000”. These bits are updated by writing of “1” to ECCCHK bit (ECCR:bit4). ECBR1[7:0] : 00000001 : error bit position at bit 0 00000010 : error bit position at bit 1 … 10000000 : error bit position at bit 7 ECBR1[15:8] (X16 = 1): 00000001 : error bit position at bit 8 00000010 : error bit position at bit 9 … 10000000 : error bit position at bit 15



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23.7. Connection example

8 bit NAND Flash 8 bit NAND Flash

Figure 23-1 Connection example of 8 bit NAND Flash Figure 23-1 Connection example of 8 bit NAND Flash

16 bit NAND Flash 16 bit NAND Flash

Figure 23-2 Connection example of 16 bit NAND Flash Figure 23-2 Connection example of 16 bit NAND Flash

NFCEX NFCLE NFALE NFREX

NFWEX NFD[8:0]

NFRDY

CSX CLE ALE REX WEX DQ[7:0] RDY

MB9G711 x8 NAND

NFCEX NFCLE NFALE NFREX

NFWEX NFD[15:0]

NFRDY

CSX CLE ALE REX WEX DQ[15:0] RDY

MB9G711 x16 NAND

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23.8. Example of access waveform 8-bit NAND Read or Write Command Issue

NFWEX

Internal clock

NFCEX

NFCLE

NFALE

XFlash Addr

NFD[7:0]

NFREX

tWACC

Base + 0x2000Base + 0x1000 Base + 0x2000

tWADC = Write address setup cycletWACC = Write access cycletWWEC = Write enable cycle

tWADC tWWEC

tWACCtWADC tWWEC

tWACC

Column Row0 Row1

Base + 0x2000

tWADC tWWEC

tWACCtWADC tWWEC

tWACCtWADC tWWEC

tWACC

NFRDY

Read / Write Command Issue Address WriteNAND mode ON

X

Row2

Base + 0x2000

RD or WR Command

Figure 23-3 8-bit NAND Read or Write Command Issue

8-bit NAND Status Read

NFWEX

Internal clock

NFCEX

NFCLE

NFALE

Flash Addr

NFD[7:0]

NFREX

tWACC

Base + 0x1000


tWADC tWWEC

tWACC

Busy

NFRDY

Status Read Command Issue Status Read

X

Status Read Command

tRADC tRIDLCtRACC

tRADC tRIDLCtRACC

Busy Ready

tRADC tRIDLCtRACC

Base + 0x0000

Status Read Status Read

tRADC = Read address setup cycletRACC = Read access cycletRIDLC = Read idle cycle

X

Figure 23-4 8-bit NAND Status Read



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8-bit NAND Data Write

NFWEX

Internal clock

NFCEX

NFCLE

NFALE

Base + 0x3000Flash Addr

NFD[7:0]

NFREX


tWADC tWWEC

tWACCtWADC tWWEC

tWACC

Data0Row1

tWADC tWWEC

tWACC

tWADC tWWEC

tWACCtWADC tWWEC

tWACC

NFRDY

Read / Write Command Issue Data Write

Row2

Base + 0x2000 Base + 0x0000

Data1 Data2 Data3

Data Write Data Write Data WriteAddress Input ends

Figure 23-5 8-bit NAND Data Write



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23.9. Operation This section describes basic operation for NAND Flash read/write access..

23.9.1. NAND Flash Access Basic data accesses are performed in (512+16) bytes of internal registers in NAND Flash. In read, several μｓ to tens of μｓ are needed for loading data to internal registers: in data write to memory cells, hundreds of us are required, in block deletion, several ｍｓ. The chip select signal must be kept “L” in data load to the internal registers. Therefore, the read / write signals to the NAND cannot be controlled. The MEMory Controller, which has a discrete enable signal for NAND, executes accesses with the chip select signal connected to the NAND Flash being held at “L”. (It can be reset to “H”). For user side, accesses made to the NAND Flash are I/O accesses (External NAND flash base address = 0x0400_0000): Write access to (External NAND flash base address + 0x2000) is converted to address issue (NFALE is asserted*) to the NAND Flash. Write access to (External NAND flash base address + 0x1000) is converted to command issue (NFCLE is asserted*) to the NAND Flash. Read/Write access to (External NAND flash base address + 0x0000) is converted to data access (NFALE and NFCLE are not asserted*) to the NAND Flash. NFCLE is output in the same timing as the address output of the access. NFALE is kept being asserted after the address issue until the write accessing to (External NAND flash base address + 0x3000) or any other write accessing (data or command) than address issue. This is because the NAND Flash is incapable of diasserting the ALE in multiple write accesses made for the address issue. In the access to +0x3000, only diassertion of NFALE and no access is made. The following charts show steps of the NAND Flash accesses. (For details of the Flash commands, refer to NAND Flash specifications.) *Note: Settings appropriate registers in CCNT module to enable NAND Flash I/O signals.

External NAND flash base address is defined in Flash Area Register (FAREA) and it is fixed at 0x0400_0000

NAND Flash Interface Address Read/Write Operation External NAND flash base address + 0x2000

Write Issue NAND flash address to NFD[7:0] NFALE is asserted

External NAND flash base address + 0x1000

Write Issue NAND flash command to NFD[7:0] NFCLE is asserted


Read/Write Read operation: Read data from NFD[7:0] (X16=0) or NFD[15:0] (X16 =1) Write operation: Write data to NFD[7:0] (X16=0) or NFD[15:0] (X16=1)


Write Deassert NFALE signal

Table 23-5 NAND Flash Interface address function



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Read Access

Stop ECC generation macro

ReadNandFlash Reduncy

from(Base +0000)

Is read redundant

finish ?

ECC Status Check

End

Write “Status Command : 0x70”

to(Base +0x1000)

Read“Flash Status”

from(Base +0x0000)

Is Status OK ? Is NFRDY= 1 ?

ReadNFRDY flag or wait

NFRDY interrupt

Initial ECC generation macro

Write “0x00” to

(Base +0x3000) to lower ALE

Is 512 bytes read ?

Read“sector data”

from(Base +0x0000)

NAND mode ON

Write “Read Command : 0x00”

to(Base +0x1000)

Write “Address”

to(Base +0x2000)

Write ECCR: X16=1(0), DECCEN=0, ECCINT=1Write ECCR: X16=1(0), DECCEN=1, ECCINT=0

Write ECCR:ECCMODE = 0 when 1 ECC unit is used for each pageWrite ECCR:ECCMODE = 1 when 2 ECC units are used for each page

Write ECCR: X16=1(0), DECCEN=0, ECCINT=0


Write ECCR: ECCCHK=1, X16=1(0), DECCEN=0, ECCINT=0

ECCMODE=0: Error flags in ECC0 (Byte 1-512 when X16=0; Half Word 1-256 when X16=1) are updated in ECCR[19:17]. ECCMODE=1: Error flags for ECC0 in 1st half page (Byte 1-256 when X16=0; Half-word 1-128 when X16=1) are updated in ECCR[19:17]. For 2nd half page (Byte 257-256 when X16=0; Half-word 129-256 when X16=1) are updated in ECCR[23:21]

When interrupt is enable, error(s) can be checked by using interrupt.

Y NYN

Y

N

Figure 23-6 Page read for NAND Flash



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Write Access

Read Generated ECC code from ECC macro

Write ECC code to spare area

To(Base + 0x0000)

Is ECC code program finish?

End

Initial ECC generation macro

Is 512bytes write?

Write“sector data”

to(Base +0x0000)

NAND mode ON

Write “Write Command : 0x80”

to(Base +0x1000)

Write “Sector Address”

to(Base +0x2000)

Write“0x00” to

(Base +0x3000) to lower ALE

Write ECCR: X16=1(0), DECCEN=0, ECCINT=1Write ECCR: X16=1(0), DECCEN=1, ECCINT=0


Y

N

Stop ECC generation macro

Write ECCR: X16=1(0), DECCEN=0, ECCINT=0


Write “Status Command : 0x70”

to(Base +0x1000)

Read“Flash Status”

from(Base +0x0000)

Is Status OK ? Is NFRDY= 1 ?

ReadNFRDY flag or wait

NFRDY interrupt

Y NYN

Write “Page Program

Command : 0x10” To (Base +0x2000)

N

Y

ECCMODE = 0: ECC code (Byte 1-512 when X16=0; Half-word 1-256 when X16=1) can be read in ECRR0 registerECCMODE = 1: ECC code for first half page (Byte 1-256 when X16=0; Half-word 1-128 when X16=1) can be read in ECCR0 registerECC code for second half page (Byte 257-512 when X16=0; Half-word 129-256 when X16=1) can be read in ECCR1 register

Figure 23-7 NAND Page Programming



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23-21




Notes in NAND Read/Write access: 1. Base Address for NAND Flash is set using Flash Area Register (FAREA) 2. Shaded boxes can be omitted when ECC is not used 3. When 2 ECC units are used, ECCMODE in ECCR register should set to “1” 4. ECC unit supports page size in 512 bytes, 512 x 8bit or 256 x 16bit, separate ECC code is required for

page size more than 512 bytes. 5. For x8 device, when address is write in WORD access, four address cycles (both NFALE and NFWEX

active) will perform. The address output to NFD[7:0] is in little endian format. For example, writing 0x1234ABCD to (External base address + 0x2000), the 1st address cycle output is 0xCD, the 2nd address cycle output is 0xAB, the 3rd address cycle output is 0x34 and the last (4th) address cycle output is 0x12. It is recommended to use BYTE access for each of the address cycle.

6. For x16 device, when address is write in WORD access to NAND Flash address (External base address + 0x2000), two address cycles (both NFALE and NFWEX active) will perform. The address output to NFD[15:0] is in little endian format. For example, writing 0x1234ABCD to (External base address + 0x2000), the first address cycle output for NFD[15:0] is 0xABCD, the next address cycle output is 0x1234. NAND Flash may be required to pull “Low” in NFD[15:8] for address input. Details can refer to NAND Flash specifications. It is recommended to use BYTE access for each of the address cycle.

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24. Real Time Clock Timer (RTC) This chapter describes the function and the operation of the Real Time Clock.

24.1. Outline This LSI is equipped with an independent powered RTC to keep track of time with information of second, minute, hour, day, week, month and year.

24.2. Feature • Powered by independent power pin (RVDD) which is isolated from the remaining of LSI circuit.

Power cut off to the main supply except RVDD is possible • Containing leap-year circuit for automatic leap-year adjustment • Alarm interrupt generation for pre-set time • 18-bit internal prescaler circuit for 1 sec. timing by which wide range of RTC crystal can be used • 16-bit internal register for checking RVDD power down or not

24.3. Related pin RTC uses following pins.

Table 24-1 RTC related pin Pin Direction Qty. Description

RXI BI 1 32.768KHz crystal terminal RXO OUT 1 32.768KHz crystal terminal RVDD Power 1 1.2V power supply for RTC operation RVSS Power 1 Digital ground for RVDD

24.4. Supply clock APB clock is supplied to RTC for bus I/F. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.


Real Time Clock Timer (RTC)

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24.5. Register This section describes RTC register.


Table 24-2 RTC register list Address


FFF5_4800H + 00H Power off status register RTCROSR 16-bit register to determine whether RTC has been powered off or not

+ 04H Second interval register RTCPRSR Pre-scalar value setting for one second which generated from 32.768KHz input clock.

+ 08H Time Register RTCTIME Storing time information + 0CH Date Register RTCDATE Storing date information + 10H Bus isolation register RTCRPON Set bit to isolate RTC from APB bus

before system power down + 14H Load Register RTCLOAD Update RTC timer + 18H Compare Register RTCCOMP Alarm clock set register + 1CH Interrupt control register RTCINTR Control interrupt output + 1CH ~

+ FFH (Reserved) – Reserved area, access prohibited



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Name R/W


Name R/W

Initial value










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24.5.2. Power off status register (RTCROSR) This register indicates whether RTC was power off or not.

Address FFF5_4800 + 00H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name ROSR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W




Write access is ignored, and read value of these bits is undefined. 15-0 ROSR[15:0] When ROSR value does not same as previous written value, RTCTIME/RTCDATE register

value are no longer valid. Note : Read this register whenever system startup to determine whether RTC time is valid or not

Note: • This register cannot be written after register bit RTCRPON.RPON is clear to “0”

24.5.3. Second interval register (RTCPRSR) This register is to set the pre-scaler value by which 1 second is generated

Address FFF5_4800 + 04H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name – – – – – – – – – – – – – – PRSR[17:16]R/W R R R R R R R R R R R R R R R/W R/W


Name PRSR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W




Write access is ignored, and read value of these bits is undefined. 17-0 PRSR[17:0] Pre-scaler value to generate the 1 sec time interval

1 second = (PRSR + 1) x RTC clock period Note: PRSR=0 is prohibited

Note: • RTC clock pre-scaler value is updated from this register value by writing “1” to register “RTCLOAD” • This register cannot be written after register bit RTCRPON.RPON is clear to “0”



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24.5.4. Time register (RTCTIME) This register holds the time information.

Address FFF5_4800 + 08H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name – – – – – – – – – – – HRS[4:0] R/W R R R R R R R R R R R R/W R/W R/W R/W R/W


Name – – MIN[5:0] – – SEC[5:0] R/W R R R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W




Write access is ignored, and read value of these bits is undefined. 20-16 HRS[4:0] The initial time of hour is defined by writing this field.

The current RTC time of hour is return by reading this field Hour = HRS + 1


13-8 MIN[5:0] The initial time of minute is defined by writing this field The current RTC time of minute is return by reading this field Minute = MIN + 1


5-0 SEC[5:0] The initial time of second is defined by writing this field The current RTC time of second is return by reading this field Second = SEC + 1

Note: • RTC time counter value is updated from this register value by writing “1” to register “RTCLOAD” • This register cannot be written after register bit RTCRPON.RPON is clear to “0”



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24.5.5. Date register (RTCDATE) This register holds the date information.


Name – – – – – – – – – YRS[6:0] R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W


Name – – – – MON[3:0] – – – DAY[4:0] R/W R R R R R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W




Write access is ignored, and read value of these bits is undefined. 24-16 YRS[6:0] The initial date of year is defined by writing this field

The current RTC date of year is return by reading this field Year = YRS + 1


11-8 MON[3:0] The initial date of month is defined by writing this field The current RTC date of month is return by reading this field Month = MON + 1


4-0 DAY[4:0] The initial date of day is defined by writing this field The current RTC date of day is return by reading this field Day = DAY + 1

Note: • RTC date counter value is updated from this register by writing “1” to register “RTCLOAD” • This register cannot be written after register bit RTCRPON.RPON is clear to “0”



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24.5.6. Bus isolation control register (RTCRPON) This register controls RTC bus isolation.

Address FFF5_4800 + 10H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – – – – – – – – – – – – – – – RPON R/W R R R R R R R R R R R R R R R R/W0




Write access is ignored, and read value of these bits is undefined. 0 RPON Bus isolation enable

0 Following register cannot be written

RTCROSR, RTCPRSR, RTCTIME, RTCDATE, RTCRPON

1 All RTC register can be written Note :

• This bit is initialized by external reset only • Write “0” before cut off the system power (except RTC power)

Note: • This register cannot be written after register bit RTCRPON.RPON is set to “0”

24.5.7. Load control register (RTCLOAD) This register controls the update of RTC timer.

Address FFF5_4800 + 14H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – – – – – – – – – – – – – – – LOAD R/W R R R R R R R R R R R R R R R W1




Write access is ignored, and read value of these bits is undefined. 0 LOAD RTC day/time update control bit

Writing “1” to update the day/time register as well as pre-scaler value to the RTC counter



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24.5.8. Time compare register (RTCCOMP) This register defines the time to be compared for interrupt generation.

Address FFF5_4800 + 18H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – – – CHRS[4:0] – – CMIN[5:0] R/W R R R R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W




Write access is ignored, and read value of these bits is undefined. 12-8 CHRS[4:0] Define the value to be compared to the current RTC hour 7-6 – Unused bits.

Write access is ignored, and read value of these bits is undefined. 5-0 CMIN[5:0] Define the value to be compared to the current RTC minute

24.5.9. Interrupt control/status register (RTCINTR) This register defines the time to be compared for interrupt generation.




Name – – – – – INTS HC MC – – – – – – HMF MMFR/W R R R R R R/W R/W R/W R R R R R R R/W0 R/W0

Initial value X X X X X X X X X X X X X X 0 0



Write access is ignored, and read value of these bits is undefined. 10 INTS Interrupt generation mode

0 Interrupt is generated when either HMF or MMF is set (Initial value) 1 Interrupt is generated when both HMF and MMF are set

Note :

• This bit is valid only when both HC and MC are set to 1 • When only one bit (HC or MC) is set to 1, an interrupt is generated by set of

HMF at HC=1 or by set of MMF at MC=1



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No. Name 9 HC Hour compare function enable bit

0 Hour compare function disabled (Initial value) 1 Hour compare function enabled

Value of RTCCOMP.CHRS[5:0] is compared with RTC current hour. When match HMF is set

8 MC Minute compare function enable bit

0 Minute compare function disabled (Initial value) 1 Minute compare function enabled

Value of RTCCOMP.CMIN[5:0] is compared with RTC current minute. When match MMF is set


1 HMF Hour compare match flag

0 Either hour compare function not enable or current RTC hour not match RTCCOMP.CHRS

1 Current RTC hour match RTCCOMP.CHRS Once the flag HMF is set to “1”, it will not clear even RTC hour not match the compare value. Write “0” to clear this flag

Note : Write “0” to clear this bit

1 MMF Minute compare match flag

0 Either hour compare function not enable or current RTC minute not match RTCCOMP.CMIN

1 Current RTC minute match RTCCOMP.CMIN Once the flag HMF is set to “1”, it will not clear even RTC minute not match the compare value. Write “0” to clear this flag

Note : Write “0” to clear this bit

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24-10




24.6. Note on application 1. Register bit RTCRPON.RPON must be clear to “0” before cut off system power (except RVDD) 2. Do not clear register bit RTCRPON.RPON in normal operation. Otherwise, RTC time register cannot

be updated 3. Confirm the register RTCROSR value is the same as pre-defined value before reading time. 4. Ensure RTC oscillator clock function properly at RVDD voltage by confirming the RTCROSR

register holds the previous value.

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25. Input Capture Timer (INCP) This chapter describes function and operation of the Input Capture Timer.

25.1. Outline Input capture timer (INCP) consists of a 16-bit free running up-down counter and edge detection circuit. The 16-bit timer value is captured when defined edge is detected at the input channels. This LSI has two input pins for capturing timer trigger.

25.2. Feature • A prescaler is equipped to provide nine different clocks for the timer count clock using APB clock • PWM channel 3 output can be used as timer count clock • 3 kinds of interrupt can be generated

25.3. Related pin INCP uses following pins.

Table 25-1 INCP related pin Pin Direction Qty. Description

IN0 I 1 Input capture channel 0 IN1 I 1 Input capture channel 1

25.4. Supply clock APB clock is supplied bus I/F and internal prescaler. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock. Furthermore, output of PWM_O3 can be selected as prescaler clock. Refer to “PWM” for details of waveform setting.


Input Capture Timer (INCP)

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25.5. Register This section describes INCP register.


Table 25-2 INCP register list Address


FFF4_7000H + 000H Input capture data register 0 IPCP0 Store 16-bit free-run counter value when edge detected at IN0

+ 004H Input capture data register 1 IPCP1 Store 16-bit free-run counter value when edge detected at IN1

+ 008H Input capture control status register IPCS Control the input capture operation + 00CH (Reserved) – Reserved area, access prohibited + 010H Compare clear register IPCPCLR Define Timer compare value at which

timer clear to “0” and interrupt generated + 014H Timer data register IPTDAT Current 16-bit free-run timer value + 018H Timer control register IPTCSR Control the 16-bit free-run timer operation + 01CH

~ + 7FFH




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Name R/W


Name R/W

Initial value










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25.5.2. Input Capture data register (IPCPx) This register holds the timer value when selected edge is detected at corresponding pins

Address IPCP0 : FFF4_7000 + 000H IPCP1 : FFF4_7000 + 004H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name CP[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W




Write access is ignored, and read value of these bits is undefined. 15-0 CP[15:0] Holds the 16-bit free-run timer value when specified edge is detected at corresponding pin



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25.5.3. Input capture control status register (IPCS) This register specify the edge to be detected on input capture pin and interrupt output

Address FFF4_7000 + 08H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name – – – – – – EDI1 EDI0 ICS1 ICS0 IE1 IE0 EDS1[1:0] EDS0[1:0] R/W R R R R R R R R R/W0 R/W0 R/W R/W R/W R/W R/W R/W

Initial value X X X X X X X X X X 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 9 EDI1 Detected edge indication bit for channel 1

0 Falling edge is detected 1 Rising edge is detected

Note : This bit is valid only when EDS1[1:0] not equal to “00”

8 EDI0 Detected edge indication bit for channel 0

0 Falling edge is detected 1 Rising edge is detected

Note : This bit is valid only when EDS0[1:0] not equal to “00”

7 ICS1 Valid edge detected flag To indicate the edge specified at EDS1[1:0] is detected at input capture channel 1

0 No specified edge detected 1 Specified edge is detected

Write “0” to clear this bit

6 ICS0 Valid edge detected flag To indicate the edge specified at EDS0[1:0] is detected at input capture channel 0

0 No specified edge detected 1 Specified edge is detected

Write “0” to clear this bit

5 IE1 Interrupt enable for input capture channel 1 To enable a interrupt output when ICS1 is set

0 No interrupt output when ICS1 is set (Initial value) 1 Interrupt output when ICS1 is set

4 IE0 Interrupt enable for input capture channel 0 To enable a interrupt output when ICS0 is set

0 No interrupt output when ICS0 is set (Initial value) 1 Interrupt output when ICS0 is set



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No. Name 3-2 EDS1[1:0] Input capture channel 1 valid edge selection bit

00 Input capture stopped (Initial value) 01 Specify rising edge is valid 10 Specify falling edge is valid 11 Specify both rising and falling edges are valid

1-0 EDS0[1:0] Input capture channel 0 valid edge selection bit

00 Input capture stopped (Initial value) 01 Specify rising edge is valid 10 Specify falling edge is valid 11 Specify both rising and falling edges are valid

25.5.4. Timer compare register (IPCPCLR) This register holds the timer compare value compared to 16-bit free-run timer.

Address FFF4_7000 + 10H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name CLR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1



Write access is ignored, and read value of these bits is undefined. 15-0 CLR[15:0] Timer compare value

Timer will compare this value with the timer value to see if change to down counting or reset to “zero” depends on the timer operation mode (i.e. setting of IPTCSR.MODE)

IPTCSR.MODE Timer behavior when timer value match this register 0 Timer reset to zero and count up again 1 Timer change to down-counting

Note : When buffer function disabled (IPTCSR.BFE = 0) or free-run timer is stopped: writing this register will change the timer compare value immediately. When buffer function enabled (IPTCSR.BFE = 1) : writing this register will not affect the timer compare value immediately. The new compare value will be effective when timer reach “zero”.

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25.5.5. Timer data register (IPTDAT) This register holds the free-run timer value

Address FFF4_7000 + 14H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name DAT[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 15-0 DAT[15:0] Current timer value

Read this register returns the current timer value Write this register when timer is stopped, the timer initial value is changed to the value of this register. Timer starts with this value. Note : Always write this register when timer is stopped (i.e. IPTCSR.STOP = 1)



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25.5.6. Timer control status register (IPTCSR) This register controls INCP 16-bit free-run timer.

Address FFF4_7000 + 18H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name ECKE ZF INTZE MSI[2:0] MCF INTMCE BFE STOP MODE SCLR CLK3 CLK2 CLK1 CLK0 R/W R/W R/W0 R/W R/W R/W R/W R/W0 R/W R/W R/W R/W R0/W1 R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0



Write access is ignored, and read value of these bits is undefined. 15 ECKE Count clock source selection bit

0 APB clock with dividing ratio setting IPTCSR.CLK[3:0] is selected (initial value) 1 PWM_O3 output is selected

Note : The timer starts counting at 2nd clock edge and both edge will be used as count clock edge

14 ZF Zero detect flag This bit is set when timer value reach zero in up/down mode or specified no of zero has been reached in up/down mode

IPTCSR.MODE Description 0 ZF is set whenever timer value reach “0” 1 ZF is set when specified number of zero is detected

MSI[2:0] is used to define the number of zero detected. Note : Write “0” to clear this bit. This flag is not set when software clear (IPTCSR.SCLR = 1)

13 INTZE Zero flag Interrupt output enable

0 Interrupt not output when ZF bit is set (initial value) 1 Interrupt output when ZF bit is set



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No. Name 12-10 MSI[2:0] Mask selection bits

These bits are used to specify the number of times to mask the compare clear interrupt in up-count mode (MODE=0). In up/down count mode (MODE = 1), they are used to set the number of masking of the 0-detection interrupt. Setting this bit to "0" does not mask the interrupt source. MSI2 bit to MSI0 bit are a 3-bit reload down counter that reload when the count value reaches "000B". The count value can also be loaded by writing directly to the MSI2 to MSI0 bits.Reading from this field returns the current value of the reload down counter. The Zero detect flag (ZF) and Match clear flag (MCF) will be affected by the value of the reload down counter. Note: When the interrupt source has been masked twice, and then the third interrupt is processed, these bits must be set to "010B".

In up-count mode (IPTCSR.MODE = 0)

In up/down count mode (IPTCSR.MODE = 1)

ZF is set when timer match zero

MCF is set when timer match IPCPCLR register

ZF is set when timer match zero

MCF is set when timer match IPCPCLR register

000 Every time Every time Every time Every time 001 2nd,4th, 6th, … time 2nd,4th, 6th, … time 010 3rd, 6th, 9th, … time 3rd, 6th, 9th, … time 011 4th, 8th, 12th, … time 4th, 8th, 12th, … time 100 5th, 10th, 15th, … time 5th, 10th, 15th, … time 101 6th, 12th, 18th, … time 6th, 12th, 18th, … time 110 7th, 14th, 21st, … time 7th, 14th, 21st, … time 111 8th, 16th, 24th, … time 8th, 16th, 24th, … time

9 MCF Match clear flag This bit is set when timer value match register IPCPCLR value

IPTCSR.MODE Description 0 MCF is set when specified number of match between timer

value and register IPCPCLR value has occurred MSI[2:0] specify the number of match to detect

1 MCF is set every time when timer value match the register IPCPCLR value regardless MSI[2:0] setting

Note : Write “0” to clear this bit.

8 INTMCE Match clear Interrupt output enable

0 Interrupt not output when MCF bit is set (initial value) 1 Interrupt output when MCF bit is set

7 BFE Timer compare register buffer

0 Timer compare register buffer disable (initial value) Writing value to Timer compare register IPCPCLR will change compare value immediately

1 Timer compare register buffer enable Writing value to Timer compare register IPCPCLR will change timer compare value when timer reach zero

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25-10





No. Name 6 STOP Timer stop bit

1 Timer stopped (Initial value) 0 Timer starts counting

5 MODE Timer operating mode

0 Timer operates in up-count mode (Initial value) The timer counts up until matching the IPCPCLR register value. Then the timer reset to “zero” and counts up repetitive

1 Timer operates in up/down-count mode The timer counts up until matching the IPCPCLR register value. Then the timer turns to count down from the matched value. When the timer reach “zero”, the timer turns to count up again

Note : When this bit is written during operation, the operating mode will not change to new setting until the timer reach “zero”

4 SCLR Software clear bit Write “1” to reset timer to “zero” at next count clock

3-0 CLK[3:0] Count clock frequency dividing ratio To divide APB clock as a timer count clock

0000 APB clock(Initial value) 0001 APB clock/ 2 0010 APB clock/ 4 0011 APB clock/ 8 0100 APB clock/ 16 0101 APB clock/ 32 0110 APB clock/ 64 0111 APB clock/ 128 1000 APB clock/ 256 Others Setting prohibited

Note : Always change count clock frequency when timer and input capture function is stopped

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26. USB Host controller This chapter describes function and operation of USB Host controller. See the following website for operation as well. Host controller specification with OHCI standard 1.0a version URL: http://h18000.www1.hp.com/productinfo/development/openhci.html Host controller specification with EHCI standard 1.0 version URL: http://www.intel.com/technology/usb/ehcispec.htm This chapter of LSI product specification includes the specification from OHCI standard version 1.0a and EHCI standard reversion 1.0.

26.1. Outline This host controller is in compliance with the USB standard 2.0 editions. It equips PHY for 1 port, host controller complying with EHCI standard 1.0 edition, and host controller complying with OHCI standard 1.0a version which corresponds to three modes, HS/FS/LS.

26.2. Specification limitation USB Host controller has following limitations:

1. OUT transmission (host ⇒ device) for 512 byte or more of packet size is unsupported. Limitation is applied to isochronous and interrupt which are able to transfer 512 byte or more (up to 1024 byte) according to the standard. IN transfer (device ⇒ host) is not limited.

2. Buffer depth setting value is fixed to 512 byte. 3. Buffer threshold setting value is limited to "buffer size - 2 or less".


USB Host controller

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http://h18000.www1.hp.com/productinfo/development/openhci.html

http://www.intel.com/technology/usb/ehcispec.htm


26.3. Feature Host controller's function list is shown below.

Table 26-1 USB host controller function list Item Function

High-speed transfer According to HC with EHCI standard 1.0 edition SPLIT transfer is supported

Full-speed/Low-speed transfer According to HC with OHCI standard 1.0a edition Number of port 1 Debug port N/A Port indicator Not supported Companion controller HC with OHCI standard 1.0a edition × 1 Power control function of port Supported Extended capability pointer Not supported Asynchronous park mode Programmable (Park value is settable) 64 bit addressing Not supported Others, original function • Micro frame length is settable

• PacketBuffer threshold is settable • PacketBuffer size is settable • Nak Reload correction function can be turned on/off • SOF interval is adjustable by register setting


USB Host controller

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26.4. Block diagram

Figure 26-1 Block diagram of USB Host controller


USB Host controller

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26.5. Supply clock AHB clock is supplied to USB Host controller. Refer to "5. Clock reset generator (CRG)" for frequency setting and control specification of the clock.

26.6. Register This section describes USB Host controller register.

26.6.1. Register list USB Host controller's register is classified into following 4 groups:

1. EHCI capability register 2. EHCI operational register 3. OHCI operational register 4. Others

Each group has following registers.

Table 26-2 EHCI capability register list Address Register Description

FFF80000H HCCAPBASE Corresponding to conjunction of HCREVISION register and CAPLENGTH register described in the EHCI specification

FFF80004H HCSPARAMS Corresponding to HCSPARAMS register described in the EHCI specification

FFF80008H HCCPARAMS Corresponding to HCCPARAMS register described in the EHCI specification

Table 26-3 EHCI operational register list Address Register Description

FFF80010H USBCMD Corresponding to USBCMD register described in the EHCI specification

FFF80014H USBSTS Corresponding to USBSTS register described in the EHCI specification

FFF80018H USBINTR Corresponding to USBINTR register described in the EHCI specification

FFF8001CH FRINDEX Corresponding to FRINDEX register described in the EHCI specification

FFF80020H CTRLDSSEGMENT Corresponding to CTRLDSSGMENT register described in the EHCI specification

FFF80024H PERIODICLISTBASE Corresponding to PERIODICLISTBASE register described in the EHCI specification

FFF80028H ASYNCLISTADDR Corresponding to ASYNCLISTADDR register described in the EHCI specification

FFF80050H CONFIGFLAG Corresponding to CONFIGFLAG register described in the EHCI specification


USB Host controller

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USB Host controller

Address Register Description FFF80054H PORTSC_1 Corresponding to PORTSC (1) register described in the EHCI

specification

FFF80090H INSNREG00 Specifying number of bit cell per 1 micro frame

FFF80094H INSNREG01 Specifying threshold of packet buffer

FFF80098H INSNREG02 Specifying packet buffer depth

FFF8009CH INSNREG03 Memory transfer break register

FFF800A0H INSNREG04 Debug register

FFF800A4H INSNREG05 Control/Status register of USB PHY

Table 26-4 OHCI operational register list Address Register Description

FFF81000H HcRevision Corresponding to HcRevision register described in the OHCI specification

FFF81004H HcControl Corresponding to HcControl register described in the OHCI specification

FFF81008H HcCommandStatus Corresponding to HcCommandStatus register described in the OHCI specification

FFF8100CH HcInterruptStatus Corresponding to HcInterruptStatus register described in the OHCI specification

FFF81010H HcInterruptEnable Corresponding to HcInterruptEnable register described in the OHCI specification

FFF81014H HcInterruptDisable Corresponding to HcInterruptDisable register described in the OHCI specification

FFF81018H HcHCCA Corresponding to HcHCCA register described in the OHCI specification

FFF8101CH HcPeriodicCurrentED Corresponding to HcPeriodicCurrentED register described in the OHCI specification

FFF81020H HcControlHeadED Corresponding to HcControlHeadED register described in the OHCI specification

FFF81024H HcControlCurrentED Corresponding to HcControlCurrentED register described in the OHCI specification

FFF81028H HcBulkHeadED Corresponding to HcBulkHeadED register described in the OHCI specification

FFF8102CH HcBulkCurrentED Corresponding to HcBulkCurrentED register described in the OHCI specification

FFF81030H HcDoneHead Corresponding to HcDoneHead register described in the OHCI specification

FFF81034H HcFmInterval Corresponding to HcFmInterval register described in the OHCI specification

FFF81038H HcFmRemaining Corresponding to HcFmRemaining register described in the OHCI specification

FFF8103CH HcFmNumber Corresponding to HcFmNumber register described in the OHCI specification

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USB Host controller

Address Register Description FFF81040H HcPeriodicStart Corresponding to HcPeriodicStart register described in the OHCI

specification

FFF81044H HcLSThreshold Corresponding to HcLSThreshold register described in the OHCI specification

FFF81048H HcRhDescriptorA Corresponding to HcRhDescriptorA register described in the OHCI specification

FFF8104CH HcRhDescriptorB Corresponding to HcRhDescriptorB register described in the OHCI specification

FFF81050H HcRhStatus Corresponding to HcRhStatus register described in the OHCI specification

FFF81054H HcRhPortStatus[1] Corresponding to HcRhPortStatus[1] register described in the OHCI specification

FFF81100H Reserved Access prohibited



FFF8110CH Reserved Access prohibited

Table 26-5 Other registers list Address Register Description

FFF82000H LinkModeSetting Setting link mode FFF82004H PHYModeSetting1 Setting mode for built-in USB PHY FFF82008H PHYModeSetting2 Setting mode for built-in USB PHY

26.6.2. Capability Register (HCCAPBASE) Address FFF8_0000H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name HCIVERSION R/W R R R R R R R R R R R R R R R R


Name (Reserved) CAPLENGTH R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0


No. Name 31-16 HCIVERSION Conformed EHCI standard version is displayed.

0100H is always read. 15-8 (Reserved) Reserved field. 7-0 CAPLENGTH Offset from EHCI register space's base address to EHCI operational register space is indicated.

10H is always read.

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26.6.3. Structural Parameter Register (HCSPARAMS) Address FFF8_0004H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) DebugPortNumber (Reserved) *1 R/W R/W R R R R R R R R R R R R R R R


Name N_CC N_PCC *2 (Reserved) PPC N_PORTS R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 *1: P_INDICATOR *2: PortRoutingRule

Bit field


31-24 (Reserved) Reserved field. 23-20 DebugPort-

Number This LSI does not equip debug port that 0H is always read.

19-17 (Reserved) Reserved field. 16 P_INDICATOR Whether to support port indicator control is indicated.

This LSI does not support it that the value is always 0H. 15-12 N_CC Number of USB 1.1 host controller attached as companion host controller is indicated.

Since this LSI has 1 host controller in accordance with the OHCI specification, 1H is read. 11-8 N_PCC Number of port per companion host controller is indicated.

Read value of this bit is 2H (indicating 2 ports are supported); however, this LSI actually supports only 1 port that software process converting 2H to 1H should be performed.

7 PortRouting- Rule

Associating method of companion host controller and port is indicated. 0H is always read in this LSI.

6-5 (Reserved) Reserved field. 4 PPC Whether to control port's power supply from host controller is indicated.

1H is always read in this LSI. 3-0 N_PORTS Number of mounted port is indicated.

Read value of this bit is 2H (indicating 2 ports are supported); however, this LSI actually supports only 1 port that software process converting 2H to 1H should be performed.


USB Host controller

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26.6.4. Capability Parameter Register (HCCPARAMS) Address FFF8_0008H



Name EECP *1 *2 *3 *4 *5 R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 *1: Isochronous ScheduleParkThreshold *2: (Reserved) *3: AsynchronousScheduleParkCapability *4: ProgrammableFrameListFlag *5: 64bitAddressingCapability

Bit field


31-16 (Reserved) Reserved field. 15-8 EECP Offset to capability list is indicated when extension function to EHCI is mounted.

00H is always read. 7-4 Isochronous-

SchedulePark- Threshold

How much distance should be kept from the current host controller for software to correctisochronous schedule safely is indicated.

3 (Reserved) Reserved field. 2 Asynchronous-

SchedulePark-Capability

Whether host controller supports park feature to high-speed queue head of asynchronous scheduleis indicated. 1H is read in this LSI.

1 Programmable- FrameList-

Flag

Whether frame list length can be set smaller than 1024 is indicated. 1H is read in this LSI.

0 64bit- Addressing- Capability

Whether 64 bit pointer can be used for data structure in the memory is indicated. 0H is read in this LSI.


USB Host controller

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26.6.5. USB Command Register (USBCMD) Address FFF8_0010H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) InterruptThresholdControl R/W R/W R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W


Name (Reserved) *1 *2 *3 *4 *5 *6 *7 *8 *9 RS R/W R R R R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 *1: AsynchronousScheduleParkModeEnable *2: (Reserved) *3: AsynchronousScheduleParkModeCount *4: LightHostControllerReset *5: InterruptOnAsyncAdvanceDoorbell *6: AsynchronousScheduleEnable *7: PeriodicScheduleEnable *8: FrameListSize *9: HCRESET

Bit field


31-24 (Reserved) Reserved field. 23-16 Interrupt-

Threshold- Control

Interrupt threshold time (the min. interval time that host controller generates interrupt) is specified. The operation with other values than the followings is undefined.

00H: (Reserved) 01H: 1 micro frame 02H: 2 micro frame 04H: 4 micro frame 08H: 8 micro frame ( = 1mS ) 10H: 16 micro frame ( = 2mS ) 20H: 32 micro frame ( = 4mS ) 40H: 64 micro frame ( = 8mS )

The operation of rewritten this field is undefined, except when HcHalted field of the USBSTS register is 0H.

15-12 (Reserved) Reserved field. 11 Asynchronous-

SchedulePark- ModeEnable

Park feature to high-speed cue of asynchronous schedule is controlled. 0H: Park feature is disabled 1H: Park feature enabled

10 (Reserved) Reserved field. 9-8 Asynchronous-

SchedulePark- ModeCount

Number of transaction that can be performed consecutively from 1 high-speed queue head in asynchronous schedule is specified. Settable range is 1H to 3H. The operation with 0H setting is undefined.

7 LightHost- Controller-

Reset

Writing 1H to this field enables to reset only EHCI host controller without influencing it to status of companion host controller and port. If reading value is 0H, reset of EHCI host controller is completed. 1H shows the controller is still in reset process.

6 InterruptOn- Async-

Advance- Doorbell

Setting 1H to this field enables EHCI host controller to generate interrupt when the process proceeds to the next asynchronous schedule. The controller sets 1H to InterruptOnAsyncAdvance field of the USBSTS register at completing cached schedule, and sets 0H to this field. In that time, the controller generates interrupt at the nearest threshold time if InterruptOnAsyncAdvanceEnable field of the USBINTR register is 1H. Operation for when 1H is set to this field during asynchronous schedule is disabled is undefined.

5 Asynchronous- Schedule-

Enable

Asynchronous schedule process of EHCI host controller is controlled. 0H: Asynchronous schedule process is skipped 1H: Asynchronous schedule process is proceeded

4 Periodic- Schedule-

Enable

EHCI host controller controls whether to proceed periodic schedule. 0H: Periodic schedule process is skipped 1H: Periodic schedule process is proceeded


USB Host controller

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USB Host controller


No. Name 3-2 FrameList-

Size Frame list size is specified.

0H: 1024 elements (4096 byte) 1H: 512 elements (2048 byte) 2H: 256 elements (1024 byte) 3H: Reserved

1 HCRESET When 1H is set to this field, host controller immediately stops the transaction in process; moreover, pipeline, timer, counter, state machine, and others in the controller are shifted to the initial state. Port register and port state machine are also shifted to the initial state, and ownership of the port is returned to companion host controller. The value of this field returns to 0H after completing the host controller's reset. However, reset process is unable to be stopped though 0H is set by software.

0 RS When value of this field is 1H, host controller processes schedule. Setting 0H to this field shifts to stop state after completing current transaction. In this case, HcHalted field of the USBSTS register becomes 1H. The operation at setting 1H to this field in other states than stop is undefined.

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26.6.6. USB Status Register (USBSTS) Address FFF8_0014H



Name *1 *2 *3 *4 (Reserved) *5 *6 *7 *8 *9 *10 R/W R R R R R R R R R R R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 *1: AsynchronousScheduleStatus *2: PeriodicScheduleStatus *3: Reclamation *4: HCHalted *5: InterruptOnAsyncAdvance *6: HostSystemError *7: FrameListRollover *8: PortChangeDetect *9: USBERRINT *10: USBINT

Bit field


31-16 (Reserved) Reserved field. 15 Asynchronous-

Schedule- Status

Asynchronous schedule is indicated. 0H: Asynchronous schedule is disabled 1H: Asynchronous schedule is enabled

14 Periodic- Schedule-

Status

Periodic schedule is indicated. 0H: Periodic schedule is disabled 1H: Periodic schedule is enabled

13 Reclamation Whether asynchronous schedule is empty is indicated. 0H: Asynchronous schedule is not empty 1H: Asynchronous schedule is empty

12 HcHalted Host controller status is indicated. 0H: Host controller is processing schedule 1H: Host controller is stop

11-6 (Reserved) Reserved field. 5 InterruptOn-

Async- Advance

Interrupt factor set by InterruptOnAsyncAdvanceDoorbell bit of the USBCMD register is occurred.

4 HostSystem- Error

When CPU accesses to host controller register and error response occurs, or Sys_interrupt bit of the CCNT module's USB setting register (CUSB) is set, this bit is set. In that time, the host controller sets 0H to RS field of the USBCMD register in order not to execute schedule.

3 FrameList- Rollover

When FrameListIndex value returns to 0 from the max. value, the value of this field becomes 1H.

2 PortChange- Detect

When following changes are detected in port, the value of this field becomes 1H. • PortOwner bit value is changed from 0H to 1H • ForcePortResume bit value is changed from 0H to 1H as a result of detecting JK transition in the

port in suspend • ConnectStatusChange bit value of the port whose PortOwner bit is 0H is changed from 0H to 1H.

1 USBERRINT When USB transaction ends by error, the value of this field becomes 1H. If IOC bit of TD in the transaction to which the error occurs is 1H, the value of USBINT field also becomes 1H.

0 USBINT When USB transaction corresponding to TD, whose IOC bit value is 1H is completed and TD retires, the value of this field becomes 1H. Moreover, the value of this field also becomes 1H when host controller detects short packet.


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26.6.7. USB Interrupt Enable Register (USBINTR) Address FFF8_0018H



Name (Reserved) *1 *2 *3 *4 *5 *6 R/W R R R R R R R R R R R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: InterruptOnAsyncAdvanceEnable *2: HostSystemErrorEnable *3: FrameListRolloverEnabel *4: PortChangeInterruptEnable *5: USBErrorInterruptEnable *6: USBInterruptEnable

Bit field

Description No. Name 31-6 (Reserved) Reserved field.

5 InterruptOn- AsyncAdvance-

Enable

Interrupt On Async Advance Interrupt Enable When this bit is written to 1H, if InterruptOnAsyncAdvance field of USBSTS register is set, interrupt occurs.

0H: Interrupt disable (initial value) 1H: Interrupt enable

4 HostSystem- ErrorEnable

Host System Error Interrupt Enable When this bit is written to 1H, if HostSystemError field of the USBSTS register is set, interrupt occurs.


3 FrameList- Rollover-

Enable

Frame List Rollover Interrupt Enable When this bit is written to 1H, if FrameListRollover field of the USBSTS register is set, interrupt occurs.


2 PortChange- Interrupt-

Enable

Port Change Detect Interrupt Enable When this bit is written to 1H, if PortChangeDetect field of the USBSTS register is set, interrupt occurs.


1 USBError- Interrupt-

Enable

USB Error Interrupt Enable When this bit is written to 1H, if USBERRINT field of the USBSTS register is set, interrupt occurs.


0 USB- Interrupt-

Enable

USB Interrupt Enable When this bit is written to 1H, if USBINT field of the USBSTS register is set, interrupt occurs.



USB Host controller

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26.6.8. USB Frame Index Register (FRINDEX) Address FFF8_001CH



Name (Reserved) FrameIndex R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-14 (Reserved) Reserved field. 13-0 FrameIndex Increment is processed at the end of each micro frame. During HcHalted field of the USBSTS

register is 0H, this register is not able to be written. Moreover, the operation when RS field of the USBCMD register is written during 1H period of time is undefined. A part of this field is used as index to the Periodic frame list, and it is determined as shown below based on FrameListSize field value of the register.

FrameListSize Index 0H Specified 1pc. out of 1024 elements by using bit 3 from bit 12 1H Specified 1pc. out of 512 elements by using bit 3 from bit 11 2H Specified 1pc. out of 256 elements by using bit 3 from bit 10 3H Reserved

26.6.9. 4G Segment Selector Register (CTRLDSSEGMENT) Address FFF8_0020H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-0 This register is unused since 64 bit addressing is not supported in this LSI.


USB Host controller

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26.6.10. Periodic Frame List Base Address Register (PERIODICLISTBASE)

Address FFF8_0024H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name BaseAddress R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name BaseAddress (con’t) (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-12 BaseAddress This field stores base address of Periodic frame list. Address from bit 31 to 12 is stored. 11-0 (Reserved) Base address of Periodic frame list should be aligned on 4KB boundary; therefore, the value

should always be 000H at writing. This field’s value during operation is undefined.

26.6.11. Asynchronous List Address Register (ASYNCLISTADDR) Address FFF8_0028H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name LinkPointerLow R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name LinkPointerLow （con’t） (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-5 LinkPointerLow This field stores pointer to the queue head of asynchronous schedule to be executed next.

Address from bit 31 to 5 is stored. 4-0 (Reserved) Reserved field.


USB Host controller

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26.6.12. Configured Flag Register (CONFIGFLAG) Address FFF8_0050H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R?W R/W


Name (Reserved) CF R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-1 (Reserved) Reserved field.

Always write 0H to this register. 0 CF Set 1H to this field at the end of setting procedure of host controller.

The value of this field affects operation of port routing logic as follows. 0H: Each port is connected to companion host controller in default 1H: All ports are connected to this controller in default


USB Host controller

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26.6.13. Port Status/Control Register 1 (PORTSC_1) Address FFF8_0054H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) *1 *2 *3 PortTestControl R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W


Name *4 *5 PP LineStatus *6 *7 *8 *9 *10 *11 *12 *13 *14 *15 R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R R/W R/W R/W R

Initial value 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: WKOC_E *2: WKDSCNNT_E *3: WKCNNT_E *4: PortIndicatorControl *5: PortOwner *6: (Reserved) *7: PortReset *8: Suspend *9: ForcePortResume *10: Over-currentChange *11: Over-currentActive *12: PortEnableDisableChange *13: PortEnabelDisable *14: ConnectStatusChange *15: CurrentConnectStatus

Bit field


31-23 (Reserved) Reserved field. 22 WKOC_E Setting 1H to this field generates wake-up event at overcurrent condition.

When PP field value is 0H, the value of this field also becomes 0H. 21 WKDSCNNT_E Setting 1H to this field enables to use device disconnect event as wake-up event.

When PP field value is 0H, the value of this field also becomes 0H. 20 WKCNNT_E Setting 1H to this field enables to use device connect event as wake-up event.

When PP field value is 0H, the value of this field also becomes 0H. 19-16 PortTest-

Control This field specifies whether port mode should be test mode. Port mode is determined as follows according to the value of this field.

0H Port mode is not test mode 1H J_STATE test mode 2H K_STATE test mode 3H SE0_NAK test mode 4H Packet test mode 5H FORCE_ENABLE test mode 6H – FH Reserved

Refer to chapter 7 of the USB specification 2.0 editions for detail of each test mode.

15-14 Port- Indicator- Control

The port indicator is controlled. Since this LSI does not support port indicator, it is not affected to writing to this field. When PP field value is 0H, the value of this field also becomes 0H.

13 PortOwner Companion host controller controls the port by setting the value of this field to 1H. When CF field value of the CONFIGFLAG register changes from 0H to 1H, the value of this field unconditionally becomes 0H. Moreover, this field’s value becomes 1H during CF field value of CONFIGFLAG register is 0H.


USB Host controller

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USB Host controller


No. Name 12 PP In this LSI, PPC field value of the HCSPARAMS register is always 1H; therefore, power supply in

the port can be controlled according to the value of this field as follows.

0H Power supply in the port is off 1H Power supply in the port is on

Port does not function when its power supply is off; moreover, the event such as device connection/disconnection is not notified. When overcurrent condition is detected, host controller sets 0H to this field.

11-10 LineStatus Condition of USB port's signal wire is indicated as follows.

0H Status of the signal wire is SE0 1H Status of the signal wire is J_STATE 2H Status of the signal wire is K_STATE 3H Status of the signal wire is undefined

When power supply of the port is off, this field value is undefined.

9 (Reserved) Reserved field 8 PortReset Writing 1H to this field starts USB reset sequence, and writing 0H ends the process. Software

needs to keep the value of this field to 1H during the time regulated in USB specification 2.0 editions. When PP field value is 0H, the value of this field also becomes 0H.

7 Suspend Writing 1H to this field makes USB suspend; in that time, data transfer to downstream port is blocked, except the case of port reset. When 1H is written during transaction, the data transfer to downstream port is blocked after completing the transaction; therefore, shifting to the suspend state may be delayed. In this case, 1H is not read from this field until state is changed to suspend. In the suspend state, resume detection is performed. Although 0H is written to this field, host controller ignores it. The controller sets the value of this field to 0H in the following cases: • 0H is written to ForcePortResume field • 1H is written to PortReset field When 1H is written to this field during port status is not enabled, the operation is undefined.

6 ForcePort- Resume

When software writes 1H to this field, resume is sent to USB signal wire. When the transition from J_STATE to K_STATE is detected on the USB signal wire during suspend, host controller sets 1H to this field. Operation for when software writes 1H to this field during port state is suspend is undefined. While this field's value is 1H, resume is sent continuously to USB signal wire. Software needs to keep this field's value to 1H in the period regulated in the USB specification 2.0 editions to write 0H in order to send resume.

5 Over-current- Change

When OvercurrentActive field value changes, the value of this field becomes 1H. This field is cleared by writing 1H, and the value becomes 0H.

4 Over-current- Active

This field's value becomes 1H as long as overcurrent continues.

3 Port- EnableDisable-

Change

When PortEnableDisable field value changes, the value of this field becomes 1H. This field is cleared by writing 1H, and the value becomes 0H.

2 Port- EnableDisable

The value 1H shows that the port is enabled. Only when connected device to the port is high-speed device in the reset sequence, host controller sets the value of this field to 1H. Although software writes 1H to this field, the port cannot be enabled.

1 Connect- Status- Change

When CurrentConnectStatus field value changes, the value of this field becomes 1H. This field is cleared by writing 1H, and the value becomes 0H.

0 Current- Connect-

Status

The value becomes 1H while device is connected to the port.

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INARY


26.6.14. Programmable Microframe Base Value Register (INSNREG00)

Address FFF8_0090H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name (Reserved) R/W R/W R R R/W R/W R/W R/W R/W R R R R R R R R


Name (Reserved) Value EN R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-14 (Reserved) Reserved field. 13-1 Value Micro frame length is set.

0 EN When 1H is written, this register function becomes enabled. This register is for verification.

26.6.15. Programmable Packet Buffer OUT/IN Threshold Register (INSNREG01)

Address FFF8_0094H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name OUT_TH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name IN_TH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0


No. Name 31-16 OUT_TH Host controller starts USB transfer when number of byte of the data set to this field is fetched

from the memory. The settable min. value is 10H. 15-0 IN_TH Host controller starts transfer to memory when number of byte of the data set to this field is stored

to packet buffer. The settable min. value is 10H.


USB Host controller

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26.6.16. Programmable Packet Buffer Depth Register (INSNREG02)

Address FFF8_0098H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16



Name (Reserved) DEPTH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0


No. Name 31-12 (Reserved) Reserved field. 11-0 DEPTH Packet buffer size is set in DWORD unit. The settable max. value is 80H.

26.6.17. Time Available Offset Register (INSNREG03) Address FFF8_009CH



Name (Reserved) Time Available Offset *1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: (Reserved)

Bit field

Description No. Name 31-9 (Reserved) Reserved field. 8-1 Time Available

Offset Reserved field. Operation with setting other values than "00H" is undefined.

0 (Reserved) Reserved field. Operation with setting other values than "0H" is undefined.


USB Host controller

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26.6.18. Debug Register (INSNREG04) Address FFF8_00A0H




Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



4 NAK reload fix is controlled. 0H: NAK reload fix is enabled 1H: NAK reload fix is disabled

3 (Reserved) Reserved field. 2 When 1H is written to this field, measurement function at the port enumeration time becomes

valid. Normally, initial value should be kept as it is. 1 When 1H is written to this field, writing to HCCPARAMS becomes valid. Normally, initial value

should be kept as it is. 0 When 1H is written to this field, writing to the HCSPARAMS register becomes valid. Normally,

initial value should be kept as it is.

26.6.19. UTMI Control Status Register (INSNREG05) Address FFF8_00A4H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) R/W R R R R R R R R R R R R R R R R/W


Name (Reserved) (Reserved) (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



17 (Reserved) Reserved field. 16-13 (Reserved) Reserved field.

12 (Reserved) Reserved field. 11-8 (Reserved) Reserved field. 7-0 (Reserved) Reserved field.


USB Host controller

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26.6.20. Revision Register (HcRevision) Address FFF8_1000H



Name (Reserved) REV R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0


No. Name 31-8 (Reserved) Reserved field. 7-0 REV Version of conformed OHCI standard is indicated.

10H is always read.


USB Host controller

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26.6.21. Control Register (HcControl) Address FFF8_1004H



Name (Reserved) RWE RWC IR HCFS BLE CLE IE PLE CBSR R/W R R R R R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



10 RWE This field is ignored since OHCI of this LSI does not support remote wake-up function. 9 RWC 0H is always read since OHCI of this LSI does not support wake-up function. 8 IR Route is directed to generate interrupt.

0H: Normal interrupt route is used 1H: SMI route is used

7-6 HCFS Operation status of OHCI is displayed, and each value indicates as follows.

0H Operation status is USBReset 1H Operation status is USBResume 2H Operation status is USBOperational 3H Operation status is USBSuspend

As a result of resume detection, OHCI updates the value of this field only when state shifts from USB suspension to USB resume.

5 BLE When the value of this field is set to 1H, bulk list process is performed from the next frame; moreover, setting 0H does not perform the process from the next frame. If ED specified by HcBulkCurrentED is removed during bulk list process stop, HcBulkCurrentED should be moved to the next ED before enabling the process.

4 CLE When the value of this field is set to 1H, control list process is performed from the next frame; moreover, setting 0H does not perform the process from the next frame. If ED specified by HcControlCurrentED is removed during control list process stop, HcControlCurrentED should be moved to the next ED before enabling the process.

3 IE This field controls whether to perform isochronous ED process. If the value of this field is 1H when isochronous ED is found during periodic list process, OHCI continues the list process. If the value of this field is 0H, OHCI stops the periodic list process and starts control list or bulk list process.

2 PLE When the value of this field is set to 1H, periodic list process is performed from the next frame; moreover, setting 0H does not perform the process from the next frame.

1-0 CBSR This field specifies ratio of control ED and bulk ED processes. Correlation of the value and the ratio is as follows.

0H 1pc. of control ED which is not empty is processed before moving to bulk ED process

1H 2pcs. of control ED which are not empty are processed before moving to bulk ED process




USB Host controller

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26.6.22. Command/Status Register (HcCommandStatus) Address FFF8_1008H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) SOC R/W R/W R R R/W R/W R/W R/W R/W R R R R R R R R


Name (Reserved) OCR BLF CLF HCRR/W R R R R R R R R R R R R R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-18 (Reserved) Reserved field. 17-16 SOC This field is incremented every time schedule overrun error is detected. When this counting

value reaches from 0H to 3H, it will return to 0H after next increment. 15-4 (Reserved) Reserved field.

3 OCR In order to request control switch to host controller driver, OS sets 1H to this field. Then the controller sets OwnershipChange field of HcInterruptStatus. This field’s value is not changed after the control switch until it is returned to 0H by host controller and software sets the value again.

2 BLF This bit is used to indicate whether a valid ED exists in the bulk list. When ED is added to the list,host controller driver writes 1H to the field, then starts bulk list process and sets this field’s value to 0H. When ED is found in the list, the controller sets value of this field to 1H to continue the process.If ED is not found, the value of this field stays in 0H and the bulk list process ends.

1 CLF Existence of valid ED in the control list is indicated. When ED is added to the list, host controller driver writes 1H to the field, then starts control list process and sets this field’s value to 0H. When ED is found in the list, the controller sets value of this field to 1H to continue the process.If ED is not found, the value of this field stays in 0H and the control list process ends.

0 HCR When 1H is set to this field, host controller starts software reset. After the process, the value becomes 0H.


USB Host controller

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26.6.23. Interrupt Status Register (HcInterruptStatus) Address FFF8_100CH

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name *1 OC (Reserved) R/W R R/W R R R R R R R R R R R R R R


Name (Reserved) RHSC FNO UE RD SF WDH SO R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *1: (Reserved)

Bit field (Note)

Description No. Name 31 (Reserved) Reserved field. 30 OC When OwnershipChangeRequest field of the HcCommandStatus register is set, the value of this

field becomes 1H. If this register is not masked, SMI occurs immediately after setting the value to this field.

20-7 (Reserved) Reserved field. 6 RHSC When HcRhStatus or HcRhPortStatus[1] register contents are changed, the value of this field

becomes 1H. 5 FNO When MSB (bit 15) of HcFmNumer is changed and HccaFrameNumber value is updated, the

value of this field becomes 1H. 4 UE When host controller accesses to memory and error response occurs, or Sys_interrupt bit of the

CCNT module's USB setting register (CUSB) is set, this bit becomes 1H. OHCI stops the process by setting value of this field to 1H, and the value becomes 0H by resetting OHCI.

3 RD When resume signal is detected from the device connected to USB, the value of this field becomes 1H, except the case that operation state of OHCI is USBResume. In this case, the value of this field does not change to 1H though resume is detected.

2 SF When OHCI starts new frame and HccaFrameNumber is updated, the value of this field becomes 1H.

1 WDH When HcDoneHead register contents are copied to HccaDoneHead, the value of this field becomes 1H. OHCI does not update HccaDoneHead value until driver saves the contents and sets the value of this field to 0H.

0 SO When schedule overrun is detected in the current frame, the value of this field becomes 1H after HccaFrameNumber is updated. In addition, SOC field value of HcCommandStatus register is incremented.

Note) Host controller sets each bit field, but it does not clear the field. Moreover, writing 1H clears bit field but it does not set the field.


USB Host controller

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26.6.24. Interrupt Enable Register (HcInterruptEnable) Address FFF8_1010H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name MIE OC (Reserved) R/W R/W R/W R R R R R R R R R R R R R R



Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31 MIE Interrupt to entire OHCI is enabled. 30 OC When 1H is written to this field, interrupt with OwnershipChange becomes enabled.

Writing 0H to this field is ignored. 29-7 (Reserved) Reserved field.

6 RHSC When 1H is written to this field, interrupt with RootHubStatusChange becomes enabled. Writing 0H to this field is ignored.

5 FNO When 1H is written to this field, interrupt with FrameNumberOverflow becomes enabled. Writing 0H to this field is ignored.

4 UE When 1H is written to this field, interrupt with UnrecoverableError becomes enabled. Writing 0H to this field is ignored.

3 RD When 1H is written to this field, interrupt with ResumeDetect becomes enabled. Writing 0H to this field is ignored.

2 SF When 1H is written to this field, interrupt with StartOfFrame becomes enabled. Writing 0H to this field is ignored.

1 WDH When 1H is written to this field, interrupt with WritebackDoneHead becomes enabled. Writing 0H to this field is ignored.

0 SO When 1H is written to this field, interrupt with SchedulingOverrun becomes enabled. Writing 0H to this field is ignored.


USB Host controller

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26.6.25. Interrupt Disable Register (HcInterruptDisable) Address FFF8_1014H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name ME OC (Reserved) R/W R/W R/W R R R R R R R R R R R R R R



Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31 MIE When 1H is written to this field, all interrupts are disabled. 30 OC When 1H is written to this field, interrupt with OwnershipChange becomes disabled.

Writing 0H to this field is ignored. 29-7 (Reserved) Reserved field.

6 RHSC When 1H is written to this field, interrupt with RootHubStatusChange becomes disabled. Writing 0H to this field is ignored.

5 FNO When 1H is written to this field, interrupt with FrameNumberOverflow becomes disabled. Writing 0H to this field is ignored.

4 UE When 1H is written to this field, interrupt with UnrecoverableError becomes disabled. Writing 0H to this field is ignored.

3 RD When 1H is written to this field, interrupt with ResumeDetect becomes disabled. Writing 0H to this field is ignored.

2 SF When 1H is written to this field, interrupt with StartOfFrame becomes disabled. Writing 0H to this field is ignored.

1 WDH When 1H is written to this field, interrupt with WritebackDoneHead becomes disabled. Writing 0H to this field is ignored.

0 SO When 1H is written to this field, interrupt with SchedulingOverrun becomes disabled. Writing 0H to this field is ignored.


USB Host controller

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INARY


26.6.26. HCCA Register (HcHCCA) Address FFF8_1018H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name HCCA (high) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name HCCA (low) (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-8 HCCA High order 24 bits of HCCA base address are stored. Since the base address must be aligned on

256 byte boundary, low order 8 bits are always become 00H. 7-0 (Reserved) Reserved field.

26.6.27. Periodic Current ED Register (HcPeriodCurrentED) Address FFF8_101CH

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PCED (high) R/W R R R R R R R R R R R R R R R R


Name PCED (low) (Reserved) R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-4 PCED High order 28 bits of pointer to current ED in the periodic list are stored. Since ED address must

be aligned on 16 byte boundary, low order 4 bits are always become 0H. 3-0 (Reserved) Reserved field.


USB Host controller

PRELIM

INARY


26.6.28. Control Head ED Register (HcControlHeadED) Address FFF8_1020H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CHED (high) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name CHED (low) (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-4 CHED High order 28 bits of pointer to ED which is head of the control list are stored. Since ED address

must be aligned on 16 bye boundary, low order 4 bits are always become 0H. This is read from HCCA by host controller at initialization.

3-0 (Reserved) Reserved field.

26.6.29. Control Current ED Register (HcControlCurrentED) Address FFF8_1024H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CCED (high) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name CCED (low) (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-4 CCED High order 28 bits of pointer to current ED in control list are stored. Since ED address must be

aligned on 16 byte boundary, low order 4 bits are always become 0H. 3-0 (Reserved) Reserved field.


USB Host controller

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26.6.30. Bulk Head ED Register (HcBulkHeadED) Address FFF8_1028H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name BHED (high) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name BHED (low) (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-4 BHED High order 28 bits of pointer to ED which is head of bulk list are stored. Since ED address must

be aligned on 16 byte boundary, low order 4 bits are always become 0H. This is read from HCCA by host controller at initialization.


26.6.31. Bulk Current ED Register (HcBulkCurrentED) Address FFF8_102CH

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name BCED (high) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name BCED (low) (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-4 BCED High order 28 bits of pointer to current ED in the bulk list are stored. Since ED address must be

aligned on 16 byte boundary, low order 4 bits are always become 0H. Only when BulkListEnable of the HcControl register is "0", writing to these bits is available.



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26.6.32. Done Head Register (HcDoneHead) Address FFF8_1030H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name DH (high) R/W R R R R R R R R R R R R R R R R


Name DH (low) (Reserved) R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-4 DH High order 28 bits of pointer which is in head of completed TD list are stored. Since TD address

must be aligned on 16 byte boundary, low order 4 bits are always become 0H. OHCI writes the value of this register to NextTD field of completed TD, and sets high order 28 bits of TD address to this field. After writing HcDoneHead register contents to HCCA, OHCI sets the value of this field to 0H.


26.6.33. Frame Interval Register (HcFmInterval) Address FFF8_1034H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name FIT FSMPS R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name (Reserved) FI R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1


No. Name 31 FIT Host controller driver toggles this field’s value every time new value is written to this register.

30-16 FSMPS Max. packet size of transmission is specified in bit without having scheduling overrun. 15-14 (Reserved) Reserved field. 13-0 FI Interval value between SOFs are written in bit time.


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26.6.34. Frame Remaining Register (HcFmRemaining) Address FFF8_1038H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name FRT (Reserved) R/W R R R R R R R R R R R R R R R R


Name (Reserved) FR R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31 FRT When the value of the FR field becomes 0H, FIT field value of the HcFmInterval register is copied

to this field. 30-14 (Reserved) Reserved field. 13-0 FR This is the counter displaying remaining time of the frame in operation. This field is

decremented every 1 bit time. When the value becomes 0H, FI field value of the HcFmInterval register is copied to this field.

26.6.35. Frame Number Register (HcFmNumber) Address FFF8_103CH



Name FN R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-16 (Reserved) Reserved field. 15-0 FN This is the counter incremented every time copy is carried out from the HcFmInterval register to

the HcFmRemaining register. When the value reaches to FFFFH, the counter value returns to 0H.


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26.6.36. Periodic Start Register (HcPeriodicStart) Address FFF8_1040H



Name (Reserved) PS R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31-14 (Reserved) Reserved field. 13-0 PS When FR field value of the HcFmRemaining register reaches to the value of this field, OHCI

prioritizes periodic list process over control list and bulk list processes. It is recommended to set about 10% lower value than the one set in FI field of the HcFmInterval register.

26.6.37. LS Threshold Register (HcLSThreshold) Address FFF8_1044H



Name (Reserved) LST R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0


No. Name 31-12 (Reserved) Reserved field. 11-0 LST OHCI starts low speed transaction only when FR field value of the FmRemaining register is larger

than the value of this field.


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26.6.38. Root Hub Descriptor A Register (HcRhDescriptorA) Address FFF8_1048H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name POTPGT (Reserved) R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R


Name (Reserved) NOCP OCPM DT NPS PSM NDP R/W R R R R/W R/W R R/W R/W R R R R R R R R

Initial value 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0


No. Name 31-24 POTPGT The value from power-on of route hub to port access ready is input to this field in 2mS unit. 23-13 (Reserved) Reserved field.

12 NOCP Notification method of overcurrent status to route hub is specified. 0H: Overcurrent status is notified according to OCPM field value 1H: Overcurrent protection is not supported

11 OCPM Notification method of overcurrent status to route hub port is specified. Specified contents in this field are valid only when NOCP field value is 0H.

0H: Status of all ports is notified altogether 1H: Status is notified by port

10 DT Device type of route hub is indicated. Since route hub must not be compound device, the value of this field is fixed to 0H.

9 NPS Whether to control power supply of route hub is specified. 0H: Power is turned on/off 1H: Power supply of the port is always on

8 PSM Power supply control method of route hub is specified. 0H: Turn the power on/off of all ports 1H: Turn the power on/off per port

7-0 NDP Route hub's number of downstream port is indicated. Read value of this bit is 2H (indicating 2 ports are supported); however, this LSI only supports 1 port, and software process should convert the value from 2H to 1H.


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26.6.39. Root Hub Descriptor B Register (HcRhDescriptorB) Address FFF8_104CH

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PPCM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W


Name DR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Note 31-16 PPCM Whether power supply of port is controlled by global power control command is specified per

port. Correspondence of bit in the port and the field is as follows.

Bit Port 16 Reserved 17 Port 1 18 This bit indicates port 2; however, this LSI actually supports

only port 1 19-31 Not supported by this LSI

Each bit value represents as follows:

0H: Power supply of port is controlled by global power control command 1H: Power supply of port is not controlled by global power control command

15-0 DR Whether the device connected to the port is detachable is specified in bit map. Correspondence of bit in the port and the field is as follows.

Bit Port 0 Reserved 1 Port 1 2-15 Not supported by this LSI

Each bit value represents as follows:

0H: Device is detachable 1H: Device is not detachable


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26.6.40. Root Hub Status Register (HcRhStatus) Address FFF8_1050H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CRWE (Reserved) OCIC LPSC R/W W R R R R R R R R R R R R R R/W R/W


Name DRWE (Reserved) OCI LPS R/W R/W R R R R R R R R R R R R R R R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


No. Name 31 CRWE When 1H is written to this field, DRWE field is cleared.

30-18 (Reserved) Reserved field. 17 OCIC When CCI field value is changed, the value of this field becomes 1H.

The value of this field is cleared by writing 1H. 16 LPSC When 1H is written to this field, SetGlobalPower command is issued.

0H is always read by reading this field. 15 DRWE When 1H is written to this field, ConnectStatusChange occurrence at remote wake-up event

detection is enabled. 14-2 (Reserved) Reserved field.

1 OCI Status of App_prt_overcur field value of CCNT's USB set register (CUSB) is reflected to this field. It is valid when NOCP field of the HcRhDescriptorA register is 0H. Each value represents as follows:

0H: Overcurrent condition is not detected (App_prt_overcur = 0) 1H: Overcurrent condition is detected (App_prt_overcur = 1)

0 LPS When 1H is written to this field, ClearGlobalPower command is issued. 0H is always read by reading this field.


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26.6.41. Root Hub Port Status/Control Register 1 (HcRhPortStatus[1])

Address FFF8_1054H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name (Reserved) PRSC OCIC PSSC PESC CSCR/W R R R R R R R R R R R R/W R/W R/W R/W R/W


Name (Reserved) LSDA PPS (Reserved) PRS POCI PSS PES CCSR/W R R R R R R R/W R/W R R R R/W R/W R R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



20 PRSC The value of this field becomes 1H after port reset. The value of this field is cleared by writing 1H.

19 OCIC Value of this field becomes valid only when overcurrent condition is set to be notified per port.The value becomes 1H when PortOverCurrentIndicator value is changed. The value of this field is cleared by writing 1H.

18 PSSC Value of this field becomes 1H at completion of resume sequence. When 1H is written or ResetStatusChange is set, the value of this field is cleared.

17 PESC Value of this field becomes 1H when PortEnableStatus is cleared by hardware. Clearing PortEnableStatus by software's writing operation does not affect to this field value. The value of this field is cleared by writing 1H.

16 CSC When connected event or disconnected event is detected, the value of this field becomes 1H. The value of this field is cleared by writing 1H.

15-10 (Reserved) Reserved field. 9 LSDA Reading and Writing has different function in this field:

At reading, whether low speed device is connected is specified. 0H: Full speed device is connected 1H: Low speed device is connected

At writing, PortPowerStatus is able to be cleared by writing 1H. Writing 0H to this field is ignored.8 PPS The status of power supply to port is output when reading.

0H: Port's power supply is off 1H: Port's power supply is on

The value of this field is set by writing 1H, and writing 0H is ignored. 7-5 (Reserved) Reserved field. 4 PRS Reset is sent to the port by writing 1H to this field and the value returns to 0H after completing

reset. Writing 0H to this field is ignored. Progress of port reset is confirmed by reading this field.

0H: Port is not in reset 1H: Port is in reset

3 POCI At reading, overcurrent condition per port is displayed. 0H: Port's current is normal 1H: Overcurrent occurs on port

Writing 1H executes resume sequence, and 0H is ignored. 2 PSS At reading, completion of port reset or host controller in USBRESUME state is displayed.

0H: Port is not suspended 1H: Port is suspended

Writing 1H sets PortSuspendStatus, and writing 0H is ignored. However, it is not set when CurrentConnectStatus is "0" that ConnectStatusChange is set instead.

1 PES When reading, this bit indicate whether port reset or port suspend is completed. 0H: Port is disabled 1H: Port is enabled

Writing 1H sets PortEnableStatus, and writing 0H is ignored. However, it is not set when CurrentConnectStatus is "0" that ConnectStatusChange is set instead.


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No. Name 0 CCS Whether device is connected at reading is displayed.

0H: Device is not connected to this port at this time 1H: Device is connected to this port at this time

Writing 1H clears PortEnableStatus, and writing 0H is ignored.

26.6.42. Link Mode Setting Register (LinkModeSetting) Address FFF8_2000H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name LMA LMB LMC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value - - - - - - - - 0 1 - - - - - - Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name LMD LME LMF R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value - - - - - - - - 0 0 0 0 0 0 - -


No. Name 31-24 LMA Do not change the value of this field. 23-22 LMB Do not change the value of this field. 21-16 LMC Do not change the value of this field. 15-8 LMD Do not change the value of this field. 7-2 LME Do not change the value of this field. 1-0 LMF Do not change the value of this field.

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26.6.43. PHY Mode Setting 1 Register (PHYModeSetting1) Address FFF8_2004H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name RESET (Reserved) PM1A ANPD *1 *2 (Reserved) PM1B R/W R R R R R/W R/W R/W R/W R R R R R R R R

Initial value 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name PM1C PM1DR/W R R/W R R R R R/W R R R R R/W R/W R/W R R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 - *1: RPDMEN *2: RPDPEN

Bit field

Description No. Name 31 RESET PHY block reset signal

0H: the reset of the PHY block is released 1H: the PHY block is reset

30-28 (Reserved) Reserved field. 27 PM1A Do not change the value of this field. 26 ANPD PHY block analog circuit power-down signal. Do not activate this bit during USB transactions.

0H: Normal operation 1H: Power down PHY block

25 RPDMEN ON/OFF control signal of D- Pull-down resistance. 0H: Pull-down resistance is off 1H: Pull-down resistance is on

24 RPDPEN ON/OFF control signal of D+ Pull-down resistance. 0H: Pull-down resistance is off 1H: Pull-down resistance is on

23-22 (Reserved) Reserved field. 21-16 PM1B Do not change the value of this field. 15-1 PM1C Do not change the value of this field.

0 PM1D Do not change the value of this field.

26.6.44. PHY Mode Setting 2 Register (PHYModeSetting2) Address FFF8_2008H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name (Reserved) SQSEL *1 R/W R R R R R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R


Name *1 COMPDISCON *2 *1 COMPUDCTL LEOP R/W R R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 *1: (Reserved) *2: COMPUPDPLS

Bit field


31-18 (Reserved) Reserved field. 17 SQSEL Do not change the value of this field.

16-15 (Reserved) Reserved field. 14-8 COMPDISCON Do not change the value of this field.


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No. Name 7 COMPUPDPLS Do not change the value of this field. 6 (Reserved) Reserved field.

5-3 COMPUPDCTL Do not change the value of this field. 2-0 LEOP Do not change the value of this field.

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SD memory controller (SDMC) FUJITSU SEMICONDUCTOR PROPRIETARY AND CONFIDENTIAL

27. SD memory controller (SDMC) SD memory controller is disclosed only for SD card licensee. Note: In this LSI, DMA mode of SDMC in CC_EXT_MODE register is not used. Therefore the CC_EXT_MODE[1] must set as “0”. DMA transfer between DMA controller and SDMC is using PIO transfer mode. ODMxREQ signals are connected to DMA request inputs (IDREQ11/12) of DMA controller. In this LSI, only block or burst transfer mode is supported for SDMC.

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Documents

MB9G711 LSI Product Specifications PRELIMINARY