mc542 A 03 2s07 - Instituto de Computaçãoducatte/mc542/Slides/mc... · “COD”- (Capítulo) MC542 3.3 Micro-Arquitetura • Micro-Arquitetura – Introdução – Recursos –

MC5423.1

2007

Prof. Paulo Cesar Centoducatte

[email protected]

www.ic.unicamp.br/~ducatte

MC542

Organização de ComputadoresTeoria e Prática

MC5423.2

MC542

Arquitetura de Computadores

Micro-Arquitetura

“DDCA” - (Capítulo 7)

“COD” - (Capítulo)

MC5423.3

Micro-Arquitetura

• Micro-Arquitetura– Introdução– Recursos– MIPS Mono-Ciclo

» Lw» Sw» R-Type» Beq» j

– MIPS Múlti-Ciclos» Lw» Sw» R-Type» Beq» j

MC5423.4

Introdução

• Micro-arquitetura: como estáimplementada a arquitetura emhardware

• Processador:– Datapath: blocos funcionais

– Controle: sinais de controle

Physics

Devices

Analog

Circuits

Digital

Circuits

Logic

Micro-

architecture

Architecture

Operating

Systems

Application

Software

electrons

transistors

diodes

amplifiers

filters

AND gates

NOT gates

adders

memories

datapaths

controllers

instructions

registers

device drivers

programs

MC5423.5

Micro-Arquitetura

• Múltiplas implementações para uma mesmaarquitetura:

– Single-cycle» Cada instrução é executada em um único ciclo

– Multicycle» A execução de cada instrução é dividida em uma série de passos menores

– Pipelined» A execução de cada instrução é dividida em uma série de passos menores

» Múltiplas instruções (parte de) executando ao mesmotempo.

MC5423.6

Micro-Arquitetura

• Program execution time

Execution Time = (# instructions)(cycles/instruction)(seconds/cycle)

• Definições:– Cycles/instruction = CPI

– Seconds/cycle = clock period

– 1/CPI = Instructions/cycle = IPC

• Desafios na implementação de uma micro-arquitetura– Custo

– Power

– Desempenho

MC5423.7

Micro-Arquitetura

• Processador MIPS (Microprocessor without Interlolocked Pipeline Stages)

– Vamos implementar um sub conjunto das instruçõesMIPS:

– R-type instructions: and, or, add, sub, slt

– Memory instructions: lw, sw

– Branch instructions: beq

MC5423.8

Micro-Arquitetura

• Estado da Arquitetura

– Determina o estado do Processador em um dado instante de tempo

PC

32 registradores

Memória

MC5423.9

Micro-Arquitetura

• Elementos de estados do MIPS:

CLK

A RD

Instruction

Memory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Register

File

A RD

Data

Memory

WD

WE

PCPC'

CLK

32 32

32 32

32

32

32

32

32

32

5

5

5

MC5423.10

Processador MIPS Single-Cycle

• Datapath

• Controle

MC5423.11


• Execução de lw

1: Fetch da Instrução

CLK

A RD

InstructionMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

RegisterFile

A RD

DataMemory

WD

WEPCPC'

Instr

CLK

MC5423.12



2: Lê o operando fonte do RF

Instr

CLK

A RD

InstructionMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

RegisterFile

A RD

DataMemory

WD

WEPCPC'

25:21

CLK

MC5423.13



3: Sign-extend o imediato

SignImm

CLK

A RD

InstructionMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

A RD

DataMemory

WD

WEPCPC' Instr

25:21

15:0

CLK

MC5423.14



4: Calcula o endereço efetivo de memória

SignImm

CLK

A RD

InstructionMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

A RD

DataMemory

WD

WEPCPC' Instr

25:21

15:0

SrcB

ALUResult

SrcA Zero

CLK

ALUControl2:0

ALU

010

MC5423.15



5: Lê o dado da memória e o escreva no RF

A1

A3

WD3

RD2

RD1WE3

A2

SignImm

CLK

A RD

InstructionMemory

CLK

Sign Extend

Register

File

A RD

DataMemory

WD

WEPCPC' Instr

25:21

15:0

SrcB20:16

ALUResult ReadData

SrcA

RegWrite

Zero

CLK

ALUControl2:0

ALU

0101

MC5423.16



6: Determina o endereço da próxima instrução

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

A RD

DataMemory

WD

WEPCPC' Instr

25:21

15:0

SrcB20:16

ALUResult ReadData

SrcA

PCPlus4

Result

RegWrite

Zero

CLK

ALUControl2:0

ALU

0101

MC5423.17


• Execução de sw

• Precisa escrever o valor do registrador na memória

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

A RD

DataMemory

WD

WEPCPC' Instr

25:21

20:16

15:0

SrcB20:16

ALUResult ReadData

WriteData

SrcA

PCPlus4

Result

MemWriteRegWrite

Zero

CLK

ALUControl2:0

ALU

10100

MC5423.18


• Instruções R-Type: add, sub, and, or, ….

• Escrever ALUResult no RF– Escreve em rd e não em rt

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PCPC' Instr25:21

20:16

15:0

SrcB

20:16

15:11

ALUResult ReadData

WriteData

SrcA

PCPlus4WriteReg4:0

Result

RegDst MemWrite MemtoRegALUSrcRegWrite

Zero

CLK

ALUControl2:0

ALU

0varies1 001

MC5423.19

Processador MIPS Single-Cycle• Instrução beq

• Determina se os conteúdos dos registradores sãoiguais

• Calcula o endereço alvo do desvio (sign-extended immediate + PC+4)

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PC0

1

PC' Instr25:21

20:16

15:0

SrcB

20:16

15:11

<<2

+

ALUResult ReadData

WriteData

SrcA

PCPlus4

PCBranch

WriteReg4:0

Result

RegDst Branch MemWrite MemtoRegALUSrcRegWrite

Zero

PCSrc

CLK

ALUControl2:0

ALU

01100 x0x 1

MC5423.20

Processador MIPS Single-Cycle - or

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB

20:16

15:11

<<2

+

ALUResult ReadData

WriteData

SrcA

PCPlus4

PCBranch

WriteReg4:0

Result

31:26

RegDst

Branch

MemWrite

MemtoReg

ALUSrc

RegWrite

Op

Funct

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

0010

01

0

0

1

0

MC5423.21

Processador MIPS Single-Cycle - sw

+

+ALU

MC5423.22


• Unidade de Controle

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB

20:16

15:11

<<2

+

ALUResult ReadData

WriteData

SrcA

PCPlus4

PCBranch

WriteReg4:0

Result

31:26

RegDst

Branch

MemWrite

MemtoReg

ALUSrc

RegWrite

Op

Funct

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

MC5423.23


RegDst

Branch

MemWrite

MemtoReg

ALUSrcOpcode5:0

ControlUnit

ALUControl2:0Funct5:0

MainDecoder

ALUOp1:0

ALUDecoder

RegWrite

Control Unit

MC5423.24


• ALU

A & B000

A | B001

A + B010

not used011

A & B100

A | ~B101

A - B110

SLT111

FunctionF2:0

ALU

N N

N

3

A B

Y

F

MC5423.25


• ALU

+

2 01

A B

Cout

Y3

01

F2

F1:0

[N-1] S

NN

N

N

N NNN

N

2

Ze

roE

xte

nd

MC5423.26


• ALU Decoder

Not Used11

Look at Funct10

Subtract01

Add00

MeaningALUOp1:0

111 (SLT)101010 (slt)1X

001 (Or)100101 (or)1X

000 (And)100100 (and)1X

110 (Subtract)100010 (sub)1X

010 (Add)100000 (add)1X

110 (Subtract)XX1

010 (Add)X00

ALUControl2:0FunctALUOp1:0

MC5423.27


• Decodificador Principal

01X010X0000100beq

00X101X0101011sw

00000101100011lw

10000011000000R-type

ALUOp1:0

MemtoRegMemWriteBranchAluSrcRegDstRegWriteOp5:0Instruction

MC5423.28


• Extendendo a Funcionalidade: addi

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB

20:16

15:11

<<2

+

ALUResult ReadData

WriteData

SrcA

PCPlus4

PCBranch

WriteReg4:0

Result

31:26

RegDst

Branch

MemWrite

MemtoReg

ALUSrc

RegWrite

Op

Funct

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

MC5423.29



00000101001000addi

01X010X0000100beq

00X101X0101011sw

00100101100011lw

10000011000000R-type

ALUOp1:0MemtoRegMemWriteBranchAluSrcRegDstRegWriteOp5:0Instruction

MC5423.30


• Extendendo a Funcionalidade: j

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB

20:16

15:11

<<2

+

ALUResult ReadData

WriteData

SrcA

PCPlus4

PCBranch

WriteReg4:0

Result

31:26

RegDst

Branch

MemWrite

MemtoReg

ALUSrc

RegWrite

Op

Funct

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

MC5423.31


• Extendendo a Funcionalidade: j

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PC0

1PC' Instr

25:21

20:16

15:0

5:0

SrcB

20:16

15:11

<<2

+

ALUResult ReadData

WriteData

SrcA

PCPlus4

PCBranch

WriteReg4:0

Result

31:26

RegDst

Branch

MemWrite

MemtoReg

ALUSrc

RegWrite

Op

Funct

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

0

1

25:0 <<2

27:0 31:28

PCJump

Jump

MC5423.32



1XXX0XXX0000100j

0

0

0

0

0

Jump

00000101001000addi

01X010X0000100beq

00X101X0101011sw

00100101100011lw

10000011000000R-type

ALUOp1:0MemtoRegMemWriteBranchAluSrcRegDstRegWriteOp5:0Instruction

MC5423.33


• Desempenho: Quão rápido é o processador?

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PC0

1PC' Instr

25:21

20:16

15:0

5:0

SrcB

20:16

15:11

<<2

+

ALUResult ReadData

WriteData

SrcA

PCPlus4

PCBranch

WriteReg4:0

Result

31:26

RegDst

Branch

MemWrite

MemtoReg

ALUSrc

RegWrite

Op

Funct

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

0

1

25:0 <<2

27:0 31:28

PCJump

Jump

MC5423.34


• O cycle time é limitado pelo caminho crítico: lw

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB

20:16

15:11

<<2

+

ALUResult ReadData

WriteData

SrcA

PCPlus4

PCBranch

WriteReg4:0

Result

31:26

RegDst

Branch

MemWrite

MemtoReg

ALUSrc

RegWrite

Op

Funct

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

1

0100

1

0

1

0 0

MC5423.35


• Caminho crítico

Tc = tpcq_PC + tmem + max(tRFread, tsext) + tmux + tALU + tmem + tmux + tRFsetup

• Na maioria das implementações os caminhos limitantessão: memória, ALU, register file. Assim,

Tc = tpcq_PC + 2tmem + tRFread + 2tmux + tALU + tRFsetup

MC5423.36


30tpcq_PCRegister clock-to-Q

Delay (ps)ParameterElement

20tsetupRegister setup

25tmuxMultiplexer

200tALUALU

250tmemMemory read

150tRFreadRegister file read

20tRFsetupRegister file setup

Tc = tpcq_PC + 2tmem + tRFread + 2tmux + tALU + tRFsetup= [30 + 2(250) + 150 + 2(25) + 200 + 20] ps

= 950 ps

MC5423.37


• Para um programa 100 bilhões de instruções executando em um processador MIPS single-cycle,

Execution Time = (# instructions)(cycles/instruction)(seconds/cycle)

= (100 × 109)(1)(950 × 10-12 s)

= 95 seconds

MC5423.38

Processador MIPS Multicycle

• Datapath

• Controle

MC5423.39


• Blocos Básicos

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

RegisterFile

PCPC'

WD

WE

CLK

EN

ALU

Restrição de Projeto:

Somente 1 pode ser usado por vez

MC5423.40


• Datapath

– datapath para o lw

Exemplo: lw $s4, 27($t2)

• Fetch da Instrução

b

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

RegisterFile

PCPC' Instr

CLK

WD

WE

CLK

EN

IRWrite

MC5423.41


• Leitura do operando fonte do RF (rs)

b

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

RegisterFile

PCPC' Instr25:21

CLK

WD

WE

CLK CLK

A

EN

IRWrite

MC5423.42


• Sign-Extend o Imediato

SignImm

b

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

PCPC' Instr25:21

15:0

CLK

WD

WE

CLK CLK

A

EN

IRWrite

MC5423.43


• Soma do Base Address ao Offset

SignImm

b

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

PCPC' Instr25:21

15:0

SrcB

ALUResult

SrcA

ALUOut

CLK

ALUControl2:0

ALU

WD

WE

CLK CLK

A CLK

EN

IRWrite

MC5423.44


• Carga do dado a partir da Memória

SignImm

b

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

PCPC' Instr25:21

15:0

SrcB

ALUResult

SrcA

ALUOut

CLK

ALUControl2:0

AL

U

WD

WE

CLK

Adr

Data

CLK

CLK

A CLK

EN

IRWriteIorD

0

1

MC5423.45


• Escrita do Dado no Register File

SignImm

b

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

PCPC' Instr25:21

15:0

SrcB20:16

ALUResult

SrcA

ALUOut

RegWrite

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A CLK

EN

IRWriteIorD

0

1

MC5423.46


• Incremento do PC de 4

PCWrite

SignImm

b

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1PCPC' Instr25:21

15:0

SrcB

20:16

ALUResult

SrcA

ALUOut

ALUSrcARegWrite

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

00

01

10

11

4

CLK

ENEN

ALUSrcB1:0IRWriteIorD

0

1

MC5423.47


• Datapath também para sw

SignImm

b

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1PC0

1

PC' Instr25:21

20:16

15:0

SrcB20:16

ALUResult

SrcA

ALUOut

MemWrite ALUSrcARegWrite

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

00

01

10

11

4

CLK

ENEN

ALUSrcB1:0IRWriteIorDPCWrite

B

MC5423.48


• Datapath para instruções R-Type

0

1

SignImm

b

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1PC0

1

PC' Instr25:21

20:16

15:0

SrcB20:16

15:11

ALUResult

SrcA

ALUOut

RegDstMemWrite MemtoReg ALUSrcARegWrite

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

ALUSrcB1:0IRWriteIorDPCWrite

MC5423.49


• Datapath para beq

SignImm

b

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1 0

1

PC0

1

PC' Instr25:21

20:16

15:0

SrcB20:16

15:11

<<2

ALUResult

SrcA

ALUOut

RegDst BranchMemWrite MemtoReg ALUSrcARegWrite

Zero

PCSrc

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

0

1Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

ALUSrcB1:0

IRWriteIorD PCWrite

PCEn

MC5423.50


• Datapath para o Processador Multicycle

ImmExt

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1 0

1

PC0

1

PC' Instr25:21

20:16

15:0

SrcB20:16

15:11

<<2

ALUResult

SrcA

ALUOut


Zero

PCSrc

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

0

1Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

ALUSrcB1:0

IRWriteIorD PCWrite

PCEn

MC5423.51


• Controle para o Processador Multicycle

SignImm

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1 0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB20:16

15:11

<<2

ALUResult

SrcA

ALUOut

31:26

Re

gD

st

Branch

MemWrite

Mem

toR

eg

ALUSrcA

RegWriteOp

Funct

ControlUnit

Zero

PCSrc

CLK

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

0

1Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

ALUSrcB1:0IRWrite

IorD

PCWrite

PCEn

MC5423.52


• Unidade de controle

ALUSrcA

PCSrc

Branch

ALUSrcB1:0

Opcode5:0

ControlUnit

ALUControl2:0Funct5:0

MainController

(FSM)

ALUOp1:0

ALUDecoder

RegWrite

PCWrite

IorD

MemWrite

IRWrite

RegDst

MemtoReg

RegisterEnables

MultiplexerSelects

MC5423.53


• Unidade de Controle– Finite state machine

– Diagrama de transição de estados para lw

MC5423.54


• Fetch da Instrução

SignImm

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1 0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB20:16

15:11

<<2

ALUResult

SrcA

ALUOut

31:26

Re

gD

st

Branch

MemWrite

Mem

toR

eg

ALUSrcA

RegWriteOp

Funct

ControlUnit

Zero

PCSrc

CLK

CLK

ALUControl2:0

AL

U

WD

WE

CLK

Adr

0

1Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

ALUSrcB1:0IRWrite

IorD

PCWrite

PCEn

0

1 1

0

X

X

00

01

0100

1

0

IorD = 0AluSrcA = 0

ALUSrcB = 01

ALUOp = 00

PCSrc = 0IRWritePCWrite

Reset

S0: Fetch

MC5423.55


• Decodificação da Instrução

IorD = 0AluSrcA = 0

ALUSrcB = 01

ALUOp = 00

PCSrc = 0

IRWritePCWrite

Reset

S0: Fetch S1: Decode

SignImm

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1 0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB20:16

15:11

<<2

ALUResult

SrcA

ALUOut

31:26

Re

gD

st

Branch

MemWrite

Me

mto

Reg

ALUSrcA

RegWriteOp

Funct

ControlUnit

Zero

PCSrc

CLK

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

0

1Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

ALUSrcB1:0IRWrite

IorD

PCWrite

PCEn

X

0 0

0

X

X

0X

XX

XXXX

0

0

MC5423.56


• Cálculo do endereço efetivo

IorD = 0AluSrcA = 0

ALUSrcB = 01ALUOp = 00PCSrc = 0

IRWritePCWrite

ALUSrcA = 1ALUSrcB = 10ALUOp = 00

Reset

S0: Fetch

S2: MemAdr

S1: Decode

Op = LWor

Op = SW

SignImm

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1 0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB20:16

15:11

<<2

ALUResult

SrcA

ALUOut

31:26

Reg

Dst

Branch

MemWrite

Mem

toR

eg

ALUSrcA

RegWriteOp

Funct

ControlUnit

Zero

PCSrc

CLK

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

0

1Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

ALUSrcB1:0IRWrite

IorD

PCWrite

PCEn

X

0 0

0

X

X

01

10

010X

0

0

MC5423.57


• Leitura da Memória e

Escrita no RF IorD = 0

AluSrcA = 0

ALUSrcB = 01

ALUOp = 00

PCSrc = 0

IRWritePCWrite

ALUSrcA = 1

ALUSrcB = 10ALUOp = 00

IorD = 1

Reset

S0: Fetch

S2: MemAdr

S1: Decode

S3: MemRead

Op = LWor

Op = SW

Op = LW

RegDst = 0

MemtoReg = 1

RegWrite

S4: Mem

Writeback

MC5423.58


• Diagrama de transição de estados para sw

IorD = 0

AluSrcA = 0ALUSrcB = 01

ALUOp = 00

PCSrc = 0

IRWritePCWrite

ALUSrcA = 1


IorD = 1IorD = 1

MemWrite

Reset

S0: Fetch

S2: MemAdr

S1: Decode

S3: MemReadS5: MemWrite

Op = LWor

Op = SW

Op = LW

Op = SW

RegDst = 0MemtoReg = 1

RegWrite

S4: MemWriteback

MC5423.59


• Diagrama de transição de estados para R-type

IorD = 0

AluSrcA = 0

ALUSrcB = 01

ALUOp = 00

PCSrc = 0

IRWrite

PCWrite

ALUSrcA = 1

ALUSrcB = 10

ALUOp = 00

IorD = 1

RegDst = 1

MemtoReg = 0

RegWrite

IorD = 1

MemWrite

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 10

Reset

S0: Fetch

S2: MemAdr

S1: Decode


S6: Execute

S7: ALU

Writeback

Op = LW

or

Op = SW

Op = R-type

Op = LW

Op = SW

RegDst = 0

MemtoReg = 1

RegWrite

S4: Mem

Writeback

MC5423.60


• Diagrama de transição de estados para beq

IorD = 0

AluSrcA = 0ALUSrcB = 01ALUOp = 00

PCSrc = 0IRWritePCWrite

ALUSrcA = 0ALUSrcB = 11

ALUOp = 00

ALUSrcA = 1


IorD = 1RegDst = 1

MemtoReg = 0RegWrite

IorD = 1MemWrite

ALUSrcA = 1



ALUOp = 01PCSrc = 1

Branch

Reset

S0: Fetch

S2: MemAdr

S1: Decode


S6: Execute

S7: ALUWriteback

S8: Branch

Op = LWor

Op = SW

Op = R-type

Op = BEQ

Op = LW

Op = SW


RegWrite

S4: MemWriteback

MC5423.61


• FSM de ControleIorD = 0

AluSrcA = 0

ALUSrcB = 01

ALUOp = 00

PCSrc = 0

IRWritePCWrite

ALUSrcA = 0

ALUSrcB = 11

ALUOp = 00

ALUSrcA = 1


IorD = 1

RegDst = 1


IorD = 1

MemWrite

ALUSrcA = 1


ALUSrcA = 1

ALUSrcB = 00

ALUOp = 01PCSrc = 1

Branch

Reset

S0: Fetch

S2: MemAdr

S1: Decode


S6: Execute

S7: ALU

Writeback

S8: Branch

Op = LW

or

Op = SW

Op = R-type

Op = BEQ

Op = LW

Op = SW

RegDst = 0


S4: MemWriteback

MC5423.62


• Extendendo a Funcionalidade para addi

SignImm

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1 0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB20:16

15:11

<<2

ALUResult

SrcA

ALUOut

31:26

Re

gD

st

Branch

MemWrite

Me

mto

Reg

ALUSrcA

RegWriteOp

Funct

ControlUnit

Zero

PCSrc

CLK

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

0

1Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

ALUSrcB1:0IRWrite

IorD

PCWrite

PCEn

MC5423.63


• FSM de Controle para addi

IorD = 0

AluSrcA = 0

ALUSrcB = 01ALUOp = 00PCSrc = 0

IRWritePCWrite

ALUSrcA = 0ALUSrcB = 11ALUOp = 00

ALUSrcA = 1


IorD = 1RegDst = 1

MemtoReg = 0

RegWrite

IorD = 1MemWrite

ALUSrcA = 1



ALUOp = 01PCSrc = 1

Branch

Reset

S0: Fetch

S2: MemAdr

S1: Decode


S6: Execute

S7: ALUWriteback

S8: Branch

Op = LW

orOp = SW

Op = R-type

Op = BEQ

Op = LW

Op = SW

RegDst = 0


S4: MemWriteback

ALUSrcA = 1



RegWrite

Op = ADDI

S9: ADDI

Execute

S10: ADDIWriteback

MC5423.64


• Extendendo a Funcionalidade para j

SignImm

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1PC0

1

PC' Instr25:21

20:16

15:0

SrcB20:16

15:11

<<2

ALUResult

SrcA

ALUOut


Zero

PCSrc1:0

CLK

ALUControl2:0

AL

U

WD

WE

CLK

Adr

0

1Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

ALUSrcB1:0

IRWriteIorD PCWrite

PCEn

00

01

10

<<2

25:0 (jump)

31:28

27:0

PCJump

MC5423.65


• FSM de Controle para j

IorD = 0

AluSrcA = 0

ALUSrcB = 01

ALUOp = 00

PCSrc = 00

IRWrite

PCWrite

ALUSrcA = 0

ALUSrcB = 11

ALUOp = 00

ALUSrcA = 1

ALUSrcB = 10

ALUOp = 00

IorD = 1

RegDst = 1

MemtoReg = 0

RegWrite

IorD = 1

MemWrite

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 10

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 01

PCSrc = 01

Branch

Reset

S0: Fetch

S2: MemAdr

S1: Decode


S6: Execute

S7: ALU

Writeback

S8: Branch

Op = LW

or

Op = SW

Op = R-type

Op = BEQ

Op = LW

Op = SW

RegDst = 0

MemtoReg = 1

RegWrite

S4: Mem

Writeback

ALUSrcA = 1

ALUSrcB = 10

ALUOp = 00

RegDst = 0

MemtoReg = 0

RegWrite

Op = ADDI

S9: ADDI

Execute

S10: ADDI

Writeback

PCSrc = 10

PCWrite

Op = J

S11: Jump

MC5423.66


• Desempenho: Quão rápido é o processador?

• Instruções gastam números diferentes de ciclos:– 3 ciclos: beq, j

– 4 ciclos: R-Type, sw, addi

– 5 ciclos: lw

• O CPI deve ser a média ponderada

• SPECINT2000 benchmark: – 25% loads

– 10% stores

– 11% branches

– 2% jumps

– 52% R-type

Average CPI = (0.11 + 0.2)(3) + (0.52 + 0.10)(4) + (0.25)(5) = 4.12

MC5423.67


• Caminho Crítico

Tc = tpcq_PC + tmux + max(tALU + tmux, tmem) + tsetup

SignImm

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1 0

1

PC0

1

PC' Instr25:21

20:16

15:0

5:0

SrcB20:16

15:11

<<2

ALUResult

SrcA

ALUOut

31:26

Re

gD

st

Branch

MemWrite

Mem

toR

eg

ALUSrcA

RegWriteOp

Funct

ControlUnit

Zero

PCSrc

CLK

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

0

1Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

ALUSrcB1:0IRWrite

IorD

PCWrite

PCEn

MC5423.68


30tpcq_PCRegister clock-to-Q

Delay (ps)ParameterElement

20tsetupRegister setup

25tmuxMultiplexer

200tALUALU

250tmemMemory read

150tRFreadRegister file read

20tRFsetupRegister file setup

Tc = tpcq_PC + tmux + max(tALU + tmux, tmem) + tsetup= tpcq_PC + tmux + tmem + tsetup= [30 + 25 + 250 + 20] ps

= 325 ps

MC5423.69


• Para um programa que executa 100 bilhões de instruções em um MIPS multicycle,

• CPI = 4.12

• Tc = 325 ps

Execution Time = (# instructions) × CPI × Tc

= (100 × 109)(4.12)(325 × 10-12)

= 133.9 seconds

• Ele é mais lento do que o MIPS single-cycle (95 segundos). Porque?– Os passos não tem o mesmo tamanho

– Overhead do seqüenciamento de cada passo (tpcq + tsetup= 50 ps)

MC5423.70

Revisão: Processador MIPS Single Cycle

SignImm

CLK

A RD

InstructionMemory

+

4

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1

A RD

DataMemory

WD

WE0

1

PC0

1PC' Instr

25:21

20:16

15:0

5:0

SrcB

20:16

15:11

<<2

+

ALUResult ReadData

WriteData

SrcA

PCPlus4

PCBranch

WriteReg4:0

Result

31:26

RegDst

Branch

MemWrite

MemtoReg

ALUSrc

RegWrite

Op

Funct

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

0

1

25:0 <<2

27:0 31:28

PCJump

Jump

MC5423.71

Revisão: Processador MIPS Multicycle

ImmExt

CLK

ARD

Instr / DataMemory

A1

A3

WD3

RD2

RD1WE3

A2

CLK

Sign Extend

RegisterFile

0

1

0

1PC0

1

PC' Instr25:21

20:16

15:0

SrcB20:16

15:11

<<2

ALUResult

SrcA

ALUOut

Zero

CLK

AL

U

WD

WE

CLK

Adr

0

1Data

CLK

CLK

A

B00

01

10

11

4

CLK

ENEN

00

01

10

<<2

25:0 (Addr)

31:28

27:0

PCJump

5:0

31:26

Branch

MemWrite

ALUSrcA

RegWriteOp

Funct

ControlUnit

PCSrc

CLK

ALUControl2:0

ALUSrcB1:0IRWrite

IorD

PCWrite

PCEn

Re

gD

st

Me

mto

Re

g

Documents

mc542 A 03 2s07 - Instituto de Computaçãoducatte/mc542/Slides/mc... · “COD”- (Capítulo) MC542 3.3 Micro-Arquitetura • Micro-Arquitetura – Introdução – Recursos –