7/26/2019 MCS-51 Instructions Set
1/17
PPENDIX B
INSTRUCTION SET
SUMM RY
This appendix contains two tables: the first identifies all of
the
8051
s instructions
in
alphabetical order; the second table lists the instructions
according to theirhex -
decimal opcodes and lists the assembly language instructions
that produced that
opcode. .
The alphabetical listing also includes documentation of the bit
pattern, flags
affected, number of
machine cycles per execution and a description of the
instruc-
tions operation and function. The list below defines the
conventions used to identify
operation and bit patterns.
I
A
AB
B
it address
page address
relative offset
C
code address
data
data address
DPTR
PC
Rr
SP
high
low
i-j
.n
aaa aaaaaaaa
bbbbbbbb
dddddddd
' '
r
orrrr
AND
NOT
OR
XOR
+
X)
X))
Abbreviations and Notations Used
Accumulator
Register Pair
Multiplication Register
8051
bit address
11-bit code address with in
2K
page
S-bit
2
s complement offset
Carry Flag
Absolute code address
Immediate data
On-chip 8-bit RAM address
Data pointer
Program Counter
Register
r=0-7)
Stack po inter
High order byte
Low order byte
Bits i through j
Bit n
Absolute page address encoded in instruction and operand
byte
Bit address encoded in operand byte
Immediate data encoded in operand byte
One byte of a 16-bit address encoded in operand byte
Data address encoded
in
operand byte
Relative offset encoded in operand byte
Register identifier encoded in operand byte
Logical AND
Logical complement
Logical OR
Logical exclusive OR
Plus
Minus
Divide
Multiply
The contents
o
X
The memory location addressed by Xl The contents o X)
Is equal to
Is not equal to
Is less than
Is greater than
Is replaced by
B-1
