MELJUN CORTES HANDOUTS_Shift Register and Counter

8/8/2019 MELJUN CORTES HANDOUTS_Shift Register and Counter

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Shift Register andCounter

LogicDesignand Switching

* Property of STI

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Master clock generator synchronizes all

subsystems of a sequential circuit

Load ControlInput

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Load control input using the input X1

the figure shows how a logic 1 at the LOAD will

allow the input X 1 to be processed bysubsystem A during each clock transition

Load ControlInput

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Load control input using the clock and the

associated timing diagram

LOAD

the control signal that will determine whether

the subsystem where the CLOCK is connected

to needs to function

Load ControlInput

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Register

a flip-flop structure that handles multiple bits of

data at any one time

called a 4-bit parallel register or buffer

register

used in most computers as high-speed

temporary data storage

Detailed implementation using flip-flops

Register andShift Registers

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schematic symbol

alternative manner of representing theimplementation

another way of drawing the register using the

same set of flip-flops but written horizontally

simplifies the correspondence between the flip-flop’s outputs and the way the output is written

from the least significant bit (LSB) to the mostsignificant bit (MSB)


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the LOAD input dictates when the register may

allow data from its inputs to be transferred andstored

Parallel Register with Load Control

Parallel/buffer register with load control input

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shows how optional inputs of flip-flops may be

used

inputs: CLEAR and PRESET

modifies the state of the associated flip-flopinstantaneously


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capable of shifting or rotating the binary

information stored in the register

has the capability of shifting stored bits to the

left or to the right for every clock pulse

used in microcomputerserial communications

to transfer information

A simple shift-left and shift-right register using D

flip-flops

Shift Register

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Summary of the input and output of the shift

register:

Initial state Q = 0000

1st rising edge: Q = 0001 SERIAL IN = 1 SERIAL OUT = 0

2nd rising edge: Q = 0011 SERIAL IN = 1 SERIAL OUT = 0

3rd rising edge: Q = 0111 SERIAL IN = 1 SERIAL OUT = 0

4th rising edge: Q = 1111 SERIAL IN = 1 SERIAL OUT = 1Successive rising edges: Q = 1111 SERIAL IN = 1 SERIAL OUT = 1

when the SERIAL IN=0, the output of the register:


1st rising edge: Q = 1110 SERIAL IN = 0 SERIAL OUT = 1

2nd rising edge: Q = 1100 SERIAL IN = 0 SERIAL OUT = 1

3rd rising edge: Q = 1000 SERIAL IN = 0 SERIAL OUT = 1

4th rising edge: Q = 0000 SERIAL IN = 0 SERIAL OUT = 0

Successive rising edges: Q = 0000 SERIAL IN = 0 SERIAL OUT = 0

Serial Loading

the method of storing a word of information

Shift Register

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Example 1:

Get the output of the following shift register

after with the following conditions:

(a) shift-left, Q=0000, SERIAL IN sequence is

0,0,0,1,0,1,1; after 7 cycles

(b) shift-left, Q=00001111, SERIAL IN alternating 0and 1; after 10 cycles

Solution:

(a) initial Q = 0000

cycle 1 Q = 0000 SERIAL IN = 0







Shift Register

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When the stored data in the register is Q =1111

and SERIAL IN= at all times, the output

will be:


1st rising edge: Q = 0111 SERIAL IN = 0

2nd rising edge: Q = 0011 SERIAL IN = 0

3rd rising edge: Q = 0001 SERIAL IN = 0

4th rising edge: Q = 0000 SERIAL IN = 0

Successive rising edges: Q = 0000 SERIAL IN = 0

Shift Register

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Solution (cont.):

(b) initial Q = 00001111










cycle 10 Q =01010101 SERIAL IN = 1

Shift Register

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Example 2:

Design an alternative implementation of the

shift-left register using JK flip-flops.

Solution:

The basic operation of the 4-bit shift (left)

register that is made using D flip-flops is as

follows:

1. D0 takes in new value from SERIAL IN

2. D1 takes old value of D0; D2 takes D3; etc.

JK flip-flop’s function table:

Shift Register

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gates and feedback are also used to allow for

increased control over the operation of the shiftregister

Shift register with load control input

Shift Registerswith Load Control

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A 4-bit shift-left register using JK flip-flops

Shift Register

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are essentially registers that go through a

sequence of states whenever input pulses are

applied

can be used to measure time or frequency (and

period)

handle binary numbers and are called binary

counters

Two types of counters:

Synchronous

the flip-flops are timed using a common clockpulse

Asynchronous

each of the outputs of the flip-flops is used to

trigger the other flip-flops

Counters

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a simple type of counter that is usually

implemented with T flip-flops or JK flip-flops

the inputs of the CLK are derived from theoutputs of the flip-flops used

A 3-bit ripple counter using JK flip-flops

A ripple counter using JK flip-flops:

1. The CLK is triggered during high-to-low logic

transitions.

2. The flip-flop that corresponds to the LSB is the

JK flip-flop that is directly connected to theinput. Each subsequent flip-flop corresponds to

a higher bit.

3. Since the inputs J and K of all the flip-flops are

tied together, each flip-flop will merely toggle

(negate its input) when triggered.

Ripple Counter

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Timing diagram of the ripple counter

Ripple counter counting sequence

Ripple Counter

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A 3-bit ripple counter using T flip-flops

This figure shows how some authors want to

present it so that the outputs are read from the

MSB to the LSB.

Ripple Counter

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Ring counter with pre-load pulse

resembles the shift register using D flip-flops

with the difference that the output from the MSBis fed back0 to the LSB input

Ring Counter

the action of going back to the beginning

SynchronousCounters

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Sequence of states

SynchronousCounters

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Step 2: Simplify using K-map method (cont.)

SynchronousCounters

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* Property of STI

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Using the D flip-flops to get the state

equation directly from the state table,

follow the steps below:

Step 1: Get the sum of minterms expression

DQ2 (Q2, Q1, Q0 ) = S(3, 4, 5, 6)

DQ1 (Q2, Q1, Q0 ) = S(1, 2, 5, 6)

DQ0 (Q2, Q1, Q0 ) = S(0, 2, 4, 6)

Step 2: Simplify using K-map method

SynchronousCounters

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The simplified equation:

DQ2 = Q2’Q1Q0 + Q2Q1’ + Q2Q0’

DQ1 = Q1’Q0 + Q1Q0’

DQ0 = Q0’

Step 3: Draw the logic diagram

SynchronousCounters

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Partial state table alongside excitation table

SynchronousCounters

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MELJUN CORTES HANDOUTS_Shift Register and Counter