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NIT Warangal
Amit Kumar Karna (4403)
Devender Budhwar (4411)
Dinesh Kumar (4412)
NIT Warangal
Special thanks to,
Mr. P. Murlidhar
Faculty, Department of E.C.E., NIT Warangal
ACKNOWLEDGEMENT
AGENDA
Introduction
Approach
VHDL implementation
RTL Viewer
Simulation results
Conclusion
INTRODUCTION
An MMU is a controller that allows a common resource memory to be shared by two or more processors depending on various input control signals.
INTRODUCTION…
Problem statement:Three processors are required to share a
synchronous RAM of size 1024*16.The address bus is 10 bits wide and the data bus is 16 bits wide. There is a r/w’ signal which allows the processors to read data from the memory or write data into the memory. The controller is supposed to control access to the common memory depending on the request signals received by the three processors depending on certain algorithms.
Requirements
Synchronous RAM
Address and Data Bus Multiplexer
AGENDA
Introduction
Approach
VHDL implementation
RTL Viewer
Simulation results
Conclusion
PRIORITY INTERRUPT ALGORITHM
Each processor is assigned a priority and depending on the priority a CPU is given access. When a lower priority processor is active and the controller receives the request signal from a higher priority processor, the latter is given access until its job is finished after which the lower priority processor is given access.
Nested interrupts should be allowed.
PRIORITY INTERRUPTstate diagram
AGENDA
Introduction
Approach
VHDL implementation
RTL Viewer
Simulation results
Conclusion
VHDL
VHSIC Hardware Description Language.
Common language for designers.
High level language.
Simulation synthesis and analysis tools are available.
Softwares: Quartus-II/Xlinix
DESIGN Unit Names
EntityMeaningful name describing the purpose of the circuit.
ArchitectureAccording to the modeling style used (i.e., Behavioral, Procedural, Dataflow, or Structural) or to some specific architecture property.
ConfigurationName of the corresponding entity with suffix "Cfg“.
PackageName of the design (i.e., top-level entity) with suffix "Pkg“.
Testbench (entity, architecture, package)Name of corresponding entity with suffix "Tb“.
Library (package)Library name with suffix "Lib".
FPGA
Benefits of using FPGAProgrammed by user at their site using programming hardware.Can implement tens of thousands of gates on logic on a single IC.Can be programmed many times.Short development time.Low cost.FPGA kit in lab: EP1C6Q240C8
Hierarchy ‘n’ fpga occupancy
COMPONENTS:-• Synchronous RAM• Address and Data Bus Multiplexer
Project navigator
AGENDA
Introduction
Approach
VHDL implementation
RTL Viewer
Simulation results
Conclusion
MMU- Entity
MAIN – RTL VIEW
MAIN – TECHNOLOGY VIEW
c lk
data_out_mux[0]~ 688
data_out_mux[1]~ 689
data_out_mux[2]~ 690
data_out_mux[3]~ 691
data_out_mux[4]~ 692
data_out_mux[5]~ 693
data_out_mux[6]~ 694
data_out_mux[7]~ 695
data_out_mux[8]~ 696
data_out_mux[9]~ 697
data_out_mux[10]~ 698
data_out_mux[11]~ 699
data_out_mux[12]~ 700
data_out_mux[13]~ 701
data_out_mux[14]~ 702
data_out_mux[15]~ 703
M ux0~ 131
M ux1~ 132
M ux2~ 132
M ux3~ 132
M ux4~ 132
M ux5~ 132
M ux6~ 132
M ux7~ 132
M ux8~ 132
M ux9~ 132
rw
q _b[0]
q _b[1]
q _b[2]
q _b[3]
q _b[4]
q _b[5]
q _b[6]
q _b[7]
q _b[8]
q _b[9]
q _b[10]
q _b[11]
q _b[12]
q _b[13]
q _b[14]
q _b[15]
addA[0]
addA[1]
addA[2]
addA[3]
addA[4]
addA[5]
addA[6]
addA[7]
addA[8]
addA[9]
addB[0]
addB[1]
addB[2]
addB[3]
addB[4]
addB[5]
addB[6]
addB[7]
addB[8]
addB[9]
addC [0]
addC [1]
addC [2]
addC [3]
addC [4]
addC [5]
addC [6]
addC [7]
addC [8]
addC [9]
dataA[0]
dataA[1]
dataA[2]
dataA[3]
dataA[4]
dataA[5]
dataA[6]
dataA[7]
dataA[8]
dataA[9]
dataA[10]
dataA[11]
dataA[12]
dataA[13]
dataA[14]
dataA[15]
dataB[0]
dataB[1]
dataB[2]
dataB[3]
dataB[4]
dataB[5]
dataB[6]
dataB[7]
dataB[8]
dataB[9]
dataB[10]
dataB[11]
dataB[12]
dataB[13]
dataB[14]
dataB[15]
dataC [0]
dataC [1]
dataC [2]
dataC [3]
dataC [4]
dataC [5]
dataC [6]
dataC [7]
dataC [8]
dataC [9]
dataC [10]
dataC [11]
dataC [12]
dataC [13]
dataC [14]
dataC [15]
penableA
penableB
penableC
data_out_mux[0]~ 688
data_out_mux[1]~ 689
data_out_mux[2]~ 690
data_out_mux[3]~ 691
data_out_mux[4]~ 692
data_out_mux[5]~ 693
data_out_mux[6]~ 694
data_out_mux[7]~ 695
data_out_mux[8]~ 696
data_out_mux[9]~ 697
data_out_mux[10]~ 698
data_out_mux[11]~ 699
data_out_mux[12]~ 700
data_out_mux[13]~ 701
data_out_mux[14]~ 702
data_out_mux[15]~ 703
M ux0~ 131
M ux1~ 132
M ux2~ 132
M ux3~ 132
M ux4~ 132
M ux5~ 132
M ux6~ 132
M ux7~ 132
M ux8~ 132
M ux9~ 132
M ux10~ 139
M ux11~ 139
M ux12~ 139
M ux13~ 139
M ux14~ 139
M ux15~ 139
M ux16~ 139
M ux17~ 139
M ux18~ 139
M ux19~ 139
M ux20~ 139
M ux21~ 139
M ux22~ 139
M ux23~ 139
M ux24~ 139
M ux25~ 139
M ux26~ 180
! AC LR
C LK
D AT AA
D AT AB
D AT AC
D AT AD
R EGO U T
LC ELL (0100)
! AC LR
C LK
D AT AA
D AT AB
D AT AC
D AT AD
R EG OU T
LC ELL ( F F F E)
! AC LR
C LK
D AT AA
D AT AC
R EG OU T
LC ELL ( 5050)
D AT AB
D AT ADC OM BOU T
LC ELL ( 0033)
D AT AA
D AT AC
D AT AD
C O M BOU T
LC ELL ( AAF 0)
! AC LR
C LK
D AT AB
D AT AD
SYN C H _D AT A
C OM BO U T
R EGO U T
LC ELL ( C F C 0)
D AT AA
D AT AB
D AT AC
D AT AD
C OM BOU T
LC ELL (F E00)
D AT AA
D AT AB
D AT AC
D AT AD
C OM BOU T
LC ELL ( 5455)
D AT AA
D AT AC
D AT AD
C O M BOU T
LC ELL ( F F A5)
D AT AA
D AT AB
D AT AC
D AT AD
C OM BOU T
LC ELL ( 1044)
D AT AA
D AT AB
D AT AC
D AT AD
C OM BOU T
LC ELL (32F F )
D AT AA
D AT AB
D AT AC
D AT AD
C O M BOU T
LC ELL ( 0100)
D AT AA
D AT AC
D AT AD
C O M BO U T
LC ELL (F A0A)
D AT AA
D AT AB
D AT AD
C O M BO U T
LC ELL ( 5544)
D AT AB
D AT AC
D AT AD
C O M BO U T
LC ELL ( 0F 0C )
D AT AA
D AT AB
D AT AD
C O M BO U T
LC ELL ( 3322)
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
D AT AIN
! O EPAD OU T
O U T PU T
m u l ti p le x:m u l t
c u r r_ s ta te .s 4
c u r r_ s ta te .s 1
c u r r_ s ta te .s 3
p re s e n t~ 1 4
c o m b ~ 3 1 3
c u r r_ s ta te .s 2
c o m b ~ 3 1 5
c o m b ~ 3 1 6
c o m b ~ 3 1 7
c o m b ~ 3 1 8
c o m b ~ 3 1 9c o m b ~ 3 2 0
rw
p e n a b le B
p e n a b le C
p e n a b le A
p re s e n t[0 ]
p re s e n t[1 ]
p re s e n t[2 ]
d a ta _ w r_ o u t[0 ]
d a ta _ w r_ o u t[1 ]
d a ta _ w r_ o u t[3 ]
d a ta _ w r_ o u t[4 ]
d a ta _ w r_ o u t[5 ]
d a ta _ w r_ o u t[6 ]
d a ta _ w r_ o u t[7 ]
d a ta _ w r_ o u t[8 ]
d a ta _ w r_ o u t[9 ]
d a ta _ w r_ o u t[1 0 ]
d a ta _ w r_ o u t[1 1 ]
d a ta _ w r_ o u t[1 2 ]
d a ta _ w r_ o u t[1 3 ]
d a ta _ w r_ o u t[1 4 ]
d a ta _ w r_ o u t[1 5 ]
s ta r t
c l k
d a ta C [0 ]
d a ta B [0 ]
d a ta A [0 ]
a d d C [0 ]
a d d B [0 ]
a d d A [0 ]
a d d C [1 ]
a d d B [1 ]
a d d A [1 ]
a d d C [2 ]
a d d B [2 ]
a d d A [2 ]
a d d C [3 ]
a d d B [3 ]
a d d A [3 ]
a d d C [4 ]
a d d B [4 ]
a d d A [4 ]
a d d C [5 ]
a d d B [5 ]
a d d A [5 ]
a d d C [6 ]
a d d B [6 ]
a d d A [6 ]
a d d C [7 ]
a d d B [7 ]
a d d A [7 ]
a d d C [8 ]
a d d B [8 ]
a d d A [8 ]
a d d C [9 ]
a d d B [9 ]
a d d A [9 ]
d a ta C [1 ]
d a ta B [1 ]
d a ta A [1 ]
d a ta C [2 ]
d a ta B [2 ]
d a ta A [2 ]
d a ta C [3 ]
d a ta B [3 ]
d a ta A [3 ]
d a ta C [4 ]
d a ta B [4 ]
d a ta A [4 ]
d a ta C [5 ]
d a ta B [5 ]
d a ta A [5 ]
d a ta C [6 ]
d a ta B [6 ]
d a ta A [6 ]
d a ta C [7 ]
d a ta A [7 ]
d a ta C [8 ]
d a ta B [8 ]
d a ta A [8 ]
d a ta C [9 ]
d a ta B [9 ]
d a ta A [9 ]
d a ta C [1 0 ]
d a ta B [1 0 ]
d a ta A [1 0 ]
d a ta C [1 1 ]
d a ta B [1 1 ]
d a ta A [1 1 ]
d a ta C [1 2 ]
d a ta B [1 2 ]
d a ta A [1 2 ]
d a ta C [1 3 ]
d a ta B [1 3 ]
d a ta A [1 3 ]
d a ta C [1 4 ]
d a ta A [1 4 ]
d a ta C [1 5 ]
d a ta B [1 5 ]
d a ta A [1 5 ]
rw A
rw Brw C
re q C
re q Bre q A
re s e t
d a ta _ rd _ o u t[0 ]d a ta _ rd _ o u t[1 ]d a ta _ rd _ o u t[2 ]d a ta _ rd _ o u t[3 ]d a ta _ rd _ o u t[4 ]d a ta _ rd _ o u t[5 ]d a ta _ rd _ o u t[6 ]d a ta _ rd _ o u t[7 ]d a ta _ rd _ o u t[8 ]d a ta _ rd _ o u t[9 ]d a ta _ rd _ o u t[1 0 ]d a ta _ rd _ o u t[1 1 ]d a ta _ rd _ o u t[1 2 ]d a ta _ rd _ o u t[1 3 ]d a ta _ rd _ o u t[1 4 ]d a ta _ rd _ o u t[1 5 ]
p re s e n t[0 ]
p re s e n t[1 ]
p re s e n t[2 ]
d a ta _ w r_ o u t[0 ]
d a ta _ w r_ o u t[1 ]
d a ta _ w r_ o u t[2 ]
d a ta _ w r_ o u t[3 ]
d a ta _ w r_ o u t[4 ]
d a ta _ w r_ o u t[5 ]
d a ta _ w r_ o u t[6 ]
d a ta _ w r_ o u t[7 ]
d a ta _ w r_ o u t[8 ]
d a ta _ w r_ o u t[9 ]
d a ta _ w r_ o u t[1 0 ]
d a ta _ w r_ o u t[1 1 ]
d a ta _ w r_ o u t[1 2 ]
d a ta _ w r_ o u t[1 3 ]
d a ta _ w r_ o u t[1 4 ]
d a ta _ w r_ o u t[1 5 ]
m e m o ry:m e m
d a ta _ w r_ o u t[2 ]
d a ta B [1 4 ]
d a ta B [7 ]
MAIN - FLOW RESULT
Memory-entity
MEMORY – RTL VIEW
MEMORY – Technology view
Memory flow summary
Mux entity
Mux flow diagram
Mux rtl
MuX – tech view
AGENDA
Introduction
Approach
VHDL implementation
RTL Viewer
Simulation results
Conclusion
SIMULATION STATE DIAGRAM
CONDITIONS GENERATED BY SIMULATION
Memory simulation
Mux simulation
MMU-SIMULATION
AGENDA
Introduction
Approach
VHDL implementation
RTL Viewer
Simulation results
Conclusion
CONCLUSION
Memory can be simultaneously serviced to multi processes.
Being an Interrupt service procedure, time of processor is managed efficiently.
FPGA/VHDL combination is a very powerful design tool.
• Versatile, Adaptable, Efficient, Economic
The given algorithm can be used to implement process scheduling.
REFERENCES
A VHDL Primer, 3rd edition : J. Bhasker
Computer Organization and Architecture:William Stallings
Thanks"It's not that i am genius,
but i stay a little longer
with problems" - Einstein.