10
Memory Memory Organization and Organization and Interfacing Interfacing CSE 2312 CSE 2312 Maher Al-Khaiyat Maher Al-Khaiyat

Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

Embed Size (px)

Citation preview

Page 1: Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

Memory Organization Memory Organization and Interfacingand Interfacing

CSE 2312CSE 2312

Maher Al-KhaiyatMaher Al-Khaiyat

Page 2: Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

Semiconductor MemorySemiconductor Memory

CapacityCapacity• Kbits (Kilobits)Kbits (Kilobits)• Mbits (Megabits)Mbits (Megabits)

OrganizationOrganization• Number of locations => Number of address Number of locations => Number of address

lineslines• Size of a location => Number of data linesSize of a location => Number of data lines

Page 3: Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

Semiconductor Memory (cont’d) Semiconductor Memory (cont’d)

SpeedSpeed• Access timeAccess time

VolatilityVolatility

ProgrammabilityProgrammability

Page 4: Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

Memory OrganizationMemory Organization

yx 2Number of locations

Number of address lines

Number of data lines

Page 5: Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

Nonvolatile MemoryNonvolatile Memory

Read-Only Memory (ROM)Read-Only Memory (ROM) Programming or BurningProgramming or Burning

• PROM; one-time programmablePROM; one-time programmable• EPROM; erasable using UV radiationEPROM; erasable using UV radiation• EEPROM; electrically erasableEEPROM; electrically erasable• Flash ROM; erasable in a flash (fast Flash ROM; erasable in a flash (fast

time)time)• Mask ROM; mask technologyMask ROM; mask technology

Page 6: Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

Volatile MemoryVolatile Memory

Random Access Memory (RAM)Random Access Memory (RAM) TypesTypes

• Static RAM (SRAM)Static RAM (SRAM) does not require refreshingdoes not require refreshing up to four transistors per cellup to four transistors per cell

• Dynamic RAM (DRAM)Dynamic RAM (DRAM) requires refreshingrequires refreshing one transistor (capacitor) per cellone transistor (capacitor) per cell

Page 7: Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

Address DecodingAddress Decoding

32Kx8

A0

A14

OE WR

MEMR MEMW

CS

D7 D0

A15A16

A17A18

A19

00000000 10001000 00000000 00000000 00000000

00000000 11111111 11111111 11111111 11111111

A0A19

Range of addresses 08000h to 0FFFFh

… … …

Page 8: Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

Conventional MemoryConventional Memory

640K of RAM640K of RAM

ROM 256K

VDR 128K

RAM 640K

00000h

9FFFFhA0000h

BFFFFhC0000h

FFFFFh

Conventional memory•MS-DOS OS•Utilities•Applications•Etc…

003FFh

004FFh

Interrupt vector table

BIOS temp data

Page 9: Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

BIOS Data AreaBIOS Data AreaStart AddressStart Address End AddressEnd Address # Bytes# Bytes DescriptionDescription

0000:00000000:0000 0000:03FF0000:03FF 10241024 Interrupt tableInterrupt table

0000:04000000:0400 0000:04010000:0401 22 Port address COM1Port address COM1

…… …… …… ……

0000:04080000:0408 0000:04090000:0409 22 Port address LPT1Port address LPT1

…….. …….. …… ……

0000:04100000:0410 0000:04110000:0411 22 List of hardwareList of hardware

0000:004120000:00412 0000:04120000:0412 11 Initialization flagInitialization flag

0000:04130000:0413 0000:04140000:0414 22 Memory size (KB)Memory size (KB)

…… …… …… ……

…… …… …… ……

Page 10: Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

DRAM Memory BanksDRAM Memory Banks

64K x 4 64K x 4 64K x 1Bank 3

64K x 4 64K x 4 64K x 1Bank 2

256K x 4 256K x 4 256K x 1Bank 1

256K x 4 256K x 4 256K x 1Bank 0

Example configuration of 640KB RAM