Memory Problems

Prof. Sin-Min Lee

Department of Mathematics and Computer Sciences

Example: Suppose we have a 40-bit virtual address separated into an x-bit virtual page number and (40 - x) -bit page offset. Using basic single page table scheme, what is the maximum number of entries in the page table and what is the size of each page (in bytes)?

ANSWER: 2^x page table entries

2^(40-x) bytes per page

one-level translation for a virtual address space of 5 bits implemented on a 4 bit physical memory.  The memory is byte addressable.  We've divided the space into 4 byte pages.  The page table resides entirely in physical memory.

.  The physical memory has no pages allocated within it's frames.  Notice that all the page table entries have zeroes in their valid bits.

Now after an access, by software to memory location 01001, physical memory has the following configuration.  Notice that the page table entry for page 2 now contains a valid mapping -- the page has been allocated in frame 3.  A page fault was taken for this translation.

Now after an access, by software to memory location 01001, physical memory has the configuration.  The page table entry for page 2 now contains a valid mapping -- the page has been allocated in frame 3.  A page fault was taken for this translation.

Next, an access is made to memory location 10110.  This access fall in page 5, therefore page 5 is now allocated into frame 2.  Another page fault is taken here.

Now, any reference that maps to virtual page 2 will be translated to physical frame 3, any reference that maps to virtual page 5 will be translated to physical frame 2.

Some time later, say a reference to 00011 is made.   Now, one of the two frames must be selected so that page 0 can be brought in.  Say, we choose page 2 for replacement (perhaps because it was least recently used). 

We choose page 2 for replacement (perhaps because it was least recently used).  Then we must write back the page, if it's dirty, and invalidate its pte.  Then we load in page 0, and update its page table entry.  After the dust settles, the memory looks as above.

Example 1. If the access time for main memory is 120 nanoseconds and the access time for associative memory is 15 nanoseconds and the hit ratio is 85 percent, then

access time = .85 x (15 + 120) + (1 - .85) x (15 + 120 +120)

= 153 nanoseconds.

Since the simple access time is 120 nanoseconds, this represents a slowdown of 27 percent compared to the simple main memory access.

The advantages and disadvantages of VM

     The cache efficiency is characterized by a Cache hit ratio H. If the latency of the cache is , and the latency for main memory is , then the effective (average) latency of a memory architecture with cache is given by the formula:

Example: A virtual memory has a page size of 1024 words, eight virtual pages, and four physical page frames. The page table is as follows:

a. List the virtual addresses that will cause page faults.

b. What are the physical addresses for virtual addresses 0, 3728, 1023, 1024, 1025, 7800, and 4096?

For the following page reference string, please show the number of page faults for a memory of size 3 page frames,, using FIFO replacement. Please show your work.    7 6 5 4 7 6 8 7 6 5 4 8

Answer: FIFO(3) page access: 7 6 5 4 7 6 8 7 6 5 4 8

hit or miss: m m m m m m m h h m m h

memory content: 7 7 7 4 4 4 8 8 8 8 8 8

6 6 6 7 7 7 7 7 5 5 5

5 5 5 6 6 6 6 6 4 4

9 page faults