MEMORY STICK™ INTERCONNECT EXTENDER CHIPSET WITH LVDS ... · PDF filememory stick™ interconnect extender chipset with lvds sn65lvdt14—one driver plus four receivers ... test

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FEATURES APPLICATIONS
DESCRIPTION
SN65LVDT14 LOGIC DIAGRAM(POSITIVE LOGIC)
SN65LVDT41 LOGIC DIAGRAM(POSITIVE LOGIC)
1Y
1Z1D
1A
1B
5Y
5Z
1R
5D
2Y
2Z2D
2A
2B2R
3Y
3Z3D
3A
3B3R
4Y
4Z4D
4A
4B4R
5A
5B5R
SN65LVDT14SN65LVDT41
SLLS530BAPRIL 2002REVISED FEBRUARY 2006
MEMORY STICK INTERCONNECT EXTENDER CHIPSET WITH LVDSSN65LVDT14ONE DRIVER PLUS FOUR RECEIVERSSN65LVDT41FOUR DRIVERS PLUS ONE RECEIVER
Memory Stick Interface Extensions With Long Integrated 110- Nominal Receiver LineInterconnects Between Host and MemoryTermination ResistorStick Operates From a Single 3.3-V Supply
Serial Peripheral Interface (SPI) Interface Greater Than 125 Mbps Data Rate Extension to Allow Long Interconnects Flow-Through Pin-Out Between Master and Slave LVTTL Compatible Logic I/Os MultiMediaCard Interface in SPI Mode
General-Purpose Asymmetric Bidirectional ESD Protection On Bus Pins Exceeds 16 kVCommunication Meets or Exceeds the Requirements of
ANSI/TIA/EIA-644A Standard for LVDS 20-Pin PW Thin Shrink Small-Outline Package
With 26-Mil Terminal Pitch
The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. It isdesigned to be used at the Memory Stick end of an LVDS based Memory Stick interface extension.
The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package.It is designed to be used at the host end of an LVDS based Memory Stick interface extension.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Serial Peripheral Interface is a trademark of Motorola.MultiMediaCard is a trademark of MultiMediaCard Association.Memory Stick is a trademark of Sony.
PRODUCTION DATA information is current as of publication date. Copyright 20022006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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TYPICAL MEMORY STICK INTERFACE EXTENSION
1Y
1Z1D
1A
1B
5Y
5Z
1R
5D
2Y
2Z2D 2A
2B2R
3Y
3Z3D 3A
3B3R
4Y
4Z4D 4A
4B4R
5A
5B5R
SCLK
BS
DIR
SD1
SD2
CBT
SCLK
BS
SDIO
MemoryStick
CBT
SCLK
BS
SDIO
DIR
MemoryStickHost
Controller
SN65LVDT41 SN65LVDT14
ABSOLUTE MAXIMUM RATINGS
PACKAGE DISSIPATION RATINGS
SN65LVDT14SN65LVDT41SLLS530BAPRIL 2002REVISED FEBRUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
over operating free-air temperature range unless otherwise noted (1)
SN65LVDT14, UNITSN65LVDT41
Supply voltage range (2) VCC -0.5 to 4 V
D or R -0.5 to 6 VInput voltage range
A, B, Y, or Z -0.5 to 4 V
Human body model (3), A, B, Y, Z, and GND 16 KV
Electrostatic discharge Human body model (3), all pins 8 KV
Charged device model (4), all pins 500 V
Continuous total power dissipation See Dissipation Rating Table
Storage temperature range -65 to 150 C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages are with respect to network ground terminal.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
TA

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RECOMMENDED OPERATING CONDITIONS
2.4 VID
2
VID
2
|VID| Differential Input Voltage V
1
00.1 0.3
2
1.5
0.5
0.2 0.4 0.6
2.5
0 0.5
Max at VCC = 3 V
C
om
mo
n-M
od
e In
pu
t Vo
ltag
e
VV
IC
Max at VCC > 3.15 V
Minimum
RECEIVER ELECTRICAL CHARACTERISTICS
MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
|VID| Magnitude of differential input voltage 0.1 0.6 V
VVIC Common-mode input voltage, See Figure 1
VCC - 0.8 V
TA Operating free-air temperature -40 85 C
Figure 1. VIC vs VID and VCC
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VITH+ Positive-going differential input voltage threshold 100See Figure 2 and Table 1 mV
VITH- Negative-going differential input voltage threshold -100
VOH High-level output voltage IOH = -8 mA 2.4 V
VOL Low-level output voltage IOL = 8 mA 0.4 V
VI = 0 V and VI = 2.4 V,II Input current (A or B inputs) 40 Aother input open
II(OFF) Power-off input current (A or B inputs) VCC = 0 V, VI = 2.4 V 40 A
Ci Input capacitance, A or B input to GND VI = A sin 2ft + CV 5 pF
Zt Termination impedance VID = 0.4 sin2.5E09 t V 88 132
(1) All typical values are at 25C and with a 3.3-V supply.
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DRIVER ELECTRICAL CHARACTERISTICS
DEVICE ELECTRICAL CHARACTERISTICS
RECEIVER SWITCHING CHARACTERISTICS
SN65LVDT14SN65LVDT41SLLS530BAPRIL 2002REVISED FEBRUARY 2006
|VOD| Differential output voltage magnitude 247 340 454RL = 100 ,See Figure 3 and mVChange in differential output voltage magnitude between|VOD| -50 50Figure 5logic states
VOC(SS) Steady-state common-mode output voltage 1.125 1.375 V
Change in steady-state common-mode output voltageVOC(SS) See Figure 6 -50 50 mVbetween logic states
VOC(PP) Peak-to-peak common-mode output voltage 50 150 mV
IIH High-level input current VIH = 2 V 20 A
IIL Low-level input current VIL = 0.8 V 10 A
VOY or VOZ = 0 V 24IOS Short-circuit output current mA
VOD = 0 V 12
IO(OFF) Power-off output current VCC = 1.5 V, VO = 2.4 V 1 A
SN65LVDT14 25Driver RL = 100 , Driver VI = 0.8 V or 2 V,ICC Supply current mAReceiver VI = 0.4 VSN65LVDT41 35
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tPLH Propagation delay time, low-to-high-level output 1 2.6 3.8 ns
tPHL Propagation delay time, high-to-low-level output 1 2.6 3.8 ns
tr Output signal rise time 0.15 1.2 ns
tf Output signal fall time CL = 10 pF, See Figure 4 0.15 1.2 ns
tsk(p) Pulse skew (|tPHL - tPLH|) 150 600 ps
tsk(o) Output skew (1) 100 400 ps
tsk(pp) Part-to-part skew (2) 1 ns
(1) tsk(o) is the magnitude of the time difference between the tpLH or tpHL of all the receivers of a single device with all of their inputsconnected together.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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DRIVER SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
VIB
VID
VIAVIC VO
A
B
RVIA VIB2
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tPLH Propagation delay time, low-to-high-level output 0.9 1.7 2.9
tPHL Propagation delay time, high-to-low-level output 0.9 1.6 2.9RL = 100 , CL = 10 pF, nsSee Figure 7tr Differential output signal rise time 0.26 1
tf Differential output signal fall time 0.26 1
tsk(p) Pulse skew (|tPHL - tPLH|) 150 500 psRL = 100 , CL = 10 pF,tsk(o) Output skew (1) 80 150 psSee Figure 7
tsk(pp) Part-to-part skew (2) 1.5 ns
(1) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.(2) tsk(pp) is the magnitude of the difference

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MEMORY STICK™ INTERCONNECT EXTENDER CHIPSET WITH LVDS ... · PDF filememory stick™ interconnect extender chipset with lvds sn65lvdt14—one driver plus four receivers ... test