METRICS:A System Architecture for Design Process Optimization

METRICS:A System Architecture for Design Process Optimization

Andrew B. Kahng and Stefanus Mantik*

UCSD CSE Dept., La Jolla, CA

*UCLA CS Dept., Los Angeles, CA

MotivationsMotivations

How do we improve design productivity ?

Does our design technology / capability yield better productivity than it did last year ?

How do we formally capture best known methods, and how do we identify them in the first place ?

Does our design environment support continuous improvement of the design process ?

Does our design environment support what-if / exploratory design ? Does it have early predictors of success / failure?

Currently, there are no standards or infrastructure for measuring and recording the semiconductor design process

Purpose of METRICSPurpose of METRICS

Standard infrastructure for the collection and the storage of design process information

Standard list of design metrics and process metrics

Analyses and reports that are useful for design process optimization

METRICS allows: Collect, Data-Mine, Measure, Diagnose, then Improve

Related WorksRelated Works

OxSigen LLC (Siemens 97-99)

Enterprise- and project-level metrics (“normalized transistors”) Numetrics Management Systems DPMS

Other in-house data collection systems e.g., TI (DAC 96 BOF)

Web-based design support IPSymphony, WELD, VELA, etc.

E-commerce infrastructure Toolwire, iAxess, etc.

Continuous process improvement

Data mining and visualization

OutlineOutline

Data collection process and potential benefits

METRICS system architecture

METRICS standards

Current implementation

Issues and conclusions

Potential Data Collection/DiagnosesPotential Data Collection/Diagnoses

What happened within the tool as it ran? what was CPU/memory/solution quality? what were the key attributes of the instance? what iterations/branches were made, under what conditions?

What else was occurring in the project? spec revisions, constraint and netlist changes, …

User performs same operation repeatedly with nearly identical inputs tool is not acting as expected solution quality is poor, and knobs are being twiddled

BenefitsBenefits

Benefits for project management accurate resource prediction at any point in design

cycle up front estimates for people, time, technology, EDA

licenses, IP re-use... accurate project post-mortems

everything tracked - tools, flows, users, notes no “loose”, random data left at project end

management console web-based, status-at-a-glance of tools, designs and

systems at any point in project

Benefits for tool R&D feedback on the tool usage and parameters used improve benchmarking

OutlineOutline

Data collection process and potential benefits

METRICS system architecture

METRICS standards

Current implementation

Issues and conclusions

METRICS System ArchitectureMETRICS System Architecture

Inter/Intra-net

DBMetrics Data Warehouse

WebServer

JavaApplets

DataMining

Reporting

Transmitter Transmitterwrapper

Tool Tool Tool

TransmitterAPI

XML

METRICS PerformanceMETRICS Performance

Transmitter low CPU overhead

multi-threads / processes – non-blocking scheme buffering – reduce number of transmissions

small memory footprint limited buffer size

Reporting web-based

platform and location independent dynamic report generation

always up-to-date

Example ReportsExample Reports

hen 95%

rat 1% bull 2%

donkey 2%

% aborted per machine

% aborted per task

BA 8%

ATPG 22%

synthesis 20%

physical18%

postSyntTA13%

placedTA7%

funcSim7%

LVS 5%

LVS convergencetime

0 100 200 300 400 500 600

LVS

%

88

90

92

94

96

98

100

Current ResultsCurrent Results

CPU_TIME = 12 + 0.027 NUM_CELLS (corr = 0.93)

More plots are accessible at http://xenon.cs.ucla.edu:8080/metrics

OutlineOutline

Data collection process and potential benefits

METRICS system architecture

METRICS standards

Current implementation

Issues and conclusions

METRICS StandardsMETRICS Standards

Standard metrics naming across tools same name same meaning, independent of tool

supplier generic metrics and tool-specific metrics no more ad hoc, incomparable log files

Standard schema for metrics database

Standard middleware for database interface

For complete current lists see:

http://vlsicad.cs.ucla.edu/GSRC/METRICS

Generic and Specific Tool MetricsGeneric and Specific Tool Metrics

tool_name stringtool_version stringtool_vendor stringcompiled_date mm/dd/yyyystart_time hh:mm:ssend_time hh:mm:sstool_user stringhost_name stringhost_id stringcpu_type stringos_name stringos_version stringcpu_time hh:mm:ss

Generic Tool Metricsnum_cells integernum_nets integerlayout_size doublerow_utilization doublewirelength doubleweighted_wl double

num_layers integernum_violations integernum_vias integerwirelength doublewrong-way_wl doublemax_congestion double

Placement Tool Metrics

Routing Tool Metrics

Partial list of metrics now being collected in Oracle8i

OutlineOutline

Data collection process and potential benefits

METRICS system architecture

METRICS standards

Current implementation

Issues and conclusions

Testbed I: Metricized P&R FlowTestbed I: Metricized P&R Flow

Placed DEF

QP ECO

Legal DEF

CongestionMap

WRoute

Capo Placer

Routed DEF

CongestionAnalysis

Incr. WRoute

Final DEF

METRICS

LEF

DEF

Testbed II: Metricized Cadence SLC FlowTestbed II: Metricized Cadence SLC Flow

DEF

Placed DEF

QP

Pearl

METRICS

QP Opt

CTGen

Incr.

Routed DEF

WRoute

Optimized DEF

LEFGCF,TLF

Clocked DEFConstraints

OutlineOutline

Data collection process and potential benefits

METRICS system architecture

METRICS standards

Current implementation

Issues and conclusions

ConclusionsConclusions

Current status complete prototype of METRICS system with Oracle8i, Java

Servlet, XML parser, and transmittal API library in C++ METRICS wrapper for Cadence and Cadence-UCLA flows,

front-end tools (Ambit BuildGates and NCSim) easiest proof of value: via use of regression suites

Issues for METRICS constituencies to solve security: proprietary and confidential information standardization: flow, terminology, data management, etc. social: “big brother”, collection of social metrics, etc.

Ongoing work with EDA, designer communities to identify tool metrics of interest users: metrics needed for design process insight,

optimization vendors: implementation of the metrics requested, with

standardized naming / semantics

http://vlsicad.cs.ucla.edu/GSRC/METRICS

Status of METRICS SystemStatus of METRICS System

Current working METRICS systems are installed within Intel and Cadence

METRICS system works properly inside a laptop

Flow MetricsFlow Metrics

Tool metrics alone are not enough Design process consists of more than one tools One tool is run multiple times Design quality depends on the design flow and

methodology (the order of the tools and the iteration within the flow)

Flow definition Directed graph G (V,E), V T { S, F }, T { T1, T2, T3,

…, Tn } (a set of tasks), S starting node, F ending node, E { Es1, E11, E12, …, Exy } (a set of edges)

Exy x < y forward path x = y self-loop x > y backward path

Flow ExampleFlow Example

S

T1

T2

T3

T4

F

Optional task

Task sequence: T1, T2, T1, T2, T3, T3, T3, T4, T2, T1, T2, T4

S

T1

T2

F

T1

T2

T3 T3 T3

T4

T2

T1

T2

T4

Flow TrackingFlow Tracking

Run Current FLOW_SEQUENCENo Task T1 T2 T3 T41 T1 1 - - - 12 T2 1 1 - - 1/13 T1 2 - - - 24 T2 2 1 - - 2/15 T3 2 1 1 - 2/1/16 T3 2 1 2 - 2/1/27 T3 2 1 3 - 2/1/38 T4 2 1 3 1 2/1/3/19 T2 2 2 - - 2/210 T1 3 - - - 311 T2 3 1 - - 3/112 T4 3 1 - 1 3/1/0/1

TASK_NOS

T1

T2

F

T1

T2

T3 T3 T3

T4

T2

T1

T2

T4

Task sequence: T1, T2, T1, T2, T3, T3, T3, T4, T2, T1, T2, T4

Multilevel FM Partitioning ExperimentMultilevel FM Partitioning Experiment

Given: initial partitioning solution, CPU budget and instance perturbations (I)

Find: number of parts of incremental partitioning and number of starts

Ti = incremental multilevel FM partitioning Self-loop multistart n number of breakups (I = 1 + 2 + 3 + ... + n)

S T1 FT2 T3 Tn...

Multilevel FM Experiment Flow SetupMultilevel FM Experiment Flow Setup

foreach testcase

foreach I foreach CPUbudget

foreach breakup

Icurrent = IinitialScurrent = Sinitial

for i = 1 to n

Inext = Icurrent + i

run incremental multilevel FM partitioner

on Inext to produce Snext

if CPUcurrent > CPUbudget then break

Icurrent = InextScurrent = Snext

end

Flow ResultsFlow Results

If (27401 < num edges 34826) and (143.09 < cpu time 165.28) and (perturbation delta 0.1) then num_inc_parts = 4 and num_starts = 3

If (27401 < num edges 34826) and (85.27 < cpu time 143.09) and (perturbation delta 0.1) then num_inc_parts = 2 and num_starts = 1

...

Actual CPU Time (secs)

Pre

dict

ed C

PU

Tim

e (s

ecs)

Wireload Model FlowWireload Model Flow

WLM flows for finding the appropriate role of WLM T1 = synthesis & technology mapping T2 = load wireload model (WLM) T3 = pre-placement optimization T4 = placement T5 = post-placement optimization T6 = global routing T7 = final routing T8 = custom WLM generation

Post-placement and pre-placement

area important steps

Choice of WLM depends on the design

ST1

T2

T3

T4

F

T5

T7

T8

T6

Datamining IntegrationDatamining Integration

DatabaseDatamining

Tool(s)

Datamining

Interface

Java

Servlet

Java

Servlet

SQL

SQL

Tables

Tables Tables

Results

ResultsDM

Requests

Inter-/Intranet

Example Applications with DMExample Applications with DM

Parameter sensitivity analysis input parameters that have the most impact on results

Field of use analysis limits at which the tool will break tool sweet spots at which the tool will give best results

Process monitoring identify possible failure in the process (e.g., timing

constraints are too tight, row utilization is too high, etc.)

Resource monitoring analysis of resource demands (e.g., disk space,

memory, etc.)

DM Results: QPlace CPU TimeDM Results: QPlace CPU Time

Actual CPU Time (secs)

Pre

dict

ed C

PU

Tim

e (s

ecs)

If (num nets 7332) then CPU time = 21.9 + 0.0019 num cells + 0.0005 num nets + 0.07 num pads - 0.0002 num fixed cells

If (num overlap layers = 0) and (num cells 71413) and (TD routing option = false) then CPU time = -15.6 + 0.0888 num nets - 0.0559 num cells - 0.0015 num fixed cells - num routing layer

...