MICASDepartment of Electrical Engineering (ESAT)

Update of the “Digital EMC project”

January 19th, 2006

AID–EMC: Low Emission Digital Circuit Design

Junfeng ZhouWim Dehaene

KULeuven ESAT-MICAS

MICASDepartment of Electrical Engineering (ESAT)

Outline

1. Circuit structure

2. Maple simulation

3. Spectre simulation 4. Future work

MICASDepartment of Electrical Engineering (ESAT)

Coupling problem !

Cgs1,2 ≈ Cgd1

∆ VDD_input

∆ Vbias

MICASDepartment of Electrical Engineering (ESAT)

Why new structure ?

1. Simple

2. Driving capability

3. Miller effect on compensation capacitor

4. Cascode device: decrease coupling from VDD_input to VDD provided that Vbias is biased as a low impedance node

MICASDepartment of Electrical Engineering (ESAT)

Stability analysis

Stability as a function of Iload (26.7u A ~ 72m A)Raux=1.852K , Caux=20p

φ≥60°Worst case

MICASDepartment of Electrical Engineering (ESAT)

Maple calculation

[ / ]diA s

dt

[ / ]diA s

dt

[ ]s

An input current step of 1 mA and100-ps rise time was used for the calculation and simulation

710 ( / )di

A sdt

[ ]I A

[ ]I A

[ ]s

[ ]s

MICASDepartment of Electrical Engineering (ESAT)

Comparison with old structure

[ ]S

[ ]S

[ / ]diA s

dt

New structureOld structure

[ / ]diA s

dt

~10 reduction !!

MICASDepartment of Electrical Engineering (ESAT)

Spectre simulation – TF

H(s)=Idd(s)/Iout(s)

Future: Theoretical Expression of TF

TF as a function of Caux

MICASDepartment of Electrical Engineering (ESAT)

Relation with Gabarit ? ?

0

6

12

18

24

30

36

42

48

54

60

66

72

78

84

105 2 3 4 5 6 8 106 2 3 4 5 6 8 107 2 3 4 5 6 8 108 2 3 4 5 6 8 109 Hz

A

B

C

D

E

F

G

H

I

K

L

M

N

O

f

dBV

V emission limitexample: H-12-n-O

Source: from Herman Casier

MICASDepartment of Electrical Engineering (ESAT)

Emergency block and PD block

MICASDepartment of Electrical Engineering (ESAT)

Shift register cell

Determine the current peak and duration:

FF FF FFFFDin

CLKRST

Out

600 [uA] × 50 × 12= 360 [mA]

Then, the output current of the special regulator : 36 [mA] ~ 72 [mA]

50 FF + 200 gates

10 × 5×

Source: from Aarnout Wieers

MICASDepartment of Electrical Engineering (ESAT)

Top level simulation

Current source simulation

Frequency simulation

MICASDepartment of Electrical Engineering (ESAT)

Current source simulation of whole circuit

[ ]I mA

[ ]V v

Current of Vbat

VDD after the regulator

VDD_input

Power down enable

[ ]V v

MICASDepartment of Electrical Engineering (ESAT)

Current source simulation of whole circuit

[ ]I mA

[ ]V v

[ ]V v

Current of Vbat

V3v3

VDD_input

Vcontrol

[ ]V v

Power down enable

MICASDepartment of Electrical Engineering (ESAT)

Frequency simulation of the whole circuit

current of Vbat

di/dt p-p =8.5x104 [A/s]

9x106 load current

FFT FFT

di/dt p-p =1.8x109 [A/s]

7x103

MICASDepartment of Electrical Engineering (ESAT)

Layout

Area: 1mm x 1.1mm

Ctank

Caux

CtankCtank

Ctank

Ctank Ctank

Ctank and Power transistors

MICASDepartment of Electrical Engineering (ESAT)

EMC test chip with special regulator

SR1, MS-FF, PMOS capa

SR2, MS-FF, NMOS capa

SR3, MS-FF, MIM capa

SR4, D-FF, PMOS capa

SR5, D-FF, NMOS capa

SR6, D-FF, MIM capa

SR7, MS-FF, no capa, PWR on GND

SR8, MS-FF, no capa, PWN next GND

SR9, MS-FF, no capa, PWR next GND

SR10, D-FF, no capa, PWR on GND

SR11, D-FF, no capa, PWR next GND

SR12, D-FF, no capa, PWR next GND

On-chipLDR

PD

On-chipSerial

regulator

PD

SR1RST Din CLK OUT

SR2RST Din CLK OUT

SR11RST Din CLK OUT

SR12RST Din CLK OUT

GND

Kelvin contact

LDO

PD

Special (KUL)regulator

Ctank

Source: from Aarnout Wieers

MICASDepartment of Electrical Engineering (ESAT)

Future work

1.Chip measurementDesign improvementRefine Theoretical analysis on EMC reduction and

maximum current capability

2.Continue research on the Clock strategy: SSCG

MICASDepartment of Electrical Engineering (ESAT)

Questions

Thank you for your attention