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COE 381 MICROPROCESSORS
UNIT 2
MEMORIES
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Chapter Objectives
Stored ProgramConcept
Addressing
AddressDecoding
CommodityMemories
Using MemoryChips
Timing
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Chapter Objectives
Reality of MemoryDecoding
Filling theMemory Map
Memory MapDetails
Separate I/O AddressSpace
EndiannessMemoryHierarchy
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Chapter Objectives
CachesHarvard
Architecture
Read OnlyMemory (ROM)
Current MemoryTechnology
Punch Cards ROM / PROM
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Chapter Objectives
More ElectrostaticMemories
MagneticMemories
More MagneticMemories
Optical Memories
Full AddressDecoding
Partial AddressDecoding
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MEMORY
SECTION 1:
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The Stored Program Concept
The concept of a stored program:
Instructions can be represented by numbers and
stored in the same way as data.
E.g. a bit pattern 01000101 represents
the number 69 or the letter E
or the an instruction for, say, multiplication
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The Stored Program Concept cont
The same memory locations may be used as
instructions and data (though rare)
Question: what is the difference between the von
Neumann architecture and the stored program
concept?
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Determining Addressable Memory
A processor with 12-bit address bus
can address up to 4Kwords of memory.
e.g. ARM which produces byte addresses
has 32-bit address bus
and hence capable of addressing up to 232
separate bytes.
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Commodity Memories
All von Neumann computers need memory
Small memories (a few Kbytes) are often on-chip
Large memories could be in one or more modules
Several types of memory exist
cost trade-offs vary according to the system requirement
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Commodity Memories (2)
D-type flip-flops
Convenient for synchronous logic (e.g. FSMs)
Very large area per bit
Transparent latches
Okay for logic but not as convenient
Smaller than D-types, but still large
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Memory Chips
The memory device shown is a 628512. This is a 4MbitSRAM chip organized as 512 Kwords of 8 bits each.
It therefore requires nineteen address lines and eightdata lines.
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Memory Chips (contd) The following table defines the memory chips behaviour.
Points to note:
All the control signals are active low
If the chip is not selected (/CS = H), nothing happens
Write enable overrides read operations
The data bus is bidirectional (either read or write saves pins)
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Timing Issues
When accessing a memory location: ensurethat
the correct data is accessed at the correct location
no other memory locations are involved
It is important that the address is stable
during the write operation
else other locations may also be affected
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Timing (2)
Thetimingdiagram
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Timing Issues (3)
Write strobe
a logical AND of the write enable and chip select
signals
both must be active for data to be written.
The timing diagram on the previous slide is
only one of the possible approaches to
strobing memory.
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Timing (4)
Different processors (& different
implementations) encode timing differently.
This is okay, as long as timing is included
somewhere on the datasheet.
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Addressing
Some definitions: Bytenow standardized as eight bits.
Nibblefour bits or half a byte
Wordthe natural size of operands, whichvaries from processor to processor (16 bits in
MU0, 32 bits in ARM). Usually the width of thedata bus.
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Addressing (2)
Widththe number of bits in a bus or a
register
Address rangethe number of elements
which can be addressed.
Typewhat the data represents.
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Addressing (3)
The memory only performs one operation at atime.
A memory operation requires the answers tosome questions:
Do what?Control (read or write)
With what?Data
Where?Address
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Address Decoding
A memory address may not always refer to
one location
The ARM processor example
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Address Decoding (2)
Addresses are decoded to the minimum
addressable size (usually a byte)
In ARM the LSB used by the address
decoder is A[2]
A[1] and A[0] act as byte selectors, whichwill be ignored when performing word-wide
operations
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Byte Access
Bus addressing is normally written in the
format N[X:Y]
Notice that when the processor reads word
00000000 it receives data on all its data lines
(D[31:0]).
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Filling the Memory Map (2)
The normal design for the memory system
would therefore be a space of 230words of 32-
bits each
This could be populated, using the 128K8-bit
RAM chips
Four RAMs (i.e. 512Kbytes)= 128KWords
A total of 230/217= 213 =8192 RAM chips
required
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Filling the Memory Map (3)
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Separate I/O Space
I/O access patterns different from memory accesses I/O access being rarer
Separate address space for I/O (e.g. x86 architecture)
Cleaner address space left just for true memory
I/O space referenced with different instructions (e.g. INand OUT ) limited addressing modes and,
possibly, a smaller address range
Same bus (with an added address line IO/mem)
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Endianness
Endianness refers to the way sub-elements arenumbered within an element
e.g. the way bytes are numbered in a word.
Two typesLittle endian and Big endian
By convention the bytes-in-a-word definition
tends to dominate.
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Little Endian Addressing
The least significant byte is at the lowest address.
e.g. Storing a word (say, 12345678) at a range of
locations starting from address 00001000 in a 32-
bit byte-addressable address space gives results:
Address 1000 contains byte 78
Address 1001 contains byte 56 Address 1002 contains byte 34
address 1003 contains byte 12
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Little Endian Addressing (2)
Displayed as bytes, a memory dump would
look like:
00001000 78 56 34 12
Performing a byte load at the starting address
would return: 00000078
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Big Endian Addressing
The most significant byte is at the lowestaddress.
Using the same word address (00001000) forthe same word (12345678):
Address 1000 contains byte 12
Address 1001 contains byte 34
Address 1002 contains byte 56
Address 1003 contains byte 78
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Big Endian Addressing (2)
Displayed as bytes, a memory dump would
look like: 00001000 12 34 56 78
If a byte load was performed on the same
address the result would be: 00000012
NB: Choice of endianness in a given processor
is arbitrary.
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Harvard Architecture
Stored program computers with separate instruction
and data buses
The Harvard architecture logically separates thefetching of instructions from data reads and writes
Its real purpose is to increase memory bandwidth
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Harvard Architecture (2)
Disadvantages: the available memory is pre-divided into
code and data areas
it is hard or impossible for the code tomodify itself
more wiring (pins, etc.)
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ADDRESS DECODING STRATEGIES
SECTION 2
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Address Decoding
Although memory space is said to be flat, itdoes not mean the physical implementation ishomogenous
Different portions of memory are used fordifferent purposes: RAM, ROM, I/O
Even if all the memory was of one type, westill have to implement it using multiple ICs
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Address Decoding
This means that for a given valid address, one
and only one memory-mapped component
must be accessed
Address decoding is the process of generating
chip select (CS*) signals from the address bus
for each device in the system
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Arrangement of 2KB Memory Blocks
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The address bus lines are split into two sections
the N most significant bits are used to
generate the CS* signals for the different
devices
the M least significant signals are passed to
the devices as addresses to the different
memory cells
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Decoding Logic for M1 and M2
000 000
000 7FF
000 800
000 FFF
001 000
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Address decoding methods
There are two types of address decoding:
Full address decoding
Partial address decoding
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Recall
A E l
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An Example
using Binary Decoder
Lets assume a very simple microprocessor
with 10 address lines (1KB memory)
We wish to implement all its memory space
using 128x8 memory chips
We will need 8 memory chips (8x128=1024)
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Solution using Decoding Table
Device Device Mem. Size (m) m-1 MEM0 128B = 27= $80 $7F
MEM1 128B = 27= $80 $7F
MEM2 128B = 27= $80 $7F MEM3 128B = 27= $80 $7F
MEM4 128B = 27= $80 $7F
MEM5 128B = 27
= $80 $7F MEM6 128B = 27= $80 $7F
MEM7 128B = 27= $80 $7F
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Solution using Decoding Table
Device Start Address End Address MEM0 $000 $07F MEM1 $080 $0FF
MEM2 $100 $17F MEM3 $180 $1FF MEM4 $200 $27F MEM5 $280 $2FF MEM6 $300 $37F MEM7 $380 $3FF
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Decoding Table
Device A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
MEM0 0 0 0
MEM1 0 0 1
MEM2 0 1 0
MEM3 0 1 1 MEM4 1 0 0
MEM5 1 0 1
MEM6 1 1 0
MEM7 1 1 1
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Solution
We will need 3 address lines to select each
one of the 8 chips
Each chip will need 7 address lines to address
its internal memory cells
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A E l
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An Example
using Random Logic
Lets assume the same microprocessor with
10 address lines (1KB memory)
However, this time we wish to implement only
512 bytes of memory
We still must use 128-byte memory chips
Physical memory must be placed on the upper
half of the memory map
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Solution using Decoding Table
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A More Difficult ExampleDevice Device Amount of
Description Name Memory toAddress .
ROM chip ROM1 4KBRAM chip RAM 4KBROM chip ROM2 8KBPeripheral 1 PERI1 2 bytes
Peripheral 2 PERI2 2 bytes
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Device Memory Mapping
Device m m-1ROM1 4K = 212= $1000 $0FFFRAM 4K = 212= $1000 $0FFF
ROM2 8K = 213
= $2000 $1FFFPERI1 2 = 21 = $0002 $0001PERI2 2 = 21 = $0002 $0001
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Device Memory Mapping
Device Name Start Address End Address
ROM1 $000000 $000FFF
RAM $001000 $001FFFROM2 $002000 $003FFFPERI1 $004000 $004001PERI2 $004002 $004003
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Address Decoding Table
DEVICE ADDRESS LINE
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ROM1 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X
RAM 0 0 0 0 0 0 0 0 0 0 0 1 X X X X X X X X X X X X
ROM2 0 0 0 0 0 0 0 0 0 0 1 X X X X X X X X X X X X X
PERI1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 X
PERI2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 X
F ll Add D di S h ti Di
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Full Address Decoding Schematic Diagram
Corresponding to Table
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Partial address decoding
only a subset of the address lines are needed
to point to the physical memory locations
Each physical memory location is identified by
several possible addresses
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Example
Lets assume the same microprocessor with
10 address lines (1KB memory)
However, this time we wish to implement only
512 bytes of memory
We still must use 128-byte memory chips
Physical memory must be placed on the upper
half of the memory map
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Solution
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Memory Map
Address Decoding Table for Partial
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Address Decoding Table for Partial
Address Decoding for Example
DEVICE ADDRESS LINE
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ROM1 0 0 0 X X X X X X X X X X X X
RAM 0 0 1 X X X X X X X X X X X X
ROM2 0 1 X X X X X X X X X X X X X
PERI1 1 0 X
PERI2 1 1 X
Partial Address Decoding for Example
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Partial Address Decoding for Example
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Partial Address Decoding Schematic Diagram
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Partial Address Decoding Schematic DiagramCorresponding to Table
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Designing Address Decoders
Address Decoding with Random Logic
Address Decoding with m-line-to-n-line
Decoders
Address Decoding with PROM
Address Decoding with FPGA, PLA and PAL
m line to n line Decoders
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m-line-to-n-line Decoders
(e.g. 74LS138 Decoder)
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Appli
cations
ofth
ethree-to-eightDe
coder
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Also, recall
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Address Decoding with PROM
Used in place of random logic or a binary
decoder
Implements truth (look-up) table instead of
Boolean logic
m-bit address at its inputs selects one of 2m
possible p-bit words
capacity of the PROM required is p*2m
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Advantages and Disadvantges
Advantages able to select memory blocks of differing size
ROM1 and RAM1 are of different size
Versatile
Disadvantages large PROM may be required for the decoding process
depending on the values of p and m making design and testing procedures complex
To solve the snag Perform basic decoding with random logic
Perform the finer decoding with PROM
An
DEVICE MEMORY ADDRESS
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Exam
pleofDecodingw
ithPROM
DEVICE MEMORY
SPACE (BYTES)
ADDRESS
RANGE
ROM1 4K 000000
000FFF
ROM2 4K 001000001FFF
ROM3 4K 002000002FFF
RAM1 2K 00C00000C7FF
PERI1 256 00E00000E0FF
PERI2 256 00E10000E1FF
PERI3 256 00E20000E2FF
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PRO
M-based
Address
Decod
er
Im
plemen
tation
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Programming
of the
Address Decoding PROM
l k
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Device Memory Space in Blocks
ROM1 2 blocks 2 entries in PROM
ROM2 2 blocks 2 entries in PROM
ROM3 2 blocks 2 entries in PROM
RAM1 1 block 1 entry in PROM
PERIs (decoder) 1 block (combined) 1 entry in PROM
Address range of
CPU
System Address Lines System Device Enables
A15 A14 A13 A12 A11 PROM1 PROM2 PROM3 RAM1 PERIs
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CPUPROM Address Input PROM Data Output
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
000000-0007FF 0 0 0 0 0 0 1 1 1 1 1 1 1
000800-000FFF 0 0 0 0 1 0 1 1 1 1 1 1 1
001000-0017FF 0 0 0 1 0 1 0 1 1 1 1 1 1
001800-001FFF 0 0 0 1 1 1 0 1 1 1 1 1 1
002000-0027FF 0 0 1 0 0 1 1 0 1 1 1 1 1
002800-002FFF 0 0 1 0 1 1 1 0 1 1 1 1 1
003000-0037FF 0 0 1 1 0 1 1 1 1 1 1 1 1
003800-003FFF 0 0 1 1 1 1 1 1 1 1 1 1 1
---------- - - - - - -do- -do- -do- -do- -do- -do- -do- -do-
00B800-00BFFF 1 0 1 1 1 1 1 1 1 1 1 1 1
00C000-00C7FF 1 1 0 0 0 1 1 1 0 1 1 1 1
00C800-00CFFF 1 1 0 0 1 1 1 1 1 1 1 1 1
00D000-00D7FF 1 1 0 1 0 1 1 1 1 1 1 1 1
00D800-00DFFF 1 1 0 1 1 1 1 1 1 1 1 1 1
00E000-00E7FF 1 1 1 0 0 1 1 1 1 0 1 1 1
00E800-00EFFF 1 1 1 0 1 1 1 1 1 1 1 1 1
00F000-00F7FF 1 1 1 1 0 1 1 1 1 1 1 1 1
00F800-00FFFF 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Decoding with FPGA, PLA
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Address Decoding with FPGA, PLA
and PAL
Address decoding using general purpose
programmable logic elements
the speed of random logic, and
the flexibility of the PROM