MicroCCh14L1

8/6/2019 MicroCCh14L1

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Chapter 14

Motorola MC68HC11 FamilyMotorola MC68HC11 Family

MCU ArchitectureMCU Architecture



Ch14L1-"Microcontrollers....", RajKamal, from Pearson Education,

2

Lesson 1

68HC11 MCU Architecture

overview




3

Outline

•• CPU Registers,CPU Registers,• MCU Architecture overview

• Address and Data Buses• Execution Unit- ALU• Ports




4

CPU Registers

• ACCA and ACCB• 16-bit Program Counter PC• 16-bit Stack Pointer S• 16-bit Index Registers IX and IY• 8- bit CCR (Condition Code

Register)




5

Microcontroller68HC11

8-bit

16-bit IndexRegisters

IXandIY

16-bitProgramCounter

PC

ClockRedu-

cible to0

FullyMOS-FET

Based

ACCAand

ACCB

Stop Instruction

8 MHzXTAL

Accumulators 16-bitStack

PointerS

CCR

Decrease

afterpush,increasebefore

pop

Internal RAM andROM, RAM,Registers ,EEPROM

InternalBus




6

Outline

• CPU Registers,

•• MCU Architecture overviewMCU Architecture overview

• Address and Data Buses• Execution Unit- ALU• Ports




7

• Fully static operation- MCU clock can be reduced to 0 – being fullyMOSFETs based

Stop Instruction




8

Performance

As per 8MHz XTL 2MHz E-Clock




9

• 68HC11 common 8-bit internal bus forthe 16-bit addressing and 8-bit data

• Princeton architecture bus

• Bus interface for 8-bit data andinstructions.• Two interrupts – Maskable Interrupt

request (IRQ) and Initialization optionas unmaskable (XIRQ)

• PC initialization using reset vectorFFFEH-FFEFH Reset




10

68HC11 Architecture Overview




11

CPU registers

IO and internaldevices Registers

AMUX

Control and Sequencing Circuit

OPTION, COPRS, PPROG, HIPRO, INIT,CONFIG,TESTI

Port C

Internal RAMand ROM,RAM, EEPROM

A8-A15

Port B

P

o r t

D

P o

r t A

P o r t

E

ADC

S/H

AD0-AD8

TCNT

Out-

compareIn CaptureCOP RTC

InterruptControl

ID

IR

A C C A

, A C C B

, I X

, I Y

, P C

, S

, C C R

Reset

Osc

PACNT

S C

I S P I

DDRC

DDRD

ExecutioExecution unitn unit




12

Memory Architecture

68HC11/12

Address InternaldevicesRegistersData and

Program,constants,stored tablesCommonMemory

Internal RAM andROM, RAM, EEPROM

IO and internal devices,System control

Registers

64 kB of linear address space




13

68HC11 Family ProgrammingModel

CPU Registers

Internal RAM andROM, RAM, EEPROM

IO and internal

devices Registers

Address Space

System Function

Control Registers

OPTION,

COPRS,

IPRO,

INIT,

CONFIG,

TESTI




14

• Processor operation of 16-bit datatype is as per word alignment atmemory in big endian [leastsignificant byte stored as higher

bits (address 1) of a word]

•Instructions have 88 data type• Few use 16- bit data types




15

A 16bit word in memoryBig Endian

Address0

Address

Byte0 (LSB)

Byte1 (MSB)

Address1

16-bit word alignment




16

Outline

• CPU Registers,• MCU Architecture overview

•• Address and Data BusesAddress and Data Buses• Execution Unit- ALU• Ports




17

Internal and External BusesInternal and External Buses

ACCA orACCB

CCR

MDR

S

MAR

InternalDevices

IXIY

PC

AD0 – AD7

A8 - A15

Internal Bus 8-bit

Bus InterfaceBus InterfaceUnitUnit




18

Outline


• Address and Data Buses•• Execution UnitExecution Unit -- ALUALU• Ports




19

• ACCA or ACCB used as 8-bit ACC oras16-bit ACCD (double accumulator)• 8-bit ALU includes multiplier and divide




20

Execution UnitExecution Unit

ACCA orACCB

CCR

Temp 1 Temp 2

ALUOR, AND,XOR

Rotate/ Shift

CMP,TST

+, - , xor ÷÷÷÷

IX

IY

IR

ID

Controland

Sequencer

Circuits

Internal RAM andROM, RAM,

Registers ,EEPROM




21

Instruction Execution

InstructionDecode

InstructionFetch

InstructionExecute

STAGE 1

STAGE 2

STAGE3 to n

Time

clock

cycle (s)




22

Control memory micro codes based -Implementation

Internal bus

Execution

IRID

Fetch

DecodeControl

andSequencer

Circuits




23

Outline


• Address and Data Buses• Execution Unit- ALU

•• PortsPorts




24

Port PAPA7

PA6PA5PA4PA3

PA1PA0

PA2

IO

OOO

II

IO

Option 1Option 1

OC1

OC2OC3OC4

IC2IC3

IC1OC5

Option 2Option 2

Cnt

OOO

II

IO

Option 3Option 3

TCNT

Out-compare

In Capture

PACNT

AddressAddress–– xx’’000H000H



Ch14L1-"Microcontrollers....", RajKamal, from Pearson Education, 25

Port PB

PB7PB6PB5PB4

PB3

PB1PB0

PB2

OOOO

OO

OO

Option 1Option 1

A15A14A13A12

A9A8

A10A11

Option 2Option 2





Port PC

PC7

PC6PC5PC4PC3

PC1PC0

PC2

DDRC7

DDRC6DDRC5DDRC4

DDRC1DDRC0

DDRC2

DDRC3

Option 1Option 1

A7

A6A5A4

A1A0

A2A3

Option 2Option 2

IO

IOIOIO

IOIO

IOIO



D7D6D5D4

D1D0

D2D3

Option 3Option 3

STRA Handshakesignals for PortSTRB




Port PD

PD2

MasterMaster

SSSCLK

TxDRxD

MISOMOSI

Option 2Option 2

IOIO

IOIO

IOIO

Option 1Option 1

SPI

SCI

PD5PD4

PD0

PD3

DDRD5DDRD4

DDRD1DDRD0

DDRD2DDRD3



PD1

SlaveSlave

SSSCLK

MOSIMISO

SPI

RxDTxD

ReceivingSCI

Option 3Option 3

Option 4Option 4

OOpptt

iioonn55




Port PEPE7

PE6PE5PE4PE3

PE1PE0

PE2

I

III

II

II

Option 1Option 1

AN7

AN6AN5AN4

AN1AN0

AN2AN3

AnalogAnalogInputInputOption 2Option 2

AddressAddress ––xx’’00AH00AH

AMUX

ADCS/H

ADCADCRegisterRegisterssADC TLADC TLRegisterRegister



• Expanded Mode used for interfacingExternal Memory and Ports

• Expanded Mode looses Port B and PortB• Recovered back by using 68HC24




Expansion ModeA15A14A13A12

A9A8

A10

A11

Port BPort BOption 2Option 2

AD7AD6AD5AD4AD3

AD0

AD2AD1

Port CPort COptionsOptions2/32/3

Latch

A0-A15

AS

E

AddressDecoder

D0-D7

CSCS

Expansion to Portsand Memory

AnAn --A15A15

Mode A=0Mode A=0

Mode B=1Mode B=1





Summary



• 68HC11 family 8-bit processor• PC, S, ACCA, ACCB, IX, IY, CCR

• Princeton architecture• 8 bit data type

• Big endian 16-bit word alignment• Two interrupts – Maskable Interrupt

request (IRQ) and Initialization option asunmaskable (XIRQ)

• PC initialization using reset vector



Internal and External MemoryAddresses-

• IO/Devices Control and StatusRegisters

• System Function Control Registers• Internal RAM• Internal ROM• EEPROM



Internal Devices

• TCNT with out compare, input capture,• SPI, SCI

• RTC• PACNT• Port E with option of analog inputs multi

channel AMUX, S/H, ADC• Port B /A8-A15,

• Port C with DDRC / AD0-AD7/ • Port A /IC1-IC3, OC1-OC5

• Port D with DDRD/SCI/SPI Master/Slave



End of Lesson 1 on MCU

Architecture overview




THANK YOU

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MicroCCh14L1