Micron Technology Clinic Tool Flow and Comparison of Micron Package Models

Micron Technology ClinicTool Flow and Comparison of

Micron Package Models

Presenter: Michael Tomer

Advisor: Dr. Ken Stevens

Tool Flow and Comparison of the Micron Package Models

►Tool flow Design of circuits and conversion of circuits to

spice format Setup of control files to run simulations

►Comparison of the Micron package models Differences between HSimPlus and Hspice

when simulating using the package models Actual differences in the signal between the

same tool►Power and signal integrity when using

varying amounts of power inputs

Tool FlowVerilog

Optimized Verilog

Structural Verilog

Spice

Verilog (logic correct)

Results

Simulation Control File

Tool Flow►Biggest problem encountered in the project

Tool Setup►Licensing

No prior experience with tools Tools failed and stopped working randomly

►As I write this, the tools which had been working earlier today have stopped working. (citing licensing issues)

►As an example I will be converting a verilog file to the spice format

Tool FlowVerilog

Optimized Verilog

Structural Verilog

Spice


Results


Verilog Creation// mod.v`timescale 1ns / 1ps

module mod( a, out, CLK);input [3:0] a;input CLK;output [1:0] out;reg [1:0] out;

always@(posedge CLK)beginout <= a % 3;end

endmodule

These are the names of the internal inputs and outputs•This is where you declare the specs of the circuit.•The [3:0] syntax means that there are 4 wires contained in the circuit.•the output of this circuit is named out.• For us to be able to assign to out in the

always block below we must also declare a reg of the same type and name.

•For this circuit, the code in the always block will run every time that the CLK signal goes from low to high

Initial Simulation►Simulation of the digital logic in the

circuit is wise to do at this level before proceeding More difficult to simulate later

►Digital logic simulation tools ModelSim SE Xilink ISE

ModelSim SE

Conversion from Verilog to Spice►Conversion from verilog to spice is

done in three steps1. Optimization and verification2. Synthesized using design compiler3. Conversion to spice

Conversion from Verilog to Spice►A set of script files are used to do

steps 1 and 2 These are based off of the scripts from

Ken Stevens ECE 6770 Advanced digital VLSI design class webpage

They have been modified to use 65nm design libraries

Step 1: Optimization and Verification► Verilog circuit is verified and optimized using Design

Compiler Prepares the RTL verilog code to be mapped to the 65nm

librariesmod.v`timescale 1ns / 1ps

module mod( a, out, CLK); input [3:0] a; input CLK; output [1:0] out; reg [1:0] out;

always@(posedge CLK) begin out <= a % 3;

endEndmodule

mod.rtlopt.vmodule mod ( a, out, CLK ); input [3:0] a; output [1:0] out; input CLK; wire N0, N1;

REM_UNS_OP rem_13 ( .A(a), .B({1'b1, 1'b1}), .REMAINDER({N1, N0}) ); \**SEQGEN** \out_reg[1] ( .clear(1'b0), .preset(1'b0), .next_state(N1), .clocked_on(CLK), .data_in(1'b0), .enable(1'b0), .Q(out[1]), .synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), .synch_enable(1'b1) ); \**SEQGEN** \out_reg[0] ( .clear(1'b0), .preset(1'b0), .next_state(N0), .clocked_on(CLK), .data_in(1'b0), .enable(1'b0), .Q(out[0]), .synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), .synch_enable(1'b1) );endmodule

Step 2: Conversion to Structural Verilog

►Design compiler will convert the file Maps the logic in the optimized verilog file

to modules in the 65nm libraries►Runs timing tests

Ensures that signals have enough time to propagate through a circuit

Step 2: Conversion to Structural Verilog (continued)

Excerpt from mod.dcopt.fullpathsStartpoint: a[2] (input port) Endpoint: clock_r_REG0_S1 (rising edge-triggered flip-flop clocked by clock) Path Group: clock Path Type: max

Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 input external delay 0.00 0.00 r a[2] (in) 0.00 0.00 r U19/Y (NAND2X1A12TR) 0.02 0.02 f U17/Y (NAND2X1A12TR) 0.02 0.04 r U14/Y (OAI22X1A12TR) 0.03 0.07 f U18/Y (XOR2X0P7A12TR) 0.03 0.10 f clock_r_REG0_S1/D (DFFQNX0P5A12TR) 0.00 0.10 f data arrival time 0.10

clock clock (rise edge) 0.28 0.28 clock network delay (ideal) 0.00 0.28 clock uncertainty -0.01 0.26 clock_r_REG0_S1/CK (DFFQNX0P5A12TR) 0.00 0.26 r library setup time -0.03 0.23 data required time 0.23 ----------------------------------------------------------- data required time 0.23 data arrival time -0.10 ----------------------------------------------------------- slack (MET) 0.13

• Scripts generate timing information•Clock rate is defined in our script files• Possibly too fast or too slow

Step 2: Conversion to Structural Verilog (continued)

mod.dcopt.vmodule mod ( a, out0, CLK ); input [3:0] a; output [1:0] out0; input CLK; wire n22, n23, n1, n2, n3, n5, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21;

A2DFFQX1A12TR clock_r_REG2_S1 ( .A(n1), .B(n12), .CK(CLK), .Q(n10) ); DFFQX0P5A12TR clock_r_REG1_S1 ( .D(n18), .CK(CLK), .Q(n9) ); DFFQNX0P5A12TR clock_r_REG0_S1 ( .D(n15), .CK(CLK), .QN(n21) ); DFFQX0P5A12TR clock_r_REG3_S1 ( .D(n2), .CK(CLK), .Q(n8) ); OAI2XB1X1A12TR U3 ( .A1N(n8), .A0(n21), .B0(n19), .Y(n20) ); XOR2X0P7A12TR U4 ( .A(n20), .B(n8), .Y(n23) ); XNOR2X0P7A12TR U5 ( .A(n7), .B(n21), .Y(n22) ); INVX16A12TR U6 ( .A(n3), .Y(out0[0]) ); INVX16A12TR U7 ( .A(n5), .Y(out0[1]) ); BUFHX1P4A12TR U8 ( .A(a[2]), .Y(n1) ); INVX0P5BA12TR U9 ( .A(a[3]), .Y(n12) ); NAND2X0P5BA12TR U10 ( .A(a[1]), .B(n16), .Y(n18) ); BUFHX1P4A12TR U11 ( .A(a[0]), .Y(n2) ); INVX0P5BA12TR U12 ( .A(n23), .Y(n3) ); INVX0P5BA12TR U13 ( .A(n22), .Y(n5) ); OAI22X1A12TR U14 ( .A0(n17), .A1(n14), .B0(n13), .B1(n12), .Y(n16) ); INVX2A12TR U15 ( .A(a[1]), .Y(n14) ); INVX2A12TR U16 ( .A(n11), .Y(n13) ); NAND2X1A12TR U17 ( .A(a[2]), .B(n11), .Y(n17) ); XOR2X0P7A12TR U18 ( .A(n16), .B(a[1]), .Y(n15) ); NAND2X1A12TR U19 ( .A(a[3]), .B(a[2]), .Y(n11) ); AND2X1A12TR U20 ( .A(n8), .B(n20), .Y(n7) ); XOR2X0P7A12TR U21 ( .A(n9), .B(n10), .Y(n19) );endmodule

mod.rtlopt.vmodule mod ( a, out, CLK ); input [3:0] a; output [1:0] out; input CLK; wire N0, N1;

REM_UNS_OP rem_13 ( .A(a), .B({1'b1, 1'b1}), .REMAINDER({N1, N0}) ); \**SEQGEN** \out_reg[1] ( .clear(1'b0), .preset(1'b0), .next_state(N1), .clocked_on(CLK), .data_in(1'b0), .enable(1'b0), .Q(out[1]), .synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), .synch_enable(1'b1) ); \**SEQGEN** \out_reg[0] ( .clear(1'b0), .preset(1'b0), .next_state(N0), .clocked_on(CLK), .data_in(1'b0), .enable(1'b0), .Q(out[0]), .synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), .synch_enable(1'b1) );endmodule

Step 3: Conversion to Spice►Mentor’s v2lvs utility converts the structural verilog

to spice format Formats are similar

Step 3: Conversion to Spicemod.dcopt.vmodule mod ( a, out0, CLK ); input [3:0] a; output [1:0] out0; input CLK; wire n22, n23, n1, n2, n3, n5, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21;

A2DFFQX1A12TR clock_r_REG2_S1 ( .A(n1), .B(n12), .CK(CLK), .Q(n10) ); DFFQX0P5A12TR clock_r_REG1_S1 ( .D(n18), .CK(CLK), .Q(n9) ); DFFQNX0P5A12TR clock_r_REG0_S1 ( .D(n15), .CK(CLK), .QN(n21) ); DFFQX0P5A12TR clock_r_REG3_S1 ( .D(n2), .CK(CLK), .Q(n8) ); OAI2XB1X1A12TR U3 ( .A1N(n8), .A0(n21), .B0(n19), .Y(n20) ); XOR2X0P7A12TR U4 ( .A(n20), .B(n8), .Y(n23) ); XNOR2X0P7A12TR U5 ( .A(n7), .B(n21), .Y(n22) ); INVX16A12TR U6 ( .A(n3), .Y(out0[0]) ); INVX16A12TR U7 ( .A(n5), .Y(out0[1]) ); BUFHX1P4A12TR U8 ( .A(a[2]), .Y(n1) ); INVX0P5BA12TR U9 ( .A(a[3]), .Y(n12) ); NAND2X0P5BA12TR U10 ( .A(a[1]), .B(n16), .Y(n18) ); BUFHX1P4A12TR U11 ( .A(a[0]), .Y(n2) ); INVX0P5BA12TR U12 ( .A(n23), .Y(n3) ); INVX0P5BA12TR U13 ( .A(n22), .Y(n5) ); OAI22X1A12TR U14 ( .A0(n17), .A1(n14), .B0(n13), .B1(n12), .Y(n16) ); INVX2A12TR U15 ( .A(a[1]), .Y(n14) ); INVX2A12TR U16 ( .A(n11), .Y(n13) ); NAND2X1A12TR U17 ( .A(a[2]), .B(n11), .Y(n17) ); XOR2X0P7A12TR U18 ( .A(n16), .B(a[1]), .Y(n15) ); NAND2X1A12TR U19 ( .A(a[3]), .B(a[2]), .Y(n11) ); AND2X1A12TR U20 ( .A(n8), .B(n20), .Y(n7) ); XOR2X0P7A12TR U21 ( .A(n9), .B(n10), .Y(n19) );endmodule

mod.v2lvs.sp$ Spice netlist generated by v2lvs$ v2007.2_26.18 Wed Jun 13 20:11:48 PDT 2007

.SUBCKT mod a[3] a[2] a[1] a[0] out0[1] out0[0] CLKXclock_r_REG2_S1 n10 n1 n12 CLK 1013 1015 A2DFFQX1A12TR Xclock_r_REG1_S1 n9 CLK n18 1013 1015 DFFQX0P5A12TR Xclock_r_REG0_S1 n21 CLK n15 1013 1015 DFFQNX0P5A12TR Xclock_r_REG3_S1 n8 CLK n2 1013 1015 DFFQX0P5A12TR XU3 n20 n21 n8 n19 1013 1015 OAI2XB1X1A12TR XU4 n23 n20 n8 1013 1015 XOR2X0P7A12TR XU5 n22 n7 n21 1013 1015 XNOR2X0P7A12TR XU6 out0[0] n3 1013 1015 INVX16A12TR XU7 out0[1] n5 1013 1015 INVX16A12TR XU8 n1 a[2] 1013 1015 BUFHX1P4A12TR XU9 n12 a[3] 1013 1015 INVX0P5BA12TR XU10 n18 a[1] n16 1013 1015 NAND2X0P5BA12TR XU11 n2 a[0] 1013 1015 BUFHX1P4A12TR XU12 n3 n23 1013 1015 INVX0P5BA12TR XU13 n5 n22 1013 1015 INVX0P5BA12TR XU14 n16 n17 n14 n13 n12 1013 1015 OAI22X1A12TR XU15 n14 a[1] 1013 1015 INVX2A12TR XU16 n13 n11 1013 1015 INVX2A12TR XU17 n17 a[2] n11 1013 1015 NAND2X1A12TR XU18 n15 n16 a[1] 1013 1015 XOR2X0P7A12TR XU19 n11 a[3] a[2] 1013 1015 NAND2X1A12TR XU20 n7 n8 n20 1013 1015 AND2X1A12TR XU21 n19 n9 n10 1013 1015 XOR2X0P7A12TR .ENDS

Step 3: Conversion to Spicemod.v2lvs.sp (with VDD,VSS

addition)

$ Spice netlist generated by v2lvs$ v2007.2_26.18 Wed Jun 13 20:11:48 PDT 2007

.SUBCKT mod a[3] a[2] a[1] a[0] out0[1] out0[0] CLK VDD VSSXclock_r_REG2_S1 n10 n1 n12 CLK VDD VSS A2DFFQX1A12TR Xclock_r_REG1_S1 n9 CLK n18 VDD VSS DFFQX0P5A12TR Xclock_r_REG0_S1 n21 CLK n15 VDD VSS DFFQNX0P5A12TR Xclock_r_REG3_S1 n8 CLK n2 VDD VSS DFFQX0P5A12TR XU3 n20 n21 n8 n19 VDD VSS OAI2XB1X1A12TR XU4 n23 n20 n8 VDD VSS XOR2X0P7A12TR XU5 n22 n7 n21 VDD VSS XNOR2X0P7A12TR XU6 out0[0] n3 VDD VSS INVX16A12TR XU7 out0[1] n5 VDD VSS INVX16A12TR XU8 n1 a[2] VDD VSS BUFHX1P4A12TR XU9 n12 a[3] VDD VSS INVX0P5BA12TR XU10 n18 a[1] n16 VDD VSS NAND2X0P5BA12TR XU11 n2 a[0] VDD VSS BUFHX1P4A12TR XU12 n3 n23 VDD VSS INVX0P5BA12TR XU13 n5 n22 VDD VSS INVX0P5BA12TR XU14 n16 n17 n14 n13 n12 VDD VSS OAI22X1A12TR XU15 n14 a[1] VDD VSS INVX2A12TR XU16 n13 n11 VDD VSS INVX2A12TR XU17 n17 a[2] n11 VDD VSS NAND2X1A12TR XU18 n15 n16 a[1] VDD VSS XOR2X0P7A12TR XU19 n11 a[3] a[2] VDD VSS NAND2X1A12TR XU20 n7 n8 n20 VDD VSS AND2X1A12TR XU21 n19 n9 n10 VDD VSS XOR2X0P7A12TR .ENDS

•V2lvs utility not perfect• Emacs script• Define power net domains

for the blocks (supports multiple power sources)• Fix naming clashes (HSPICE

not case sensitive)• Correct unconnected net

problems •Hand editing

Step 3: Conversion to Spice►Result

A spice file of the circuit that is ready to be simulated

mod.v2lvs.sp (with VDD,VSS addition)

$ Spice netlist generated by v2lvs$ v2007.2_26.18 Wed Jun 13 20:11:48 PDT 2007

.SUBCKT mod a[3] a[2] a[1] a[0] out0[1] out0[0] CLK VDD VSSXclock_r_REG2_S1 n10 n1 n12 CLK VDD VSS A2DFFQX1A12TR Xclock_r_REG1_S1 n9 CLK n18 VDD VSS DFFQX0P5A12TR Xclock_r_REG0_S1 n21 CLK n15 VDD VSS DFFQNX0P5A12TR Xclock_r_REG3_S1 n8 CLK n2 VDD VSS DFFQX0P5A12TR XU3 n20 n21 n8 n19 VDD VSS OAI2XB1X1A12TR XU4 n23 n20 n8 VDD VSS XOR2X0P7A12TR XU5 n22 n7 n21 VDD VSS XNOR2X0P7A12TR XU6 out0[0] n3 VDD VSS INVX16A12TR XU7 out0[1] n5 VDD VSS INVX16A12TR XU8 n1 a[2] VDD VSS BUFHX1P4A12TR XU9 n12 a[3] VDD VSS INVX0P5BA12TR XU10 n18 a[1] n16 VDD VSS NAND2X0P5BA12TR XU11 n2 a[0] VDD VSS BUFHX1P4A12TR XU12 n3 n23 VDD VSS INVX0P5BA12TR XU13 n5 n22 VDD VSS INVX0P5BA12TR XU14 n16 n17 n14 n13 n12 VDD VSS OAI22X1A12TR XU15 n14 a[1] VDD VSS INVX2A12TR XU16 n13 n11 VDD VSS INVX2A12TR XU17 n17 a[2] n11 VDD VSS NAND2X1A12TR XU18 n15 n16 a[1] VDD VSS XOR2X0P7A12TR XU19 n11 a[3] a[2] VDD VSS NAND2X1A12TR XU20 n7 n8 n20 VDD VSS AND2X1A12TR XU21 n19 n9 n10 VDD VSS XOR2X0P7A12TR .ENDS

Tool FlowVerilog

Optimized Verilog

Structural Verilog

Spice


Results


Spice File Simulation►HSpice and HSimPlus require a control

file to simulate These control files define circuits, input

stimulus, output measurements, and other options

►Hard to program from scratch without example

►Hard to set up properly even with good examples

Control Filesmod.wop.sp SPICE simulation of our simple inverter

* SPICE simulation of our simple inverter

* SPICE simulation of our simple inverter

* include our circuit.include 'mod.v2lvs.sp'

* include the library.include '/home/micron/design/65nm/data/cmos10sfrvt_a12.cdl'

* include the transistor models.lib '/home/micron/design/65nm/data/skew.file' stats.include '/home/micron/design/65nm/data/fixed_corner'.include '/home/micron/design/65nm/data/HSpice_example.param'.lib '/home/micron/design/65nm/data/lib.models.10sf' 10sf_models**.include '/home/micron/design/65nm/data/nfet.inc'**.include '/home/micron/design/65nm/data/pfet.inc'

*** define usage of the subcircuitsx1 DIE_DQ3 DIE_DQ2 DIE_DQ1 DIE_DQ0 DIE_DQ5 DIE_DQ4 DIE_DQ6 pwr1 gnd mod

* ".option post" generates the outputs for cscope.option acct=1 post

*Give initial Voltage and ground powers.nodeset v(pwr1) = 1.2 v(gnd) = 0.0

*Give Initial signal voltages.nodeset v(DIE_DQ0) = 1.2 v(DIE_DQ2) = 1.2 v(DIE_DQ4) = 1.2+ v(DIE_DQ6) = 1.2

* set up our power and ground sourcesVCC1 pwr1 0 DC 1.2

VSS1 gnd 0 DC 0.0

(continued on next slide)

•.include and .lib tell the simulator what files to use• We include our mod.v2lvs.sp

which contains our circuit

•Defines the voltage and ground pins

•Defines initial voltages (helps HSimplus and HSpice)

•Makes the simulator generate waveform outputs

•Instantiates and defines use of sub-circuits (more on this later)

Control Files (continued)mod.wop.sp (continued)* define input waves for first gate.* these are switching simultaneously.* PULSE commands are initial-voltage pulse-voltage, time-offset,* rise-time fall-time high-delay cycle-time

VA3 DIE_DQ3 0 PULSE(0 1.2 0p 100p 100p 10000p 20000p)VA2 DIE_DQ2 0 PULSE(0 1.2 2500p 100p 100p 10000p 20000p)VA1 DIE_DQ1 0 PULSE(0 1.2 5000p 100p 100p 10000p 20000p)VA0 DIE_DQ0 0 PULSE(0 1.2 7500p 100p 100p 10000p 20000p)VA6 DIE_DQ6 0 PULSE(0 1.2 0p 100p 100p 1000p 2000p)

.save type=nodeset level=all

*** This lowers precision - 1 is default (up to 4).param HSimparprecision = 0

* run a transitent analysis for two clock cycles.TRAN 1p 40000p START=0ps

* plot transient voltages.PLOT TRAN V(DIE_DQ0) V(0) (0,1.2).PLOT TRAN V(DIE_DQ1) V(0) (0,1.2).PLOT TRAN V(DIE_DQ2) V(0) (0,1.2).PLOT TRAN V(DIE_DQ3) V(0) (0,1.2).PLOT TRAN V(DIE_DQ4) V(0) (0,1.2).PLOT TRAN V(DIE_DQ5) V(0) (0,1.2).PLOT TRAN V(DIE_DQ6) V(0) (0,1.2)

.PLOT TRAN V(pwr1) V(0) (0,1.2)

.PLOT TRAN V(gnd) V(0) (0,1.2)

* measure the power.MEAS rmsen rms I(VCC) from = 0ps to 40000ps

.end

•Define inputs for the circuits• Here we are doing a 10000ps

pulse with various offsets for DIE_DQ0-DIE_DQ3

• DIE_DQ6 here is a clock signal

•Sets HSim’s precision factor. (lower is slower)•Instructs the simulator to simulate for a specific amount of time. (40000 pico-seconds)

•Instructs the simulator to plot the output waveforms of signals from 0 to 1.2 volts

•Measures the average (rms) power of VCC from 0ps to 40000ps

Control Files (continued)*** define usage of the subcircuitsx1 DIE_DQ3 DIE_DQ2 DIE_DQ1 DIE_DQ0 DIE_DQ5 DIE_DQ4 DIE_DQ6 pwr1 gnd mod

► Where do we get all of this info x# at the start gives it a unique identifier for this instantiation of this circuit mod at the end tells us what circuit it is The rest of them are arbitrary names chosen by whatever naming scheme you see fit.

► So what should I put here and how many of them should I put?► First look at the spice file

.SUBCKT mod a[3] a[2] a[1] a[0] out0[1] out0[0] CLK VDD VSS

x1 DIE_DQ3 DIE_DQ2 DIE_DQ1 DIE_DQ0 DIE_DQ5 DIE_DQ4 DIE_DQ6 pwr1 gnd mod

•Remember these names have been arbitrary chosen

Control Files (continued)►To connect circuits

Set the name of the outputs of one to be the inputs of another

In this example the outputs of mod circuit x1 used as some of the inputs to x2



Micron Package Models►Micron provided two models of the

resistive, capacitive, and inductive effects of a package Single layer package Two layer package

Control Files (continued)►The same principals apply to using the

micron control files Only much more complicated

Micron Single Layer Model► I/O Pins*** include the single layer package.include 'v48c_x8_production_11704_DQs_pkg.inc'

***using the single layer power delivery packagex0 DIE_DQ0_PKG001 DIE_DQ1_PKG001 DIE_DQ2_PKG001 DIE_DQ3_PKG001+ DIE_DQ4_PKG001 DIE_DQ5_PKG001 DIE_DQ6_PKG001 DIE_DQ7_PKG001 DIE_DQS_PKG001+ DIE_DQS#_PKG001 DIE_DM_PKG001 DIE_TDQS#_PKG001 gnd gnd gnd gnd gnd gnd+ gnd gnd gnd gnd gnd gnd pwrQ pwrQ pwrQ1 pwrQ2 pwrQ3 pwrQ3 pwrQ3 gnd gnd+ gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd pwr pwr pwr1 pwr2 pwr3 pwr+ pwr pwr pwr pwr pwr pwr pwr BGA_VSSA_PKG001 BGA_VSSB_PKG001 BGA_VSSC_PKG001+ BGA_VSSD_PKG001 BGA_VSSE_PKG001 BGA_VSSF_PKG001 BGA_VCCA_PKG001+ BGA_VCCB_PKG001 BGA_VCCC_PKG001 BGA_VCCD_PKG001 BGA_VSSQ1_PKG001+ BGA_VSSQ2_PKG001 BGA_VSSQ3_PKG001 BGA_VSSQ4_PKG001 BGA_VSSQ_PKG001+ BGA_VCCQ2_PKG001 BGA_VCCQ3_PKG001 BGA_VCCQ_PKG001 BGA_VCCQ1_PKG001+ BGA_VSS1_PKG001 BGA_VSS2_PKG001 BGA_VSS3_PKG001 BGA_VSS4_PKG001+ BGA_VSS_PKG001 BGA_VCC3_PKG001 BGA_VCC_PKG001 BGA_VCC1_PKG001+ BGA_VCC2_PKG001 BGA_TDQS#_PKG001 BGA_DM_PKG001 BGA_DQS#_PKG001+ BGA_DQS_PKG001 BGA_DQ7_PKG001 BGA_DQ6_PKG001 BGA_DQ5_PKG001 BGA_DQ4_PKG001+ BGA_DQ3_PKG001 BGA_DQ2_PKG001 BGA_DQ1_PKG001 BGA_DQ0_PKG001+ v48c-11704-dq-str-pwrs-unmer_wrapper

Micron Two Layer Model► I/O Pins*** include the two layer package.include 'v48c_x8_2metal_layer_0523_DQs_pkg.inc'

***using the two layer power delivery packagex0 DIE_DQ0_PKG001 DIE_DQ1_PKG001 DIE_DQ2_PKG001 DIE_DQ3_PKG001+ DIE_DQ4_PKG001 DIE_DQ5_PKG001 DIE_DQ6_PKG001 DIE_DQ7_PKG001 DIE_DQS_PKG001+ DIE_DQS#_PKG001 DIE_DM_PKG001 DIE_TDQS#_PKG001 gnd gnd gnd gnd gnd gnd gnd+ gnd gnd gnd gnd gnd pwrQ1 pwrQ1 pwrQ pwrQ pwrQ pwrQ pwrQ1 gnd gnd gnd gnd+ gnd gnd gnd gnd gnd gnd gnd gnd gnd pwr pwr pwr pwr pwr pwr pwr1 pwr pwr+ pwr pwr pwr pwr BGA_VSSQ1A_PKG001 BGA_VSSQ1B_PKG001 BGA_VSSQC_PKG001+ BGA_VCCQ_PKG001 BGA_VCCQ1_PKG001 BGA_VSSA_PKG001 BGA_VSSB_PKG001+ BGA_VSSC_PKG001 BGA_VSSD_PKG001 BGA_VSSE_PKG001 BGA_VSSF_PKG001+ BGA_VSSG_PKG001 BGA_VSSH_PKG001 BGA_VSSI_PKG001 BGA_VCCA_PKG001+ BGA_VCCB_PKG001 BGA_VCCC_PKG001 BGA_VCCD_PKG001 BGA_VCCE_PKG001+ BGA_VCCF_PKG001 BGA_VSSQ1_PKG001 BGA_VSSQ_PKG001 BGA_VCCQ3_PKG001+ BGA_VCCQ2_PKG001 BGA_VSS1_PKG001 BGA_VSS_PKG001 BGA_VCC1_PKG001+ BGA_VCC_PKG001 BGA_TDQS#_PKG001 BGA_DM_PKG001 BGA_DQS#_PKG001+ BGA_DQS_PKG001 BGA_DQ7_PKG001 BGA_DQ6_PKG001 BGA_DQ5_PKG001+ BGA_DQ4_PKG001 BGA_DQ3_PKG001 BGA_DQ2_PKG001 BGA_DQ1_PKG001 BGA_DQ0_PKG001+ sol_v48c_523_dq_dm_str_pwr_unmergedSnks_wrapper

Simple ALUInput (op)

Output

00 out(31:0) <= a+b01 out(31:0) <= a-b10 out(31:0) <= a*b11 out(31:16) <= a%b

out(15:0) <= a/b

Alu Without Package (WOP) Power

HSpice

HSim

Alu Without Package (WOP) Output

HSpice

Alu Without Package (WOP) Output

HSpice HSim

Single Layer Package vs WOP Output in HSpice

Single Layer WOP

Single Layer Package vs WOP Output in HSpice (more detail)

Single Layer WOP

Single Layer Package vs WOP Output in HSim (more detail)

WOP Single Layer

Single Layer Package Power in HSpice

HSpice

Single Layer Package Power in HSim

HSim

Single Layer Package Power in HSpice and HSim

HSpice HSim

Single Layer Package Output in HSpice and HSim

HSpice HSim

Two Layer Package vs WOP Output in HSpice

Single Layer WOP

Two Layer Package vs WOP Output in HSpice

Single Layer WOP

Two Layer Package vs WOP Output in HSim

Single Layer WOP

Two Layer Package Power in HSpice

HSpice

Two Layer Package Power in HSim

HSim

Two Layer Package Power in HSpice and HSim

HSpice HSim

Two Layer Package Output in HSpice and HSim

HSpice HSim

Two Layer vs Single Layer vs WOP Output in HSpice

WOP Single Layer Two Layer

Two Layer vs Single Layer vs WOP Output in HSpice

WOP Single Layer Two Layer

Package Power•Micron packages had a majority of pins dedicated to power and ground lines

•For simplicity sake, most of our tests use just one of the power inputs

•All of our experiments don’t use the package for signal outputs, only for power input

Split Power Experiment•Modified the ALU circuit to take in 8 power lines. •Set 1/8 of sub circuits in the ALU to use each of the power lines

Power Graphs of Split Power In HSpice

Regular vs Split Power in HSim

Split Power

Single Power

Regular vs Split Power in HSim

Split PowerSingle Power

Regular vs Split, Output in HSim

Split Power

Single Power

Regular vs Split, Output in HSim

Split PowerSingle Power

►Developed a tool flow Created circuits design in behavioral verilog Synthesized designs into spice format using

65nm technology part libraries►Developed necessary scripts to support

conversion Created control files and simulation vectors

for comparing designs►Performed comparative studies

Developed ALU test circuit Compared package models

►Dual layer package has less power supply noise►Splitting power delivery into multiple power lines

reduces noise

Conclusions

Documents

Micron Technology Clinic Tool Flow and Comparison of Micron Package Models