Microprocessor and Interfacing II

Lectures Notes

Eng. Elayan Abu Gharbyeh2011

1 Introduction to Data Transfer and Interfacing Techniques

InterfacingWhen we discuss interfacing, We are interested in 2 things:Designing logic circuits (hardware) and writing instructions (software) to enable the microprocessor to communicate with peripherals (I/O devices).

The logic circuits are called I/O ports or interfacing devices.

Formats of Data Transfer• The microprocessor communicates with its peripherals in either of two formats:• Synchronous:

– At the same time.– The transmitter and receiver are synchronized with the same clock.

• Asynchronous:– At irregular intervals.

• The Synchronous format is used in high-speed data transmission. • The Asynchronous format is used for low speed data transmission.• Data transfer between the microprocessor and peripherals is primarily synchronous.

Modes of Data Transfer• The microprocessor receives (or transmits) binary data in either of two modes:• Parallel The entire word (4-bit, 8-bit, 16-bit) is transferred at one time.• Serial Data are transferred one bit at a time over a single line.• Requires parallel-to-serial or serial-to-parallel conversion.

Types of I/OThe microprocessor identifies the peripherals based on their interfacing technique either as:• Memory-mapped A peripheral is connected as if it were a memory location. It is identified with a 16-bit address. Data transfer is implemented using memory-related inst.• Peripheral-mapped A peripheral is identified with an 8-bit address. The microprocessor uses special instructions to implement data transfer.

Controlling Data TransferThere are two ways to control the transfer of data between the microprocessor and its peripherals:• Microprocessor-controlled:

1

The microprocessor initiates the communication with the peripheral. (when peripherals are slow)

• Peripheral-controlled:The peripheral initiates the communication.

Microprocessor Controlled Data Transfer

Microprocessor-controlled data transfer can take place under five different conditions:• Unconditional• Polling (Status check)• Interrupt• With READY signal• With Handshake signal

1. Unconditional:The microprocessor assumes that the peripheral is always available.

For example, displaying data at LED port involves simply enabling the port, transfers data, and going to execute the next inst.

2. Polling (status check): The microprocessor is kept in a loop to check whether data are available. For example, reading data from the Keyboard.

3. InterruptWhen a peripheral is ready to transfer data, it sends an interrupt signal to the microprocessor.

The microprocessor stops executing the program, accepts/sends the data from/to the peripheral, and then return to the program.

4. Data transfer with READY signal:Usually happens when the peripheral’s response time is slower than the execution time of the microprocessor.

The READY signal can be used to extend the execution time (By adding T-states). And is commonly used in a system with slow memory chips

5. Data transfer with Handshake signals:Signals are exchanged between the microprocessor and a peripheral prior to actual data transfer.This is to ensure the readiness of the peripheral and to synchronize the timing of the data transfer.An Example of that would be, interfacing A/D converterHandshake signals can be used with status check or interrupts.

Peripheral-Controlled Data TransferThis is used when the device is much faster than the microprocessor. An example would be the DMA.

– The DMA controller sends a HOLD signal to the microprocessor.– The microprocessor releases the system bus.– The data are transferred at high speed without the intervention of the microprocessor

End of Part 1

2 Interrupts

Introduction

The interrupt I/O is a process of data transfer whereby an external device or a peripheral caninform the processor that it is ready for communication and it requests attention.

The process is initiated by an external device and is asynchronous, meaning that it can be initiated at any time without reference to the system clock. However, the response to an interrupt request is directed or controlled by the microprocessor.

The interrupt requests are classified in two categories: maskable interrupt and nonmaskable interrupt. More specifically four maskable interrupts and one nonmaskable interrupt. Among these four maskable interrupts, one is nonvectored. The other three are vectored to specific locations

THE 8085 INTERRUPTThe 8085 interrupt process is controlled by the Interrupt Enable flip-flop, which is internal to the processor and can be set or reset by using software instructions.

If the flip-flop is enabled and the input to the interrupt signal INTR (pin 10) goes high, the microprocessor is interrupted. This is a maskable interrupt and can be disabled.

Steps for the 8085 Interrupt process

Step 1: The interrupt process should be enabled by writing the instruction EI in the main program.The instruction EI sets the Interrupt Enable flip-flop.The instruction DI resets the flip-flop and disables the interrupt process.

Interrupts

4 Maskable

3 Vectored

RST 7.5

RST 6.5

RST 5.5

1 Non-Vectored INTR

1 Non-maskable Vectored TRAP

EI (Enable Interrupt):1 -byte instruction.Sets the Interrupt Enable flip-flop and enables the interrupt process. System reset or an interrupt disables the interrupt process.

DI (Disable Interrupt):1-byte instruction.Resets the Interrupt Enable flip-flop and disables the interrupt.It should be included in a program segment where an interrupt from an outside source cannot be tolerated.

Step 2: When the microprocessor is executing a program, it checks the INTR line during the execution of each instruction.

Step 3: If the line INTR is high and the interrupt is enabled, the microprocessor:• Completes the current instruction• Disables the Interrupt Enable flip-flop• Sends a signal called INTA - Interrupt Acknowledge (active low).• The processor cannot accept any interrupt requests until the interrupt flip-flop is enabled again.

Step 4: The signal INTA is used to insert a restart (RST) instruction through external hardware.• The RST instruction is a 1-byte CALL instruction that transfers the program control to a specific memory location on Page 00H (The first 256 bytes).

Step 5: When the microprocessor receives an RST instruction:• It saves the memory address of the next instruction on the stack.• The program is transferred to the CALL location.

Step 6: Assuming that the task to be performed is written as a subroutine at the specified location, the processor performs the task. This subroutine is known as a service routine

Step 7: The service routine should include the instruction EI to enable the interrupt again.

Step 8: At the end of the subroutine, the RET instruction retrieves the memory address where the program was interrupted and continues the execution.

RST Instruction

The 8085 instruction set includes eight RST (Restart) instructions:• RST 0 , ………., RST 7 • These are 1-byte Call instructions that transfer the program execution to a specific location on page 00H, as listed in the following Table.

Implementing the RST instruction (STEP 4) To implement Step 4 in the interrupt process, insert one of these instructions in the microprocessor by using external hardware and the signal INTA.

In the following circuit, instruction RST 5 is built using a tri-state buffer

RST 5 instruction implementation

Example: An Implementation of the 8085 Interrupt• Write a main program to count continuously in binary with a one-second delay between each count.• Write a service routine at XX70H to flash FFH five times when the program is interrupted, with some appropriate delay between each flash.

Main ProgramXX00 LXI SP,XX99HXX03 EIXX04 MVI A,00HXX06 NXTCNT: OUT PORT1XX08 MVI C,01HXX0A CALL DELAYXX0D INR AXX0E JMP NXTCNT

Service RoutineXX70 SERV: PUSH BXX71 PUSH PSWXX72 MVI B,0AHXX74 MVI A,00HXX76 FLASH: OUT PORT1XX78 MVI C,01HXX7A CALL DELAYXX7D CMAXX7E DCR BXX7F JNZ FLASHXX82 POP PSWXX83 POP BXX84 EIXX85 RET

Issues in Implementing Interrupts

1. Is there a minimum pulse width required for the INTR signal?

The microprocessor checks INTR, one clock period before the last T-state of an instruction cycle. In the 8085, the Call instructions require 18 T-states; therefore, the INTR pulse should be high at least for 17.5 T-states.In a system with 3 MHz clock frequency the input pulse to INTR should be at least 5.8 µs long.(1/3MHz *17.5)

2. How long can the INTR pulse stay high?The INTR pulse can remain high until the interrupt flip-flop is set by the EI instruction in the service routine.If it remains high after the execution of the El instruction, the processor will be interrupted gain, as if it were a new interrupt.

3. Can the microprocessor be interrupted again before the completion of the first interrupt service routine?The answer to this question is determined by the programmer.After the first interrupt, the interrupt process is automatically disabled. If instruction El is written at the beginning of the routine, the microprocessor can be interrupted gain during the service routine.

Multiple Interrupts and Priorities how to use INTR for multiple peripherals and how to determine priorities among these peripherals when two or more of the peripherals request interrupt service simultaneously .One solution is using an 8-to-3 priority encoder that determines the priorities among interrupting devices.

This device has 8 inputs and 3 outputs. The inputs are assigned increasing priorities according to

the increasing index of the input.

Input 7 has highest priority and input 0 has the lowest. The 3 outputs carry the index of the highest priority

active input.

The following Figure shows how this circuit can be used with a Tri-state buffer to implement an interrupt priority scheme.

Function Table for the priority encoder

Using the priority Encoder

When an interrupting device requests service, one of the input lines goes low, which makes line E0 high and interrupts the microprocessor

When the interrupt is acknowledged and the signal INTA enables the tri-state buffer, the code corresponding to the input is placed on lines D5, D4, and D3.

For example, if the interrupting device on line I5 goes low:

The output of the encoder will be 010. This code is inverted by the buffer 74LS366 and combined with other high data lines.

Thus, the instruction 11101111 (EFH) is placed on the data bus. This is instruction RST 5.

If there are simultaneous requests, it responds to the higher-level input, ignoring the lower-level input.

One of the drawbacks of this scheme is that the interrupting device connected to the input I7 always has the highest priority. And this is one of the drawbacks of this schema.

this device is being replaced by a more versatile one called a Programmable Interrupt controller (8259A)

8085 Vectored Interrupt The 8085 has five interrupt inputs; one is called INTR which was discussed so far. Three are called RST 5.5, RST 6.5, and RST 7.5, and the fifth is called TRAP, a non-maskable

interrupt.

These last four (RSTs and TRAP) are automatically vectored (transferred) to specific locations on memory page 00H without any external hardware.

They do not require the INTA signal or an input port; the necessary hardware is already implemented inside the 8085.

TRAP A nonmaskable interrupt that has the highest priority among the interrupt signals. It need not be enabled, and it cannot be disabled.

RST 7.5, 6.5, and 5.5 These maskable interrupts are enabled under program control by two instructions:

El (Enable Interrupt) described earlier SIM (Set Interrupt Mask)

SIM: Set Interrupt Mask. This is a 1-byte instruction and can be used for three different functions

SIM Instruction and Functions Set mask for RST 7.5, 6.5, and 5.5 interrupts. Bit D3 is a control bit and should = 1 for bits D0,

D1 and D2 to be effective.

Reset RST 7.5 flip-flop .Bit D4 is additional control for RST 7.5. If D4 = 1, RST 7.5 is reset. This is used to override (or ignore) RST 7.5 without servicing it.

The third function is to implement serial I/O (discussed in Chapter 16).

Interrupts Priority and Vector Locations

As shown from this schema, all of the interrupts can be masked entirely by EI, or individually by the SIM instruction and its code.

Triggering Mechanism

RST 7.5 Triggering LevelThis is positive-edge sensitive and can be triggered with a short pulse. The request is stored internally by the D flip-flop until the microprocessor responds to the request or until it is cleared by Reset or by bit D4 in the SIM instruction.

RST 6.5 , RST 5.5 Triggering LevelsThese interrupts are level-sensitive, meaning that the triggering level should be on until the microprocessor completes the execution of the current instruction.

TRAP Triggering LevelIt is level- and edge sensitive, meaning that the input should go high and stay high to be acknowledged. It cannot be acknowledged again until it makes a transition from low to high. Examples

Level Sensitive Edge Sensitive Level and Edge

Enable all the interrupts in an 8085 system:

Reset the 7.5 interrupt from the last Example:

PENDING INTERRUPTSBecause there are several interrupt lines, when one interrupt request is being served, other interrupt requests may occur and remain pending.The 8085 has an additional instruction called RIM (Read Interrupt Mask) to sense these pending interrupts.

RIM: Read Interrupt MaskThis is a 1-byte instruction that can be used for the following functions: To read interrupt masks: This instruction loads the accumulator with 8 bits indicating the

current status of the interrupt masks. To identify pending interrupts: Bits D4, D5, and D6 identify the pending interrupts. To receive serial data. Bit D7 is used to receive serial data.

Bit Pattern for the RIM Instruction

Example

EI ;enable interruptsMVI A,08H ;bit pattern to enable all interruptsSIM ;enable RST 7.5, 6.5, 5.5

MVI A,18H ;Set D4=1SIM ;Reset 7.5 interrupt flip-flop

Assuming the microprocessor is completing an RST 7.5 interrupt request, check to see if RST 6.5 is pending. If it is pending, enable RST 6.5 without affecting any other interrupts; otherwise, return to the main program.

Summary

Restart as a software instruction

RIM ;read interrupt maskMOV B,A ;save mask info.ANI 20H ;check if RST 6.5 is pending?JNZ NEXT ;RST 6.5 is pendingEI ;RST is not pending ,return to mainRET

NEXT: MOV A,B ;get mask info.ANI 0DH ;enable RST 6.5 (00001101)ORI 08H ;enable SIM (00001x0x)SIMJMP SERV ;jump to RST 6.5 service routine

After the breakpoint routine, the program should return to executing the main program at the breakpoint.The breakpoint procedure allows the user to test programs in segments.For example, if RST 6 is written in a program, the program execution is transferred to location 0030H; it is equivalent to a 1-byte call instruction. This can be used to write a software breakpoint routine.

Illustrative Program:This code illustrates the use of a procedure to display the accumulator content and the PSW into PORT1 and PORT2 when A is entered through a keyboard, and then returns when 0 is entered.

Here when an interrupt with an RST 6 code is initiated, this procedure is called. Arguably, this could also be called from within a program as a normal instruction

BRKPNT is called in the RST 6 code segment.

BRKPNT: PUSH PSW Save RegistersPUSH BPUSH DPUSH H

KYCHK: CALL KBRD Administers a Key in A Function KBRD abstracted hereCPI 0AH Is it key A?JNZ RETKY NO? check Zero keyLXI H,0007H Yes? Load A Location HL= SP+7 = SP’-3

which is ADAD SP Add the content of SP to HLMOV A,MOUT PORT1 Display ADCX H Decrease HL by one HL= SP’-4MOV A,M Which is the PSWOUT PORT2 Display PSW

JMP KYCHK Go back to check again

RETKY: CPI 00H Is it Key Zero?JNZ KYCHK No? check for next entryPOP H Yes? Restore registers

Stack Pointer Position

Content Label

SP: SP’-A L SP’-9 H SP’-8 E SP’-7 D SP’-6 C SP’-5 B SP’-4 PSW SP’-3 A SP’-2

PCLow

SP’-1 High

SP’ X

POP DPOP BPOP PSWRET Restore PC content

So if at any at any point the programmer desires to view the content of the accumulator within the program for debugging purposes, the user/programmer could inject RST 6 within the code.

Additional I/O Concepts and ProcessesThe 8085 interrupt I/O, described earlier, is limited because of its single interrupt pin and hardware requirements to determine interrupt priorities.To circumvent these limitations, a programmable interrupt controller such as the 8259A is used to implement and extend the capability of the 8085 interrupt.Another I/O process, Direct Memory Access (DMA), is commonly used for high-speed data transfer.

Programmable Interrupt Controller:The 8259A• The 8259A is a programmable interrupt managing device.• The primary features of the 8259A are:

– It manages eight interrupt requests.– It can vector an interrupt request anywhere in the memory map through program control without additional hardware for restart instructions.– It can solve eight levels of interrupt priorities in a variety of modes.– With additional 8259A devices, the priority scheme can be expanded to 64 levels.

• One of the major limitations of the 8085 interrupt scheme is that all requests are vectored to memory locations on page 00H, which is reserved for ROM or EPROM,• Access to these locations is difficult after a system has been designed.• In addition, the process of determining priorities is limited, and extra hardware is required to insert Restart instructions.• The 8259A overcomes these limitations and provides many more flexible options.• It can be employed with 16-bit Intel microprocessors as the 8086/8088 as well.

3 General-Purpose Programmable Peripheral Devices

The 8255A Programmable Peripheral InterfaceThe 8255A is a widely used, programmable, parallel I/O device.It can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O.It is flexible, versatile, and economical (when multiple I/O ports are required).It is an important general-purpose I/O device that can be used with almost any microprocessor.

The 8255A I/O Ports

The 8255A has 24 I/O pins that can be grouped primarily in two 8-bit parallel ports: Port A and Port B, with the remaining eight bits as Port C.

The eight bits of port C can be used as individual bits or be grouped in two 4-bit ports:CUPPER (CU) , CLOWER (CL).

The functions of these ports are defined by writing a control word in the control register.

Pin Configuration and Names

Block DiagramBlock Diagram

Expanded version of the Internal Structure and the Control Logic

RD (Read): This control signal enables the Read operation. When the signal is low, the MPU reads data from a selected I/O port.

WR (Write): This control signal enables the Write operation. When the signal goes low, the MPU writes into a selected I/O port or the control register.

RESET (Reset): This is an active high signal; it clears the control register and sets all ports in the input mode.

CS, A0, and A1: These are device select signals. CS is connected to a decoded address, and A0 and A1 are generally connected to MPU address lines A0 and A1(respectively)

Ports Selection

The CS signal is the master Chip Select, and A0 and A1 specify one of the I/O ports or the control register as given below:

Addressing for the example above

Communication StepsTo communicate with peripherals through the 8255A, three steps are necessary:

1. Determine the addresses of ports A, B, and C and of the control register according to the Chip Select logic and address lines A0 and A1.2. Write a control word in the control register.3. Write I/O instructions to communicate with peripherals through ports A, B, and C.

Operation Modes

CS A1 A0 Selection0 0 0 Port A0 0 1 Port B0 1 0 Port C0 1 1 Control Register1 X X No Selection

CSA7 A6 A5 A4 A3 A2 A1 A0

Hex Address Selection

100000 0 0 80H A100000 0 1 81H B100000 1 0 82H C100000 1 1 83H Control Register

Mainly there are two main Modes, BSR Mode, and I/O Mode.

I/O Mode The I/O mode can be activated by setting D7 to 1, the rest of the control word can specify

the detailed configuration for each port. Keep in mind that there are 2 Groups and 3 Ports, A,B, and C. C contains 2 sub Ports, CLower, and CUpper. They are configured differently, but addressed

with the same address

Control Groups

Mode 0Simple Input/output configuration

Applies to Group A, and Group B In this mode, ports A and B are used as two simple 8-bit I/O ports and port C as two 4-bit ports.

Each port (or half-port, in case of C) can be programmed to function as simply an input port or an output port.

The input/output features in Mode 0 are as follows: Outputs are latched . Inputs are not latched . Ports do not have handshake or interrupt capability

Configuration for Mode 0Mode 0 Mode 0

D7 D6 D5 D4 D3 D2 D1 D0

I/O Group B Port A CUpper Group A Port B CLower

1 00 0/1 0/1 0 0/1 0/11 to configure Input, 0 to configure output

Example: Mode 0

I/O

Group BPort B

CLower

Group ACUpper

Port A

Given the Following circuit, write a program to input from Port B and Port CL, the output to Port A and CU Things we need to do:

Input from B , Output to A Input from CL , Output to CH

Solution:Step 1) Configure the Ports Addresses (Memory Addressing)From the hardware configuration, we know that the port addresses are as following:

A15 A14 A13 A12 A11 A12 A11 A0 A7 A6 A5 A4 A3 A2 A1 A0 AddPort A 1 X X X X X X X X X X X X X 0 0 8000HPort B 1 X X X X X X X X X X X X X 0 1 8001HPort C 1 X X X X X X X X X X X X X 1 0 8002H

CR 1 X X X X X X X X X X X X X 1 1 8003HA range of addresses can be used, we’ll adopt the following:

Port A = 8000H Port B = 8001H Port C = 8002H Control Register = 8003H

Step 2) Configure I/O Mode for the Control RegisterMode 0 Output Output Mode 0 Input Input

D7 D6 D5 D4 D3 D2 D1 D0

I/O Group B Port A CUpper Group A Port B CLower

1 00 0 0 0 1 1Control word = 10000011 = 83H

Step 3) Program Code

MVI A,83H Load accumulator with the control wordSTA 8003H Write word in the control register to initialize the portsLDA 8001H Read switches at port BSTA 8000H Display the reading at port ALDA 8002H Read switches at port CANI 0FH Mask the upper four bits of port C; these bits are not input dataRLC

Rotate and place data in the upper half of the accumulatorRLCRLCRLCSTA 8002H Display Data at PortHLT

Mode 1Input or Output with Handshake

Applies to Group A, and Group B In Mode 1, handshake signals are exchanged between the MPU and peripherals prior to data transfer. The features of this mode include the following:

Two ports (A and B) function as 8-bit I/O ports. They can be configured either as input or output ports.

Each port uses three lines from port C as handshake signals. The remaining two lines of port C can be used for simple I/O functions.

Input and output data are latched. Interrupt logic is supported.

Configuration for Mode 1Mode 1 Mode 1

D7 D6 D5 D4 D3 D2 D1 D0

I/O Group B Port A CUpper Group A Port B CLower

1 01 0/1 X 1 0/1 X1 to configure Input, 0 to configure output

Mode 1 - Input Configuration

Handshake Signals Functions STB (Strobe Input): Generated by a peripheral device to indicate that it has transmitted a

byte of data. The 8255A, in response to STB, generates IBF and INTR. IBF (Input Buffer Full): Is an acknowledgment by the 8255A to indicate that the input latch

has received the data byte. INTR (Interrupt Request): An output signal that may be used to interrupt the MPU. This

signal is generated if STB,IBF, and INTE (Internal flip-flop) are all at logic 1. INTE (Interrupt Enable): An internal flip-flop used to enable or disable the generation of

the INTR signal. The two flip flops INTEA and INTEB are controlled by bits PC4 and PC2, respectively, through the BSR mode .

Note: to enable INTE for Port A, and Port B, we need to access the control Register through the BSR Mode. It is later discussed

Input Timing waveform

Basically, this is the structure of operation1) An Input device initiates STB Signal.2) The 8255A generates an IBF response when the data is received.3) The 8255A generates an INTR signal if INTE is enabled

Then the microprocessor can read the signal from the latched port.

Status and Control WordControl Word

Mode 1 Mode 1D7 D6 D5 D4 D3 D2 D1 D0

I/O Group B Port A CUpper Group A Port B CLower

1 01 1 X 1 1 X1 to configure Input, 0 to configure output

Status Word for Mode 0 InputD7 D6 D5 D4 D3 D2 D1 D0

I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB

The status word can be read from Port C, we are mostly interested in the IBF Latch at D5 and D1 which specifies whether data is availableThis word is meant only to be Read, other information include interrupt availability and the status of the Interrupt latch enable INTE

Programming NotesThere are two programming models for operation in Mode 1

Status Check I/O1) Read Port C2) If IBF is set

Read from PeripheralInterrupt Based I/O

1) When Data is available an interrupt is set

2) An Interrupt procedure reads data

Mode 1 - Output ConfigurationHandshake Signals Functions

OBF (Output Buffer Full): An output signal that goes low when the MPU writes data into the output latch of the 8255A. This signal indicates to an output peripheral that new data are ready to be read.

ACK (Acknowledge): An input signal from a peripheral that goes low when the peripheral receives the data from the 8255A ports.

INTR (Interrupt Request): An output signal, it can be used to interrupt the MPU to request the next data byte for output. The INTR is set when OBF, ACK, and INTE are all active.

INTE (Interrupt Enable): An internal flip-flop, needs to be set to generate the INTR signal. The two flip-flops INTEA and INTEB are controlled by bits PC6 and PC2, respectively, through the BSR mode.

Note: to enable INTE for Port A, and Port B, we need to access the control Register through the BSR Mode. It is later discussed

Output Timing waveform

Basically, this is the structure of operation1. The 8255A generates an OBF signal (Data ready for write)2. The output device generates ACK when the data is received.3. The 8255A generates an INTR signal if INTE is enabled

Status and Control WordControl Word

Mode 1 Mode 1D7 D6 D5 D4 D3 D2 D1 D0

I/O Group B Port A CUpper Group A Port B CLower

1 01 0 X 1 0 X1 to configure Input, 0 to configure output

Status Word for Mode 0 InputD7 D6 D5 D4 D3 D2 D1 D0

OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB

The status word can be read from Port C, we are mostly interested in the IBF Latch at D5 and D1 which specifies whether data is available

Example: Mode 1The following Figure shows an interfacing circuit using the 8255A in Mode 1. Port A is designed as the input port for a keyboard with interrupt I/O, and port B is designed as the output port for a printer with status check I/O.

Things we need to do:1. Find port addresses by analyzing the decode logic.2. Determine the control word to set up port A as input and port B as output in Mode 1.3. Determine the BSR word to enable INTEA (port A).4. Determine the masking byte to verify the OBFB line in the status check I/O (port B).5. Write initialization instructions and a printer subroutine to output characters that are stored

in memory.