Microprocessor Final Ver1 Part7

7/18/2019 Microprocessor Final Ver1 Part7

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N i dung môn h cộ ọN i dung môn h cộ ọ

1. Gi i thi u chung v h vi x lýớ ệ ề ệ ử

2. B vi x lý Intel 8088/8086ộ ử 3. L p trnh h p ng ch! 8086ậ ợ ữ

". # ch c v$! r% d li uổ ứ ữ ệ

&. Ng t v$ x lý ng tắ ử ắ6. #ru' c p ( nh tr c ti p )*+ậ ộ ớ ự ế

,. -c ( vi x lý trn th c tộ ử ự ế



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-h ng , -c ( vi x lý trn th c tươ ộ ử ự ế-h ng , -c ( vi x lý trn th c tươ ộ ử ự ế

Gener%l purp!e micr!pr!ce!r

Intel 80x86

u h ng pht tri nướ ể

*icr!c!ntr!ller4i 5i u hi n c % *!t!r!l%ề ể ủ

7 vi 5i u hi n 80&1ọ ề ể7 vi 5i u hi n +4ọ ề ể 9:;-


)igit%l ign%l pr!ce!r #ex% Intrument

*!t!r!l%

9hilip




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Intel 80x86






*!t!r!l%

9hilip




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Intel "00"Intel "00"

<irt micr!pr!ce!r

=1>,1? "@(it pr!ce!r

2300 #r%nit!r =9@*;:?A 10 µm

0.06 *I9:A 108 7CA

6"0 ('te %ddre%(lemem!r'

@1&4 p!Der uppl'



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Intel 8008Intel 8008

<irt 8@(it pr!ce!r

=1>,2?

-!t E&00F %t thi timeA

% "@(it pr!ce!r c!ted

E&0

-!mplete 'tem h%d 2('te +*

200 7C cl!c

reHuenc'A 10 µmA 3&00

#;A 0.06 *I9:A 16('te %ddre%(le

mem!r'

18 pin p%c%geA

multiplexed %ddre %nd

d%t% (u



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:ec!nd gen. 8@(itpr!ce!rAintr!duced in 1>,"

"0 pin p%c%geAN*;:A &00intructi!n/A 6µmA 2 *7CA &4 JK124 p!Der uppl'A6 #;A 0.6" *I9:

6" ('te %ddrep%ce =% l%rge %

deigner D%ntMA)N 1>,"?



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16@(it pr!ce!r intr!duced in 1>,>

3 µmA & % 8 *7CA 2>#;A 0.33 % 0.66*I9:A 1 *('te

%ddre%(le mem!r'



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Intr!duced 1>,8 -l!c reHuenc' 8 @ 10 *7C

16 bit integer CPU

address

data16

20



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Intr!duced 1>83 1.& µmA 13" #;A 0.> t! 2.6 *I9:

-l!c reHuenc' 6 @ 2& *7C

16 bit integer CPU

address

data16

24

MMU



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Intel 80386xIntel 80386x

Intr!duced 1>86 1 µmA 2,& #;A 16 t! 33 *7CA & t! 11 *I9:

-l!c reHuenc' 16 @ 2& *7C

:!tD%re upp!rt %nd h%rdD%re pr!tecti!n !r multit%ing

32 bit integer CPU

address

data16

24

MMU



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Intel 80386dxIntel 80386dx

Intr!duced 1>88 -l!c reHuenc' 16 @ "0 *7C


32 bit integer CPU

address

data32

32

MMU



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Intel 80"86dxIntel 80"86dx

Intr!duced 1>8> -l!c reHuenc' 2& @ &0 *7C


:upp!rt !r p%r%llel pr!ceing

-%che reHuired extern%l mem!r' i n!t %t en!ugh

address

data32

32

8 Kbyte cache 32 bit integer CPU

64 bit PUMMU

© 200



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Intel 80"86xIntel 80"86x

Intr!duced 1>8> 0.8 µmA 1.2 *#;A 20 t! "1 *I9:

-l!c reHuenc' 2& @ &0 *7C




address

data32

32


MMU

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Intel 80"86dx2Intel 80"86dx2

Intr!duced 1>>2 -l!c reHuenc' intern%l &0 @ 66 *7CA extern%l 2& @ 33 *7C




address

data32

32


64 bit PUMMU

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Intel 9entiumIntel 9entium

Intr!duced 1>>3 =.8 µmA 3.1 *#;? up t! =.3& mmA ".& *#; incl. **?

-l!c reHuenc' intern%l 60 @ 166 *7CA extern%l 66 *7C

:upp!rt !r p%r%llel pr!ceing c%che c!herence pr!t!c!l

:uper c%l%r

address

data64

32

64 bit PU!tatic branch

"redicti#n $nit

32 bit integer

"i"e%ined CPU

32 bit integer

"i"e%ined CPU

MMU

8 Kbyte

"r#gra& cache

8 Kbyte

data cache

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Intel 9entium 9r!Intel 9entium 9r!

Intr!duced 1>>&A 0.3& µmA 3.3 4A &.& *#;A 3&OA 38, pin -l!c reHuenc' 1&0 @ 200 *7C Intern%lA 60 @ P100 *7C xtern%l

:uper c%l%r =" Intr./c'cle?A uper pipelined =12 t%ge?

:upp!rt !r 'mmetric%l multipr!ceing =≤" -9Q?

*-* 2&6@102" ('te L2 "@D%' et %!ci%tive c%che

Dyna&ic branch

"redicti#n $nit

MMU

'nstr$cti#n

dis"atch $nit

32 bit integer

"i"e%ined CPU

64 bit"i"e%ined PU

(ddress

generati#n $nit

32 bit integer

"i"e%ined CPU

32 bit integer

"i"e%ined CPU address

data

64)*CC

36

8 Kbyte +1

"r#gra& cache

8 Kbyte +1

data cache

t# +2 cache

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Intel 9entium IIIntel 9entium II

Intr!duced 1>>,A 0.2& µmA 2.0 4A > *#;A "3 OA 2"2 pin -l!c reHuenc' 200 @ &&0 *7C Intern%lA 100 @ 22& *7C L2 c%cheA 66

@ 100 *7C xtern%l


:upp!rt !r 'mmetric%l multipr!ceing =≤8 -9Q?

:ingle dge -!nt%ct -%rtridge Dith #herm%l :en!r 2&6@102" ('te

L2 "@D%' et %!ci%tive c%che

Dyna&ic branch

"redicti#n $nit

MMU

'nstr$cti#n

dis"atch $nit

64 bit

"i"e%ined PU

64 bit"i"e%ined PU

(ddress

generati#n $nit

32 bit integer

"i"e%ined CPU

32 bit integer


data

64)*CC

36

16 Kbyte +1

"r#gra& cache

16 Kbyte +1

data cache

t# +2 cache*CC

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Intel 9entium IIIIntel 9entium III

Intr!duced 1>>>A 0.18 µm A 6L*A 1.8 4A 28 *#;A 3,0 pin -l!c reHuenc' "&0 @ 1130 *7C Intern%lA 100@133 *7C xtern%l


:upp!rt !r 'mmetric%l multipr!ceing =≤2 -9Q?

Dyna&ic branch

"redicti#n $nit

MMU

'nstr$cti#n

dis"atch $nit

64 bit

"i"e%ined PU

64 bit"i"e%ined PU

(ddress

generati#n $nit

32 bit integer

"i"e%ined CPU

32 bit integer


data

64)*CC

36

16 Kbyte +1

data cache

256 Kbyte +2 $ni,ied

cache

16 Kbyte +1

"r#gra& cache

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I t l 9 ti I4



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Intel 9entium I4Intel 9entium I4

Intr!duced 2002A 0.13 µm !r >0nm A 1.8 4A && *#; -l!c reHuenc' 1A" t! 3.8 G7C Intern%lA "00 t! 800 *7C xtern%l


NeDer veri!n 7'per thre%dingA 3.8 *7C

Dyna&ic branch

"redicti#n $nit

MMU

'nstr$cti#n

dis"atch $nit

64 bit

"i"e%ined PU

64 bit"i"e%ined PU

(ddress

generati#n $nit

32 bit integer

"i"e%ined CPU

32 bit integer


data

64)*CC

36

16 Kbyte +1

data cache

256-512-1024 Kbyte +2

16 Kbyte +1

"r#gra& cache

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I t l 9 ti I4



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+v%il%(le %t 3.80< G7CA 3.60< G7CA 3."0< G7C %nd 3.20< G7C

:upp!rt 7'per@#hre%ding #echn!l!g'1 =7# #echn!l!g'? !r%ll reHuencie Dith 800 *7C r!nt ide (u =<:B?

:upp!rt IntelR xtended *em!r' 6"#echn!l!g'2 =IntelR*6"#?

:upp!rt xecute )i%(le Bit c%p%(ilit'

Bin%r' c!mp%ti(le Dith %pplic%ti!n running !n previ!umem(er ! the Intel micr!pr!ce!r line

Intel NetBurtR micr!%rchitecture

<:B reHuenc' %t 800 *7C

7'per@9ipelined #echn!l!g' +dv%nce )'n%mic xecuti!n

4er' deep !ut@!@!rder executi!n

nh%nced (r%nch predicti!n

,,&@l%nd 9%c%ge

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I t l 9 ti I4



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16@B Level 1 d%t% c%che

1@*B +dv%nced #r%ner -%che =!n@dieA ullpeed Level 2 =L2?c%che? Dith 8@D%' %!ci%tivit' %nd rr!r -!rrecting -!de=--?

1"" :tre%ming :I*) xteni!n 2 =::2? intructi!n

13 :tre%ming :I*) xteni!n 3 =::3? intructi!n

nh%nced l!%ting p!int %nd multimedi% unit !r enh%ncedvide!A %udi!A encr'pti!nA %nd 3) per!rm%nce

9!Der *%n%gement c%p%(ilitie

:'tem *%n%gement m!de

*ultiple l!D@p!Der t%te

8@D%' c%che %!ci%tivit' pr!vide impr!ved c%che hit r%te !nl!%d/t!re !per%ti!n

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I+@6" =It%nium?I+@6" =It%nium?

)eign t%rted in 1>>"F irt %mple !n the m%ret

in 2001 6"@(it %ddre p%ce ="x10> G('teF De Dill never

need th%t muchS?

2&6 6"@(it integer %nd 128 82@(it l!%ting p!int

regiterF 6" (r%nch t%rget regiterF 6" 1@(itpredic%te regiter

"1 (it intructi!n D!rd length

10@t%ge pipeline

ep%r%te L1 d%t% %nd pr!gr%mA >6 ('te L2 uniied!n@chipA " *('te L3 uniied !@chip

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© DHBK 2005



Intel 80x86u h ng pht tri nướ ể





*!t!r!l%

9hilip


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© DHBK 2005

#rend !r gener%l purp!e#rend !r gener%l purp!e

pr!ce!rpr!ce!r

7igher cl!c reHuencie "., @P 30 G7C

<%ter mem!r' 120 n @P &0 n n!t pr!p!rti!n%l t! cl!c reHuenc' incre%e TP ue !

c%che %nd peci%l )+* mem!rie =e.g. :)+*?

Limited (' p!Der diip%ti!n TP decre%ing p!Deruppl' v!lt%ge

9%r%llel pr!ceing

*em!r' Dith pr!ce!r inte%d ! pr!ce!r Dithmem!r'

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#he uture gener%l ch%r%cteritic#he uture gener%l ch%r%cteritic

!%dm%p 2001 2002 200" 200, 2010 2013 2016

!%dm%p 1>>8 1>>, 1>>> 2002 200& 2008 2011 201"

!%dm%p 1>>& 1>>& 1>>8 2001 200" 200, 2010

Line Didth =nm? 3&0 2&0 180 130 >0 6& "& 32 22

um(er !G

m%

18 22 22@

2"

2" 2"@

26

26@

28

28 2>@

30

O%Ger iCe

=mm?

200 200 300 300 300 300

um(er !G

Diring level

"@& 6 6@, , ,@8 8@> > 10

9!Der uppl'

4 det!p

3.3 1.8@

2.&

1.&@

1.8

1.1@

1.&

1.0@

1.2

0.,@

0.>

0.6 0.& 0."

*%x. p!Der

diip%ti!n/chip

80 ,0 >0 130 160 1,0 1,& 183

Oill 22 nm (e the end ! the c%ling r%ce !r -*;:U:!me (elieve10 nm Dill (e the endSSthere%terA emic!nduct!r drive Dill (e c%ttered=**:A en!rA m%gneticA !pticA p!l'merA (i!A S?)epending !n %pplic%ti!n d!m%in (eide %nd (e'!ndilic!n

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B id d ( d ili =



Beide %nd (e'!nd ilic!n =e.g.Beide %nd (e'!nd ilic!n =e.g.

p!l'mer electr!nic?p!l'mer electr!nic?

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Beide %nd (e'!nd ilic!n %pplied t! utureBeide %nd (e'!nd ilic!n %pplied t! uture

%m(ient intelligent envir!nment%m(ient intelligent envir!nment

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© DHBK 2005



Beide %nd (e'!nd ilic!n %pplied t! utureBeide %nd (e'!nd ilic!n %pplied t! uture

%m(ient intelligent envir!nment%m(ient intelligent envir!nment


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Beide %nd (e'!nd ilic!n %pplied t!Beide %nd (e'!nd ilic!n %pplied t!

%m(ient intelligent 7!meL%( =2002?%m(ient intelligent 7!meL%( =2002?


© DHBK 2005



!%dm%p 2001 2001 200" 200, 2012 2016

!%dm%p 1>>8 1>>, 1>>> 2002 200& 2008 2011 201"

!%dm%p 1>>& 1>>& 1>>8 2001 200" 200, 2010

um(er !G #; 6* 11* 21* ,6* 200* &20* 1."G 3.6G

;n chip l!c%l

cl!c6 GreH. =*7C?

,&0 12&0 2100 3&00 6000 10000 16>03

;n chip gl!(%l

cl!c6 GreH. =*7C?

300 3,& 1200 1600 2000 2&00 3000 36,"

-hip iCe =mm

2

? 2&0 300 3"0 "30 &20 620 ,&0 >01

#he uture high per!rm%nce =#he uture high per!rm%nce =µµ9?9?

-#; Intel %' in 2001 200&

"2& *#;

100 nm

1600 mm2

30 G7C !n chip

Dith!ut peciic me%ure lie individu%l tr%nit!r p!Der@d!Dn 3000 OA i.e. 3000 %mp...

1.8 G#; in 2010

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#he uture high per!rm%nce =#he uture high per!rm%nce =µµ9?9?

© DHBK 2005



9r!ce!r per!rm%nce9r!ce!r per!rm%nce

1>80 1>8& 1>>0 1>>& 2000 200&

#ime

9er!rm%nce

1

10

100

1

10

100

1*

&&V/'e%r

xp!nenti%l gr!Dth !r 3 dec%deW

#hi i c%lled X*!!reY l%DY num(er ! tr%nit!r

d!u(le ever' 18 m!nth=G!rd!n *!!reA !under Intel -!rp.?

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9r!ce!r per!rm%nce9r!ce!r per!rm%nce

:m%ller line iCe

*!re tr%nit!r TP p%r%llelim1>83 1 intructi!n per " cl!c c'cle

2002 8 intructi!n per cl!c c'cle

:m%ller c%p%cit!r TP %ter

1>83 " *7C

2002 2800 *7C

:peed@up 2&000

n%(le neD %pplic%ti!nQ*#: Dith l%rge r!lled@up ;L) creen en%(ling De(

d!Dnl!%d%(le ervice =e.g. virtu%l meeting?

)! De ind %pplic%ti!n th%t %re dem%nding en!ugh!r next dec%deY pr!ce!rU

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#he uture )+*#he uture )+*

!%dm%p 2001 2003 200, 2011 2016 U U

!%dm%p 1>>8 1>>, 1>>> 2002 200& 2008 2011 201"

!%dm%p 1>>& 1>>& 1>>8 2001 200" 200, 2010

um(er !G (it

per chip

6"* 2&6* 1G "G 16G 6"G 2&6G 1#

-hip iCe =mm

2

? 1>0 280 "00 &60 ,>0 1120 1&80 22"0

© DHBK 2005



*em!r' denit'*em!r' denit'

1>80 1>8& 1>>0 1>>& 2000 200&

#ime

9er!rm%nce

1

10

100

1

10

100

1*

&&V/'e%r

9r!ce!r

10V/'e%r

*em!r'

G%p

© DHBK 2005



*em!r' denit'*em!r' denit'

:ill center ! gr%vit'

Q:+ pr!ce!r =IntelA *!t!r!l%A #IA S? Z%p%n mem!r' =N-A #!hi(%A S?

<uture I- T pr!ce!r K mem!r'OhereUUU

*em!r' denit' gr!D %ter th%n need 1>83 &12 ('te [ 6" (it/chip T 6" chip/9-

2001 2&6 *('te [ &12 *(it/chip T " chip/9-

-!mpen%ted i '!u ell %t le%t 16 time m!re 9-S

S !r i '!u ind neD %pplic%ti!n =Q*#:A c%rAS?

2010 " G('te [ 6" G(it/chip T 0.& chip/9-

N! need !r uch % l%rge mem!r' chipS

S unle '!u ind neD %pplic%ti!n =3) vide!S?

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9!Der c!numpti!n9!Der c!numpti!n

9!Der =O/cm2?

1

10

100

1

1.&µ LineDidth1µ 0.,µ 0.&µ 0.3&µ 0.2&µ 0.18µ 0.13µ 0.1µ

386"86

9 9 9r!

9 II 9 III 9 "7!t pl%te

Nucle%r re%ct!r

9r!ce!r %rchitecture deign driven (' mem!r' (!ttlenecJ p!Der pr!(lemW

NevertheleA Xc!!ling t!DerY i nece%r'W

© red P#%%ac/. Keyn#te at Micr#

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-!!ling t!DerM

© DHBK 2005




Let u d! % c%lcul%ti!n

7!D l!ng c!uld % G:* uing % 9entium 3 =h%rdl' p!Derulen!ughS? l%t !n % ingle (%tter' ch%rgeU

-%p%cit' ! % (%tter'600 m+h [ "4 T 2"00 mOh

9!Der c!numpti!n 9entium 3 "& O

;ne ch%rge l%t !r S 3 minuteWWW Let u turn the c!mput%ti!n upide d!DnOe D%nt % G:* t! l%t !r 2"0 h!ur !n % ingle ch%rge.

7!D much p!Der m%' (e c!numed (' the pr!ce!rU

-%p%cit' ! % (%tter'

600 m+h [ "4 T 2"00 mOh 9!Der c!numpti!n pr!ce!r 10 mO

9!i(le vi% peci%liC%ti!n t! the %pplic%ti!ndedic%ted h%rdD%reS

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:umm%r' !n techn!l!gic%l trend:umm%r' !n techn!l!gic%l trend

#echn!l!gic%ll' pe%ingA De c%n h%ve the %me

exp!nenti%l ev!luti!n !r %n!ther dec%de #hi give u %t le%t " dec%de ! exp!nenti%l

ev!luti!nA never een in hit!r'

nd@uer price t%'ed the %me !r even decre%ed

:ince 30 'e%rA the price !r % (r%nd neD pr!ce!r i1000 Q:)

:! %r !r the g!!d neDS

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)eign iue)eign iue

1>80 1>8& 1>>0 1>>& 2000 200&

#ime

9er!rm%nce

1

10

100

1

10

100

1*

&&V/'e%r

)eignc!mplexit'

10V/'e%r

)eignpr!ductivit'

G%p

Qn!rtun%tel'A G!rd!n *!!reY l%D i %l! v%lid !r thedeign c!mplexit'A Dhich d!u(le ever' 18 m!nthS

S %nd D!reA deign pr!ductivit' d!u(le !nl' ever'

10 'e%r

© DHBK 2005



)eign iue)eign iue

Oe c%n (uild exp!nenti%ll' c!mplex circuitA (ut

De c%nn!t deign them)eign ! 9entium " 8 'e%rA during l%t 2 'e%r Dith %

te%m ! 1000 per!n

Oh! c%n %!rd thiUUU

© DHBK 2005










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© DHBK 2005

ể



Gi i thi u v vi 5i u hi nớ ệ ề ề ểGi i thi u v vi 5i u hi nớ ệ ề ề ể

4i 5i u hi n T -9Q K B nh K cc h i gh\p n iề ể ộ ớ ố ố

ng! i vi K cc h i ch c n]ngạ ố ứ 9;*

+*

+)-/)+-

#imer

B t ! xung nh pộ ạ ị 9O*

Q+#

Q:B

...

© DHBK 2005

ề ể



4i x lý v. 4i 5i u hi nử ề ể4i x lý v. 4i 5i u hi nử ề ể

4i x lý l$ m t -9Q 5 c d ng tr!ng cc m'ử ộ ượ ử ụ

t^nh. -c vi ( 5i u hi n v$ cc ( vi x lý c_ (% 5i mộ ề ể ộ ử ể

hc nh%u ch^nh %ui n tr`c ph n c ngA ph m viế ầ ứ ạng d ngA v$ 5 c 5i m t p l nh.ứ ụ ặ ể ậ ệ

i n tr`c ph n c ng * t ( vi x lý ch l$ m t -9Qế ầ ứ ộ ộ ử ỉ ộ5 n l tr!ng hi m t ( vi 5i u hi n l$ m t I- ch %ơ ẻ ộ ộ ề ể ộ ứ -9Q v$ cc m ch ng! i vi ch^nh c % m t m' t^nhạ ạ ủ ộh!$n ch nh =nh +*A ;*A gi%! di n n i ti pA gi%!ỉ ư ệ ố ế

di n !ng !ngA ( 5 nh th iA m ch x lý ng t?ệ ộ ị ờ ạ ử ắ ng d ng 4i x lý th ng 5 c dang nh m t -9QỨ ụ ử ườ ượ ư ộ

tr!ng cc m' t^nh tr!ng hi cc vi 5i u hi n 5 cề ể ượ d ng tr!ng cc thi t ( nh 5 5i u hi n ccử ụ ế ị ỏ ể ề ểh! t 5 ng.ạ ộ

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ề ể



4i x lý v. 4i 5i u hi nử ề ể4i x lý v. 4i 5i u hi nử ề ể

# p l nhậ ệ

# p l nh c % vi x lý thin v x lý d li u.ậ ệ ủ ử ề ử ữ ệ-h`ng c_ th l$m vi c v i " (itA ('teA D!rdA th m ch^ể ệ ớ ậ

d!u(le D!rd.

-h 5 5 % ch ch! ph\p tru' nh p cc m ng d li u l nế ộ ị ỉ ậ ả ữ ệ ớ( ng cch d ng c!n tr v$ 5 % ch !et.ằ ử ụ ỏ ị ỉ

# p l nh c % vi 5i u hi n dang 5 5i u hi n ccậ ệ ủ ề ể ể ề ểtru' nh p v$! v$ r%.ậ-h`ng c_ cc l nh ch! ph\p thi t l p v$ x! cc (itệ ế ậ

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:erie c!ntinuedF t'pic%l %pp. m!demA multimedi% 1>>>A 0.18 µmA &*LA 3&2 pinA 2&0 *7CA 1.84A 1.>OA E130 :uper c%l%r =8 Intr./c'cle?A 2000 *I9:A c%le Dell till ,00 *7C =6000

*I9:? ;ptimum ch!ice Dhen %ll d%t% it in !n@chip mem!r'

,i9ed MU+

16916:;32

,i9ed MU+

16916:;32

,i9ed (+U

32)32:;40

,i9ed (+U

32)32:;40

,i9ed (+U-branch

32)32:;40

,i9ed (+U-branch

32)32:;40

integer (CU

32)32

integer (CU

32)32

2916KByte D:(M

A!had# %#ad

2916KByte D:(M

A!had# %#ad

2916KByte D:(M

A!had# %#ad

2916KByte D:(M

A!had# %#ad

29128KB P:(M

A!had# %#ad

( - c%#c/ "$&"

4 channe% DM(

2 !eria% "#rts

2 i&ers

*9t &e&#ry

inter,ace

data

address1E

32

*9"ansi#n b$s

data

address23E

32

*9terna% &e&#ry

© DHBK 2005

#ex% Intrument #*:320-6203#ex% Intrument #*:320-62037igh end <ixed 9!int7igh end <ixed 9!int




:erie c!ntinuedF t'pic%l %pp. (%e t%ti!n 2000A 0.1& µmA &*LA 18 mm2 p%c%ge iCeA 300 *7CA 1.&4A 1.&O :uper c%l%r =8 Intr./c'cle?A 2"00 *I9:

;ptimum ch!ice Dhen %ll d%t% it in !n@chip mem!r'

,i9ed MU+

16916:;32

,i9ed MU+

16916:;32

,i9ed (+U

32)32:;40

,i9ed (+U

32)32:;40

,i9ed (+U-branch

32)32:;40

,i9ed (+U-branch

32)32:;40

integer (CU

32)32

integer (CU

32)32

2964KByte D:(M

A!had# %#ad

2964KByte D:(M

A!had# %#ad

2964KByte D:(M

A!had# %#ad

2964KByte D:(M

A!had# %#ad

256KByte P:(M

128KB P:cache-(M

( - c%#c/ "$&"

4 channe% DM(

2 !eria% "#rts

2 i&ers

*9t &e&#ry

inter,ace

data

address1E

32

*9"ansi#n b$s

data

address23E

32

*9terna% &e&#ry

© DHBK 2005

#ex% Intrument #*:320-6211#ex% Intrument #*:320-62117igh end <ixed 9!int7igh end <ixed 9!int




:erie c!ntinuedF t'pic%l %pp. m!demA multimedi% 1>>>A 0.18 µmA &*LA 2&6 pinA 1&0 *7CA 1.84A 1.&OA E2& 4LIOA 1.2 GI9:F che%p =2&E in X>>A &E in X01? ;ptimum !r r%nd!m %cce t! l%rge mem!r' p%ce 80V ! per!rm%nce ! -6x Dith ininite !n@chip mem!r'

,i9ed MU+

16916:;32

,i9ed MU+

16916:;32

,i9ed (+U

32)32:;40

,i9ed (+U

32)32:;40

,i9ed (+U-branch

32)32:;40

,i9ed (+U-branch

32)32:;40

integer (CU

32)32

integer (CU

32)32

4KByte +1 Dcache

A2 ay set ass#c

4KByte +1 Pcache

A2 ay set ass#c

4916KByte +2

cache Adirect &a"

( - c%#c/ "$&"

16 channe% DM(

2 !eria% "#rts

2 i&ers

*9t &e&#ry

inter,ace

data

address1

16

H#st "#rt

data

address30

32

*9terna% &e&#ry

© DHBK 2005

#ex% Intrument #*:320-6"16#ex% Intrument #*:320-6"167igh end <ixed 9!int7igh end <ixed 9!int




:%mple Zune 2001A 0.12 µmA 6 L*A &32 pinA "00 *7C@600 *7CA 1.24At%rt %t >&E in v!lume

:uper c%l%r =8 Intr./c'cle?A 3200@"800 *I9: :u(@D!rd =8(it !r 16(it? p%r%llelim :peci%liCed intr. G%l!i <ield *ultA (it m%nipul%ti!n

,i9ed MU+

16916:;32

,i9ed MU+16916:;32

,i9ed (+U

32)32:;40

,i9ed (+U

32)32:;40

,i9ed (+U-branch32)32:;40

,i9ed (+U-branch

32)32:;40

integer (CU

32)32

integer (CU32)32

( - c%#c/ "$&"64 channe% DM(

3 !eria% "#rts

3 i&ers

16 Kbyte +1P

direct &a""ed

16 Kbyte +1D2ay d$a% access

1 Mbyte (M-+2

4ay

D$a% *M' 7 HP' 7

PC' 7 Ut#"ia

data

addressE

32

HP'

data

address30

64

*9terna% &e&#ry

data

address30

16

@iterbi dec#der

acce%erat#r

$rb# dec#der acce%erat#r

© DHBK 2005

#ex% Intrument #*:320-6,01#ex% Intrument #*:320-6,017igh end <l!%ting 9!int7igh end <l!%ting 9!int



7igh end <l!%ting 9!int7igh end <l!%ting 9!int

:erie c!ntinuedF t'pic%l %pp. vide! c!mprei!n

Intr!duced 1>>8A 0.18 µmA &*LA 3&2 pinA 16, *7CA 1.84

:uper c%l%r =8 Intr./c'cle?F 4LIOF 1 G<L;9

<!reeen !r X00 &0E =c. -6211? J 3 G<L;9 =c. -6202?

i9ed-%#at MU+

32932-64964

i9ed-%#at MU+

32932-64964

i9ed-%#at (+U

32)32-64)64

i9ed-%#at (+U

32)32-64)64

i9ed (+U-Branch

%#at 1-9 7 9

i9ed (+U-Branch

%#at 1-9 7 9

integer (CU

32)32

integer (CU

32)32

16KByte D:!(M

16KByte D:!(M

16KByte D:!(M

16KByte D:!(M

64KByte

P:!(M-cache

( - c%#c/ "$&"

4 channe% DM(

!eria% inter,ace

2 i&ers

*9t &e&#ry

inter,ace

data

address1

16

H#st inter,ace

data

address23

32

*9terna% &e&#ry

© DHBK 2005 #ex% Intrument #*:320-6,11#ex% Intrument #*:320-6,117igh end <l!%ting 9!int7igh end <l!%ting 9!int



7igh end <l!%ting 9!int7igh end <l!%ting 9!int

:erie c!ntinuedF t'pic%l %pp. vide! c!mprei!n 2000A 0.18 µmA &*LA 2&6 pinA 100 *7CA 1.84A 2OA E20 4LIOA 600 *<l!p ;ptimum !r r%nd!m %cce t! l%rge mem!r' p%ce 80V ! per!rm%nce ! -6x Dith ininite !n@chip mem!r'

i9ed-%#at MU+

32932-64964

i9ed-%#at MU+

32932-64964

i9ed-%#at (+U

32)32-64)64

i9ed-%#at (+U

32)32-64)64

i9ed (+U-Branch

%#at 1-9 7 9

i9ed (+U-Branch

%#at 1-9 7 9

integer (CU

32)32

integer (CU

32)32

( - c%#c/ "$&"

4 channe% DM(

!eria% inter,ace

2 i&ers

*9t &e&#ry

inter,ace

data

address1

16

H#st inter,ace

data

address23

32

*9terna% &e&#ry4KByte +1 Dcache

A2 ay set ass#c

4KByte +1 Pcache

A2 ay set ass#c

4916KByte +2

cache Adirect &a"

© DHBK 2005

#ex% Intrument#ex% Intrument



M!320C541 A15

© DHBK 2005




M!320C545 A15

© DHBK 2005




M!320C80 A14

© DHBK 2005










*!t!r!l%

9hilip


© DHBK 2005 *!t!r!l% *-&6xxx*!t!r!l% *-&6xxx+udi! <ixed 9!int+udi! <ixed 9!int



+udi! <ixed 9!int+udi! <ixed 9!int

2" (it G!r %udi! 16 (it d%t% K !verGl!D

16 #r 24 bit

integer CPU

+##" c#ntr#%%er !e%ecti#n #, "eri"hera%s

(DC. D(C. c#&&.

ti&ers. P'.

(CU

P(M

>(M

?(Maddress

data

24

18

(CU

© DHBK 2005

*!t!r!l% *-&6002*!t!r!l% *-&6002



© DHBK 2005

*!t!r!l% *-&6166*!t!r!l% *-&6166



© DHBK 2005






*icr!c!ntr!ller4i 5i u hi n c % *!t!r!l%ề ể ủ7 vi 5i u hi n 80&1ọ ề ể7 vi 5i u hi n +4ọ ề ể 9:;-



*!t!r!l%

9hilip


© DHBK 2005 9hilip 4:9@19hilip 4:9@1<ixed 9!int 4ide!<ixed 9!int 4ide!




12 (it G!r vide! 8 (it d%t% K !verGl!D

-l!c <reHuenc' 2, *7C

1 intructi!n per %mple peri!d G!r 7)#4A

2 intructi!n per %mple peri!d G!r #4

12 bit

integer (+U

12 bit

integer (+U

512912 bit

Me&#ry e%e&ent

512912 bit

Me&#ry e%e&ent

12 bit

integer (+U10918 cr#ss:bar

12

12

10





(+U (+U (+U M* M*

$t"$ts

'n"$ts

© DHBK 2005

9hilip 4:9@19hilip 4:9@1<ixed 9!int 4ide!<ixed 9!int 4ide!

$t"$t

's




(+UMe&#ry

*%e&ent

206 #r%nit!r

1.1O diip%ti!n

2, *7C cl!c 1,6 pin

Intr!duced in 1>>1




<ixed 9!int 4ide!

12 (it G!r vide! 8 (it d%t% K !verGl!D

-l!c <reHuenc' &" *7C

2 intructi!n per %mple peri!d G!r 7)#4A

" intructi!n per %mple peri!d G!r #4

22950 cr#ss:bar 22

12

12

12 bit

integer (+U1

12 bit

integer (+U2

512912 bit

Me&#ry e%e&ent1

512912 bit

Me&#ry e%e&ent2

12 bit

integer (+U12

512912 bit

Me&#ry e%e&ent4




<ixed 9!int 4ide!

1.1& * #r%nit!r

&O diip%ti!n

&" *7C cl!c GreHuenc'

208 pin

Intr!duced in 1>>"

© DHBK 2005

:!n' Gr%phic ngine:!n' Gr%phic ngine



9l%'t%ti!n 3

:t%tu pr!t!t'pe in 2001 28,.& *#;

2&6 *(it !n@chip em(edded )+*

2000@(it Dide intern%l (u

"62 mm2

180 nm -*;:

© DHBK 2005






*icr!c!ntr!ller4i 5i u hi n c % *!t!r!l%ề ể ủ7 vi 5i u hi n 80&1ọ ề ể7 vi 5i u hi n +4ọ ề ể 9:;-



*!t!r!l%

9hilip


© DHBK 2005

#rend !r ):9 pr!ce!r#rend !r ):9 pr!ce!r




N! neD gener%ti!n th%t repl%ce !ld gener%ti!nA

(ut multiple c!@exiting %rchitecture line O!rd length %pplic%ti!n dependent+ut!m!tive 16@(it ixed p!int =e.g. -2x?

:peech 32@(it l!%ting p!int =e.g. -30?

+udi! 2"@(it ixed p!int =e.g. *-&6?

#elec!mmunic%ti!n 16@32 (it ixed p!int =e.g. -&xA -6x?

4ide! 12@32 (it ixed p!int =e.g. -8x?

:ingle %rchitecture line i Dh!le %mil' dierent mem!r' J !n@chip peripher%l

!r em(edded %pplic%ti!n =c. micr!c!ntr!ller?

© DHBK 2005





)eterminitic (eh%vi!r

n! c%cheA n! virtu%l mem!r'A (ut !n@chip +* (%n n! !ut@!@!rder executi!n

del%'ed (r%nch predicti!n

Incre%ing %ddre p%ce 12 @P 32

*ultiple uncti!n !n ingle chip -9QA <9QAmultiple +* (%nA +-QA l!!p c!ntr!llerA +)-A)+-A 9O*A eri%l inter%ceA S

;ten pr!vii!n !r p%r%llel pr!ceing

Documents

Microprocessor Final Ver1 Part7