Microprocessors. Architectures and Applications

Eugen LUPU

Annamaria MES ARO$

Aurel SUCIU

MICROPROCESSORS

Architectures and Applications

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Editura RISOPRINT Cluj-Napoca 2003

Contents

CONTENTS PREFACE ..... ... . ................................... ............ ............................ 3

1. X86 PROCESSORS IDENTIFICATION .. . ........ .. ................ . ................ 51.1. Introduction 1.2. CPUID detection 1.3. CPUID outcome 1.4. The processor signature 1.5. The processor feature flags 1.6. The processor name 1. 7. The processor serial number 1 .8. The access to the processor serial number 1.9. Applications 1.1 a.Exercise

2. THE TIMER CIRCUIT ... . ................... ................... .......................... 192.1. Functional Description 2.2. The timer pin assignment 2.3. The timer circuit programming 2.4. The timer circuit in PC 2.5. Applications and exercises

3. THE REAL TIME CLOCK AND THE CMOS MEMORY .. .. ... ...... . ... . ....... 293.1. General information 3.2. MC 146818 circuit . 3.3. The content of the memory and its accessing mode 3.4. System services for CMOS - RTC data access 3.5. Applications and exercises

4. THE PROGRAMMABLE INTERRUPT CONTROLLER ................ . .. .. . .... 394.1. Interrupts in data processing 4.2. The 8259A overview 4.3. PIC Programming 4.4. 18259A controller modes 4.5. The PIC employment in PC 4.6. Exercise

5. APPLICATIONS ON THE INTERRUPT SYSTEM ... ........... . .... . ............ 515.1. The application support 5.2. Exercise

6. OMA 18237A CONTROLLER ..... . .. . ................... . ......... ....... . . .. . . . ...... 556.1. DMA transfer principle 6.2. OMA controller overview 6.3. Functional Description of DMA Controller 6.4. Connecting the 18237 A controller. 6.5. The DMA controller in IBM-PC 6.6. Exercise

Contents

7. OMA DATA TRANSFER ON PC-AT ................................................. 71 7.1. The application description 7.2. The program 7.3. Exercise

8. DESIGNING THE ISA-BUS COMPLIANT BOARDS ............................ 79 8.1. Buses in PC 8.2. The ISA bus 8.3. General considerations for designing a board on ISA-bus 8.4. Application 8.5. Exercise

9. THE PARALLEL PORT IN IBM-PC COMPUTERS ....... . . . . . . . . .. .. . . . ... .... 91 9.1. Generalities regarding the parallel port 9.2. The Standard Parallel Port (SPP) 9.3. Data transfer modes between standard ports 9.4. Parallel port-related BIOS services 9.5. Extensions of the parallel port 9.6. Application 9.7. Exercise

10. THE PARALLEL PORT IN IEEE 1284/94 STANDARD ...................... 103 10.1. IEEE 1284-1994 standard 10.2. Enhanced Parallel Port (EPP) 10.3. Extended Capabilities Port (ECP) 10.4. Application 10.5. Exercise

11. ON THE MEMORY IN PC SYSTEMS ............................................. 117 11.1. The memory organization 11.2. The PC memory map 11.3. Applications 11.4. Exercise

12. THE CACHE MEMORY ............................................................... 129 12.1. An overview of cache memory 12.2. Architecture of the cache memory 12.3. Cache memory components 12.4. Cache memory organization 12.5. The Pentium processors cache memory 12.6. Cache memory characteristics identification 12.7. Exercise

APPENDIX 1: X86 PROCESSORS IDENTIFICATION ...................... 141 APPENDIX 2: THE REAL TIME CLOCK AND THE CMOS MEMORY ... 144 APPENDIX 3 : DESIGNING THE ISA-BUS COMPLIANT BOARDS ...... 149 APPENDIX 4: THE PARALLEL PORT IN IBM-PC COMPUTERS ... . .... 151 APPENDIX 5: THE CACHE MEMORY ......... . . ..... .............. .............. 154

REFERENCES .... . .................. . ............ . . . . ........ . .. ...... . . . . . . . . . . ........ 157

PREFACE

This book is sp l it i nto 1 2 chapters, which present aspects closely

connected to the PC hardware . Besides the topic d iscussed , each chapter

presents severa l appl ications l inked to that topic. The book presents

aspects concern ing the processor, the memory, the programmable

control lers employed , the buses and the paral le l port of the PC .

It is recommended to the students i n e lectrical engineering and to

anyone interested to get deeper understanding of computers hardware .

The fi rst chapter covers the different aspects regard ing the

identification of the processor used in the PC , its type and resources that

can be obta ined using the CPU I D instruction .

The second one presents the t imer circuit ( 18253/8254 ) , its

employment mode and its role in a PC. Some appl ications us ing this circu it

are proposed as wel l .

The Real Time Clock and the CMOS memory (MC1 468 1 8) are

detai led in the thi rd chapter.

Chapters 4 and 5 describe the Programmable I nterrupt Control ler

( 18259A) and propose some appl ications on the PC i nterrupt system .

Aspects on the D i rect Memory Access Control ler ( 18237 A) and a OMA

data transfer appl ication on a PC-AT are presented i n the fol lowing two

chapters.

In chapter 8 , an overview of the PC buses is envisaged , focusing on

the ISA-AT bus. Aspects on design ing the ISA bus compl iant cards and a

design example are a lso presented .

The chapters 9 and 1 O present the PC Standard Parallel Port and its

enhanced version described in the IEEE 1284/94 standard. Some

appl ications of these peripherals are d iscussed as wel l .

MICROPROCESSORS

The fol lowing chapter deals with the memory organ ization i n PC

systems and with the way of connecting a memory extension (SRAM and

EPROM) to the PC- ISA bus.

The role and the operation princip le of the cache memory and the

way its characteristics can be obtained by using the CPU ID instruction are

covered in the l ast chapter.

The attached appendices conta in data book information concern ing

some circu its and devices used in the presented appl ications.

The authors wish to thank prof. Sergiu NEDEVSCHI and assoc. prof.

Zoltan BARUCH from the Computer Science and Automation Facu lty of

C luj-Napoca for reviewing the materia l and to assoc. prof. GRANESCU

MARINELA for the l ingu istic review.

We a lso thank to a l l of those who helped us in pub l ish ing th is book,

especial ly to our sponsors the compan ies SOJZA (Sighetul-Marmafiei) and

INFOMIN (Baia-Mare) and to Mr. Cristian Vasi/ache for h is contri bution to

the figure editi ng .

4

Ph .D. eng . Eugen LUPU

E lectron ics& Telecommunications

Faculty of Cluj-Napoca

Communications Department

Eugen [email protected] . ro

XB6 Processors Identification

1. X86 PROCESSORS IDENTIFICATION 1.1 Introduction

At the same time with I ntel Arch itecture progress, in new processor generations and models it became essential to provide a software modality to detect the processor features. This mechanism of identification evolved at the same time with I ntel architecture: 1 . In itially, I ntel publ ished code sequences which could detect minor

implementations or differences in architecture for processor generation identification.

2. With 386-processor development, I ntel implemented the identification signature of the processor, which provides the family and the model of the processor.

3. The processor identification signature expanded at one time with the implementation of CPUID instruction for the new versions of 486. This instruction provides not only the processor signature but also information about the offered faci lities, the producer, the type of the processor, the model number, stepping and cache memory dimension and organization .

1.2 CPUIQ detection

Starting with the I ntel 486 processor fami ly, the processors are able to execute the CPU ID instruction . To execute the CPUID instruction , the program has to establ ish if the processor supports the instruction . This can be done in two ways: The instruction is executed and then one verifies if there appeared an

exception due to an i l legal operation One verifies if the ID flag 21st bit of EFLAG register (see Appendix 1 ) can

be modified . If the program can change this flag value, then the processor supports the CPU ID instruction . For this test the fol lowing sequence can be used:

pushfd pop eax mov ebx , eax xor eax , 0 0 2 0 0 0 0 0h push eax ' , popfd pushfd pop eax cmp eax , ebx j z NO CPUID

saves EFLAGS on s tack l oads EFLAGS in EAX saves EFLAGS in EBX Sets ID bit ( 2 1 s t ) saves EAX on stack EFLAGS=EAX saves EFLAGS on stack l oads EFLAGS in EAX has the 21st bit change? Z= 1 CPUID is not supported

5


1.3 CPUID outcome

The CPUID instruction has multiple functions, depending on the content of EAX register. The execution of CPUID for different values in EAX provides a complete image of the processor and its capabilities. The functions can be divided in two categories: standard functions, that provide usual information of x86 processors and extended functions, that provide additional information about the producer (Intel, AMO etc). To determine the highest value supported by the CPUID instruction in the EAX register for the standard functions, the program must set the register value to "O" and then execute the CPUID instruction as follows:

MOV EAX,OOh CPU ID

After the execution of this sequence, a value is returned in EAX as a parameter of CPUID; this is the maximum value for EAX. The extended functions of CPUID instruction were introduced by AMO; they return additional information about the processor. To determine the highest value accepted in the EAX register by the CPUID instruction, in order to return the extended information about the processor the program must set EAX register to "8000_0000h", then run the instruction that returns the needed value in EAX.

MOV EAX, eopoOOOH CPU ID

The extended functions are supported by the processors provided by other producers too, starting with:

AMO K6 K6-2 Cyrix GXm Cyrix Ill "Joshua" IDT C6-2 VIA Cyrix Ill Transmeta Crusoe Intel Pentium 4

Additionally, one can check the ASCII string that identifies the producer. If EAX=O, the CPUID instruction returns the producer identifier in the EBX, EDX and ECX registers. These registers contain the ASCII string "Genuinelntel" (see Table 1 . 1 ) for Intel processors or different producer specific strings (see Table 1.2).

6

X86 Processors Identification

31 ... 2 3 ... 15 ... 7 0 ECX l (6C) e (65) t (74) n (6e) BDX I (49) e (65) n (6e) i (69) BBX u (75) n (6e) e (65) G (47)

Table 1.1 INTEL ID string

ID string Producer Genuineintel Intel UMC UMC UMC UMC Authent icAMD AMD Cyrixinstead Cyr ix NexGenDriven NexGen CentaurHauls Centaur RiseRiseRise Rise Techn. GenuineTMx86 Transmeta

Table 1. 2 Processors producers ID s tring

The standard and extended functions are presented in Table 1 .3 . Differences may occur with different producers, certain functions being supported only by some processors (example 8084_000xh for Transmeta or 8FFF _FFFxh for AMD), therefore specific documentation is recommended.

Parameter Information re turned by CPUID instruction EAX"O EAX the highest value recognized by CPUID

EBX: EDX: ECX ID of the producer (ASCII string) EAX"l EAX the processor signature: 32 MSB (95-64) from

the 96 bits of the processor serial number EDX processor feature flags EBX Brand ID on bits 7 .. 0

EAX,,2" EAX:EBX:ECX:EDX information about cache and TLB descriptors (Translation Lookaside Buffer)

EAX,,3" EDX:ECX the 64 LSB from the 96 bits of the processor serial number

EAX .. aooo_ooooh EAX the highest value recognized by CPUID for extended functions

EAX .. 0000_0001h EAX extended processor signature and extended feature flags

EAX,,8000 0002h EAX:EBX:ECX:EDX processor name EAX .. aooo 0003h EAX:EBX:ECX:EDX processor name EAX,,8000 0004h EAX:EBX:ECX:EDX processor name EAX .. 0000 0005h" Ll TLB/ cache information EAX .. aooo 0006h" L2 TLB/ cache information EAX .. aooo 0007h" Advanced power management feature lags EAX .. aooo 0008h" Physical address and linear address size

* Intel proce s sors #AMD proces sors Table 1 . 3 CPUID outcome

7


Figure 1. 1 is a capture of the values returned by an application executed on a PC with Intel processor, for EAX set at different values.

: ) EAX =00000003 : EAX =00000686 : EDX=038?F9FF

Flags =000B?046

EAX =03020101 EBX=00000000 ECX =00000000 EDX=0C040882

Fig 1.1 Processor identifying application

1.4 The processor signature

Beginning with the Intel 486 family, the processor will return an identification signature in the EDX register after RESET (see Fig 1 .2). The identification signature is a 32 bits value, consisting of 8 fields; two of them are reserved (see Fig 1 .2}. EDX

31 .. 28 27 .. 20 19 1615 14 13 12 11 8 7 - 4 3 - 0 Family Model Type Family Model ID extension extel\sion code number version

Fig.1.2 The EDX register value after RESET

The processors which recognize CPUID return the processor -------identification-filg!l_ture in EAX for EAX=4_ hsee Fig 1 . 1)_,_Figure 1.2 indicates the signature formatTorTnTel processors s arting with 486. The Table A 1 in Appendix 1 shows the values returned to EAXJor the Intel processors. The processor type specified by th_e_biisJD positions 12_JJQ _13 indicates if the proc-ess6r is OEM original Overdrive orTfTfls-a-aual processor (capable of working simultaneously with another processor in a system). Table 1.4 indicates the returned bit values in the positions 1_2 and 13 of the EAX register, depending on the processor type:

_

_ _

Value Description 00 Original OEM processor 01 Overdrive processor 10 Dual processor 11 Intel reserved

Table 1.4 The processor type (bits 12 and 13)

8


The family values specified by the bits 8 1 1 indicate if the processor belongs to I ntel 386 family, I ntel 486, Pentium, P6 or Pentium 4. The P6 processor family includes all the processors based on Pentium Pro architecture that have a family code equal with 6 and Pentium 4 processors have the code F .

The model number specified by the bits 4 . . . 7 indicate the processor family mos from indicate the version number of that model . Older versions of I ntel 486 processors SX/DX/DX2 do not know CPUID, so they can return the signature only on RESET.

1.5 The processor feature flags When EAX=1 , CPUID wil l load the EDX register with the processor

feature or resources flags. The current flag indicates which features the processor supports. Table 1 .5 indicates the different values of the features flags. For future processors flags values one should consult the reference guide or user guide or own documentation . By testing the processor feature flags in developed appl ications, the software can detect and avoid eventual errors and incompatibi l it ies. it j Name I Description when I flag=l Comments

0 FPU Floating point unit The processor contains on chip a FPU on-chip which supports the 387 coprocessor

floating point instructions set 1 VME Virtual Mode The processor supports extensions for

extension 8086 virtual mode 2 DE Debug. Extension The processor supports I/O

interruption 3 PSE Page size extension The processor supports 4MB pages 4 TSC Time stamp counter RDTSC instruction is supported

including CR4.TSR bit for access/ privHege control

5 MSR Model Specific Model specific egisters are registers implemented with RDMSR,WRMSR

instructions 6 PAE Physical Address Physical addresses greater than 32

extension bits are supported 7 MCE Machine check Machine check exception 18 and

exception CR4.MCE bit are supported 8 cx0 CMPXCHG8 instruction The compare and exchange instruction

supported CMPXCHG8, on 8 bits is supported 9 APIC On-chip APIC The processor contains a software-

hardware suooorted accessible local APIC 10 - Reserved -11 SEP Fast system call Indicates if the processor supports

SYSENTER SYSEXIT instructions 12 MTRR Memory type range The processor supports memory type

registers range registers (MTRR CAP register)

9


13 PGE Page Global Enable The global bit from PDE and PTE are supported, indicating TLB entries. CR4.PGE bit controls this feature

14 MCA Machine check Machine check architecture is architecture supported (MCG CAP register)

15 CMOV Conditional move The processor supports CMOSVcc and if instruction FPU flag (bO)is set, it supports supported FCMOVCC and FCOMI instructions too

16 PAT Page attribute table Indicates if the processor supports PAT- allows an Operation System to specify attributes of memory on 4KB granularity through a linear address

17 PSE- 36-bit Page size Indicates if the processor supports 36 extension 4MB pages capable to access physical

addresses greater that 4GB 18 PSN The processor serial The processor supports a 96 bits

number is present serial number and this option is and enabled activated

19 CLFSH CLFSH instruction is Indicates that the processor supports supported the CLFSH instruction

20 - Reserved -21 DS Debug store The processor can rewrite the history

of the branch to/from addresses into a memory buffer

22 ACPI Thermal Monitor and The processor implements internal Software Controlled MSRs for processor temperature Clock Facilities monitoring and performance modulation supported under software control

/23 MMX Intel Architecture The processor supports MMX technology '--"' MMX technology specific instruction set

Supported 24 FXSR Fast floating point Indicates if the processor supports

save and restore FXSAVE and FXRSTOR instructions S' SSE Streaming SIMD The processor supports Streaming extensions supported extension SIMD to Intel architecture

SSE2 Streaming SIMD The processor supports the streaming extension 2 SIMD extension 2 instructions

27 SS Self-Snoop The processor manages memory conflicts by executing a cache snoop for transactions issued to the bus

28 - Reserved -29 TM Thermal monitor The processor implements the thermal

supported control circuit TCC 30 - Reserved -31 - Reserved -

Table 1 . 5 The f eature flags values reported in the EDX regi ster

10


1.6 The processor name

At the same time with Pentium Ill, Pentium I l l Xeon and Intel Celeron model 8, Intel extended the identification concept by adding the Brand ID information, which is an 8-bit number accesible by CPUID instruction. When EAX=1, CPUID loads the processor Brand ID in the O -7 bits in EBX. This field was introduced to eliminate identity ambiguities (such as the difference between Pentium II and Pentium II Xeon - 51 2K L2 cache), providing a unique value for every processor name. Table 1.6 shows the correspondence between the bits from the EBX and the corresponding names.

EBX o ... 7 Description ooh Not supported Olh Int e l Celeron processor 02h Int e l Pentium I I I processor 03h Int e l Pentium I I I Xeon proce s sor 04 h Intel Pent ium I I I proces s o r 08h Intel Pent ium 4 proc e s sor OEh Intel Xeon proce s sor A l l other values Re served

Table 1 . 6 Brand ID corresponding to values in EBX (bits 7 . . 0)

1. 7 The processor serial number

The Pentium Ill and Pentium Ill Xeon processors extend the identification concept by attaching the processor serial number. The serial number is a 96-bit number accessible by CPUID. This number can be used by applications to identify the processor and the system. The serial number of the processor creates a software identity accessible to an individual processor. Combined with other features, the serial number can be applied to user identification. Applications include authentication data, backup/restore protection, file access protection or documents exchange between users. The serial number is a modality to check the products. In the case of system service, the serial number can be used to differentiate users or for error report.

The serial number provides an identifier for the processor but one should not consider it as a unique number. There are some ways that can report wrong serial numbers. For example, if a processor operates outside a specified operating system, the processor will not read correctly its serial number. BIOS or software improper operations can produce wrong serial numbers.

1 1


1.8 The access to the processor serial number

To determine if the processor series' characteristic is supported, the software must execute CPU I D with the EAX register set to "1":

MOV EAX , O lH CPUID

After running CPU I D , EDX contains the feature flags. If the j 8th bit fr fla is 1, the seri n_ller of !!Je pro.@"'-_or is suppofled. If the 18th bit from the register is O, thr.o.c_es.sor serial 11umbefTsnoi supp_orted or ltisdisaI)ledotnerwiSefue-serial number is supported. This bit can be conlrolled from the (for the newer processors) or by specific appliCatiOns provided by the producer. To disable the access to the !Iial nJ1ter one must set to "1" th--21.s.t_Qii_gf BBL_CR_CTL MSR register (ModeTSpecffiCReglsterfrOm-address 119h). Once set, this bit cannot be modified until the processor reset. Tne next sequence is an example that can be used to disable the access to the processor serial number:

MOV ECX , 1 1 9h ..

RDMSR OR EAX , 0 0 2(')0,0 0 0h WRMSR

;reads MSR ;set s the 2 1 s t bit ;writes MSR

The 96-bit serial number is the concatenation of three 32-bit entities. To access the most significant 32 bits of the serial number, the program must set the EAX register to 1 and then execute CPU I D : .

MOV EAX , O lh CPU ID

After running CPU ID , EAX contains the most significant 32 bits (95-64) of the serial number. This value from EAX must be saved before obtaining the other 64 bits of the serial number. In order to access the other 64 bits, the program must set EAX to 3 and then execute CPUID :

MOV EAX , 0 3 h CPUID

After running CPUID , EDX contains the middle 32 bits (63-32) of the serial number and ECX contains the less significant 32 bits (31-0). The program must then concatenate the most significant 32 bits, EDX and ECX before returning the complete serial number on 96 bits. The serial number must be displayed as 6 groups of 4 hex digits.

1 2


1.9 Applications

Analyze the fol lowing programs CPU ID .CPP and CPU I D .ASM and then run it on the PC. Analyze the results .

#pragma hdrstop # inc lude # inc lude #inc lude #inc lude void decode_reg(int ) ; void print reg(int reg ) ; void PrintLeve l Cpuid(int l evel ) ; void cpuid(uns igned inp ) ; unsigned l ong Lax , Lbx , Lcx , Ldx;

void cpuid ( uns igned inp ) {

asm {

} ; }

. 596 mov eax , inp cpuid mov Lax , eax mov Lbx , ebx mov Lcx , ecx mov Ldx , edx

int main( ) {

int i; uns i gned long l i , maxi , maxei; / * Print the information returned by CPUID for the l eve l O * / cpui d(O ) ;

{

maxi =Lax ; / /maximum parameter number for(i= O ; i


printf ( " \n\nDoes not support extended l evel for CPUID " ) ; printf ( 1 1\n\n " ) ;

/ * Producer ID and maximum level supported by CPUID*/ cpuid ( O ) ; print f ("ID : \ " " ) ; for (i= O ; i> ( S *i ) ) ; for ( i= O ; i> ( S *i ) ) ; for ( i= O ; i> ( S *i ) ) ; printf ( " \ " ; CPUID l evel %ld\n " , maxi ) ; //wa it for any key press getch ( l ; exit ( 0 ) ;

/ * Register decoding x void decode_reg ( int x )

register value * /

{ x &= Oxf f ;

printf ("%02x 11,x); } / / Print reg i s ter value void printreg (int reg ) {

decode_reg ( reg >> decode_reg ( reg >> decode_reg ( reg >> decode_reg ( reg ) ;

}

24 ) ; 1 6 ) ; Sl ' I

/ / Print cpuid l evel and returned values void PrintLevel Cpuid (int level ) {

cpuid ( l eve l ) ; print f ( 11\n eax : " ) ;

printreg (Lax) ; print f ( " \n ebx: " ) ;

printreg ( Lbx ) ; print f ( " \n e cx: " ) ;

printreg ( Lex) ; print f ( " \n edx: " ) ;

printreg ( Ldx) ;

1 4


TITLE CPU ID JUMPS . model small . stack 1ooh . data

saved_ cpuid vendor id cpu_type themodel stepping id_ f l ag inte l_proc id_msg Pent ium in tel mode lmsg steppingm sg fami lymsg period data CR int e l id

. code

.8 0 8 6

dd db db db db db db db db db db db db db db db

s tart: mov mov mov and call cal l mov int

get_cpuid proc . 5 8 6

? 12 dup (? ) ? ? ? 0 0 "Thi s system has $ " "Pentium(TM) microprocessor" , 1 3 , 1 0 "Intel Proces sor system " , 1 3 , 1 0 " $"

" $ "

" Mode l : $ " "Version : $"-" Fami ly : $ " 1 1 11 , 1 3 , 1 0 , 11 $ 11 ? , 13 , 1 0 , "$ " "Or iginal Intel "

ax , data ds , ax e s , ax sp not , 3 get_cpuid print ax, 4 c 0 0h 2 1h

set segment reg i s t er set segment reg i s ter al ign stack to avoid AC error

program end

mov id_ f l ag , 1 set ind i cator f l ag for CPU ID

mov cpuid mov

; test for Intel mov mov mov mov mov

compare: repe cmp jne

eax , O

dword ptr producer

dword ptr dword ptr s i , o f fset d i , o f fset cx, l ength

cmpsb

parameter for CPUID

vendor_id , ebx

vendor_ id[+ 4 ] edx vendor_id[ + 8 ] , ecx vendor id intel id intel_id

cx , O cpuid_data

i f Int e l original ecx

15

0

intel_processor : mov mov

cpuid_data :

intel_proc , 1 [intel - 1 ) , '

mov eax , 1 cpui d mov saved_cpui d , eax and eax , O F O OH shr eax, 8 mov cpu_type , al

mov eax,saved_cpuid mov stepping,al and stepping,OFH

mov eax,saved_cpuid mov themodel,al and themodel,OF shr themode l , 4

end_get_cpuid : . 8 0 8 6

ret get_cpuid

..

endp


adds space for message " original Inte l "

save for u l terior use mask informat ion about family

saves CPU type

recover data

mask model number

mask informat ion about model

; This procedure displays the processor features

print proc push ax push bx push ex push dx ; ver i fy i f the processor supports CPUID cmp id_f l ag,1 ; if yes disp l ay informat ion j e print_cpuid_data mov dx,of fset id_msg mov ah , 9h int 2 1h display init i a l message

print_cpuid_data : cmp cpu_type,5 j ne print_cpuid_cont mov dx,offset Pent ium mov ah 9 int 2 1h

print_cpuid_cont : mov dx, o f fset fami lymsg display " fami ly : " mov ah 9h int 2 1h

a l , cpu_type mov mov add

byte ptr dataCR,al byte ptr dataCR,3 0H

16

convert t o ASCI I

mov dx , of f set dataCR mov ah 9h int 2 1h mov ' dx , of fset steppingmsg mov ah 9h int 21h mov al , stepping mov byt e ptr dataCR , al add byte ptr dataCR , 3 0H mov dx o f f set dataCR mov ah , 9h int 21h mov dx , of fset modelmsg mov ah , 9h int 21h mov al , themodel mov byte ptr dataCR , al add byte ptr dataCR , 3 0H mov dx , of f set dataCR mov ah, 9h int 21h

end_print : pop dx pop ex pop bx pop ax ret

print endp end start

1.10 Exercise

a. Analyze the results from fig . 1 . 1


display CPU type

di splay "serial no : "

convert t o ASCI I di sp . serial number

display "mode l : "

convert to ASCI I display model number

b. Using the turbo debugger TD32 test the standard and extended functions of the CPUI D instruction . Analyze the results obtained on your PC.

c. If the processor al lows it, determine its serial number d. Study the possibi l ity of accessing the processor serial number.

17


PC CPUs Year Number of transistors

1st. 8086 and 8088 1978-81 29,000 Generation

2nd. 80286 1984 134' 000 Generation

3rd. 80386DX and 80386SX 1987-88 275,000 Generation

4th. 80486SX, 80486DX, 1990-92 1,200,000 Generation 80486DX2 and 80486DX4

5th. Pentium 1993-95 3,100,000 Generation Cyrix 6X86 1996

AMD KS 1996 IDT WinChip C6 1997 3,500,000

5th. Pentium MMX 1997 4,500,000 Generation IBM/Cyrix 6x86MX 1997 6,000,000 Improved IDT WinChip2 3D 1998 6,000,000

6th. Pentium. Pro 1995 5,500,000 Generation AMD K6 1997 8,800,000

Pentium II 1997 7,500,000 AMD K6-2 1998 9,300,000

6th. Mobile Pentium II 1999 27,400,000 Generation Mobile Celeron 18,900,000 Improved Pentium III 9,300,000

AMD K6-3 Pentium III CuMine 28,000,000

7th. AMD original Athlon 1999 22,000,000 Generation AMD Athlon Thunderbird 2000 37,000,000

Pentium 4 2001 42,000,000

18

The Timer Circuit

2. THE TIMER CIRCUIT 2.1 Functional Description

The 1 8253 circuit ( 1 8254 for PC-AT) is a programmable timer/counter that conta ins three independent 1 6-bit counters, having attached the adequate logic for tt.le communication with the microprocessor and other devices. The m icroprocessor sees this circuit as a successive 1/0 ports table; the ci rcuit can be used as a counter for outside events , programmable square wave generator, delay circu it for processes contro l , etc.

The i nterna l block schematic of the circuit is represented i n figure 2 . 1 . The data bus buffer i s o n 8 bits, bi-d i rectional, with three-states output; i t is the 18253 circuit i nterface to the system data bus.

D0 ... 07 Data Bus

Buffer

/RD /WR R/W /CS Logic AO

Al

word Registe

0

1

2.

Fig.2.l The timer block diagram

CLKO GA TEO OUTO

CLKI GATE! OUT!

CLK2 GATE2 OUT2

Through this buffer, the data is transferred from and to the circuit; this is the way to program the working mode for the three existing channels, by loading the counters y.tith the adequate time values or by reading the values from the counters.

The counters (chan nels) 0 , 1 ,2 are identica l , i ndependent, each one being a 1 6-bit presetable countdown counter. Each counter can be selected to count BCD or binary. Their content can be read anytime without being modified .

19

The Timer Circuit

The R/W logic allows the circuit selection and the circuit registers reading and writing control. The operations that take place for different combinations of the control signals are presented in table 2 . 1 . The control word register keeps the circuit programming information, which selects the desired work mode for different channels.

/CS /RD /WR Al AO Function 0 1 0 0 0 Loads counter O 0 1 0 0 1 Loads counter 1 0 1 0 1 0 Loads counter 2 0 1 0 1 1 Loads the contro l reg ister 0 0 1 0 0 Reads counter 0 0 0 1 0 1 Reads counter 1 0 0 1 1 0 Reads counter 2 0 1 1 1 1 Not func t i oning 1 x x x x Unse lected c i rcui t 0 1 1 x x Not funct ioning

Table 2 . 1 Register operations for the timer

2.2 The t imer p in assignment

The circuit ha 24 pins with the functions shown in figure 2.2. Bes!de the power, data and control signals, the typical signals for each channel are the following: Clk, (Clock)- are the clock entries (pulses) for the counter. The maximum allowed frequency is 2 ,6 MHz (for 18254 is 1 0 MHz) Gate.- these entries can work as validation gates for the clock entries or as counting start pulses, depending on the programming mode of the circuit. Out,- represents the channels outputs, whose evolution is dependent on the circuit-programming mode.

8 CLKO 9 GO 11

OUTO 10 5 4 CLKI 15 3 GI 14 2 13

n 23 CLKl 18 19 G2 16 20 OUTl 11

ll cs 8253

Fig . 2 . 2 The timer pins assignment

20

The Timer Circuit

2.3 The timer programming

The programming can be made by writing in the contro l word register the control byte correspond ing to the desired working mode . The bit sign ificances of the control byte are shown in figu re 2 .3 . The selected channel is considered to be programmed if one has set the control word and one or two bytes are written in the counter (accord ing to bits 5 and 4) ; th is operation is fol lowed by a ris ing and a fal l i ng edge of the clock signal . The time diagrams for the channels work modes are presented i n figure 2 .4 .

Mode 0 - Interrupt on Terminal Count. After load ing the adequate control word , the selected counter output is forced to "O" and then the counter is loaded with the programmed va lue, wh ich wi ll be decremented at each clock pu lse . The output wil l be " 1 " only when the va lue from the counter becomes "O" and remains in th is stage unti l a new load ing of the counter , occurs . The decrementation process continues after reach ing the final value . The counter reload ing stops the current operation if the fi rst byte is loaded or it starts a new operation if the last byte is loaded . Q..,

' 4) . f f .R.

.. I

51

5 4

so 01 00

00- reads counter 0 1 - reads/loads low byte 1 0- reads/loads h igh byte

3

M2

2

M1

0 \ \ \ t,}\n "" O:

--7 . \A ' {j\ .

MO N

0- binary counting 1- BCD counting

1 1 -reads/loads low and then 000 - mode o ( lntrerrupt on Terminal Count) high byte 001 - mode 1 ( Programmable One-Shot)

00 - counter 0 01 - counter 1 1 0 - counter 2

x 1 0 - mode 2 ( Rate Generator) x1 1 - mode 3 ( Square Wave Rate Generator) 1 00 - mode 4 ( Software Triggered Strobe) 1 0 1 - mode 5 (Hardware Triggered Strobe)

1 1 - i l legal command

Fig .2. 3 The control byte

Mode 1 - Programmable One-Shot. The counter output changes from "1" to "O" only after the control word and the counter had been loaded and the signal appl ied to the gate has a ris ing edge . This edge launches the decrementation and at passing through "O", the output wi l l become "1" again. If a new value is loaded i n the counter during the counting , it wi l l not affect the length of the pulse unti l a new start. The current value of the

21

The Timer Circuit

counter can be read without affecting the output. If a ris ing edge i s present at the GATE input at some time during the pulse, it produces a new start of the counting from the last value stored in the counter (fig .2.4 ) .

Mode 2 - Rate Generator (D ivide by n counter) . The output wi l l be " 1 " for (n- 1 )T cLK periods after the control word and the counter value load ing and it wi l l became "O'' i n the n-th period . If the GATE input is forced to "O'' during the counting , the output wi ll become " 1 " and when the GATE input returns in " 1 " , the counter will decrement again from the in itia l va lue; the GATE input can be used for the counter synchron ization . The counter decrementation starts immediately after the last data byte load ing and if the counter is reloaded during this period , the change wi l l be reflected in the next period .

Mode o Interrupt on Terminal Count CL Ki WR OUTi ------( n= 4 )-----------+---+---+---+--/

Mode 1 Programmable

CL Ki GATE

_ __,

OUTi 3 2 3 2 0. (n=3) ._I --+I ---+---+1---+l---+-----'1 Mode 2 Rate Generator CL Ki WR OUTi I 3 21 I (n=3J I Square Wave Rate Generator ..._ _ __.. Mode 3 CLKi WR OUTi (n=4)

2

Mode 4 Software Triggered Strobe CLKi

WR

0(4)

OUTi---------1----1----'--- Mode CL Ki

3 I 2

GATE 4 3 OUTi 0 (n=4,--+---+--1---l1----+----+----:_1 _ ____,

Fig . 2 . 4 Timer operation modes

22

The Timer Circuit

........-- u. - e.ve....... ,.Z -:. Mode 3 - Square Wave Rate Generator. C' ""' L( - JJ . (?1+1,Yi... - (j Mode 4- Software Triggered Strobe. After th is mode programming, the selected channel output becomes " 1 " and the decrementation starts after loading the selected counter with the computed value. When the counter wi l l get to 0, the output becomes "O" for a clock period and then it returns to "1 " . The counting is inh ib ited by the GATE input pass ing to "O" and it is resumed from the last loaded value when the GATE input passes to "1 " aga in ; this a l lows the implementation of a retriggerable . The counter reloading can appear in two cases: - when the counter is generating a single-pulse ( in th i s case the current

pulse is not affected , but at its end ing a new sing le-pulse wi l l be generated , adequate to the new value) ;

- when the counter is standing-by, a pulse wil l be generated , adequate to the new value stored in the counter.

Mode 5 - Hardware Triggered Strobe. The counter wi l l start counting after the counter value load ing on the ris ing edge of the GATE input. When the counter arrives in 0, for a CLK period , a ris ing edge on the GATE input retriggers the counter.

I Low Or Rising Edge High e B Falling Edge 0 - Disab l e s counting - Enables

Counting 1 -Initiates counting

- Re s e t s output a f t e r next c l ock

2 - Di s ab l e s Counting - Reloads counter - Enab l e s - Se t s output - Initiate s counting counting immediate ly high

3 - Dis ab l e s counting - Initiat e s counting - Enab l e s - S a l e s output counting immediate ly high

4 - Dis ab l e s counting - Enables counting

5 - Initiates counting

Table 2 . 2 The Gate signal operations summary

2.4 The timer circuit in PC

For compatib le IBM computers, one uses a timer circuit for fulfi l l ing d ifferent functions. The three circuit channels are used for:

23

The Timer Circuit

the system clock - CO DMA transfer request (on 0 DMA channel ) for DRAM refresh - C 1 (for PC-XT) loudspeaker command - C2; see fig .2 .5 . The clock inputs at the three channels resu lts from the PCLK signa l ,

d ivided by 2 , so 1 . 1 93 MHz, starting from 1 4 . 3 1 8 1 8 MHz chosen quarts frequency osci llator. The reserved PC port addresses for the t imer circuit are between 40h-43h.

Channel 0 is programmed in mode 3, with the d ivid ing value 0, that is 216 ; at the OUTO output there result pulses with a period of 55ms ( 1 8 ,2 pu lses/s) that generate interrupts at 18259A interrupt control ler IRQO input. The generated hard interrupts are type 8 interrupts and they are used for the system clock implementation ; its handler rea l izes :

the system clock value update the floppy un it motor stopping after 2 seconds of inactivity the launch ing of the 1 Ch interrupt, for user routine .

Beside the 08h interrupt, the I NT 1 Ah soft i nterrupt offers services connected to the system clock. For PC-XT, channel 1 command the DMAC (18237A) DRQO input, generating the DRAM memory refreshing cycles. Channel 2 , after passing trough a gate type val idation logic (control led by the PIO circu it at PC-XT or 18042 at PC-AT} and an ampl ifier stage , commands the PC loudspeaker (fig .2 .5 ) .

1. 193MHz .-----.. IRQO(l8259A) ---CLKO OUTO-----+

' 1 GATEO

CLKl OUTl ' l' GATEl

BO Bl

DRQO (PC-XT) -----

PORT B (61H) PIO-I8255A

Fig . 2 . 5 The use of timer channels in PC

24

The Timer Circuit

2.5 Applications and exercises

2.5.1 The next appl ication generates the fourth octave notes i n the PC loudspeaker. The notes frequencies in Hz are showed in the fol lowing table :

DO 2 61. 6 Fa# 3 7 0 DO# 2 7 7 . 2 Sol 3 92 Re 3 9 3.7 Sol# 4 1 5. 3 Re# 3 1 1. 3 La 4 4 0 Mi 3 2 9. 6 La# 4 6 6 . 2 Fa 3 4 9 . 2 Si 3 9 3 . 9

The notes are generated in the loudspeaker by programming the channel 2 of the 18253 timer circuit with an adequate d ivid ing value, knowing that at the CLK 2 input we have a frequency of 1 , 1 93 1 8 M Hz . The values can be computed l i ke this :

knote=1, 1 93 1 8 MHz I fnote For example for the note La, kLa=27 1 1 . The contro l of the signal on the loudspeaker can be made through BO

and 8 1 bits of the 6 1 h address port. The channels connecting schematic of the 18253 timer circuit is presented in fig .2 .5 .

a . Analyze and execute the fol lowing "DOREMI" program b. Transpose the program for other octaves c. Generate a melody.

; * - - - - - - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - * ; * I DO REM I * . I * - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - * I I code s egment para 'CODE' ; Def ine s CODE segment

org l O Oh ; starts at l O Oh a f t e r PSP assume c s: code , ds : code, e s : code , s s : code

sound proc near ; - - mes s age - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

mov ah , 9 ; s t ring print ing func t i on mov dx , of f s e t mes_in ; me s s age address_ offse t -int 2lh ; DOS interrupt

; - - redire c t s the t imer rout ine to the user rou t i ne - - -1 m

m

o

o

v

v

ax , 3 5)-ch ; reads timer interrupt addres s i n ES : BX int 2 lh ;DOS interrupt t ime_o l d , bx ; save s old interrupt offset address

mov t ime_ol d+ 2 , es ; and s egment addres s mov dx , o f f set s ound_ti ; new routine o f f s e t addres s

25

mov ax , 2 5 l ch int 2 1h

The Timer Circuit

; loads address in TVI f rom DS : DX ; DOS interrupt

; - - sounds generat ion - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -xor bl , bl ; start with Do f rom the IV octave mov dl , 9 ; note l ength in t ime 0 . 5 sec ( 9 * 1 / 1 8s= 0 . 5 )

nextone : cal l p l ay_note ; note genera t i on inc b l ; next not e cmp b l , 1 2 ; all notes have been generated? j ne nextone ; i f Not = - - > generate next note

; - - t imer old int e rrupt - - - - - - - - - - - - - -mov cx , ds ; Saves DS mov ax , 2 5 1 ch ; funct i on number for vector recovery in TVI l ds dx , dword p t r t ime_ol d ; loads old address in DS : DX int 2 1h ; DOS interrupt mov ds , cx ; DS recover

; - - end message - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -mov ah , 9 mov dx , of fset mes out int 2 1h mov int

sound endp

ax , 4 C O Oh 2 1h

; program end

; = =ma in p rogram data = = = = = = = = = = = = = = = = = = = = = = = = = = mes_in db Odh , O ah , " Generat ing notes f rom I V octave , Odh , O ah , " $ " mes out db O dh , Oah , 11 End 11 , 0 dh , Oah , 11 $ 11 ; - -

-PLAY_NOTE : Generat ing note - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

; - - Input BL = note number f rom Do , octave IV ; - - DL = note l ength in 1 / 1 8 second mul t ip l es

Output i - - Registers : AX , ex , ES and FLAGS are mod i f ied

play_not e proc near push dx ; saves DX and BX on stack push bx mov al , Ob6h ; prepares the sound generat i on

; ( C2 , LSB/MSB , M3 , b inary ) out xor shl mov out mov out in or mov mov out

4 3 h , al ; l oads the value in t imer cont rol reg ister bh , bh ; BH= O , of fset for note addressing in the tab l e bx , 1 ; doubles the value ( the tab l e is for words ) ax , [note +bx] ; reads note value 4 2h , a l ; loads the low byte in t imer reg ister ( C2 ) a l , ah 4 2 h , a l al , 6 1h

al , l lb end_s , 1 nr_s , dl 6 1h , a l

; loads high byte in t imer regist e r ( C2 ) ; reads the l oudspeaker cont rol b i ts ; B its B O , Bl ( 6 1h ) act ivate the l oudspeaker ; Note must be generated ; Saves the note l ength ; Act ivates the loudspeaker

play : cmp end_s , O j ne p l ay

; Note done ? ; No - - > wa i t

26

The Timer Circuit

in and out pop pop ret

a l , 6 lh a l , l l l l l l O Ob 61h , a l

; reads l oudspeake r contro l b i t s ; Se t s to O b i t s B O , Bl ; D i s ab l e s l oudspeaker

bx ; Recove rs BX and DX f rom s t ack dx

; back in the program pl ay_not e endp

; - - new user int e r rupt ( l Ch ) of the t imer - - - - - - -sound_t i proc f a r ; ca l led 1 8 t ime s per s econd

dee c s : nr s ; De c rement s coun t e r j ne e n d s t ; i f # 0 j ump , = 0 done mov c s : end_s , O ; passed note l ength

end s t : i re t ; back sound ti endp

; = = var i ab l e s for rout ines = = = = = = = = = = = = t ime_ol d d w ( ? ) , ( ? ) ; o l d addre s s f o r t ime r interrup t nr s db ( ? ) ; rema ining l ength for a not e , in second

; l /1 8 mul t ip l e s end s db ( ? ) ; indi c a t e s i f the not e was generated

not e dw 4 5 6 0 , 4 3 04 , 4 0 6 3 , 3 8 3 4 ; dividing va lues for the not e s dw 3 61 9 , 3 41 6 , 3 2 2 4 , 3 04 3 ; f rom octave IV : Do , Do# , Re , Re # , M i dw 2 8 7 3 , 2 711 , 2 5 5 9, 2 4 1 5 ; Fa , Sol , S o l # , La , La# , S i

; = = End = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = code ends end sound

; CODE segment end ; p rogram end

* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * I I

2.5.2 On an ISA expansion slot the schematic from figure 2 .7 is . connected to the PC . The timer channels are used as i n figure 2 .6 .

SYSCLK/ 1 6

'1 ' CLKO GATEO

D

CLK

OUTO

SET

r--+-''\/\l\--o+5

OUT! '1 '

CLK2 GATE2

Fig . 2 . 6 The timer channels connection

27

OUT2

a . To what address i s the 18253 ci rcuit connected?

The Timer Circuit

b . Starti ng from the SYSCLK = 1 2M Hz frequency, generate a 1 Hz s ignal on the OUT1 output. c . Make the necessary connections and program the c ircuit to obta in an externa l ly commandeq pu lse of 0 , 5 sec. at the OUT1 output. d. Transpose the "DOREMl .ASM" program for the expansion board loudspeaker.

. 17:0 ,., '1 .,,r

3

6 c

8 B

1 1 A

AOW AOR

1 5 14 13 1 2 . 1 1 1 0 9 7

, '\ \ . t-=--U... \ ' \

O IJT'2 Al G2 E!1.... CLK2 lll!B RD

O UT1 07 G 1 D6 CLK1 D5 D4 D3 O UTIJ D2 GO SYS CLK/16 01 CLl

The RTC and the CMOS Memory

3. TH E REAL TI M E CLOCK AND TH E CMOS M E MORY

3.1 General i nformation Starting with IBM PC/AT computers, a CMOS memory has been

introduced , p laced on the main board , with the purpose to store some information concern ing the system configuration even after it had been shut down . The information is used for the system in it ial ization , thus a l lowing a flexible configuration , d ifferent from one computer to another (d ifferent RAM memory, d ifferent floppy d isc un its and hardware-d isc types, etc . ) . CMOS memory stores also t ime and a larm i nformation , refreshed by the RTC (Real Time Clock) and a few bytes used to keep information concern ing the system d iagnosis during booting .

The fi rst type used the MC1 468 1 8 ci rcu it, mounted on the main board , having a capacity of 64 bytes , suppl ied from a battery to store the CMOS memory contents even after the computer had been shut down . MC 14681 8 incorporated a lso the Real Time Clock that has its own osci l lator. Different peripheral ci rcu its producers have real ized their own constructive forms for the CMOS memory, some of them al lowing 1 28 bytes memory. CMOS memory addressing is the same for any CMOS memory type and for most of the bytes the sign ificance remains the same.

The three categories of i nformation stored in the CMOS memory are : I nformation concern ing the system configuration (ex: avai lab le RAM

memory, types of flexible disk un its , type and specific featu res of the fixed d isk un it) .

I nformation provided by the Real Time Clock, concern ing the time (seconds, minutes, hours, month year) and the a larm (the a larm is a faci l ity of the RTC which a l lows a hardware interrupt generation I RQ8 (type vector 70H) each time the current time becomes the same as the t ime the alarm is set) .

System d iagnosis i nformation , provided during the booting phase . The shutdown byte , used in the PC-AT restart mecan ism, where it

remains after a CPU reset, to exit from the protected mode.

An important th ing is that the real t ime clock is refreshed independently by the centra l un it , whi le the system clock used by B IOS is refreshed ( 1 8 .2 times per second ) at the timer generated i nterrupts on the 0 timer channel to I RQO.

29


3.2 MC 1 4681 8 ci rcuit 3.2.1 Internal Block Diagram MC146818 has 4 logical blocks :

The interface with the bus - conta ins : -demult ip lexers for address and data s igna ls demult ip lexing -reset logic -read-write selection log ic

The Real Time Clock comprises : a quartz square wave generator and a programmable d ivider mounted with a prescaler register and a meter. Th!3 clock is i ncremented by the programmable divider output and its role is to refresh the reg isters : seconds, minutes , hours , weekday, month day, month , year and to compare them with the a larm registers . If the values are equ ivalent , the IRQ l ine wi l l be activated . All the reg isters are in the CMOS memory and they are avai lab le for reading/writing .

Power management b lock ensures the switch ing from the supplying source to the battery when the source is interrupting and s igna ls th is to the system through the PS l ine .

CMOS memory is a low consumption memory, with a capacity of 64 bytes, accessib le through the bus-interfacing b lock.

A AD O - AD7 . < AS D S

R /WR RST

/CS -D -onur

IRQ

CKFS , P S

- -Bus . D O - D 7 D O - D7

' " v I n t e r f a c E . AO - A7

' v

1

D O -D7 . RTC ,. n _ ,. ., AO - A7

I Power management - -Addres s Data Bus Bus

CMOS Memory

Fig . 3 . 1 The MC14 6 8 1 8 block diagram

30


3.2.2 Circuit pin assignment

The circuit is encapsulated in a 24-pin package, whose sign ifications are:

OSCI ADO OSC2 ADI

AD2 RESET AD3 IRQ AD4

ADS AS AD6 OS AD7 PS 23 CKFS SQW

cs CK OUT 21 RiW

Fig . 3 . 2 RTC pin assignment

AD0-7 - multip lexed address and data signals /CS - Chip Select R/W - Read/Write AS - Address Strobe DS - Data Strobe PS - Power Sense, used to control VRT (Val id RAM and Time) bit from register D, who is 0 when PS is low CKFS - Clock out Frequency Select, used for CKOUT frequency selection : if CKFS is connected to VDD, CKOUT = OSC1 , if CKFS is connected to GND, CKOUT = OSC1 I 4 CKOUT - output s ignal of time base frequency d ivided by 1 or 4 /I RQ - Interrupt Request ( IRQ8 in PC), active as long as the i nterrupt generating bit is active and the interrupt va l idating bit is set VCC - +SV GND - ground OSC1 -2 - quartz inputs (4 . 1 94304MHz/1 .048576MHz/32. 768KHz) SOW - Square s ignal output, obta ined by d ivid ing the OCS 1 signa l ; the 1 5 frequencies are obtained depending on the bits 83 - BO from register A RESET - does not affect the clock, the calendar or the RAM; at the system start it mainta ins low for a whi le , its effect being the P IE , AIE , U IE , UF, IRQF, PF bits reset

3 1


3.3 The CMOS memory content and its accessi ng mode The CMOS memory locations are used to store the information

presented in the table below, the rest of it being avai lab le to the user. I n case of using this circuit in a PC, the locations have the destination presented in the appendix 2.

Addr CMOS memory content used by the RTC o oh Current s econd for RTC * O lh Al arm s econd for* 02h Current minute * 0 3 h Alarm minut e * 0 4 h Current hour* O Sh Al arm hour* 0 6 h Day f rom week ( l = Sunday ) * 0 7 h Day f rom month* 0 8 h Current month* 0 9h Curren t year ( the last two dig i t s ( superior

dig i t s ) are at addres s 3 2 h ) * O ah S tatus reg i s t er A of RTC Obh S t atus reg i s ter B of RTC Och S tatus reg i s t e r C of RTC

( Read interrupt s t atus reg i s t e r ) O dh S tatus regi ster D of RTC ( D7 = 1 supp l ied I c i rcui t , D=O battery empty

*The content of 00h-09h locations are read i n hex. Example: I f the location 02h contains 1 2h then current minute is 1 2 .

Table 3 . 1 CMOS memory addresses used by the RTC

Register A {R/W} 7 6 - 4 3 - 0

Update in progre s s ( UI P ) DV2 - DVO Rate s e l e c t o r for SQW : RS 3 - RS O

U IP - (Update I n Progress) is a status bit (flag) that can be controlled by the program. When this flag is " 1 '' , it indicates an update cycle in progress or starting soon . DV2 - DVO - allow different conditions establishment, th rough a program, according to the quartz type that will be used RS3 - RSO - bits for rate selection , allows selecting one of the 15 dividing possibilities of the 22 level divider or the divider output disabling

Register B {R/W} 7 6 5 4 3 2 1 0

I SET I PIE I AIE I UIE I SQWE I DM I 24 / 12 I DSE I SET = O time update going on ordinary

32


= 1 one can in itia l ize the time and calendar PIE (Periodic I nterrupt Enable} = 1 enables the periodic interrupt, th roug h flag PF AI E (Alarm I nterrupt Enable} = 1 enables i nterrupt through alarm flag AF UIE (U pdate-ended Interrupt Enable) = 1 enables interrupt through flag U F SQWE (Square Wave Enable) = 1 activates rectangular s ignal to SQW output, with a frequency selected through RS3 - RSO OM (Data Mode) = 1 indicates ti me and calendar binary u pdating , else BCD updating 24/1 2 = 1 activates 24h/day counting mode DSE (Dayl ight Savings Enable) = 1 activates automatic summer/wi nter hour passing

Register C (Read only) - i s used by the I NT70 h i nterrupt handler, to determine i n what situation it was generated

7 6 5 4 . 3 2 1 0 I IRQF I PF I AF I UF I 0 I 0 I 0 I 0 I

IRQF - i nterrupt request flag is active ("1 ") if at least one of the fol lowing conditions is true: PF = P I E = 1 ; UF = U I E = 1 ; when this bit is " 1 " , / IRQ pin is low. The register bits reset at the register reading or when the signal /RESET is active PF - period ic interrupt flag is set on " 1 " when a certain front is detected at the d ivider channel . Its periodicity is commanded by the RS3 - RSO bits . AF - alarm i nterrupt flag activates if current time equals alarm time and generates an i nterrupt if flag AIE = 1 U F - U pd ate - ended interrupt flag , is activated after every u pdating cycle. If U I E = 1 , the U F activation sets bit I RQF and activates i nterrupt signal / I RQ .

Register D (Read only)

7 6 5 4 3 2 1 0 I VRT I 0 I 0 0 I 0 I 0 I 0 I 0

VRT - Val id RAM and Time indicates RAM content status depending on the tension level on pin PS. VRT = O indicates that the level on PS is low, so the battery is empty.

Reading and writing CMOS memory locations

To read the content of a CMOS memory location one must fol low the next steps:

Send to port ?Oh the address of the location that wi l l be read Read the location value from port 71 h

33

Example: mov a l , addr e s s out 7 0h , a l in a l , 7 1h


To write a location of the CMOS memory one fol lows the next steps: Send to port ?Oh the address of the location Write the new value to port 7 1 h

Example : mov a l , address out ? O h , al mov a l , new_value out 7 lh , al

3.4 System services for CMOS - RTC data access

The operating system al lows user access to the system clock (used by B IOS) and to the real time clock (wh ich updates independently) through B IOS services I NT 1 Ah . For data read ing from CMOS - RTC , the operat ing system provides the fol lowing services ( INT 1 Ah) :

AH=02H Reads the clock from CMOS -RTC Output: CH = hour in BCD (EX: CX=1 1 49H=1 1 :49)

CL = minutes in BCD DH = seconds in BCD CY = 1 when RTC is locked

AH=03h Time sett ing in CMOS-RTC Input: CH , CL = hours , minutes in BCD

DH = seconds i n BCD DL = 1 sets automatic change winter/summer t ime

AH=04h - Reads date from CMOS Output: CH = century in BCD (Ex: CX= 1 987h= 1 987)

CL = year i n BCD DH = month i n BCD (Ex: DX=03 1 2h=March) DL = day in BCD CF = CY = 1 if RTC is locked

AH=OSh Sets date in CMOS Input: CH , CL = century , year in BCD

DH, DL = month , day i n BCD AH=06h - Sets the RTC alarm . At the set t ime, the user i nterrupt routine is ca l led from the address corresponding to INT 4Ah . I t may be only one alarm activated .

34

Input: CH, CL = hours , minutes in BCD DH = seconds i n BCD


Output: CF = CY = 1 RTC is locked or an alarm is active

AH=07h - Resets the RTC alarm

The system configuration can be read with INT 1 1 h . It returns to AX the fol lowing b its configuration .

01 5 - 01 4 Para l l e l Port 0 0 Not ins t a l l ed 0 1 1 1 0 2 1 1 3

0 1 3 1 - S e r i a l printer instal l ed 0 1 2 1 - Game adaptor ins t a l l ed D l l - 0 9 Port RS2 3 2 0 0 0 Not ins t a l l ed

0 0 1 . . 1 1 1 1. ..... 7 port s instal l e d

D B 1 - DMA pres ent 07 - 0 6 F l oppy d i sk driver 0 0 1

0 1 2 1 0 3 1 1 4

D S - 04 V i deo Mode 0 0 Re s e rved 0 1 4 0 color c o lumns 1 0 8 0 color c o l umns 1 1 Monochrome TTL

D3 -D2 RAM memory s i ze 0 0 0 0 1 1 6 k 1 0 3 2 k 1 1 6 4 k +

D l 1 - Mathema t i c coproce s s or ins t a l l e d D O 1 - D i s k un i t ins t a l l e d

Table 3 . 2 System configuration provided by INTllh in AX

This i nformation can also be found i n the system memory at the address 0 :04 1 0h .

3 .5 Application and exercise

a. Study and execute the fol lowing appl ication, written in C language, appl ication that d isplays information about date and hour, read from the CMOS memory.

35


#inc lude < dos . h > #include < S t diO . h> # inc lude < coni o . h> typede f unsigned char byte ; #def ine Rt cAdrPort Ox7 0 #def ine Rt cDataPort Ox7 1 #de f ine Seconds 0 #de f i ne M inutes 2 #define Hours 4 #de f ine Dayl 6 # de f ine Day 7 #de f ine Month 8 # de f ine An 9 #def ine Reg A 1 0 #define RegB 1 1 #de fine RegC 1 2 #de f ine RegD 1 3 #define Diagnose 1 4 #define Century 1 5

/ / Funct ion that reads a locat i on f rom CMOS

byte CmosRead ( byte Address ) {

byt e retur ; asm {

} ;

mov a l ,Address out Rt cAdrPort , a l in a l ,Rt cDat aPort mov retur,Al

return ( retur ) ;

/ / Funct ion that wr i t e s to a locat i on f rom CMOS

vo id CmosWr i t e ( byte Address,byte Content ) {

asm { mov a l ,Address out Rt cAdrPort,al mov a l , Content out Rt cDataPort,al } ;

void ma in ( vo i d ) {

whil e ( b i oskey ( l ) == O ) { c l rscr ( ) ; i f ( ! ( CmosRead ( Di agnose ) &l2 8 ) ) / /verifies bat tery status

36


{ / / reads RTC emp l oy mode f rom reg i s t er B

p r i nt f ( " RTC i s u s ed in %d hours mode \ n " , ( CmosRead ( RegB ) & O x 0 2 ) * 6 + 1 2 ) ; / / reads hour

p r i n t f ( " The t ime i s : %x . % 0 2 x . % 0 2 x \ n " , Cmo sRead ( Hour ) , Cmo sRead ( M i nut e ) , Cmo s Read ( S e conds ) ) ; / / reads da t e p r i n t f ( " Da t e : % x . % 0 2 x . 2 %x% 0 2 x \ n \ n\ n " , Cmo sRead ( Day ) , Cmo sRead ( Month ) , Cmo s Read ( Century ) , Cmo sRead ( Year ) ) ;

} ;

} e l s e

p r i nt f ( " At t ent i on ! RTC B a t t e ry empty\ n " ) ; de l ay ( S O O ) ;

b . Mod ify this program so as to read from CMOS the type and number of floppies and hard d isks of the system.

c . Modify th is program so as to read from CMOS the type of v ideo card . d . Rewrite the appl ication using system services.

37

The Programmable Interrupt Controller

4. TH E P ROG RAM MABLE INTERRU PT CONTROLLER

4. 1 Interrupts i n data processing

Most of the computer components need to exchange information with the microprocessor and wait for its attention when they requ i re a data transfer. The microprocessor supervises the data transfer between different components in order to prevent the data losses . The microprocessor can supervise the data transfer in two d ifferent ways : Pol l ing the microprocessor tests the devices one by one and serves

the one that requ i res a special attention . Pol l ing can be used in the case of some devices or in microprocessor systems but not in PCs, because it is too slow. Many processing cycles can be lost, because most of the times the devices response is negative . In add ition , the devices need data transfer or attention with d ifferent frequencies (e.g . the mouse needs much less attention than a hard-d isk when i t is activated for data transfer) .

Interrupt- i s another way of approaching the data transfer and it consists in letting the devices ask for attention when they need it, whi le the 'microprocessor can take care of other duties , wasting less t ime than in pol l ing mode . When an interrupt is sensed , the microprocessor qu its the program run and properly serves the device that put it off.

The microprocessors genera l ly have only one p in for the interrupt requests , but there can be more exterior interrupt sources . When the system needs more interrupts , an i nterrupt control ler carrying out certai n duties is placed between the interrupt sources and the microprocessor. Some of the duties carried out by the i nterrupt control ler are :

Mult iplexing the interrupts from d ifferent sources to the microprocessor p in

Solving the priority problems for s imultaneous interrupts The generation of an interrupt vector which ind icates the address of the

program that handles the interrupt

The above tasks are solved differently for some microprocessors (e .g . Z80) . The i nterrupt system is d istributed to each ci rcuit from the Z80 fami ly and the i nterrupt priorities are solved depending on the c ircu it position on a priority chai n cal led "daisy-chain" . The circu its a lso provide the correspond ing i nterrupt vector. The PIO Z80 circuit from figure 4 . 1 has

39


maximum priority , be ing the fi rst component on the priority chain connected through the I E I ( I nterrupt Enable I nput) and I EO ( I nterrupt Enable Output) s ignals . The P IC (Programmable I nterrupt Contro l ler) 1 8259A circuit is used in PC.

' I ' IE I IEO 1---- IE I IEO 1---- IE I IEO

PIO Z80 CTC Z80

INT INT INT INT (Z80)

Fig . 4 . 1 The priority chain ( ' Daisy- Chain ' )

4.2 The 8259A overview The 1 8259A circuit is made in NMOS technology in a 28-pin capsu le .

Th is circuit is compatib le with the 18259 contro l ler (used with 1 8080) and due to its additional functions it can be used i n the 180x86 microprocessor systems. The c ircuit a l lows interrupt requests active on the increasing edge or on "h igh" level and it can be used in the system by itself, managing 8 interrupt levels , or more cascaded circu its can be used , to manage up to 64 i nterrupt leve ls . Based on an i nterrupt-handl ing ru le that can be programmed , the control ler finds out if there is at least one interrupt request and sets the INT s ignal on high leve l . If the microprocessor accepts the i nterrupt, it generates an i nterrupt accepting sequence of more /I NTA run cycles (2 i n 18088/18086 mode and 3 in 1 8080 mode) to recognize the i nterrupt. During these cycles, the control ler puts on the data bus the information requ i red by the microprocessor for determin ing and executing the routine associated to the accepted interrupt leve l .

4.2. 1 . The 18259A control ler architecture The P IC b lock d iagram has the fol lowing functional b locks :

I nterrupt Request Register { IRR) - memorizes a l l the i nterrupt requests coming from the outside . I n Service Register { ISR) -memorizes i n service interrupt requests at a certain time . After an i nterrupt has been served , the corresponding bit from ISR is i nva l idated . The reset can be done automatical ly or programmed . Priority Resolver {PR) - compares the I RR reg ister content with ISR reg ister content and determines the i nterrupt request with greater priority than the i nterrupt being served , in which case it generates a new interrupt request by sett ing the corresponding bit in ISR during / INTA first cycle .

40


Interrupt Mask Register ( IMR) - al lows the inval idation of some interrupt levels by setting the corresponding bits in the reg ister. Data Bidirectional Ampl ifier - has 'three-state' b id i rectional l ines, connecting the control ler interface to the data bus. The control words, status information and vector type are transferred through the ampl ifier. Cascading Logic The 18259A control lers can be cascaded to i ncrease the number of interrupts ; one control ler is the master and the rest of them s lave (maximum 8 slave circuits) . The slave control lers generate interrupt requests on the IRi master input through the slave control ler connected to that input. The CASO-CAS2 signals of the master control ler are output signals through which the slave control lers receive a code from the master circuit . The s lave c ircu it which recogn izes the code (the prioritary one) wi l l transmit, during / INTA cycles , the data for the accepted interrupt request, so that the routine can be determined and executed . Read I Write Logic The processor sees the control ler as an input-output port set . Through AO , /WR, /CS and DO - D7 signals , the processor programs the control ler using command words and through AO , /RD , /CS and DO - D7 signals it reads the status registers .

/RD /WR AO !CS

CASO CASI CAS2

/SP//EN

Data idirec tiona

buf f er I'NTERNAL

.---------. BUS

Read/Write Logic

Cascading Logic

/ I'NTA I'NT

Control Logic

IMR

Fig . 4 . 2 I 8 2 5 9A PIC internal block diagram

41


. 4.2.2 I nternal registers The address for the 18259A interrupt control ler programming is 20H

(for XT-PC) and the associated port addresses are l isted bel low:

Port I/O Significance 2 0H I Read IRR , I'sR 2 1H I Read IMR 2 0H 0 Wr i t e OCW2 i f D4 , D3 = 0 0 2 0H 0 Wr i t e OCW3 if D4 = 1 2 0H 0 Wr i t e I CWl , i f D4 = 1 2 1H 0 Wr i t e OCWl , I CW2 , I CW3 , I CW4

Table 4 . 1 Port addresses for PIC

The address for the slave PLC_.!s Q_OH ( in AT-PC)

Interrupt Request Register ( IRR) : { in al , 20H)

7 6 5 4 3 2 0 I IRQ7 I IRQ6 I IRQS I IRQ4 I IRQ3 I IRQ2 I IRQl IRQO I RQi = O there was no interrupt request on l ine ' i '

= 1 interru pt request on l ine ' i '

In Service Register ( ISR) : {in al, 20H)

7 6 5 I

I = 0 there is no interru pt = 1 there is an interru pt

4 3 2 0 W2 Wl WO

\

W2 , W 1 , WO contain the binary code of the most pribritary level which req uested interru pt

Interrupt Mask Register ( IMR) : { i al , 2H) 7 6 5 4 3 2 I 1Kl I M6 I MS I M4 I M3 M2

Mi = 0 I R Q 1 interrupt l ine is not masked = 1 I RQ 1 l ine is masked

W>oJY2\,.Q 'S Priority Resolver {PR)

0 Ml MO

The user does not have access to this register. The reg ister compares the current i nterrupt priority level with the one from ISR.

42


4.2.3 18259A circuit pins assignment

Name I /O /CS I

/WR I

/RD I

AO 0

D7 -DO I / O

CASO - I / O CAS2

/SP//EN I / O

INT 0

IRO - IR7 I

/INTA I

Pin 1

2

3

2 7

4 -1 1

1 2 -1 4

1 6

1 7

1 8 -2 5

2 6

Function C i rcui t select i on Act ive on ' 0 ' l eve l when command words are rece ived f rom the microprocessor Act ive on ' 0 ' l eve l when reading I 8 2 5 9A c i rcui t s t atus AO together with / CS , / RD , / WR determine the command/ s t atus word which t he microproces sor wri t e s / reads in/ f rom I 8 2 5 9A c i rcui t . Norma l ly i s connected t o 0 addr e s s l ine (Al for I 8 0 8 6 ) B i di rect ional dat a l ines for cont ro l , s t atus information tran s f e r and interrupt vector t rans fer .

For cas cading

S l ave Program/ Enabl e Buf f er is a doubl e func t i ona l i ty pin . I n buf f ered mode i s used as a bus tran s f e r cont rol s igna l and in unbu f f ered mode , S P= l for MASTER and SP= O for SLAVE INTerrupt - output connec t e d to INT proces sor input ; through i t , the interrupt reque s t are t ransmi t t ed ( Interrupt Reque s t ) - asynchronous input s connected to the o f f - l ine c i rcui t s whi ch generat e interrup t s t o t he proces sor , us ing P I C I 8 2 5 9A ( INTerrupt Acknowledge ) - used for interrupt acknowledge and int errupt vector reading

Table 4 . 2 Pins functions

I R O I R 1 I R 2 I R 3 I R4 IR5 I R 6 I R 7

CASO CA51 CAS2

Fig . 4 . 3 Circuit pin assignment

43


4.3 PIC Programming

The circuit has on ly two ports for writing or reading program status, so one must fol low a certain order in send ing the command words to the P IC . There are two types of words for working with 18259A:

- I n itia l ization words ICW1 , ICW2 , ICW3, ICW4 - Operation words OCW1 , OCW2, and OCW3 The words sending order is presented in the d iagram from figure 4 .4 .

The ICW and OCW words structure is presented below:

ICW1 (OUT 20H, AL) 7 6 5 4 3 2 1

1 I LTIM I I SNGL I The empty positions have sign ificance in 8080 mode.

ICW4 = O ICW4 is not necessary

S N G L

LTIM

ICW2 (OUT 21 H , AL)

= 1 ICW4 is necessary = O cascaded mode = 1 single mode (only one 8259A circu it) = O IRQ7 interrupt active on edge = 1 interrupts active on level

0 ICW4

7 6 5 4 3 2 0 I T7 I T6 TS T4 T3 x x x Ti are bits 3 to 7 from the code sent in the second /I NTA cycle. The number (type) of the interrupt vector for s ingle mode is 8 ( IRQO) , 9 ( IRQ 1 } , . . . F ( IRQ7) .

ICW3 (OUT 21 H , Al-) : for master 7 6 5 4 3 2 0 I S7 I S6 I SS I S4 S3 S2 Sl s o

Si = 1 there is a slave connected to l i ne ' i '

ICW3 (OUT A1 H , AL) : for slave 7 6 5 4 3 2 0 1 x x x x ID2 IDl IDO I

102 , 10 1 , 100: the identification code of the slave PIC (corresponds to IRQ l ine number from the master where it is connected ) . It is compared with the code emitted on CAS0 . . . 2 by the master.

ICW4 (OUT 21 H, AL) 7 6 5 4 3 0 0 0 I SFNM I BUF

PROC = O 8080 mode, = 1 8086 mode AEOI = auto EOI , = 0 manual EOI

44

2 1 0 M/S I AEOI I PROC I


BUF M/S SIGNIFICANCE 0 x No external data buf fer l 0 Ext ernal dat a buf fer ; s l ave P I C l l External da t a buf fer ; mas t e r P I C

SNFM (Special Ful ly Nested Mode) = 0 Priority working mode . Only the prioritary interrupts are accepted (the interrupts with the same or less priority are ignored due to ISR) = 1 Specia l mode for priorities (only for master) . Other interrupts are accepted, regard less their priority ; an interrupt with the same priority as the one being served wi l l not be accepted

OCW1 (OUT 21 H, AL) : for the i nterrupt mask 7 6 5 I M7 I M6 I MS

Mi = 0 unmasked level = 1 masked level

OCW2 (OUT 20H , AL) 7 6 5 R SL I EOI

4 3 M4 M3

4 3 0 0

2 0 M2 Ml MO

2 1 0 L2 Ll LO

R (Rotate) = 1 : unt i l the. next OCW2 . the. last served interrupt gets 8 lowest priority SL (Specific Level ) = 1 : specific EOI is used . See the table below for priority mode selection . EOI (End of I nterrupt) = 1 : P IC is announced at the end of the served interrupt procedure L2 , L 1 , LO: conta in the binary code of the served priority level

R SL EOI Significance 0 0 0 Rotate in AEOI mode - Clear 0 0 1 Non - spec i f i c EOI 0 1 0 No e f fect 0 1 1 Spec i f i c EOI 1 - 0 0 Rot a t e in AEOI mode - S e t 1 0 1 Rotate t o non - spec i f i c EOI 1 1 0 Set s priority 1 1 1 Rotate t o spec i f i c AEOI

OCW3 (OUT 20H ,AL) : masked mode, reg ister read selection 7 6 5 4 3 2 1 0 I ESMM I SMM I 0 l p I PR I RIS

ESMM (Enable Special Mask Mode) = 1 : special mask mode val idation SMM (Special Mask Mode) = 1 : special mask mode RP, RIS: select reg isters that wil l be read in the next instruction

45


P = O pol l ing mode {pseudo-interrupt mode: I NT is not val idated to the microprocessor. IRR register is swept through the program )

= 1 normal mode ESMM SMM Significance RR RIS Signi ficance

0 1

1

x No e f fect 0 Spec i a l mask

reset 1 Spec ial mask

s e t t ing

NO

NO

ICWl

ICW2

ICW4

Ready for interrupts (OCW)

0 x IMR s e l e c t i on 1 0 I RR s e l e c t i on 1 1 I S R s e l e c t ion

Fig . 4 . 4 The flow chart for PIC programming

4.4 18259A controller modes Ful ly Nested Mode This mode is instal led after the in itia l ization if another mode is not

programmed . The seventh interrupt level has the lowest priority and zero level becomes the most important. During interrupt acknowledge cycle , the most important priority request is determined and the vector associated to the interrupt is placed on the data bus. Meanwhi le the corresponding bit from ISR is set. In EOI mode, this bit is set to 1 and it needs an expl icit

46


command for erasing it before interrupt service routine ends. I n AEOI mode the bit stays in 1 unti l the last i nterrupt acknowledge / INTA cycle ends. As long as the ISR bit is set, any other interrupt requests are ignored , except the more prioritary ones that are served (if the microprocessor is set to accept the interrupt requests) .

EOI mode The ISR bit corresponding to the served i nterrupt i s automatical ly

reset i n AEOI mode (without using a special command) or using a command word activated before EOI mode interrupts serving routi ne ends. In cascaded mode, the served interrupt corresponding bit has to be erased from both master and s lave .

AEOI mode Automatic End of I nterrupt - is activated when AEOI bit from ICW4 is

1 and it is equ ivalent with a non-specific EOI command activated when the interrupt recogniz ing cycle ends (the th i rd for 18080 and the second for 18086 mode) .

Automatic (non-specific) priority rotation There are cases when an off- l ine device after being served becomes

the last one in the priority l ist and it wi l l not be served unti l the other seven off- l ine devices from the priority l ist wi l l be served properly.

Specific Priority Rotation The user can dynamical ly change the priority order from the program.

A low priority level is defi ned and the other levels wi l l be mod ified according to this one.

Interrupt masking Each i nterrupt request i nput can be masked us ing IMR, which is

programmed with OCW.

Special mask mode In this mode the interrupt requests with the same priority, as the

served interrupt, are inval idated but the more prioritary or less prioritary than the served one are accepted . Th is mode is programmed with ESMM = 1 and SMM = 1 i n OCW3 .

Pol l ing mode In th is mode, the interrupt system is inval idated at the microprocessor

level . The i nterrupt requests are scanned using a pol l ing command . Pol l ing mode is set with P = 1 in OCW3. The 18259A control ler hand les the first read ing cycle (/RD and /CS) as the fi rst cycle from the i nterrupt accepting sequence . The most prioritary request bit is set i n ISR.

47


Specific Fu l ly Nested Mode This mode is necessary in the systems with severa l cascaded 18259A

control lers and it is programmed from the master. (Through SFNM = 1 in ICW4 ) . Th is mode is s im i lar to Fu l ly Nested Mode with some exceptions. When an interrupt request coming from a slave is served , the master circuit does not i nva l idate th is slave . In this way the most prioritary interrupt requests coming form the same slave are properly served . I n the normal mode (FNM) , when an i nterrupt request coming from a slave is served , the correspond ing master input is inva l idated and even the more prioritary i nterrupt requests than the one being served wi l l not be accepted .

Buffered mode When the 18259A control ler is cascaded in the unbuffered mode, the

/SP//EN s igna l is used as an i nput s ignal contro l l ing the type (master or slave) . There are system configurations that need communication between the 18259A control ler and the bus, using a b id i rectional ampl ifier (buffer) . I n this case the /SP//EN signal i s used as an output s igna l to establ ish the bid irect ional ampl ifier transfer d i rection :

/EN = 0 transfer from the control ler to the microprocessor /EN = 1 transfer from the microprocessor to the control ler

Because of th is , i n the buffered mode a program chooses the control ler type . The th i rd bit from ICW4 programs the buffered mode and the second bit programs the master/s lave type .

Cascaded Mode One 18259A master control ler can be i nterconnected with maximum 8

slave contro l lers to implement an i nterrupt system with 64 priority levels . The master controls the slave control lers through CASO . . . CAS2 cascading l ines . The slaves I NT outputs, in cascaded configuration , are

CASO CASO /EN CAS1 CAS1 /EN

CAS2 CAS2

I R O I R 1

I RO I R2 I R 1 1 7 I R 3 I R 2 I N T I R4 I R 3 I R S I R 4 I R6 I R S I R 7

1 7 I R 6 I N T I R 7

PIC MASTER PIC SLAVE

Fig . 4 . 5 PIC cascading in PC -AT

48


connected to the master I Ri inputs . If a slave i nterrupt request is active and th is i nterrupt request is the most prioritary one, the master wi l l va l idate the correspond ing s lave through the cascad ing l ines, so that the slave put the interrupt routine address or the interrupt type on the data bus .

4.5 The PIC employment i n PC I n PC-XT computers only one 18259A control ler is used , with 20h

reference address and having the 8 i nputs assigned to the off- l ine devices l isted below:

Interrupt Input Off - l ine device Vector ( type ) IRQO ( mo s t prior i t ary ) CO T imer 0 8 h ' IRQl Keyboard 0 9 h I RQ2 Not used OAh IRQ 3 COM2 O Sh I RQ4 COMl O Ch I RQS Hard Disk ODh I RQ 6 Fl oppy D i sk OEh I RQ 7 LPT O Fh

Tabla 4 . 3 P C - XT interrup t s emplcx-ment

I n PC-AT computers there are two cascaded control lers (see figure 4 .3 . ) , having 20h as master address and AOh for slave . The typical uti l ization and other possib le uti l ization are l isted in table 4 .2 .

Non-masked Interrupt (NMI) There is a separate p in for non-masked interrupt request, which is

active on edge. The " I " bit setting does not i nfluence the acceptance of N M I . The non-masked i nterrupt is used i n PC when a parity error is detected .

IRQ Priority Vector Typical Other Ut i l i ti e s Employment 0 1 0 8h Timer -1 2 0 9h Keyboard -

2 OAh Cascading Modem , EGA adapter , - ( I RQS - 1 5 ) COM3 / 4

OBh COM2 ( serial Modem , SB , COM4 , 3 1 1 port ) Network Cards ( NC ) 4 1 2 O Ch COMl COM3 , Modem , SB , NC

5 1 3 ODh Sound Blaster LPT2 / 3 , COM3 / 4 , ( SB ) , HD Modem , NC

6 1 4 O Eh Fl oppy D i s k Tape acce lerator Contro l l e r

49


7 1 5 O Fh LPTl ( Para l l e l LPT2 , COM3 / 4 , Modem , port ) SB , NC B 3 7 0h Real t ime c l ock -

9 4 7 1 h - NC , SB , SCSI adapter , PC! device

10 5 7 2 h - NC , SB , IDE channe l , PCI device 6 7 3 h NC , SB , SCSI adapter , 1 1 - VGA card

1 2 7 7 4 h - PS / 2 NC , SB , SCSI adapter , mouse IDE channe l

1 3 B 7 5 h Coproces sor -( FPU)

1 4 9 7 611 IDE - 1 channe l SCS I adapter ( HD ) 1 5 1 0 7 7 h IDE - 2 channe l SCSI adap t e r , NC

Table 4 . 4 PC-AT interrupts employment

4.6 Exercise a . Study the arch itecture and programming mode for the 18259A control ler

and the employment of the control ler in the IBM-PC compatible computers .

b . Write a test program for P IG . c . Where can we find the addresses of the interrupt handler routines i n

IVT, for the requests from the slave P IG inputs?

d . Write a program sequence which masks the i nterrupts coming from d ifferent devices (timer, keyboard , floppy d isk) and notice the effect after runn ing the program.

e . What is the role of the fol lowing sequence? mov a l , 2 0 h out 2 0h , a l

f. What is the IRET instruction run effect?

g . What i nvolves the two 18259A contro l lers cascading accord ing to the connections, programming and priorities?

50

Applications on the Interrupt System

5. APPLICATIONS ON TH E I NTERRU PT SYSTEM

5.1 The applications support

The appl ication presented below is an example of how the interrupt system can be used . This example shows the major aspects , such as the interrupt red i rect, its solving and the development of a hand ler routine .

On IRQ7 input (the less prioritary input destined for LPT paral le l port) of the 8259A control ler (master) there are two possib i l it ies to generate an interrupt: with a switch or from the channel 2 of a timer circu it with the base address 1 OOh (see fig . 5 . 1 ) . The interrupt source selection is done with a jumper.

' I '

SYSCLK/16

+5V

D S

CLK R

Q t-----.

GATE2 2 -....;::,_ _ : OUT2 i---=u1 CLI


i rq7_o l d d w 2 DUP ( ? ) Old irq7 interrupt addres s me s i n db O dh , Oah , " Push the but ton connec t ed t o

I RQ7 1 1 , O dh , Oah , " $" me s out db O dh , Oah , 11 Done 11 , Odh , Oah , 1 1 $ 1 1 charac ter db 3 0h DATA ENDS ; - - - - - - - - - - - - - - - - -CODE SEGMENT PARA PUBLI C ' CODE ' MAIN PROC FAR ASSUME CS : CODE , DS : DATA , SS : STACK , ES : NOTHING push ds xor ax , ax push ax mov ax , dat a mov ds , ax mov ah , 9

; for return

mov dx , of f s e t me s in ; me s s age display ; me s s age addre s s o f f s e t ; DOS interrupt cal l int 2 lh

c l i ; - - Red i rect interrupt IRQ7 to user ' s rout ine - - - - - - - -

mov ax_1;3 5 0 fh -:, Co?l-. ; Read t imer interrupt addres s in ES : BX .!I int 2 lh - - - - ; DOS interrupt cal l t _ uVP}( mov i rq7_o ld , bx Ct-Tiu&) save old interrupt o f f s e t addre s s

(l 'I- _ ,,,ry mov i rq7 o l d + 2 , e s ; and segment addres s .,(_ \:. ' -V '- push ds ' , -

mov dx , of f s e t me s out int 2 1h mov ah , 0 2 mov dl , 0 7 int 2 1h mov ax , 4 CO Oh int 2 1h MAIN ENDP

IRQ7 INT PROC NEAR push ax push ds mov ax , data mov ds , ax mov ah , O eh mov a l , charac ter int l Oh inc character


; beep at exi t

; end program t hrough ; exit DOS funct ion c a l l

; - - new interrupt rout ine - - -

; character display

mov a l , 7 generates s ound int l Oh ov al , 2 0h ; EOI

out 2 0h , al pop ds pop ax iret ; return END

; = = End = = ===-=== = = = = = = = = = = = = = = = = = = = = = = = = = = = code ends end ma in

; CODE segment end ; program end

* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * , ,

5.2 Exercise

a. Analyze the I NT7 .ASM appl ication and run it .

b . Rewrite the appl ication : us ing the control ler i n pol l i ng mode us ing software clean ing instead of the fl i p-flop .

c. Adapt the appl ication for the second interrupt source (channel2 - t imer)

d . The th i rd i nterrupt source i s a phone d ia l d isk (see figu re 5 .2 ) . Write an appl ication that takes the impulses from i t a nd d isp lays the d ialed number. Attention to clean ing !

53

IR 7

PC ,-........................... -........................................... .......................... .

! PARALLEL PORT 10 -ACK

+5

! - IRQBN

4K7

1 8 - 2 5 GND


Dial disk

Fig . 5 . 2 Dial disk application schematic

l. '"111

' lft>l"Ji L . .

. ; ' . . . .. .

54

The OMA Controller

6. THE DIRECT M EMORY ACCES CONTROLLER

6. 1 OMA transfer principle

The transfer of a data block between a periphera l device and the memory can be made using a program, with I N/OUT commands or using d i rect memory access. I n the fi rst case , the transfer is relatively slow (- 1 00ko/s) due to the necessary operations; the data fol lows the path (described in figure 6 . 1 ) : peripheral device - microprocessor - memory . To increase the speed of data transfer between faster periphera l equipment (Hard/Floppy d isc) and memory, if the external equ ipment has d i rect access to the memory, we have an advantage, i . e . avoid ing the data passing through the microprocessor. Th is leads to a transfer rate of - 1 Mo/s . This accessing mode is possible using the specia l ized DMAC ci rcuit (D i rect Memory Access Control ler) . The princip le of the DMA transfer is presented i n fig . 6 . 1 ) .

M 0 T Memory

+ i DMA I

' '

'

' : " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ... .. ... .. .. .. .. .. .. .. .. ... .. .. .. . ; - 1 11 I

Address Bus

Data Bus .. -

IQ IQ GI tJ 0 M

l ._ I .-: . . . . . . . . . . . , , . , , . , , , , , . . , . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 : -control Bus ..

Ill 0 M - HOLD ::fl

HLDA HLDA _ .

(> ... . . ...

I (; .. , -..391 '---------, _ . 'DREQ DMA Cont ro l l er DACK _

'

'

i l '

'

I ' l 1 111 1 Per ipheral

Devi c e

Fig . 6 . 1 Direct memory access transfer principle

-.

If the periphera l equipment has to write data in the memory, the necessary steps for implementing a DMA cycle are :

1 . The periphera l system performs a request through the DREQ signal to the DMA con

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Microprocessors. Architectures and Applications