Microprocessors seminar

7/30/2019 Microprocessors seminar

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whose invention is attributed to Jack Kilby of TI and Robert Noyce of Fairchild The first

practical IC was fabricated in 1959 at Fairchild and Texas Instruments and Fairchild

began its commercial manufacture in 1961 [Tredennick96].

As manufacturing technology evolved, more and more transistors were put on single

silicon chips with the maximum number of transistors per chip doubling every year

between 1961 and 1971 [Tredennick96]. The basic functional units evolved from simple

gates to arithmetic units, small memories, and special-purpose functions such as

multiplexers and decoders. In 1967 Fairchild introduced an 8-bit ALU chip that included

its own accumulator.

It was inevitable that someone would eventually invent the microprocessor because, by

the late 1960's, computers built from discrete transistors and simple integrated circuits

already existed. Moreover, integrated circuits were getting more and more complex day

by day.

1.1.1 Intel 4040

Credit for creating the world's first microprocessor, the Intel 4004, goes to Hoff and

Fagin, although William Aspray [Aspray97] in the Annals of the History of Computing

points out that the microprocessor's development was a more complex and interesting

story than many realize.

In 1969 Bob Noyce and Gordon Moore [FaginHoff97] set up the Intel Corporation to

produce semiconductor memory chips for the mainframe industry. A year later Intel

began to develop a set of calculator chips for a consortium of two Japanese companies.

One of Hoff's major contributions was to replace the complex and slow shift registers

used to store data in the calculator with the DRAM memory cells that Intel was

developing as storage elements. This step provided the system with more and faster

memory.

1.1.2 Intel 4004

Announcing a new Era of Integrated Electronics -Headlines, Intel 4004 Ad

The first functioning 4004 chip was created in 1971. Busicom's actual calculator was

constructed from a 4004 CPU, four 4001 ROMs, two 4002 RAMs and three 4003 shift

registers appeared in 1971. By the end of 1971 the 4004 was beginning to generate a

significant fraction of Intel's revenue.

1.1.3 Intel 8008


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Intel's 8008 microprocessor didn't last a long time. As the first 8-bit microprocessor it

was relatively crude and unsophisticated. It had a poorly implemented interrupt

mechanism and multiplexed address and data buses. The first really popular general-

purpose 8-bit microprocessor was Intel's 8080 (in production in early 1974). This had a

separate 8-bit data bus and 16-bit address bus. This address bus could address up to

216 = 64K bytes of data (a gigantic memory space in 1975).

1.1.4 Intel 8080

The Intel 8080 was the second 8-bit microprocessor designed and manufactured

by Intel and was released in April 1974 .[1] It was an extended and enhanced variant of

the earlier 8008 design, although without binary compatibility . The initial specified clock

frequency limit was 2 MHz and with common instructions having execution times of 4, 5,

7, 10 or 11 cycles this meant a few hundred thousand instructions per second . The

8080 has sometimes been labeled "the first truly usable microprocessor", although

earlier microprocessors were used for calculators and other applications. The

architecture of the 8080 strongly influenced Intel's 8086 CPU architecture, which

spawned the x86 family of processors.

1.1.5 Other Microprocessors

Shortly after the 8080 went into production, Motorola created its own competitor, the 8-

bit 6800. Although the 8080 and 6800 were broadly similar in terms of performance,

they had rather different architectures.

Frederico Faggin left Intel with Ralph Ungerman in 1994 to found Zilog. Their first

processor, the Z80, was manufactured in 1976. This device represented a considerable

advance over the 8080 and was object-code compatible with the 8080. That is, the

Z80's architecture was a superset of the 8080's architecture and could execute the

8080's machine code instructions.

Just as Fagin left Intel to create the Z80, Chuck Peddle left Motorola to join MOS

Technology and to create the 6502. The 6502's object code was not backward

compatible with the 6800.

Ed Roberts, the owner of a small company called MITS developed a microcomputer

was called Altair 8800.

1.2 Introduction to Intel 8085
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The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977. It was binary

compatible with the more-famous Intel 8080 but required less supporting hardware, thus

allowing simpler and less expensive microcomputer systems to be built. The "5" in the model number came from the fact that the 8085 requires only a +5-

volt (V) power supply, 80 is because of it is invented in decade 80 and 8 is due to 8 bit.

Both processors 8085 and 8080 were sometimes used in computers running the CP/M

operating system , and the 8085 also saw use as a microcontroller , by virtue of its low

component count. Both designs were eclipsed for desktop computers by the

compatible Zilog Z80 , which took over most of the CP/M computer market as well as

taking a share of the booming home computer market in the early-to-mid-1980s.

The 8085 had a long life as a controller. Once designed into such products as

the DECtape controller and the VT100 video terminal in the late 1970s, it served for

new production throughout the life span of those products (generally longer than the

product life of desktop computers).

The 8085 is a conventional von Neumann design based on the Intel 8080. Unlike the

8080 it does not multiplex state signals onto the data bus, but the 8-bit data bus was

instead multiplexed with the lower part of the 16-bit address bus to limit the number of

pins to 40. Pin No. 40 is used for the power supply (+5v) and pin No. 20 for ground. Pin

No. 39 is used as the hold pin. Pins No. 15 to No. 8 are generally used for address

buses. The processor was designed using nMOS circuitry and the later "H" versions

were implemented in Intel's enhanced nMOS process called HMOS, originally

developed for fast static RAM products. Only a 5 Volt supply is needed, like competing

processors and unlike the 8080. The 8085 uses approximately 6,500 transistors .[1]

The 8085 incorporates the functions of the 8224 (clock generator) and the 8228 (system

controller), increasing the level of integration. A downside compared to similar

contemporary designs (such as the Z80) was the fact that the buses required

demultiplexing; however, address latches in the Intel 8155, 8355, and 8755 memory

chips allowed a direct interface, so an 8085 along with these chips was almost a

complete system.

The 8085 has extensions to support new interrupts, with three maskable interrupts

(RST 7.5, RST 6.5 and RST 5.5), one non-maskable interrupt (TRAP), and one

externally serviced interrupt (INTR). The RST n.5 interrupts refer to actual pins on theprocessor, a feature which permitted simple systems to avoid the cost of a separate

interrupt controller.
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Like the 8080, the 8085 can accommodate slower memories through externally

generated wait states (pin 35, READY), and has provisions for Direct Memory

Access (DMA) using HOLD and HLDA signals (pins 39 and 38). An improvement over

the 8080 was that the 8085 can itself drive a piezoelectric crystal directly connected to

it, and a built in clock generator generates the internal high amplitude two-phase

clock signals at half the crystal frequency (a 6.14 MHz crystal would yield a 3.07 MHz

clock, for instance).

The 8085 is a binary compatible follow up on the 8080, using the same basic instruction

set as the 8080. Only a few minor instructions were new to the 8085 above the 8080

set.
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Chapter: 2

Architecture of 8085 Microprocessor

Intel 8085, introduced by Intel in 1977 is an 8-bit microprocessor. It was an update of Intel 8080 microprocessor. The 8080 processor was updated with Enable/Disable

instruction pins and Interrupt pins to form the 8085 microprocessor.

2.1 Features of 8085 microprocessor

8085 microprocessor is an 8 -bit microprocessor with a 40 pin dual in line package.

The address and data bus are multiplexed in this processor which helps in p roviding

more control signals.

8085 microprocessor has 1 Non -Maskable interrupt and 3 Maskable interrupts. Itprovides serial interfacing with serial input data (SID) and serial output data (SOD).

It has a set of registers for performing various operations. The various registers include

Accumulator (register A)

Registers: B, C, D, E, H and L

Stack pointer

Program Counter

Temporary register

Instruction register

2.2 Architecture of 8085 microprocessor

8085 consists of various units and each unit performs its own functions. The various

units of a microprocessor are listed below:

Accumulator

Arithmetic and logic Unit

General purpose register

Program counter

Stack pointer

Temporary register

Flags

In struction register and Decoder

Timing and Control unit

Interrupt cont rol

Serial Input/output control

Address buffer and Address-Data buffer

Address bus and Data bus


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Consider that an instruction is being executed by processor. As soon as the ALU

finished executing the instruction, the processor looks for the next instruction to be

executed. So, there is a necessity for holding the address of the next instruction to be

executed in order to save time. This is taken care by the program counter.

A program counter stores the address of the next instruction to be executed. In other

words the program counter keeps track of the memory address of the instructions that

are being executed by the microprocessor and the memory address of the next

instruction that is going to be executed.

Microprocessor increments the program whenever an instruction is being executed, so

that the program counter points to the memory address of the next instruction that is

going to be executed. Program counter is a 16-bit register.

2.2.5 Stack pointer

Stack pointer is also a 16 -bit register which is used as a memory pointer. A stack is

nothing but the portion of RAM (Random access memory).

So does that mean the stack pointer points to portion of RAM?

Yes. Stack pointer maintains the address of the last byte th at is entered into stack.

Each time when the data is loaded into stack, Stack pointer gets decremented.

Conversely it is incremented when data is retrieved from stack.

2.2.6 Temporary Register

As the name suggests this register acts as a temporary memory during the arithmetic

and logical operations. Unlike other registers, this temporary register can only be

accessed by the microprocessor and it is completely inaccessible to programmers.

Temporary register is an 8 -bit register.

2.2.7 Flags In 8085

Flags are nothing but a group of individual Flip -flops. The flags are mainly associated

with arithmetic and logic operations.

The flags will show either a logical (0 or 1) (i.e.) a set or reset depending on the data

conditions in accumulator or various other registers.

A flag is actually a latch which can hold some bits of information. It alerts the

processor that some event has taken place.

But why are they called flags?


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The possible solution is from the small flags which are found on the mail boxes in

America. The small flag indicates that there is a mail in the mail box. Similarly this

denotes that an event has occurred in the processor.

Intel processors have a set of 5 flags.

Carry flag

Parity flag

Auxiliary carry flag

Zero fla g

Sign flag

Consider two binary numbers.

For example:

100 0000

1000 0000

When we add the above two numbers, a carry is generated in the most significant bit.

The number in

the extreme right is least significant bit, while the number in extreme left is most

significant bit. So a

ninth bit is generated due to the carry. So how to accommodate 9th bit in an 8 bit

register?

For this purpose the Carry flag is used. The carry flag is set whenever a carry is

generated and reset

whenever there is no carry.

Parity checks whether its even or add parity. This flag returns a 0 if it is odd parity and

returns a 1 if it is an even parity. Sometimes they are also called as parity bit which is

used to check errors while data transmission is carried out. Zero flag shows whether the output of the operation is 0 or not. If the value of Zero

flag is 0 then the result of operation is not zero. If it is zero the flag returns value 1.


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Si gn flag shows whether the output of operation has positive sign or negative sign. A

value 0 is returned for positive sign and 1 is returned for negative sign.

2.2.8 Instruction Register and Decoder Instruction register is 8 -bit register just like every other register of microprocessor.

Consider an instruction. The instruction may be anything like adding two data's, moving

a data, copying a data etc. When such an instruction is fetched from memory, it is

directed to Instruction register. So the instruction registers are specifically to store the

instructions that are fetched from memory.

There is an Instruction decoder which decodes the information present in the

Instruction register for further processing.

2.2.9 Timing and Control Unit

Timing and control unit is a very important unit as it synchronizes the registers and

flow of data through various registers and other units. This unit consists of an oscillator

and controller sequencer which sends control signals needed for internal and external

control of data and other units.

The oscillator generates two -phase clock signals which aids in synchronizing all the

registers of 8085 microprocessor.

Signals that are associated wit h Timing and control unit are:

Control Signals: READY, RD, WR, AL E

Status Signals: S0, S1, IO/M

DMA Signals: HOLD, HLDA

RESET Signals: RESET IN, RESET OUT

2.2.10 Interrupt Control

As the name suggests this control interrupts a process.

Consider that a microprocessor is executing the main program.

Now whenever the interrupt signal is enabled or requested the microprocessor shifts

the control from main program to process the incoming request and after the completion

of request, the control goes back to the main program.

For example an Input/outp ut device may send an interrupt signal to notify that the data

is ready for input.

The microprocessor temporarily stops the execution of main program and tr ansfers

control to I/O device.

After collecting the input data the control is transferred back to main program.

2.2.11 Serial I/O control


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The input and output of serial data can be carried out using 2 instructions in 8085.

SID -Serial Input Data

SOD -Serial Output Data

Two more instructions are used to perform serial -parallel conversion needed for serial

I/O devices.

S IM

RIM

2.2.12 Address buffer and Address-Data buffer

The contents of the stack pointer and program counter are loaded into the address

buffer and address-data buffer. These buffers are then used to drive the external

address bus and address-data bus. As the memory and I/O chips are connected to

these buses, the CPU can exchange desired data to the memory and I/O chips.

The address -data buffer is not only connected to the external data bus but also to the

internal data bus which consists of 8-bits. The address data buffer can both send and

receive data from internal data bus.

2.2.13 Address bus and Data bus

We know that 8085 is an 8 -bit microprocessor. So the data bus present in the

microprocessor is also 8-bits wide. So 8-bits of data can be transmitted from or to the

microprocessor. But 8085 processor requires 16 bit address bus as the memory

addresses are 16-bit wide.

The 8 most significant bits of the address are transmitted with the help of address bus

and the 8 least significant bits are transmitted with the help of multiplexed address/data

bus. The eight bit data bus is multiplexed with the eight least significant bits of address

bus. The address/data bus is time multiplexed. This means for few microseconds, the 8

least significant bits of address are generated, while for next few seconds the same pin

generates the data. This is called Time multiplexing.

But there are situations where there is a need to transmit both data and address

simultaneously. For this purpose a signal called ALE (address latch enable) is used.

ALE signal holds the obtained address in its latch for a long time until the data is

obtained and so when the microprocessor sends the data next time the address is also

available at the output latch. This technique is called Address / Data demultiplexing.

2.3 8085 Microprocessor Pin Diagram description

Properties

Single + 5V Supply

4 Vectored Interrupts (One is Non Maskable)


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Serial In/Serial Out Port

Decimal, Binary, and Double Precision Arithmetic

Direct Addressing Capability to 64K bytes of memory

The Intel 8085A is a new generation, complete 8 bit parallel central processing unit

(CPU). The 8085A uses a multiplexed data bus. The address is split Between the 8 bit

Address bus and the 8 bit data bus.

Fig.2. : PIN Diagram of Intel 8085 Microprocessor

Fig.2. : Signal Groups of 8085


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Pin Description

2.3.1 A6 - A1s (Output 3 State)

Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0

Address, 3 stated during Hold and Halt modes.2.3.2 AD0 - 7 (Input/Output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address)

appear on the bus during the first clock cycle of a machine state. It then becomes the

data bus during the second and third clock cycles. 3 stated during Hold and Halt

modes.

2.3.3 ALE (Output)

Address Latch Enable: It occurs during the first clock cycle of a machine state and

enables the address to get latched into the on chip latch of peripherals. The falling

edge of ALE is set to guarantee setup and hold times for the address information.

ALE can also be used to strobe the status information. ALE is never 3stated.

2.3.4 SO, S1 (Output)

Data Bus Status. Encoded status of the bus cycle:

S1 S0

O O HALT

0 1 WRITE

1 0 READ

1 1 FETCH

S1 can be used as an advanced R/W status.

2.3.5 RD (Output 3state)

READ; indicates the selected memory or 1/0 device is to be read and that the Data

Bus is available for the data transfer.

2.3.6 WR (Output 3state)

WRITE; indicates the data on the Data Bus is to be written into the selected memory

or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt

modes.

2.3.7 READY (Input)

If Ready is high during a read or write cycle, it indicates that the memory or

peripheral is ready to send or receive data. If Ready is low, the CPU will wait for

Ready to go high before completing the read or write cycle.

2.3.8 HOLD (Input)


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HOLD; indicates that another Master is requesting the use of the Address and Data

Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as

soon as the completion of the current machine cycle. Internal processing can continue.

The processor can regain the buses only after the Hold is removed. When the Hold is

acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

2.3.9 HLDA (Output)

HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and

that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold

request is removed. The CPU takes the buses one half clock cycle after HLDA goes

low.

2.3.10 INTR (Input)INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only

during the next to the last clock cycle of the instruction. If it is active, the Program

Counter (PC) will be inhibited from incrementing and an INTA will be issued. During

this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt

service routine. The INTR is enabled and disabled by software. It is disabled by Reset

and immediately after an interrupt is accepted.

2.3.11 INTA (Output)INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD

during the Instruction cycle after an INTR is accepted. It can be used to activate the

8259 Interrupt chip or some other interrupt port.

RST 5.5

RST 6.5 - (Inputs)

RST 7.5

RESTART INTERRUPTS; These three inputs have the same timing as I NTR except

they cause an internal RESTART to be automatically inserted.

RST 7.5 ~~ Highest Priority

RST 6.5

RST 5.5 o Lowest Priority

The priority of these interrupts is ordered as shown above. These interrupts have a

higher priority than the INTR.

2.3.12 TRAP (Input)

Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as

INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of

any interrupt.


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2.3.13 RESET IN (Input)

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA

flipflops. None of the other flags or registers (except the instruction register) are

affected The CPU is held in the reset condition as long as Reset is applied.

2.3.14 RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is

synchronized to the processor clock.

2.3.15 X1, X2 (Input)

Crystal or R/C network connections to set the internal clock generator X1 can also be

an external clock input instead of a crystal. The input frequency is divided by 2 togive the internal operating frequency.

2.3.16 CLK (Output)

Clock Output for use as a system clock when a crystal or R/ C network is used as an

input to the CPU. The period of CLK is twice the X1, X2 input period.

2.3.17 IO/M (Output)

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and

Halt modes.

2.3.18 SID (Input)

Serial input data line The data on this line is loaded into accumulator bit 7 whenever a

RIM instruction is executed.

2.3.19 SOD (output)

Serial output data line. The output SOD is set or reset as specified by the SIM

instruction.

2.3.20 Vcc

+5 volt supply.

2.3.21 Vss

Ground Reference.

2.4 8085 microprocessor Functional Description

The 8085A is a complete 8 bit parallel central processor. It requires a single +5 volt

supply. Its basic clock speed is 3 MHz thus improving on the present 8080's

performance with higher system speed. Also it is designed to fit into a minimum

system of three IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip.

The 8085A uses a multiplexed Data Bus. The address is split between the higher 8bit


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Address Bus and the lower 8bit Address/Data Bus. During the first cycle the address

is sent out. The lower 8bits are latched into the peripherals by the Address Latch

Enable (ALE). During the rest of the machine cycle the Data Bus is used for memory

or l/O data.

The 8085A provides RD, WR, and lO/Memory signals for bus control. An Interrupt

Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are

synchronized. The 8085A also provides serial input data (SID) and serial output data

(SOD) lines for simple serial interface.

In addition to these features, the 8085A has three maskable, restart interrupts and one

non-maskable trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus

control.

2.4.1 Status Information

Status information is directly available from the 8085A. ALE serves as a status strobe.

The status is partially encoded, and provides the user with advanced timing of the

type of bus transfer being done. IO/M cycle status signal is provided directly also.

Decoded So, S1 Carries the following status information:

2.4.2 HALT, WRITE, READ, FETCH

S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of address

are multiplexed with the data instead of status. The ALE line is used as a strobe to

enter the lower half of the address into the memory or peripheral address latch. This

also frees extra pins for expanded interrupt capability.

2.4.3 Interrupt and Serial l/O

The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP. INTR

is identical in function to the 8080 INT. Each of the three RESTART inputs, 5.5, 6.5.

7.5, has a programmable mask. TRAP is also a RESTART interrupt except it is

nonmaskable.

The three RESTART interrupts cause the internal execution of RST (saving the

program counter in the stack and branching to the RESTART address) if the interrupts

are enabled and if the interrupt mask is not set. The non-maskable TRAP causes the

internal execution of a RST independent of the state of the interrupt enable or masks.

The interrupts are arranged in a fixed priority that determines which interrupt is to be

recognized if more than one is pending as follows: TRAP highest priority, RST 7.5,

RST 6.5, RST 5.5, INTR lowest priority This priority scheme does not take into

account the priority of a routine that was started by a higher priority interrupt. RST

5.5 can interrupt a RST 7.5 routine if the interrupts were re-enabled before the end of


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the RST 7.5 routine. The TRAP interrupt is useful for catastrophic errors such as

power failure or bus error. The TRAP input is recognized just as any other interrupt

but has the highest priority. It is not affected by any flag or mask. The TRAP input is

both edge and level sensitive.

2.4.4 Basic System Timing

The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower

8bits of address on the Data Bus. Figure 2 shows an instruction fetch, memory read

and l/ O write cycle (OUT). Note that during the l/O write and read cycle that the l/O

port address is copied on both the upper and lower half of the address. As in the 8080,

the READY line is used to extend the read and write pulse lengths so that the 8085A

can be used with slow memory. Hold causes the CPU to relingkuish the bus when it is

through with it by floating the Address and Data Buses.

2.4.5 System Interface

8085A family includes memory components, which are directly compatible to the

8085A CPU. For example, a system consisting of the three chips, 8085A, 8156, and

8355 will have the following features:

2K Bytes ROM

256 Bytes RAM

1 Timer/Counter

4 8bit l/O Ports

1 6bit l/O Port

4 Interrupt Levels

Serial In/Serial Out Ports

In addition to standard l/O, the memory mapped I/O offers an efficient l/O addressing

technique. With this technique, an area of memory address space is assigned for l/O

address, thereby, using the memory address for I/O manipulation. The 8085A CPU

can also interface with the standard memory that does not have the multiplexed

address/data bus.

2.5 The 8085 Programming Model

In the previous tutorial we described the 8085 microprocessor registers in reference to

the internal data operations. The same information is repeated here briefly to provide

the continuity and the context to the instruction set and to enable the readers who

prefer to focus initially on the programming aspect of the microprocessor.

The 8085 programming model includes six registers, one accumulator, and one flag

register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer


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and the program counter. They are described briefly as follows.

Fig.2. : Programming Model of 8085 Microprocessor


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Chapter: 3

Instruction Set of 8085

3.1 Instruction Naming Conventions:

The mnemonics assigned to the instructions are designed to indicate the function of the

instruction. The instructions fall into the following functional categories:

3.1.1 Data Transfer Croup:

The data transfer instructions move data between registers or between memory and

registers.

MOV MoveMVI Move Immediate

LDA Load Accumulator Directly from Memory

STA Store Accumulator Directly in Memory

LHLD Load H & L Registers Directly from Memory

SHLD Store H & L Registers Directly in Memory

An 'X' in the name of a data transfer instruction implies that it deals with a register pair (16-

bits);

LXI Load Register Pair with Immediate data

LDAX Load Accumulator from Address in Register Pair

STAX Store Accumulator in Address in Register Pair

XCHG Exchange H & L with D & E

XTHL Exchange Top of Stack with H & L

3.1.2 Arithmetic Group:

The arithmetic instructions add, subtract, increment, or decrement data in registers or

memory.

ADD Add to Accumulator

ADI Add Immediate Data to Accumulator

ADC Add to Accumulator Using Carry Flag

ACI Add Immediate data to Accumulator Using Carry

SUB Subtract from Accumulator

SUI Subtract Immediate Data from Accumulator

SBB Subtract from Accumulator Using Borrow (Carry) Flag

SBI Subtract Immediate from Accumulator Using Borrow (Carry) Flag

INR Increment Specified Byte by One


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DCR Decrement Specified Byte by One

INX Increment Register Pair by One

DCX Decrement Register Pair by One

DAD Double Register Add; Add Content of Register

Pair to H & L Register Pair

3.1.3 Logical Group:

This group performs logical (Boolean) operations on data in registers and memory and on

condition flags.

The logical AND, OR, and Exclusive OR instructions enable you to set specific bits in the

accumulator ON or OFF.

ANA Logical AND with Accumulator

ANI Logical AND with Accumulator Using Immediate Data

ORA Logical OR with Accumulator

OR Logical OR with Accumulator Using Immediate Data

XRA Exclusive Logical OR with Accumulator

XRI Exclusive OR Using Immediate Data

The Compare instructions compare the content of an 8-bit value with the contents of the

accumulator;

CMP Compare

CPI Compare Using Immediate Data

3.1.4 Rotating Group:

The rotate instructions shift the contents of the accumulator one bit position to the left or

right:

RLC Rotate Accumulator Left

RRC Rotate Accumulator Right

RAL Rotate Left Through Carry

RAR Rotate Right Through Carry

3.1.5 Complement and carry flag instructions:

CMA Complement Accumulator

CMC Complement Carry Flag

STC Set Carry Flag

3.1.6 Branch Group:

The branching instructions alter normal sequential program flow, either unconditionally or

conditionally. The unconditional branching instructions are as follows:

JMP Jump


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CALL Call

RET Return

Conditional branching instructions examine the status of one of four condition flags to

determine whether the specified branch is to be executed. The conditions that may be

specified are as follows:

NZ Not Zero (Z = 0)

Z Zero (Z = 1)

NC No Carry (C = 0)

C Carry (C = 1)

PO Parity Odd (P = 0)

PE Parity Even (P = 1)

P Plus (S = 0)

M Minus (S = 1)

Thus, the conditional branching instructions are specified as follows:

Jumps Calls Returns

C CC RC (Carry)

INC CNC RNC (No Carry)

JZ CZ RZ (Zero)

JNZ CNZ RNZ (Not Zero)

JP CP RP (Plus)

JM CM RM (Minus)

JPE CPE RPE (Parity Even)

JP0 CPO RPO (Parity Odd)

Two other instructions can affect a branch by replacing the contents or the program

counter:

PCHL Move H & L to Program Counter RST Special Restart Instruction Used

with Interrupts

3.1.7 Stack I/O, and Machine Control Instructions:

The following instructions affect the Stack and/or Stack Pointer:

PUSH Push Two bytes of Data onto the Stack

POP Pop Two Bytes of Data off the Stack

XTHL Exchange Top of Stack with H & LSPHL Move content of H & L to Stack Pointer

3.1.8 The I/O instructions are as follows:


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IN Initiate Input Operation

OUT Initiate Output Operation

3.1.9 The Machine Control instructions are as follows:

EI Enable Interrupt SystemDI Disable Interrupt System

HLT Halt

NOP No Operation

3.2 Addressing Modes

Addressing mode

Register - references the data in a register or in a register pair.

Register indirect - instruction specifies register pair containing address, where the data islocated.

Direct, Immediate - 8 or 16-bit

Instructions can be categorized according to their method of addressing the hardware

registers and/or memory.

3.2.1 Implied Addressing:

The addressing mode of certain instructions is implied by the instruction s function. For

example, the STC (set carry flag) instruction deals only with thecarry flag, the DAA (decimal adjust accumulator) instruction deals with the accumulator.

3.2.2 Register Addressing:

Quite a large set of instructions call for register addressing. With these instructions, you

must specify one of the registers A through E, H or L as well as the operation code. With

these instructions, the accumulator is implied as a second operand. For example, the

instruction CMP E may be interpreted as 'compare the contents of the E register with the

contents of the accumulator.Most of the instructions that use register addressing deal with

8-bit values. However, a few of these instructions deal with 16-bit register pairs. For

example, the PCHL instruction exchanges the contents of the program counter with the

contents of the H and L registers.

3.3.3 Immediate Addressing:

Instructions that use immediate addressing have data assembled as a part of the instruction

itself. For example, the instruction CPI 'C' may be interpreted as compare the contents of the accumulator with the letter C. When assembled, this instruction has the hexadecimal

value FE43. Hexadecimal 43 is the internal representation for the letter C. When this


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instruction is executed, the processor fetches the first instruction byte and determines that it

must fetch one more byte. The processor fetches the next byte into one of its internal

registers and then performs the compare operation.

Notice that the names of the immediate instructions indicate that they use immediate data.

Thus, the name of an add instruction is ADD; the name of an add immediate instruction is

ADI.

All but two of the immediate instructions uses the accumulator as an implied operand, as in

the CPI instruction shown previously. The MVI (move immediate) instruction can move its

immediate data to any of the working registers including the accumulator or to memory.

Thus, the instruction MVI D, OFFH moves the hexadecimal

value FF to the D register.

The LXI instruction (load register pair immediate) is even more unusual in that its immediate

data is a 16-bit value. This instruction is commonly used to load addresses into a register

pair. As mentioned previously, your program must initialize the stack pointer; LXI is the

instruction most commonly used for this

purpose. For example, the instruction LXI SP,3OFFH loads the stack pointer with the

hexadecimal value 30FF.

3.3.4 Direct Addressing:

Jump instructions include a 16-bit address as part of the instruction. For example, the

instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the

current contents of the program counter with the new value 1000H.

Instructions that include a direct address require three bytes of storage: one for the

instruction code, and two for the 16-bit address

3.3.5 Register Indirect Addressing:

Register indirect instructions reference memory via a register pair. Thus, the instruction

MOV M,C moves the contents of the C register into the memory address stored in the H

and L register pair. The instruction LDAX B loads the accumulator with the byte of data

specified by the address in the B and C register pair.

3.3.6 Combined Addressing Modes:

Some instructions use a combination of addressing modes. A CALL instruction, for

example, combines direct addressing and register indirect addressing. The direct address

in a CALL instruction specifies the address of the desired subroutine; the register indirect

address is the stack pointer. The CALL instruction pushes the current contents of the

program counter into the memory location specified by the stack pointer.

3.3.7 Timing Effects of Addressing Modes:


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Addressing modes affect both the amount of time required for executing an instruction and

the amount of memory required for its storage. For example, instructions that use implied or

register addressing, execute very quickly since they deal directly with the processor s

hardware or with data already present in hardware registers. Most important, however is

that the entire instruction can be fetched with a single memory access. The number of

memory accesses required is the single greatest factor in determining execution timing.

More memory accesses therefore require more execution time. A CALL instruction for

example, requires five memory accesses: three to access the entire instruction and two

more to push the contents of the program counter onto the stack.

The processor can access memory once during each processor cycle. Each cycle

comprises a variable number of states. (See below and the appendix of USING THE SDK -

85 MICROPROCESSOR TRAINER). The length of a state depends on the clock frequency

specified for your system, and may range from 480 nanoseconds to 2 microseconds. Thus,

the timing for a four state instruction may range from 1.920 microseconds through 8

microseconds. (The 8085 have a maximum clock frequency of 5 MHz and therefore a

minimum state length of 200 nanoseconds.)

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