12.5.03

הטכניון - מכון טכנולוגי לישראל

המעבדה למערכות סיפרתיות מהירותהפקולטה להנדסת חשמל

Mid-Term PresentationMid-Term Presentation

  Fast Ethernet Card with FPGAFast Ethernet Card with FPGAProject num. 0622Project num. 0622

Students:Students: Alex ShpinerAlex Shpiner

Eyal AzranEyal Azran

Supervisor:Supervisor: Boaz MizrahiBoaz Mizrahi

Project Description Programming FPGA device on the network card which Programming FPGA device on the network card which

connects PCI Bus with Fast Ethernet network.connects PCI Bus with Fast Ethernet network.

Transmitting and receiving packages over the network.Transmitting and receiving packages over the network.

Developing algorithm for arbitration between transmitting Developing algorithm for arbitration between transmitting

and receiving packages.and receiving packages.

Allowing future development of the device, such as adding Allowing future development of the device, such as adding

UTOPIA port or manipulation of the transmitted packages.UTOPIA port or manipulation of the transmitted packages.

General scheme of the card:General scheme of the card:

UTOPIA FPGA Ethernet Interface

PCI Interface

MAC PHY

PLX

PCIBridge

MAC

PHY

CIF

GNR

MCF

TRN

RCV

ARB

Scheme of the blocks in the FPGA:Scheme of the blocks in the FPGA:

Shared bus

PCI

ETHERNET

Path of the packages over the card:

PCIBridge

MAC+

PHYCIF

TRN

RCV

FIFO

FIFO FIFO

FIFO

FPGA

ARB Shared bus

Transmitting rates and FIFO sizes:

FPGATRN FIFO

FPGARCV FIFO

MAC TRN FIFO

MACRCV FIFO

PCI

ETHERNET100

Mbit/sec1

Gbit/sec1

Gbit/sec

128 bytes2kbytes

Quantum calculation

Time to fill MAC FIFO = 128X8bit/100 Mbitps = 10240 nsClock cycle = 1/33Mhz = 31 nsCycles to fill MAC FIFO = 10240/31 = 331 cyclesFPGA-MAC transfer rate = 33Mhz X 32bit = 1Gbit/sTime to flush MAC FIFO = 128X8bit/32 bits = 32 cycles

=> Quantum = 32 cycles

Focus on the arbitration algorithm

ARBTRN RCV

request

done

grant

done

request

grant

Arbitration algorithmArbitration algorithm

Algorithm is based on round robin technique. Each entity will have specified quantum time. Early finish – by raising DONE signal. Receiver has higher priority than the transmitter. FIFO overflow control by interrupts.

Arbitration with PCI bus and devices configuration is controlled by sending specific address to the CIF.Wide range of addresses will be used for future expansions.

ScheduleSchedule

21/05/03 - Simulate and synthesize RCV unit.28/05/03 - Test and debug RCV unit.04/06/03 - Write ARB code.11/06/03 - Simulate and debug ARB.18/06/03 - Connecting ARB with the components.25/06/03 - Simulate and debug whole system.

Final Moed A Exams.30/07/03 - Final testing on the hardware.06/08/03 - Finalize project book.