Midterm Exam 06: Exercise 2 Atomic Shared Memory

Midterm Exam 06:Midterm Exam 06:Exercise 2Exercise 2

Atomic Shared MemoryAtomic Shared Memory

Midterm Exam: Exercise 2 – Atomic shared memory

Slide 2

Atomic registerAtomic register• Every failed (write) operation appears to Every failed (write) operation appears to be either complete or not to have been be either complete or not to have been invoked at allinvoked at all

AndAnd• Every complete operation appears to be Every complete operation appears to be executed at some instant between its executed at some instant between its invocation and reply time events invocation and reply time events

• In other words, atomic register is:In other words, atomic register is:•Regular (READ returns the latest value written,

or one of the values written concurrently), and•READ rd’ that follows some (complete) read rd does not return an older value (than rd)


Slide 3

Non-Atomic Execution 1Non-Atomic Execution 1

P2

P1

W(5) W(6)

R1() -> 5 R2() -> 0 R3() -> 25


Slide 4


P2

P1

W(5) W(6)

R1() -> 5 R2() -> 6 R3() -> 5


Slide 5


P2

P1

W(5)

R() -> 6

P2

P1

W(5)

R() -> 5

W(6)crash


Slide 6

Atomic Execution 1Atomic Execution 1

P2

P1

W(5) W(6)

R1() -> 5 R2() -> 5 R3() -> 5


Slide 7


P2

P1

W(5) W(6)

R1() -> 5 R2() -> 6 R3() -> 6


Slide 8

P2

P1

W(5)

R() -> 5

W(6)crash



Slide 9

P2

P1

W(5)

R() -> 5

P2

P1

W(5)

R() -> 6

W(6)crash



Slide 10

Best case complexityBest case complexity• We build algorithms for the worst We build algorithms for the worst case (or case (or unlucky) unlucky) situationssituations• Asynchrony• Concurrency• Many failures

• However, very frequently situation However, very frequently situation is not that bad (is not that bad (luckylucky executions) executions)• Synchrony• No concurrency• Few failures (or none at all)

• Practical algorithms should take Practical algorithms should take advantage of the advantage of the luckylucky executions executions


Slide 11

Exercise 2Exercise 2• Give a 1-writer n-reader atomic Give a 1-writer n-reader atomic register implementation (n=5, majority register implementation (n=5, majority of processes is correct) in whichof processes is correct) in which• L2: all read/write operations* complete in at most 2 round-trips• In every round-trip, a client (writer or reader) sends a message to all processes and awaits response from some subset of processes

• L1: all lucky read/write operations* should complete in a single round-trip• A read/write operation op is lucky if:

• The system is synchronous: messages among correct processes delivered within the time (known to all correct processes)

• op is not concurrent with any write operation• At most one process is faulty

*invoked by a correct client


Slide 12

The majority algorithm The majority algorithm [ABD95][ABD95]

• All reads and writes complete in a All reads and writes complete in a single round-tripsingle round-trip• A client sends a message to all processes and waits for response from a majority

• However, this algorithm implements However, this algorithm implements only only regularregular register (not register (not atomic)atomic)

• To make the algorithm atomic: To make the algorithm atomic: • readers impose a value with a highest timestamp to a majority of processes (requires a second round-trip)


Slide 13

Lucky operationsLucky operations• If the operation is lucky, the client will If the operation is lucky, the client will be able to receive (at least) 4 (out of 5) be able to receive (at least) 4 (out of 5) responses responses

timer=2timer=2

tt t+2t+2t+t+


Slide 14

SolutionSolution

• In the following slides we In the following slides we modify the majority algorithm of modify the majority algorithm of [ABD95][ABD95]• [ABD95] is given in slides 30-32, Regular Register Algorithms lecture notes – in Shared Memory part 2


Slide 15

Algorithm - Write()Algorithm - Write()• Write(v) at p1 (the writer)Write(v) at p1 (the writer)

• ts1++• trigger(timer=2)• send [W,ts1,v] to all• when receive [W,ts1,ack] from majority

• Wait for expiration of timer

• If received 4 acks then• Return ok

• else• Send [W2,ts1,v] to all• when receive [W2,ts1,ack] from majority

• Return ok

• At piAt pi• when receive [W,ts1, v] from p1

• If ts1 > sni then• vi := v• sni := ts1

• send [W,ts1,ack] to p1

• when receive [W2,ts1, v] from p1

• If ts1 > sni2 then• vi2:= v• sni2 := ts1

• send [W2,ts1,ack] to p1


Slide 16

How the (How the (luckylucky) write works) write works

p1 p1

(writer)(writer)

p2p2

p3p3

p4p4

p5p5

write(v)write(v)

ts1++ ts1++ %ts1=1%ts1=1

trigger(timer=2)send [W,ts1,v] to all

vi,snivi,sniv2i,sn2iv2i,sn2i



vi,snivi,sniv2i,sn2iv2i,sn2iv0,0v0,0v0,0v0,0

v0,0v0,0 v0,0v0,0

v0,0v0,0v0,0v0,0

v0,0v0,0v0,0v0,0

v0,0v0,0v0,0v0,0v1,1v1,1

v1,1v1,1

v1,1v1,1

v1,1v1,1

ACKACK


Slide 17

How the How the (unlucky)(unlucky) write write worksworks

p1 p1

(writer)(writer)

p2p2

p3p3

p4p4

p5p5

write(v)write(v)

ts1++ ts1++ %ts1=1%ts1=1

trigger(timer=2)send [W,ts1,v] to all




vi,snivi,sniv2i,sn2iv2i,sn2iv0,0v0,0v0,0v0,0

v0,0v0,0 v0,0v0,0

v0,0v0,0 v0v0,,00

v0,0v0,0

v0,0v0,0v0,0v0,0v1,1v1,1

v1,1v1,1

v1,1v1,1

ACKACK

v0,0v0,0send[W2,ts1,v] to send[W2,ts1,v] to

allall

wait for majority wait for majority of acksof acks

v1,1v1,1

v1,1v1,1

v1,1v1,1


Slide 18

Algorithm - Read()Algorithm - Read()• Read() at piRead() at pi

• rsi++• trigger(timer=2)• send [R,rsi] to all• when receive [R,rsi,snj,vj] from majority

• v := vj with the largest snj

• Return v

• At piAt pi• when receive [R,rsj] from pj

• send [R,rsj,sni,vi] to pj


Slide 19


• rsi++• trigger(timer=2)• send [R,rsi] to all• when receive [R,rsi,snj,vj,sn2j,v2j] from majority

• Wait for expiration of timer

• v := vj with the largest snj

• Return v


• send [R,rsj,sni,vi,sn2i,v2i] to pj


Slide 20


• rsi++• trigger(timer=2)• send [R,rsi] to all• when receive [R,rsi,snj,vj,sn2j,v2j] from majority

• Wait for expiration of timer• v := vj or v2j with the largest snj or sn2j

• If v is some v2j or there are 3 responses where vj=v and snj=snMAX then• Return v

• else • Send [W,ts1,v] to all• when receive [W,ts1,ack] from majority

• Return ok


• send [R,rsj,sni,vi,sn2i,v2i] to pj


Slide 21

How the How the lucky lucky read worksread works

p2p2

p3p3

p4p4

p5p5

p1p1

Following the Following the luckylucky write write

p5 knows that a value with p5 knows that a value with the largest timestamp the largest timestamp has already been imposed has already been imposed to a majority to a majority (in our case p2,p3 (in our case p2,p3 and p4)and p4)


Slide 22

How the How the lucky lucky read worksread works

p2p2

p3p3

p4p4

p5p5

p1p1

Following the Following the unlucky (2 round-trip)unlucky (2 round-trip) write write

p5 saw a (at least one) p5 saw a (at least one) « green » value with the « green » value with the largest timestamp: largest timestamp: hence, this value has hence, this value has already been imposed to already been imposed to a majority in the 1st a majority in the 1st round-trip of the writeround-trip of the write


Slide 23

Unlucky readUnlucky read• Must impose a value with the largest Must impose a value with the largest timestamp to a majority of processestimestamp to a majority of processes• If v is some v2j or there are 3 responses where vj=v and snj=snMAX then• Return v

• else • Send [W,ts1,v] to all• when receive [W,ts1,ack] from majority • Return ok

• W not W2! W not W2! • Readers impose a value on « yellow » not « green » variables

• Only the writer writes into the « green » variables (v2i,sn2i)


Slide 24

An offline exerciseAn offline exercise

• Try to rigorously prove Try to rigorously prove correctness of this algorithmcorrectness of this algorithm

• Proving correctness may appear Proving correctness may appear on the final examon the final exam

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Midterm Exam 06: Exercise 2 Atomic Shared Memory