MIPS architecture (single cycle, no pipeline) - Eurecomsoc.eurecom.fr/CompArch/lectures/MIPS/main.pdfMIPS architecture (single cycle, no pipeline) S. Coudert and R. Pacalet January

Computer Architecture

MIPS architecture (single cycle, nopipeline)

S. Coudert and R. PacaletJanuary 4, 2018

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Outline

Introduction

Data paths

Assembling data paths

Control logic

Examples

Designing the control logic

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.2/41 S. Coudert and R. Pacalet January 4, 2018

Outline

Introduction

Data paths


Control logic

Examples


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Introduction

Instruction Set Architecture (ISA): functional descriptionCPU architecture: ISA hardware implementationMain architecture components:

• Combinatorial– Operators (computing units, data paths)– Multiplexors (select inputs depending on current instruction)

• Storage: registers, register files, on-chip and off-chip RAMs. . .• Wires and buses (connect storage and operators)• Finite state machines (controllers)

Main steps of CPU architecture design:• Identify data paths for each instruction and each instruction step• Assemble data paths with wires, buses and multiplexors• Design control and controllers

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The global picture

i

j

k$j

$ib

$k

21 3

a

Control

PC

reg1 (read)

reg2 (read)

reg3 (write)

RegistersProgram

memory

addressrdata1

rdata2

wdata

rdata

wdata

rdata

address

Data

memory

AL

U

Program counter provides address to program memoryInstruction fields specify operation (control) and operands (registers, immediate)ALU computes results

• To be stored in a register (a)• To be used as a memory address (b)

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Program Counter (PC) and instruction fetch

Instruction (32 bits)

AD

DMU

X

4PC+4

PC

Program

memory

address

rdata

MIPS addressing unit: byteRegisters and instructions: 32 bits (4 bytes)Pointing to next instruction: add 4 to PC

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Outline

Introduction

Data paths


Control logic

Examples


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Data path for R-format instructionsAssembly: OP $k, $i, $j ($k ← $i OP $j)ALU function specified by func instruction field

k

j

i

$j

$k

$i

write enable

Instruction

0

shift

dst

src2src1

op

i j shiftkop funct

fun

ct

Registers

Control

wdata

wr

rd2

rd1

rdata1

rdata2

AL

U

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Data path for load instructionsAssembly: lw $j, 100($i) ($j ←Mem[$i +100])Address shift converted from 16 to 32 bits (signed extension)

$ij

i

100100

16 32

$i+100

$j :

add

Mem($i+100)write signalread signal

instruction

35

add

dest

address sh

ift

i j35 100

extended

Sign

Memory

MemData

dataWrite

AddressALUReadregister 2

Readregister 1

Writeregister

Writedata

Registers

Readdata 1

data 2Read

Control

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Data path for store instructions

Assembly: sw $j, 100($i) (Mem[$i +100]← $j)

$ij

i

100100

16 32

$i+100

add

$j :

write signal

instruction

i j 10043

add

add

ress shift

43

src

extended

Sign

ALU

Memory

MemData

dataWrite

AddressReadregister 2

Readregister 1

Writeregister

Writedata

Registers

Readdata 1

data 2Read

Control

Mem($i+100)

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Data path for branch instructionsAssembly: beq $i, $j, 100 (goto +100 instr. if $i == $j)n instructions = 4×n address shift (left shift by 2)

leftshift

2

PC+4

PC

$ij

i

$j :

16 32

100100

sele

cts

PC

so

urc

e

zero?

subtract

instruction

i j 1004

address sh

ift4

regreg

extended

Sign

ALU

AD

D

Readregister 2

Readregister 1

Writeregister

Writedata

Registers

Readdata 1

data 2Read

Control

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Outline

Introduction

Data paths


Control logic

Examples


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1

0

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 20−15

Ins 25−21

instruction

Ins 15−0

Combining R−format with load andimmediate arithmetic instructions:

a multiplexor to select the destination register

Ins 15−11

Ins 31−26

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16 32

Result

ZeroALU

1

0

1

0

Signextend

Combining R−format with load, writeand immediate arithmetic instructions:

a multiplexor to select the second ALU operand

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 20−15

Ins 25−21

instruction

Ins 15−0

Ins 15−11

Ins 31−26

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ALUCtrl

16 32

Result

ZeroALU

1

0

1

0

Signextend

Combining R−format with load andimmediate arithmetic instructions:

a multiplexor to select the signalto write in destination register

Writedata

Address

MemoryData

Data

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 20−15

Ins 25−21

instruction

Ins 15−0

Ins 5−0

1

0

Ins 15−11

Ins 31−26

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Instructions

ALUCtrl

16 32

4

Result

ZeroALU

Memory

Ins 31−0

Address

Writedata

Address

MemoryData

Data

Signextend

AD

D

1

0

1

0

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 15−11

Ins 20−15

Ins 25−21

PC

with instruction execution

Ins 15−0

Ins 5−0

0

1

Ins 31−26

Combining instruction fetch

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Instructions

ALUCtrl

16 32

4

Result

ZeroALU

Memory

Ins 31−0

Address

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

AD

D

1

0

1

0

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 20−15

Ins 25−21

PC

AD

D

0

1

Ins 15−0

with branch instructions

a multiplexor to select PC source

Combining PC increment

Ins 5−0

1

0

Ins 15−11

Ins 31−26

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Data paths: global picture

Instructions

ALUCtrl

16 32

4

Result

ZeroALU

Memory

Ins 31−0

Address

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

AD

D

1

0

1

0

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 20−15

Ins 25−21

PC

AD

D

0

1

Ins 15−0

Ins 5−0

0

1

Ins 15−11

Ins 31−26

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Outline

Introduction

Data paths


Control logic

Examples


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Control signals

Instructions

ALUCtrl

16 32

4

1

0

1

0Result

ZeroALU

Memory

Ins 31−0

Address

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

AD

D

DestReg

Branch

MemRead

MemWrite

RegWrite

ALUsrc

ALUop

MemToRegReadregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 20−15

Ins 25−21

PC

AD

D

0

1

Ins 15−0

Ins 5−0

Ins 15−11

Ins 31−26

1

0

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Control logic

Instructions

ALUCtrl

con

tro

l

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

16 32

4

1

0Result

ZeroALU

Memory

Ins 31−0

Address

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

AD

D

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 20−15

Ins 25−21

PC

AD

D

0

1

Ins 15−0

Ins 5−0

1

0

1

0

Ins 15−11

Ins 31−26

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ALU control logic

ALU

Ctrl Decoder

con

tro

l

OP

co

de

Controlerimplementation

function field

5

Result

Zero

ALU

ALUop

function field

ALU control entryALU control entry

2ALUop

AND

OR

ADD

000

001

010

110

111

ALU control entry Arithmetic or logical operation

ALU behaviour

SUB

1 if src1 < src2, else 0

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ALU decoder

ALU control block

Decoder

lw 00 load xxxxxx addition

sw

beq

R−type

R−type

R−type

R−type

R−type

00

01

10

10

10

10

10

store

addition

branch if =

substraction

or

and

xxxxxx

xxxxxx

100000

100010

100100

100101

101010

addition

substraction

addition

substraction

or

and

OP code ALUop instr OP codefunction

control entryALU

1 if <, else 0 1 if <, else 0

function field

ALU control entry

ALUop

func[0]

func[1]

func[2]

func[3]

ALUop[1]

ALUop[0]

ALU[2]

ALU[1]

ALU[0]

ALUop

ALU control entryfu

nct

ion

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Outline

Introduction

Data paths


Control logic

Examples


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Execution example: R-format

Example: add $1,$2,$3 ($1← $2+$3)0 12 3 0 32

Corresponding pseudo-code:

1: Instr ←Memory [PC]2: PC ←PC+43: ALU_inA←Registers[Instr [25 : 21]];ALU_inB ←Registers[Instr [20 : 16]]4: ALU_out ←ALU_inA+ALU_inB5: Registers[Instr [15 : 11]]←ALU_out

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ALUCtrl

Instructions

con

tro

l

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

16 32

4

0 12 3 0 32

1

0

1

0Result

ZeroALU

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

AD

D

Memory

Ins 31−0

Address

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 20−15

Ins 25−21

PC

AD

D

0

1

Ins 15−0

Ins 5−0

1

0

Ins 15−11

Ins 31−26

$1← $2+$3Instr ←Memory [PC]

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ALUCtrl

Instructions

con

tro

l

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

16 32

4

0 12 3 0 32

00

1

0

1

0Result

ZeroALU

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

Memory

Ins 31−0

Address

AD

D

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 20−15

Ins 25−21

AD

D

Ins 15−0

Ins 5−0

1

0

PC

0

1

Ins 15−11

Ins 31−26

$1← $2+$3PC ←PC+4

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ALUCtrl

Instructions

con

tro

l

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

16 32

4

0 12 3 0 32

2

3 $2

$3

0

1

0Result

ZeroALU

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

AD

D

Memory

Ins 31−0

Address

1

0Writeregister

Writedata

data 2Read

Registers

PC

AD

D

0

1

Ins 15−0

Ins 5−0

register 1Read

Readregister 2

Readdata 1

1

0

Ins 15−11

Ins 31−26

$1← $2+$3 ALU_inA←Registers[Instr [25 : 21]]ALU_inB ←Registers[Instr [20 : 16]]

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Instructions

ALUCtrl

con

tro

l

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

16 32

4

0 12 3 0 32

2

3 $2

32

32

10

010

$3

1

0

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

AD

D

Memory

Ins 31−0

Address

Result

ZeroALU

1

0Writeregister

Writedata

data 2Read

Registers

PC

AD

D

0

1

register 1Read

Readregister 2

Readdata 1

1

0

Ins 15−11

Ins 31−26

$1← $2+$3ALU_out ←ALU_inA+ALU_inB

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Instructions

ALUCtrl

con

tro

l

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

16 32

DestReg

RegWrite

4

0 02 3 1 32

2

3 $2

$3

32

32

1

−> $1

0

1

1

1

0

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

Memory

Ins 31−0

Address

AD

D

Result

ZeroALU

1

0

Registers

PC

AD

D

0

1

register 1Read

Readregister 2

Readdata 1

registerWrite

Writedata

data 2Read

1

0

Ins 31−26

$1← $2+$3Registers[Instr [15 : 11]]←ALU_out

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Instructions

ALUCtrl

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

16 32

4

con

tro

l

02 3 1 320

2

3 $2

$3

32

32

1

−> $1

0

0 0

01

10

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

AD

D

Memory

Ins 31−0

Address

Result

ZeroALU

1

0

1

0

PC

AD

D

register 1Read

Readregister 2

Readdata 1

registerWrite

Writedata

data 2Read

1

0

1

0

Registers

$1← $2+$3

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Execution example: load

Example: lw $2,100($1) ($2←Memory [$1+100)1 2 10035

Corresponding pseudo-code:

1: Instr ←Memory [PC]2: PC ←PC+43: ALU_inA←Registers[Instr [25 : 21]];ALU_inB ← sign_ext([Instr [15 : 0]])4: ALU_out ←ALU_inA+ALU_inB5: Registers[Instr [20 : 16]]←Memory [ALU_out]

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ALUCtrl

Instructions

con

tro

l

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

16 32

4

PC=PC+4Instr=Mem[PC]

00

1 2 10035lw $2, 100($1)

1

0

1

0Result

ZeroALU

Writedata

Address

MemoryData

Data

Signextend

Shiftleft 2

AD

D

Memory

Ins 31−0

Address

Readregister 1

Readregister 2

Writeregister

Writedata

Readdata 1

data 2Read

Registers

Ins 20−15

Ins 25−21

AD

D

Ins 15−0

Ins 5−0

1

0

PC

1

0

Ins 15−11

Ins 31−26

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ALUCtrl

Instructions

con

tro

l

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

4

16 32

35

ALU_inA=Reg[Instr[25−21]]1 2 100

100

1

$1

100

1

ALU_inB=s_ext(Instr[15−0])lw $2, 100($1)

1

0Result

ZeroALU

Writedata

Address

MemoryData

Data

Shiftleft 2

AD

D

Memory

Ins 31−0

Address

Signextend

1

0Writeregister

Writedata

Ins 20−15

AD

DIns 5−0

1

0

PC

register 1Read

Registers

Readdata 1

Readdata 2

1

0

register 2Read

Ins 15−11

Ins 31−26

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Instructions

ALUCtrl

con

tro

l

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

4

16 32

35 1 2 100

100

1

100

00

$1

x

Mem_Addr=ALU_inA+ALU_inBlw $2, 100($1)

Result

ZeroALU

Writedata

Address

MemoryData

Data

Shiftleft 2

AD

D

Memory

Ins 31−0

Address

1

0

Signextend

1

0

Ins 20−15

AD

DIns 5−0

PC

register 1Read

Registers

Readdata 1

Readdata 2

1

0

register 2Read

Ins 15−11

0

1registerWrite

Writedata

Ins 31−26

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Instructions

ALUCtrl

con

tro

l

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

4

16 32

35 1 2 100

100

1

100

2

−> $2

1

0

$1

Reg[Inst[20−16]=Mem_datalw $2, 100($1)

Result

ZeroALU

Writedata

Address

MemoryData

Data

Shiftleft 2

AD

D

Memory

Ins 31−0

Address

1

0

Signextend

1

0

Ins 20−15

AD

DIns 5−0

PC

register 1Read

Registers

Readdata 1

Readdata 2

1

0

register 2Read

dataWrite

Writeregister

0

1

Ins 15−11

Ins 31−26

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Instructions

ALUCtrl

con

tro

l

DestReg

Branch

MemRead

MemToReg

ALUop

MemWrite

ALUsrc

RegWrite

4

16 32

35 1 100

100

1

$1

100

2

−> $2

1

0

00

2

00

x

lw $2, 100($1)

Result

ZeroALU

Shiftleft 2

1

0

AD

D

1

0

Memory

Ins 31−0

Address

Signextend

Writedata

Address

MemoryData

Data

Ins 20−15

AD

DIns 5−0

register 1Read

Registers

Readdata 1

Readdata 2

register 2Read

dataWrite

Writeregister

0

1

PC

1

0

Ins 15−11

Ins 31−26

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Outline

Introduction

Data paths


Control logic

Examples


..........

.....

......

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.....

.....

......

.....

.....

.....

......

.....

.....

.....

......

.....

......

.....

.....


Control function

R−

form

at

LW

OU

TP

UT

SIN

PU

TS

Control function can be defined by truth tables

OP5

OP2

OP1

OP4

OP3

OP0

DestReg

ALUsrc

MemToReg

RegWrite

MemRead

MemWrite

Branch

ALUop1

ALUop0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

0

1

0

0

0

1

1

0

1

1

1

1

0

0

0

0

..........

.....

......

.....

.....

.....

......

.....

.....

.....

......

.....

.....

.....

......

.....

......

.....

.....


Control function

R−

form

at

OU

TP

UT

SIN

PU

TS

Control function can be defined by truth tables

OP5

OP2

OP1

OP4

OP3

OP0

DestReg

ALUsrc

MemToReg

RegWrite

MemRead

MemWrite

Branch

ALUop1

ALUop0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

0

1

0

0

0

1

1

0

1

1

1

1

0

0

0

0

1

0

1

0

1

1

x

1

x

0

0

1

0

0

0

0

0

0

1

0

0

x

0

x

0

0

0

1

0

1

LW

SW

BE

Q

..........

.....

......

.....

.....

.....

......

.....

.....

.....

......

.....

.....

.....

......

.....

......

.....

.....


Control implementation

BE

Q

SW

LW

R−

form

at

OP0OP1OP2OP3OP4OP5

DestReg

ALUsrc

MemToReg

RegWrite

MemRead

MemWrite

Branch

ALUop1

ALUop0

IN

PU

TS

OU

TP

UT

S

..........

.....

......

.....

.....

.....

......

.....

.....

.....

......

.....

.....

.....

......

.....

......

.....

.....


Documents

MIPS architecture (single cycle, no pipeline) - Eurecomsoc.eurecom.fr/CompArch/lectures/MIPS/main.pdfMIPS architecture (single cycle, no pipeline) S. Coudert and R. Pacalet January