MIPS Assembly Tutorial

Types of Instructions

• There are 3 main types of assembly instructions– Arithmetic - add, sub, mul, shifts, and, or,

etc.– Load/store– Conditional - branches

Arithmetic Instructionsadd a, b, c a = b+cadd a, a, d a = d+a = d+b+cadd a, a, e a = e+a = e+d+b+c

Example: Translate the following instructions to assembly code

a = b+cd = a-e

Solution:

add a, b, csub d, a, e

Arithmetic InstructionsExample: Translate the following instructions to assembly code. Remember with RISC, only 1

operation per instruction! HINT - you may need temporary variables

f = (g+h) - (i+j)

Solution:

add t0, g, hadd t1, i, jsub f, t0, t1

Operands

• In assembly code, you can’t use variables such as a, b, c, etc

• In RISC instruction sets, operands must be registers such as r1, r2, r3, etc– r0 is typically reserved to hold the

immediate value of 0 – There is a limited number of registers

• MIPS has 32

Arithmetic Instructions Using Registers

Example: Translate the following instructions to assembly code. Assume that g, h, i, and j are

already stored in r1, r2, r3, and r4. Store f in r5

f = (g+h) - (i+j)

Solution:

add r6, r1, r2add r7, r3, r4sub r5, r6, r7

What about more data??

• With only a limited number of registers, not all data can be stored in registers at the same time. – Registers only store data that is currently being

operated on• Variables are stored in memory and then

loaded into registers when needed using data transfer instructions– Load word (lw) and store word (sw)

Load and store word• Load word format

– lw destination register, memory location• Store word format

– sw source register, memory location• Memory location format

– Offset(base address)• Base address = starting location of data in memory• Offset = how far away is location to access from base

address– Values are added together

LW ExampleExample: Assume that A is an array of 100 words. Assume the base address is stored in r3, g is in r1

and h is in r2

g = h + A[8]

Solution:

lw r4, 8(r3)add r1, r2, r4

Offset

Base Address

This is simplified,

more details later…

Data in Memory

• All variables/data are stored in memory– You will need to do this in your assembler– Your ISS will need a data structure to hold

main memory• Array is fine

Addressing Data

• Architecture usually addresses data in bytes (byte addressable)– 32-bit architecture = 4 bytes = 1 word

• lw/sw load/store 1 word or 4 bytes– Thus, data/inst addresses are multiples of 4

• Data is word aligned to be more efficient

Data in Memory...

10010

1011

12840

Address Data

...

LW/SW ExampleExample: Assume that A is an array of 100 words. Assume the base address is stored in r3 and h is stored in r2. You may directly calculate the offset.

Remember, each data piece is 4 bytes when calculating the offset

A[12] = h+A[8]Solution:

lw r1, 32(r3)add r4, r2, r1sw r4, 48(r3)

LW/SW ExampleExample: Assume that A is an array of 100 words. Assume the base address is stored in r3 and g, h,

and i are in r1, r2, and r4 respectively. Calculate the offset using assembly instructions but don’t use multiplication yet (mult instruction is different)

g = h + A[i]

Solution:add r5, r4, r4 # Temp reg r5=2*iadd r5, r5, r5 # Temp reg r5=4*iadd r5, r5, r3 # t1 = addr of A[i] (4*i+r3)lw r6, 0(r5) # Temp reg r0=a[i]add r1, r6, r2 # g=h+a[i]

Translating MIPS Assm Language to Machine Language

• Translate human readable assembly code to machine readable code (binary)– I will show examples in decimal for

readability– This is what you assembler will do but it

will output in binary.

MIPS -> Machine LanguageExample: Show the real MIPS language version of the following instruction in both decimal and binary

add r0, r1, r2

Solution: decimal

Each segment is referred to as a field. Details to come….

binary

0 0 1 2 0 32

000000 00000 00001 00010 00000 1000006 bits 5 bits 5 bits 5 bits 5 bits 6 bits

MIPS Fields• MIPS fields are giving names to make

them easier to discuss

• op: Basic operation of the instruction, typically called the opcode• rs: The first register source operand• rt: The second register source operand• rd: The register destination operand, it gets the result of the operation• shamt: Shift amount (0 if not shift instruction)• funct: Function. This field selects the specific variant of the operation in

the op field, and is sometimes called the function code

op rs rt rd shamt funct6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

MIPS Fields

• Problem occurs with an instruction needs a longer field than that showed on the previous slide– I.e. LW must specify 2 registers and a constant.

Limited to 5-bit constant if use previous format.• Solution: There are different formats for

different types of instructions– Previous slide is R-type (R-format):

• R=register

MIPS Fields

• I-type (I-format)– I=immediate– Now LW can specify an address up to 16-

bits• Opcode determines the format

op rs rt address6 bits 5 bits 5 bits 16 bits

MIPS Instruction Encoding

MIPS Asm -> Machine Language

Example: Assume r1 is the base of A and r2 corresponds to h, the C statement:

is compiled to:

What is the MIPS machine code for these three instructions? (Use figure 3.5)

A[300] = h + A[300]

lw r0, 1200(r1)add r0, r2, r0sw r0, 1200(r1)

MIPS Asm -> Machine Language

decimal

binary

op rs rt rdAddress/shamt funct

Solution:

lw r0, 1200(r1)add r0, r2, r0sw r0, 1200(r1)

0 0 2 0 0 32

35 0 1 1200

43 0 1 1200

000000 00000 00010 00000 00000 32

100011 00000 00001 0000 0100 1011 0000

101011 00000 00001 0000 0100 1011 0000

Decision Instructions

• Branch/jump instructions– Conditional branches

• beq register1, register2, Label• bne register1, register2, Label

– Unconditional branches• j Label

Decision InstructionsExample: Assume f->r0, g->r1, h->r2, i->r3, j->r4

if ( i==j ) goto L1f = g+h

L1: f = f-i

Solution:beq r3, r4, L1add r0, r1, r2

L1: sub r0, r0, r3Labels will need to

be translated to instruction address in your assembler

Decision InstructionsExample: Assume f->r0, g->r1, h->r2, i->r3, j->r4

if ( i==j )f = g+h

L1: elsef = g-h

L2:

Solution:bne r3, r4, L1add r0, r1, r2j L2

L1: sub r0, r1, r2L2:

Decision InstructionsExample: A is 100 elements with the base address

in r5. g->r1, h->r2, i->r3, j->r4

Loop: g = g+A[i]i = i+jif ( i!=h ) goto Loop

Solution:Loop: add r6, r3, r3

add r6, r6, r6add r6, r6, r5lw r7, 0(r6)add r1, r1, r7add r3, r3, r4bne r3, r2, Loop

While Loop

• Goto statements are bad, just used them as an example.

• You will want to use while loops– Or for loops but I am just showing you

while loops

While LoopExample: Base address of save is in r6. i->r3, j->r4,

k->r5

while ( save[i] == k )i = i+j

Solution:Loop: add r1, r3, r4

add r1, r1, r1add r1, r1, r6lw r0, 0(r1)bne r0, r5, Exitadd r3, r3, r4j Loop

Exit:

Other Styles of MIPS Addressing

• Constant or immediate operands– Programs often use constant values

– I.e. incrementing to the next data element while scanning an array

• addi instruction - adds an immediate value to a register

Immediate OperandsExample: What is the machine code for the

following? (Remember the I-format instruction)

addi r4, r4, 4

Solution:decimal

binary

op rs rt Immediate

8 4 4 4

001000 00100 00100 0000 0000 0000 0100

Addressing in Branches and Jumps

• Last instruction format - J-type (J-format)

• Branches do not use J-type.– Must specify 2 registers to compare– Use I-type

opcode Target address