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6.004 Computation StructuresSpring 2009
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L05 Sequenial Logic 16.004 Spring 2009 2/19/09

Sequenial Logic:adding a litle state

Lab #1 is due onigh(checkoff meeing by nex Thursday).

modified 2/17/09 10:26

QUIZ #1 Tomorrow!(covers hru L4/R5)


6.004: Progress so far

01101

PHYSICS: Coninuousvariables, Memory, Noise,f(RC) = 1 - e-/RC

COMBINATIONAL: Discree,memoryless, noise-free,lookup able funcions

2.71354 vols

C B A Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

Wha oherbuildingblocks do weneed in order

o compue?


Somehing We Can Build (Ye)

Wha if you were given he following design specificaion:

When he buton is pushed:1) Turn on he ligh if

i is off

2) Turn off he ligh ifi is on

The ligh should changesae wihin a second

of he buton press

buton ligh

Wha makes his circui so differenfrom hose weve discussed before?

1. Sae i.e. he circui has memory2. The oupu was changed by a inpu

even (pushing a buton) raherhan an inpu value


Digial SaeOne model of what wed like to build

Plan: Build a Sequenial Circui wih sored digial STATE

Memory sores CURRENT sae, produced a oupuCombinaional Logic compues

NEXT sae (from inpu, curren sae)OUTPUT bi (from inpu, curren sae)

Sae changes on LOAD conrol inpu

CombinaionalLogic

CurrenSae

NewSae

Inpu Oupu

MemoryDevice

LOAD

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Needed: Storage

Combinaional logic is stateless:

valid oupus always reflec curren inpus.

To build devices wih sae, we need componens which storeinformaion (e.g., sae) for subsequen access.

ROMs(and oher combinaional logic) sore informaion wired in o heirruh able

Read/Writememory elemens are required o build devices capable ofchanging heir conens.

How can we sore and subsequenly access -- a bi? Mechanics: holes in cards/apes Opics: Film, CDs, DVDs, Magneic maerials Delay lines; moonbounce Sored charge


Sorage: Using Capaciors

Weve chosen o encode informaion using volages and we know

from 6.002 ha we can sore a volage as charge on a capacior:

Pros:compac low cos/bi

(on BIG memories)Cons:

complex inerfacesable? (noise, )

i leaks! refreshTo wrie:Drive bi line, urn on access fe,force sorage cap o new volage

To read:precharge bi line, urn on access fe,deec (small) change in bi line volage

N-channel fe servesas access swich VREF

word line

Biline

Suppose we refreshCONTINUOUSLY?


Sorage: Using Feedback

IDEA: use posiive feedback o mainain sorage indefiniely.Our logic gaes are buil o resore marginal signal levels, sonoise shouldn be a problem!

VIN VOUT

Resul: a bisablesorage elemen

Feedback consrain:VIN = VOUT

VTC forinverer pair

VIN

VOUT Three soluions:wo end-poins are sablemiddle poin is unsable

No affecedby noise

Well ge back o his!


Y

S

B

Setable Sorage Elemen

Is easy o build a setable sorage elemen (called a lach)using a lenientMUX:

0

1

G

0011

D

----01

QIN

01----

QOUT

0101

sae signalappears as boh

inpu and oupu

Q follows D

Q sable

A

D

G

Q

Heres a feedback pah,so is no longer a

combinaional circui.

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New Device: D Lach

G

D Q

D

TPD

V1 V2

V2V1

TPD

G

Q

G=1:Q follows D

G=0:Q holds

G=1: Q Follows D, independently of Q

G=0: Q Holds sable Q, independently of D

Y

0

1

A

D

G

QQ

BUT A change in D or Gcontaminates Q, hence Q

how can this possiblywork?


A Plea for Lenience

Y0

1

A

D

G

Q

D

TPD

V1 V2

V2V1

TPD

G

Q

Assume LENIENT Mux, propagaiondelay of TPD

Then oupu valid when

Q

Does lenience guaranteeaworking lach?

Wha if D and Gchange a abou he

same ime Q=D sable for TPD ,

independently of G; or

G=1, D sable for TPD,independently of Q; or

G=0, Q sable for TPD ,independently of D

G D Q Q

1 0 X 0

1 1 X 1

X 0 0 0

X 1 1 1

0 X 0 0

0 X 1 1

Q(D,G)

Q(D,Q)

Q(G,Q)


Dynamic Disciplinefor our lach:

D Sable

wih a litle discipline

Y

0

1

A

D

G

Q

To reliably latch V2:

Q

Apply V2 o D, holding G=1 Afer anoher TPD, Q & D boh valid

for TPD; will hold Q=V2 independently ofG

Se G=0, while Q & D hold Q=D

Afer TPD, V2 appears a Q=Q

Afer anoher TPD, G=0 and Qare sufficien o hold Q=V2independently of D

D

G

Q

V2

V2

TPD TPD

TSETUP THOLD

TPD

TSETUP = 2TPD: inerval prior toG

ransiion for which D mus besable & valid

THOLD = TPD: inerval followingGransiion for which D mus besable & valid


Les ry i ou!

Combinaional

LogicG

D QCurren

Sae

NewSae

Inpu Oupu

Plan: Build a Sequenial Circui wih one bi of STATE

Single lach holds CURRENT saeCombinaional Logic compues

NEXT sae (from inpu, curren sae)OUTPUT bi (from inpu, curren sae)

Sae changes when G = 1 (briefly!)

Wha happenswhen G=1?

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Combinaional Cycles

CombinaionalLogic

G

D QCurren

Sae

New

Sae

Inpu Oupu

When G=1, lach is Transparent

provides a combinaional pah from D o Q.Can work wihou ricky iming consrans on G=1 pulse:

Mus fi wihin conaminaion delay of logicMus accommodae lach seup, hold imes

Want to signal an INSTANT, not an INTERVAL

Looks like a supidApproach o me

1


Flakey Conrol Sysems

Heres a sraegyfor saving 3 buckson he SumnerTunnel!


Escapemen Sraegy

The Soluion:Add wo gaesand only open

one a a ime.


Edge-riggered Flip Flop

G

D Q

G

D Q D QD

CLK

Q D

CLK

Qmaser slave

Observaions:

only one lach ransparen a any ime:maser closed when slave is openslave closed when maser is open no combinaional pah hrough flip flop

Q only changes shorly afer 01

ransiion of CLK, so flip flop appearso be riggered by rising edge of CLK

The gae of hislach is open when

he clock is low

The gae of his

lach is open whenhe clock is high

Wha doesha one do?

0101S

D

G

Q

(he feedback pah in one of he maser or slave laches is always acive)

Transiions markinstants, no inervals

Figure by MIT OpenCourseWare.

Figure by MIT OpenCourseWare.

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Flip Flop Waveforms

G

D Q

G

D Q D QD

CLK

Q D

CLK

Qmaser slave

D

CLK

Q

maser closedslave open

slave closedmaser open


Um, abou ha hold ime

G

D Q

G

D QD Q

maser slave

CLK

Consider HOLD TIME requiremen for slave:

Negaive (1 0) clock ransiion slave freezes daa:

SHOULD be no oupu glich, since maser held consan daa; BUT

maser oupu conaminaed by change in G inpu!

HOLD TIME of slave no me, UNLESS we assume sufficienconaminaion delay in he pah o is D inpu!

Accumulaed CD hru inverer, G Q pah of maser mus coverslave HOLD for his design o work!

The masers conaminaiondelay mus mee he hold

ime of he slave


Flip Flop Timing - I

CLK

D

QD QD

CLK

Q

CD

CD: minimum conaminaion delay, CLK Q

>SETUP

SETUP: seup imeguarantee that D has propagated through feedback path before master closes

>HOLD

HOLD: hold imeguarantee master is closed and data is stable before allowing D to change


Single-clock Synchronous Circuis

Single-clock Synchronous Discipline

No combinaional cycles

Only care abou value of regiser daainpus jus before rising edge of clock

Period greaer han everycombinaional delay

Change saved sae afer noise-inducing logic ransiions havesopped!

Well use Flip Flops and Registers groups of FFs sharing a clockinpu in a highly consrained way o build digial sysems:

Single clock signal shared amongall clocked devices

Does hasymbol

regiser?

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Flip Flop Timing - II

CLK

1

1 = CD,reg1 + CD,1 > HOLD,reg2

1D Q D Q

CLK

reg1 reg2Quesions for regiser-based designs:

how much ime for useful work(i.e. for combinaional logicdelay)?

does i help o guaranee aminimum CD? How boudesigning regisers so ha

CD,reg > HOLD,reg?

wha happens if CLK signal

doesn arrive a he woregisers a exacly hesame ime (a phenomenonknown as clock skew)?

2

2 = PD,reg1 + PD,1 < CLK - SETUP,reg2

QR1

CD,reg1

CD, 1 PD, 1

PD,reg1

QR1


Model: Discree Time

Acive Clock Edges puncuae ime ---

Discree Clock periods Discree Sae Variables Discree specificaions (simple rules eg ables relaing

oupus o inpus, sae variables)

ABSTRACTION: Finie Sae Machines (nex lecure!)

CombinaionalLogic

CurrenSae

New

Sae

Inpu Oupu

MemoryDevice

Clock


Sequenial Circui Timing

Quesions:

Consrains on TCD for he logic? Minimum clock period? Seup, Hold imes for Inpus?

Combinaional

Logic

CurrenSae

NewSae

Inpu Oupu

Clock CD,L = ?PD,L = 5ns

CD,R = 1nsPD,R = 3nsS,R = 2nsH,R = 2ns

> 1 ns

> 10 ns (TPD,R+TPD,L+ TS,R)

TS = TPD,L +TS,RT

H= T

H,R-T

CD,L

This is a simple Finite State Machine more nex lecure!!


SummarySequenial Circuis (wih memory):

Basic memory elemens: Feedback, deailed analysis =>

basic level-sensiive devices(eg, lach)

2 Laches => Flop Dynamic Discipline:

consrains on inpu iming

Synchronous 1-clock logic: Simple rules for sequenial

circuis

Yields clocked circui wih TS, THconsrains on inpu iming

Finie Sae Machines

Nex Lecure Topic!

>s >h

Clk

Q

D

>cd

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MIT6_004s09_lec05.pdf