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6.004 Computation StructuresSpring 2009
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L07 - Synchronization 16.004 Spring 2009 2/26/09

Synchronizaion, Measabiliyand Arbiraion

Due onigh: Lab #2 Lab #1 checkoff meeing

"If you can' be jus,be arbirary"

- Wm Burroughs, Naked Lunch- US Supreme Court 12/00

Did you voe for Bush or Gore?Didn have enough ime o decide.

Well, which hole did you punch?

Boh, bu no very hard...

modified 2/23/09 09:30 L07 - Synchronization 26.004 Spring 2009 2/26/09

The Imporance of being Discree

Digial Values:Problem: Disinguishing volages

represening 1 from 0

Soluion: Forbidden Zone: avoidusing similar volages for 1and 0

Digial Time:Problem: Which ransiion

happened firs? quesionsSoluion: Dynamic Discipline: avoid

asking such quesions inclose races

VOL

VIL

VIH

VOH

VOUT

VINVOL VIL VIH VOH

tS tH

Clk

Q

D

tCD

tPD

We avoid possible errors by disciplines ha avoid asking he oughquesions using a forbidden zonein boh volage and ime dimensions:


If we follow hese simple rules

Can we guaranee ha our sysem will always work?

Wih careful design we can make sure ha he dynamic

discipline is obeyed everywhere*...

D Q D QOutIn

Combinational

logic

D QOut

Combinational

logic

D QIn

Clk

Combinational

logic

D QCombinational

logic

D QCombinational

logic

D QOut

Combinational

logic

* well, almoseverywhere...


Which edgeCame FIRST?

The world doesn run on our clock!

Wha if each buton inpu isan asynchronous 0/1level?

LockB1 UB0

0

10

1

To build a sysem wih asynchronous inpus, we have o break he rules:we canno guaranee ha seup and hold ime requiremens are me a heinpus!

So, les use a synchronizer a each inpu:

0

1 (Unsynchronized)

U()

(Synchronized)

S()

Clock

Synchronizer

Valid excep for brief periodsfollowing acive clock edges

Bu whaAbou heDynamic

Discipline?

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The Asynchronous Arbier:a classic problem

ArbiterB

C

SB:

C:

at tB

at tC

B:

C:

S:tDtD

>tE >tE

tD

Arbier specificaions:finie D (decision ime)finie E (allowable error)value of S a ime C+D:

1 if B < C E0 if B > C + E0, 1 oherwise

CASE 1 CASE 2 CASE 3

UNSOLVABLE

For NO finie valueof E and D is hisspec realizable,even wih reliablecomponens!


Violaing he Forbidden Zone

The image cannotbe displayed.Yourcomputermaynot have enoughmemorytoopenthe image,or the image mayhave beencorrupted.Restartyour computer,and thenopenthe file again.Ifthe red xstillappears,youmay have todelete the image and theninsertit again.

tB-tC

Arbier

Oupu

1

o

(tB=tC)B

Earlier

C

Earlier

ArbiterB

C

SB:

C:

at tB

at tC

Issue: Mapping he coninuousvariable (B C)ono he discreevariable S in bounded ime.

Wih no forbidden zone, all inpus have o bemapped o a valid oupu. As he inpuapproaches disconinuiies in he mapping, iakes longer o deermine he answer. Givena paricular ime bound, you can find an inpu

ha won be mapped o a valid oupuwihin he alloted ime.


Unsolvable?ha can be rue...

Les jus use a D Flip Flop:

D QB:

C:

at tB

at tC

DECISION TIMEis TPD of flop.

ALLOWABLE ERRORis max(SETUP, HOLD)

Our logic:

TPD

afer TC

, well have

Q=0 iff B + SETUP < C

Q=1 iff C + HOLD < B

Q=0 or 1 oherwise.

Were lured by he digialabsracion ino assumingha Q mus be eiher 1 or 0.Bu les look a he inpu lachin he flip flop when B and Cchange a abou he sameime...

G

D Q

G

D QB

C

maser slave


The Myserious Measable Sae

Vin

Vout

VTC of

closed latch

VTC of feedback

path (Vin=Vout)

Latched ina 0 state

Latched ina 1 state

Latched inan undefined

state

Y

0

1

QVout

Vin

Recall ha he lach oupu is hesoluion o wo simulaneousconsrains:

1. The VTC of pah hruMUX; and

2. Vin = Vou

In addiion o our expeced sable soluions, we find an unsableequilibrium in he forbidden zone called he Measable Sae

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Measable Sae: Properies

1. I corresponds o an invalidlogic level

he swiching hreshold of he device.2. Is an unsableequilibrium; a small

perurbaion will cause i oaccelerae oward a sable 0 or 1.

3. I will setle o a valid 0 or 1...evenually.

4. BUT depending on how close i is ohe Vin=Vou fixed poin of he device

i may ake arbirarily long o setleou.

5. EVERY bisable sysem exhibis aleas one measable sae!

EVERY bisable sysem?Yep, every las one.

Coin flip??

Could land on edge.Horse race??Phoo finish.

Presidenial Elecion??

(Wheres his wibeen hiding???)


Observed Behavior:ypical measable sympoms

Following a clock edge on an asynchronous inpu:

We may see exponenially-disribued measable inervals:

Or periods of high-frequency oscillaion (if he feedback pah is long):

CLK

D

Q

Q


Mechanical Measabiliy

If we launch a ball up a hill weexpec one of 3 possibleoucomes:

a) Goes overb) Rolls backc) Salls a he apex

Tha las oucome is nosable.- a gus of wind- Brownian moion

- i doesn ake much

State A

State B

Metastable State

State A

State B


How do balls relae o digial logic?

Our hill is analogous o he derivaiveof he VTC (Volage TransferCurve) a he measablepoin, he derivaive (slope) isZERO.

Noice ha he higher he gain hruhe ransiion region, he seeperhe peak of he hill... making iharder o ge ino a measablesae

We can decrease he probabiliy ofgeting ino he measablesae, bu assuming coninuous

models of physics we caneliminae he slope=0 poin!

Vin

Vout

in

out

V

V

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The Measable Sae:Why is i an ineviable risk of synchronizaion?

Our acive devices always have a fixed-poin volage, VM, such haVIN=VM implies VOUT = VM

Violaion of dynamic discipline pus our feedback loop a some volageV0 near VM

The rae a which V progresses oward a sable 0 or 1 value isproporional o (V - VM)

The ime o setle o a sable value depends on (V0 - VM); isheoreically infinie for V0 = VM

Since heres no lower bound on (V0 - VM), heres no upper bound onhe setling ime. Noise, uncerainy complicae analysis (bu don help).


Skech of analysis I.0

1 (Synchronized)

S()

Clock

SynchronizerAssume asynchronous 0->1a TA, clock period CP:

Whas he FF oupu volage,V0, immediaely afer TA?

A

C

< S+H

CP

VM

1. Whas he probabiliy ha hevolage, V0, immediaely aferTA is wihin of VM?

)(

2)(][ 0

LH

HS

M

VVCP

ttVVP

+

V0

tA-tC

Poenial rouble comes when V0 is near he measable poin, VM


Skech of analysis II.

We can model ourcombinaionalcycle as anamplifier wih gainA and sauraion

a VH, VL

A

0

1Vout

Vin

0

R

C

VH

VL

Vou

Vin

Slope = A

2. For Vou near VM, Vou() is anexponenial whose ime consanreflecs RC/A:

3. Given inerval T, we can compue aminimum value of = |V0-VM| ha willguaranee validiy afer T:

Vou()- VM e(A-1)/RC

e /

(T) (VH VM) e -T/

4. Probabiliy of measabiliy afer T iscompued by probabiliy of a V0yielding (T)

PM(T) P[|V0-VM| < (T)]

K e -T/


Failure Probabiliies vs DelayMaking conservaive assumpions abou he disribuion of V0 and sysemime consans, and assuming a 100 MHz clock frequency, we ge resuls likehe following:

Average imeDelay P(Measable) beween failures

31 ns 3x10-16 1 year33.2 ns 3x10-17 10 years

100 ns 10-45 1030 years!

[For comparision:Age of oldes hominid fossil: 5x106 yearsAge of earh: 5x109 years]

Lesson: Allowing a bi of setling ime is an

easy way o avoid measable saes inpracice!

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Modern Reconciliaion:delay buys reliabiliy

D Q D QOut

Combinational

logic

D QIn

Clk

A metastable state herewill probably resolve itself

to a valid level before itgets into my circuit.

And one here will almost certainlyget resolved.

D Q D QOut

Combinational

logic

D QD QIn

Clk

Synchronizers, exra flipflops beween heasynchronous inpu andyour logic, are he besinsurance againsmeasable saes.

The higher he clock rae,he more synchronizersshould be considered.

SETTLING TIMECures

Measabiliy!


Things we CANT build

1. Bounded-ime Asynchronous Arbier:

S valid afer pd following (eiher) edgeArbier

B

C

S S=0 iff B edge firs, 1 iff C edge firs,1 or 0 if nearly coinciden

D QAsynchronousInpu

Oupu = D a acive clock edge, eiher 1 or 0iff D invalid near clock edgeQ valid afer pd following acive clock edge

2. Bounded-ime Synchronizer:

> 3.14159 ?ConinuousVariable

3. Bounded-ime Analog Comparaor:

0 or 1,finie pd


Some hings we CAN build1. Unbounded-ime Asynchronous Arbier:

S valid when Done=1; unbounded ime.

ArbierB

C

SS=0 iff B edge firs, 1 iff C edge firs,1 or 0 if nearly coincidenDone

2. Unbounded-ime Analog Comparaor:

> 3.14159 ?ConinuousVariable

0 or 1

Done

After arbitrary interval,decides whether input attime of last active clock

edge was above/belowthreshold.

3. Bounded-ime combinaional logic:

Produce an output transition within a fixedpropagation delay of first (or second)

transition on the input.


Ineresing Special Case Hacks

For systems with unsynchronized clocksof same nominal frequency. Data goes totwo flops clocked a half period apart; one

output is bound to be clean. An observercircuit monitors the slowly-varying phaserelationship between the clocks, andselects the clean output via a lenient MUX.

CLK2

Daa1

delay

Daa2

CLK1

CLK2

Mesochronous communicaion:

Consrains on clock iming periodiciy,ec can ofen be used o hide imeoverhead associaed wih synchronizaion.

Exploits fact that, given 2 periodicclocks, close calls are predicable.Predicts, and solves in advance,

arbitration problems (thus eliminating

cost of delay)

Predicive periodic synchronizaion:

CLK1

Daa1

CLK2

Daa2

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Every-day Measabiliy - I

BitBucketCafe

The imagecannotbedisplayed.Yourcomputermaynothaveenoughmemorytoopenthe image,

Ben Bididdle ries he famous

6.004 defense:

Ben leaves he Bi Bucke Cafand approaches fork in heroad. He his he barrier in hemiddle of he fork, laerexplaining I can be expecedo decide which fork o ake inbounded ime!.

Is he acciden Bens faul?

Yes; he should have sopped unil his decisionwas made.

Judge R. B. Traor, MIT 86


Every-day Measabiliy - IIGIVEN:

Normal raffic ligh: GREEN, YELLOW, RED sequence 55 MPH Speed Limi Sufficienly long YELLOW, GREEN periods Analog POSITION inpu digial RED, YELLOW, GREEN inpus digial GO oupu

Can one reliably obey....

PLAUSIBLE STRATEGIES:

A. Move a 55. A calculaed disance D from ligh, sample color (using anunbounded-ime synchronizer). GO ONLY WHEN sable GREEN.

B. Sop 1 foo before inersecion. On posiive GREEN ransiion, gun i.

LAW #1: DONT CROSS LINE while ligh is RED.GO = GREEN

LAW #2: DONT BE IN INTERSECTION while ligh is RED.


Summary

As a sysem designer

Avoid he problem alogeher, where possible Use single clock, obey dynamic discipline Avoid sae. Combinaional logic has no measable

saes!

Delay afer sampling asynchronous inpus: a

fundamenal cos of synchronizaion

The mos difficul decisionsare hose ha mater he leas.

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