Mixed signal SoC: Current status and future prospectBoard Level (Disc.+Bip) 20W $ 8,000 Conventional product World 1st Monolithic Bipolar (3um) 2W $ 800 World lowest power CMOS (1.2um)

Kitakyushu A. Matsuzawa 1

アナ・デジ混載SoC：

開発の現状と将来動向

Mixed signal SoC:Current status and future prospect

松澤昭Akira Matsuzawa

東京工業大学（元松下電器半導体社）

Tokyo Institute of Technology （Matsushita Electric Industrial Co., Ltd , before this April)


Contents

• Introduction• Current electronics and mixed signal technology • CMOS as an analog device• Development strategy and design system for

mixed signal SoC• Issues of mixed signal SoC and solutions• Summary


Current electronics andmixed signal technology


Home Home ServerServer

NetworkNetwork

ITSITS

CS/BSCS/BS

WW--CDMACDMA

HII StationHII Station

DVDDVDDVCDVC

Digital TVDigital TV

Image of current electronicsDigital consumer electronics and networking drive current electronics.

ADSL, FTTH

DAB

Digital TV

Home network

Ethenet

IEEE 1394, USB, Blue tooth, Wireless LAN


Mixed signal technology :Digital networkingｓ

Side-streamDescramber

&Trellis, Viterbi decoder

DACDACDACDAC

250Mbaud (PAM-5)

ADCADCADCADC

3-NEXTCanceller

Echo Canceller

DFE

Slicer

Clock Recovery

FFE

TX1TX2

TX3TX4

Pulse Shaping

Side-streamScramber

&Trellis,Viterbi

Symbol EncoderLine

I/F 6b, 125MHz ADC, DAC

Analog circuit

The mixed signal technology enables high speed digital networking.

Digital circuit

Error correction

Equalization Encryption

Noise cancellation

Digital

Data and clock recovery

Data conversion

Analog


Mixed signal tech. ; Digital read channel

Variable Gain Amp.Variable

Gain Amp.Analog

FilterAnalog

FilterA to D

ConverterA to D

ConverterDigital

FIR FilterDigital

FIR FilterViterbiError

Correction

ViterbiError

Correction

ClockRecoveryClock

RecoveryVoltage

ControlledOscillator

Voltage ControlledOscillator

DataOut

Data In(Erroneous)

Data Out(No error)

Analog circuit

Digital circuit

Digital storage also needs high speed mixed signal technologies.

Pickup signal


Mixed signal SoC for DVD RAM system

0.18um- eDRAM

24M Tr16Mb DRAM

500MHzMixed Signal

Goto, et al., ISSCC 2001

This enables high readability for weak signal from DVD RAM pickup.

World fastest and highly integrated mixed signal CMOS SoC


Recent developed mixed signal CMOS LSIs

5G RF LAN 12b 50MHz ADC 2ch12b 50MHz DAC 2ch

AFE for ADLS 12b 20MHz ADC+DAC

Digital network1394b (1GHz)

AFE for Digital Camera12b 20MHz ADC+AGC

2GHz RF CMOS

AFE (Analog Front End)


Application area in mixed signal CMOS tech.

NetworkCommunication

NetworkCommunication

RecordingRecording

OutputOutput

InputInput

・Cellular phone: PDC, W-CDMA・RR-Net: Bluetooth, IEEE802.11・Broad cast: STB, DTV, DAB

・Optical:FTTH, OC-xx・Metal: ADSL, VDSL, Power line modem

・Serial: IEEE1394, USB, Ethernet・Parallel: DVI, LVDS

・DVD, VDC, HDD

Wireless

Wired

・LCD, PDP, EL, Audio drive

・Camera, Others

Power supplyPower supply ・ Switching supply, Every LSIs (On-chip)

Almost all the products need mixed signal CMOS LSI tech.


Digital technology in real world

• High robustness• Programmability• Time shift (memory)• Error correction• High Scalability

Pure digital

Media(Cable, Disc, Air, etc) Real world

Damaged digital

Recovered digital

Advantages of Digital Tech.

Mixed signal technology(Analog+Digital)

Mixed signal technology(Analog+Digital) Reconstruction

But, digital can address this issue by own advantages,but needs the help of an analog tech.

NoiseDistortionInterferenceLimited bandwidth

Not only digital, but also analog;ADC, DAC, Filter, and PLL are needed

Digital signals suffer heavy damage in the real world.


Progress in A/D converter; video-rate 10b ADC

1980 1982 1993 Now

Board Level (Disc.+Bip)20W

$ 8,000

Conventional product World 1st Monolithic

Bipolar (3um)2W

$ 800

World lowest power

CMOS (1.2um)30mW$ 2.00

CMOS (0.15um)10mW$0.04

SoC Core

Our developed.Our developed. Our developed.

ADC is a key for the mixed signal technology.We have reduced the cost and power of ADC drastically;1/ 2,000 for Power and 1/200,000 for the cost!

CMOS technology attained it.

Analog Devices Inc.

dulling past 20 years


Progress in high-speed ADC

0.1

10

Pd/2

N[m

W]

Reported Pd of CMOS ADCs

Conversion rate [x100Msps]

1

1mW/Gsps

10mW/Gsps

This Work

101

1 order down

6b, 1GHz ADC2W,1.5um Bipolar

6b, 800MHz ADC400mW, 2mm2

0.25umCMOS

ISSCC 2002

ISSCC 2000

ISSCC 1991

World fastest CMOS ADC

World lowest Pd HS ADC7b, 400MHz ADC50mW, 0.3mm2

0.18umCMOS

World fastest 6b ADC

High speed ADC has reduced its power and area down to be embedded.


Difficulty of analog in LSI technology

RuleDesign　1

tox

L

W

XjLeff

0.7x

Perf

orm

ance

(Log

)

Scaling

(Log)

Integration2

1L

∝

Speed 5.1

1L

∝

Dynamic range =

5.1L∝Noise + mismatch

Signal swing

Scaling Rule

New circuit technology or architecture are needed

Dynamic range has been reduced with technology scaling.


並列型ADCの課題

～

入力アナログ信号

基準電圧

C1

C2

C3

C4

C5

C6

C7

Vr1

Vr2

Vr4

Vr3

Vr5

Vr6

Vr7

基準抵抗列比較器列論理回路列

クロック

エンコーダ

変換デジタル出力　

量子化電圧

オフセット電圧

1 0 0

1 0

1

オフセット電圧ばらつき： σ(m V)

超高速バイポーラ

0 0 .5 1 . 0 1 . 5

高精度バイポーラ

誤差 0 .5 LSB以下

誤差 1 .0 LSB以下

MOSデバイス

オフセット電圧ばらつき

σoff

実際の量子化電圧

Va

理想量子化電圧

Vq

１コード当たりの

微分非直線性誤差

=Va-Vq

Vq

2mV : 10bit歩

留(%

)

並列型は2N個の比較器が必要比較器間の「しきい値電圧」はわずか2mV !!

0.2mVのオフセットばらつきでも歩留りは1%程度超高速バイポーラやMOSは論外!!消費電力の急増

通常の超LSI技術では限界がある。

新規変換方式の開発


補間型A/D変換方式

D 1

D 2

D 0

D 8

D 6

D 7

下位比較器列

～

C 1

C 2

C 3

C 4

C 5

C 6

C 7

上位基準抵抗列上位比較器列

差動増幅器

入力信号

補間抵抗列

Vn

CVn

CVn-1

Vn-1

V i1

V i3

CV i3

CV i1

Vr , n-1

Vr , n

Vr, n-1 Vr, n

Vn-1

CVn-1

CVn

Vn

Vi1

Vi2

Vi3

CVi1

CVi2

CVi3

D1

D2

D3

D4

D5

D6

D7

D0 D8

入力電圧

差動増幅器の出力電圧

・補間電圧

補間電圧

補間電圧

増幅された信号

1対の増幅器を用いて、その差動出力端間を抵抗で分圧した信号同士を比較する。


補間型A/D変換方式の効果

G=1

G=8

ΔVoff2

入力換算オフセット電圧

ΔVbe ΔVbe8

下位比較器の

入力オフセット電圧

0

4

8

12

1616

12

8

4

0

+ΔV

-ΔV

ΔV：電圧誤差

0

23

1

0

1

2

3

1

0

2

3

0123

理想直線

0

4

8

12

16

入力電圧

(a)A/D変換動作 (b)A/D変換特性

大きなオフセット電圧があっても滑らかな特性になる

微分非直線性の比較器の等価オフセット電圧は増幅器の利得, G分の１、増幅器のオフセット電圧の影響は補間数, m分の１になる。また、直並列型のような大き

なエラーを生じることは原理上ありえない。22

2

⎟⎟⎠

⎞⎜⎜⎝

⎛+⎟

⎟⎠

⎞⎜⎜⎝

⎛=

Gmcompdiff

off

σσσこれによりトランジスタの要求精度が緩和できた。

高精度化が可能となった。


超ローパワーCMOS 10b ADC

0.1

0 .5

発表年

1

0 .0 5

10

5

ボード

著者らによる開発

0.01

他グループによる開発

'80 '82 '84 '86 '88 '90 '92 '94

（当時は 500mWが普通）

ビデオカメラ用には10bのADCの開発が期待されていた。

しかも超ローパワーで動作することが他を引き離す鍵であった。

新規なA/D変換方式である、容量補間方式と容量ネットワークによる誤差分散により10b, 20MHzで30mWという画期的な超ローパワーを実現した。

Kusumoto, et al., ISSCC ‘93

この値は現在でもトップクラスである。

@0.8umCMOS ADC

消費電力1000分の１！


容量補間技術

Vi n

ラッチVr f

V r f '

ラッチ

ラッチ

ラッチ

ラッチ

ラッチVr c

上位比較器

下位比較器前段増幅器第１補間回路第２補間回路

除去されたインバータ

V i n

V r

V r + 4 V q

S 1 a

S 1 b

C i a

C i b

S 2I NV 1 a

I NV 1 b

I NV 2

Cc

Cc

q 1 a

q 1 b

V o 1 a

V o 1 b

V b 2

Cp q p

I NV 1 a

I NV 1 b

I NV 2

S 1 a

S 1 b

S 2

Cc

Cc

q '1 a

q '1 b Cp

回路状態 1 , I NV 1 a , I NV 1 b :増幅状態 , I NV 2 :バイアス状態

回路状態 2 , I NV 1 a , I NV 1 b :バイアス状態 , I NV 2 :増幅状態

容量補間により、精度を4倍向上消費電力を1/4に

補間・オフセットキャンセル・増幅パイプライン処理を同時に実現

スイッチ・容量・インバータの単純な構成により、高速・高精度低電力ADCを実現


補間機能を持つダイナミックコンパレータ

VSS

VDD

In1+ In2+m2

m7

m9 m10

m3 m4m1

m5 m6

m8

m11 m12

In1- In2-

Out+Out-

CLK

Vrn-1 Vrn

CVn-1

Vn-1CVn

Outp

ut o

fPr

e-am

plifi

ers

Vn

N-1 N

Vrn-1 VrnVin

Vn-1CVn-1 VnCVn

Reference Resistor

mnVV)nm( n1n +− −

mnCVCV)nm( n1n +− −

1 2 3 4

Pre-Amplifiers

ComparatorLatches

with Interpolation

Circuits

0

Gate width ratioW1:W2=(m-n)/m : n/m

W1 W2 W1 W2

静止電力を消費しないダイナミックF/Fと重み付けされたゲート幅による補間回路を結合

等価的に高精度コンパレータを実現


Early stage mixed signal CMOS LSI for CE

6b Video ADC

8b low speed ADC;DAC

Digital Video filter

8b CPU

1993 Model: Portable VCR with digital image stabilizing

Success of CMOS ADC and DAC enabled low cost mixed signal CMOS LSI.This also enabled low cost and low power digital portable AV products.

System block diagram


CMOS as analog device


CMOS as analog device

CMOS Bipolar CommentSwitch action ++ --

Low Input current ++ --

High gm - + CMOS is ¼ of Bip.

Low Capacitance + - This results in Cp issue

fT + + Almost same

Voltage mismatch -- ++ CMOS is 10x of Bip.

1/f noise -- ++ CMOS is 10x to 100x of Bip.

Low Sub. effect - +

Offset cancel ++ --

Analog calibration ++ --

Digital calibration ++ --

Embed in CMOS ++ --

Only CMOS can realizeswitched capacitor circuits

CMOS has a variety of techniquesto address the self issues

CMOS has many issues as analog device,but also has a variety of circuit techniques


GHz operation by CMOS

inT

Cgmfπ2

≡

Cutoff frequency of MOS becomes higher than that of Bipolar.Over several GHz operations have attained in CMOS technology

1995 2000 2005

1G

10G

100G

100M

Freq

uenc

y (H

z)

200M

500M

2G

5G

20G

50GfT : Bipolar (w/o SiGe)

fT

Year

eff

satTpeak

Lvfπ2

≈

D R/C for HDDIEEE 1394

/60 (CMOS )Digital circuits

fT : CMOS

0.35um

0.25um0.18um

0.13um

fT

CellularPhone

/10 (CMOS )

CDMA

RF circuits

5GHz W-LAN


World first 1394b transceiverFor 1Gbps networking

0.25um 3AL_CMOS

5Gbps Eye pattern

0.18um 4AL_CMOS

Test chip for 5Gbps wire line

Digital consumer needs over GHz wire line networking.CMOS has attained 5Gbps data transfer.

CMOS technology for over GHz networking


fT: MOS vs. Bipolar

⎟⎠⎞

⎜⎝⎛

≡

2effV

IdsgmTU

Icgm ≡

Teff nUV 2min = n: 1.4

BipCMOS gmgm41,

21

<

mVq

kTUT 26≈≡

（Same operating current）

CingmfT π2

≡

BipCMOS CinCin41,

21

< （Same fT）

Veff/2: 50-100mV(actual ckt.)

Even if fT of MOS is same as that of Bipolar, fT of MOS is easily lowered by a parasitic capacitance.Because, gm of MOS is ½ to ¼ of that of Bipolar at the same current.

MOS Bipolar


Parasitic effect: CMOS CT filter

The high frequency ckt. with a scaled device is strongly affected from parasitic effects.Circuit optimization with layout and parasitic effect is needed.


Transistor issue: VT mismatch

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

5

0

10

15

)(1 1−mLW

μ

ΔV

T(σ

:mV

)

0.4um Nch

0.4um Pch

0.13um Nch In w/o Halo*

0.13um Nch Boron w. Halo*

* Morifuji, et al., IEDM 2000.

Larger gate area is needed for the small VT mismatch.Scaling and proper channel structure can improve this.

LWTV ox

T ∝Δ

Larger gate area

Tox scaling

Channel engineering


Development strategy and design systemfor mixed signal SoC


Full DVD system integration in 0.13um tech.

PixelOperationProcessor

PixelOperationProcessor

IOProcessor

IOProcessor

AVDecode

Processor

AVDecode

Processor

Back -EndBack -End

SystemCont-roller

SystemCont-roller

CPU１CPU１CPU2CPU2

VCOVCO

ADCADC

Gm-CFilterGm-CFilter

PRMLRead

Channel

PRMLRead

ChannelServo DSPServo DSP

AnalogFront EndAnalog

Front End

Front-EndFront-EndAnalog FE+Digital R/C

0.13um, Cu 6Layer, 24MTrOkamoto, et al., ISSCC 2003

Advanced mixed signal SoC has been successfully developed.


System: DVD player

ConsoleConsolePanelPanel

HeadHeadAmpAmp

DemodulationDemodulationECCECC

ACAC--3 Output3 Output

MPEG 2MPEG 2VideoVideo

ACAC--3 Audio3 Audio

System ControllerSystem ControllerMCUMCU

CDCDDEMDEM

16M16MSDRAMSDRAM

DriverDriver

Optical DiscOptical Disc Optical Optical HeadHead

Pre AmpPre AmpStereo OutputStereo Output

Video OutputVideo Output

CopyCopyProtectionProtection

PhotoPhoto--receptivereceptiveCompoundCompound

ServoServoDSPDSP

AnalogAnalogFront EndFront End

ODCODC

AV DecoderAV DecoderRed Laser UnitRed Laser Unit

Servo DSPServo DSP System Controller MCUSystem Controller MCU

4M4MDRAMDRAM

Red LaserRed Laser

：：FirstFirst--Gen.Gen.

：：SecondSecond--Gen.Gen.

：：ThirdThird--Gen.Gen.

：：FourthFourth--Gen.Gen.

ReadReadChannelChannel

OSAPI

High-speedAnalog-Digital

32bit MCUDRAM Embedded Media Core

Processor

MPEGAlgorithm

Analog

Memory

Current electrical systems are complicated and needs analog and memory.


Scaled CMOS technology

Seven latticesGate

Si

SiO2

100nm

Transistor Cu Interconnection

Current Scaled CMOS technology is very artistic.

Matsushita’s 0.13um CMOS technology


Development strategy and system

12 Mon

FirstDVD ROM

8xDVD ROM

12 Mon 3 Mon

12xDVD ROM

6 Mon 6 Mon12 Mon

Time‘97 ‘00

2.6GRAM

2nd G2.6GRAM

4.7GRAM

Combo16x

DVD ROMCombo

6x DVD ROM

Sale

s (A

.U)

The product time slot is narrow and the development cost is huge.

Conventional analog LSI needs 2 or 3 re-designs.This can not be accepted to mixed signal SoC

Advanced development strategy and design system must be established.


System target driven development

Process dev.

Cell Lib. Dev.

SoC design

System target.

Process modif.Design modif.

Unconformity

Spec. Cost and Time

Conventional

Advanced

Process dev.

Cell Lib. Dev.

SoC design

System target

MP

MP

Shorten dev. TAT

Collaboration System driven!

System target driven can reduce unconformities and shorten the TAT.

to solve boundary problems


Making roadmap

Making roadmapand meetings

System

SoC DesignCell Lib.

Process

Fab

EDA

Test

Package

Making roadmap makes a good communication and a corroborationbetween different groups.

Device

ReliabilityHigh IddLow Ioff

POELow inductance

High yieldQuick ramp-upAnalog control

Low-kCuSTIAnalog

Cell heightHP AnalogHP I/O

Mixed signalClockingPower routing Mixed signal

Large system’s verification

EMI simCross-talk simMixed signal sim

Iddq testWafer burn-inMixed signal

Quick parameter extractionFuture issues and tradeoffs

Future demand

Solutions


Modeling and simulation

SimulatorN

SimulatorN

SimulatorN+1

SimulatorN+1

SimulatorN-1

SimulatorN-1

Target Target

Chip design Library/ Circuit DeviceTo processFrom system

Verify Verify

Tpd Ids Tox, L, VT

Final stage: Quick with high accuracy

<8%Planning stage: Very quick with enough accuracy

Sensitivity analysisOptimize between trade-offs

Quick iteration Quick iteration

Model development!

The collaboration should be done with simulators.Making a good model and a simulator will make our core-competence.


Strategy for the mixed signal SoC

• System design– Digital calibration for analog adjustment and unknown parameters.– System optimization to reduce analog area and increase robustness.

• System verification– Fast and accurate mixed signal system simulator with behavioral model to

verify and optimize the mixed signal system.– Create the target performance for circuit blocks.

• Circuit design– Ultra fast and accurate circuit simulation for P.V.T and fluctuation analysis

to verify the performance and robustness.– Circuit optimizer to find the sweet spot of the circuit.– Automated creation of analog behavioral model for system sim.

• Process and device development– Develop suitable analog option device– Early analog parameter extraction ( mismatch, temp. and voltage chara.)– Monitor and control the analog parameters in Fab.


Design flow for mixed signal SoC

System design(Mixed signal level)

Circuit design(SPICE +Behavioral)

Layout design(Semi/Full automated)

TransistorsPassivesSubstrate

PackageCable

Device parameters(SPICE, Noise, Mismatch)

Required SPEC

Optimizer

Parasitic effect

Actual Circuit model

Bottom up flow

Design flow from a system to a layout with top down and bottom up process should be used for designing the mixed signal SoC. An accurate and a variety of device parameters is an another key.

Top down flow

Unified design flow controller


Multi-language simulation

Multi-language simulation is 56x faster than SPICE with same accuracy.This will contribute to shorter design TAT and higher design quality.

SPICE+Verilog D+Verilog A


Mixed signal system designNeeds the mixed signal simulation for total signal processing. Many parameters and processing methods should be optimized.

ENCODER

DECODER

PRECODER

ADC PREQUALIZER

VITERBIDETECTOR

M-RANDOM

ＢＥＲ

NOISE

Encoder/Decoder Methods

Processing MethodResolution

# of Taps

# of Taps

# of PathBoost level

Filter

AnalogDigital

Real disc signal Finally, system is checked by real disc signals.


System simulation

System verification

SNR

BER

4b

5b

6b7b

RLL (2, 10) recorded data

Viterbi decoded result

PR(3,4,4,3) waveform

ADC resolution effect

Perfection of the mixed signal system should be verifiedand optimized by system simulation.


ADSL Analog Front End

Tuning


Digital Signal

Processor

G.C.

LNA

１．１ＭＨｚ１３８ＫＨｚ

ADC

DAC

VCO

DAC XTAL

Dig

ital I

nter

face

０～－ 15dB

0～ 31dB

12

12

8

Rx Data

Tx Data

局側： Solid lines

宅側： Dotted lines

Tuning


Digital Signal

Processor

G.C.

LNA

１．１ＭＨｚ１３８ＫＨｚ

ADC

DAC

VCO

DAC XTAL

Dig

ital I

nter

face

０～－ 15dB

0～ 31dB

12

12

8

Rx Data

Tx Data

局側： Solid lines

宅側： Dotted lines

ExternalLine

Interface


LSI design using behavioral language

LNA

Filter

D/A

A/D

Output driver

VCXO cont.

BufferBuffer

Filter

Control logic

Example: Analog Front End chip for ADSL system.


Analog: Verilog-A

Logic: Verilog-D

Analog behavioral model

Hierarchical and behavioral system design

A system should be described in behavioral language, hierarchically.


Virtual System test using Verilog AMS and Matlab

MatlabDMT modulation

Target LSI

Verilog-AMS

MatlabDMT demodulation

QAM constellation

Q

I

MTPR TEST (DMT Carrier hole)f

FIR FFTFIRIFFTConstellationENC

ConstellationDEC

> 66dB

Matlab is used as a soft DSP

We can test the designed mixed signal system virtually,by using Verilog AMS and Matlab.


Fitting between behavioral and Spice

Verilog-A Sim

SPICE sim

Verilog-A

SPICE

Function checkIn Verilog-AMS

Specification

Circuit design(SPICE+Verilog AMS)

Fitting check

Behavioral modelextraction

If needed

The combination of Verilog AMS and SPICE assures system perfection.


Unified mixed signal circuit simulator

Design flow controller

Design flow controllerOptimizationOptimizationSystem levelSystem level Specification Simulation

Results

DocumentationTest bench

PVT analysisSpec sheet

Behavioral modelOptimization

Simulation flow

DocumentationTest bench

PVT analysisSpec sheet

Behavioral modelOptimization

Simulation flow

New design system can increase design speed, 10x to 50x.

Verilog-AMS+SPICE


Controller for automated simulation

Project nameProject name

Test bench (20 types)Test bench (20 types)

Parameter seepParameter seep

Spec sheet-PLL simulation results-Behavioral modeling

Spec sheet-PLL simulation results-Behavioral modeling

Behavioral model calibration Behavioral model calibration

OptimizationOptimization

Design procedureDesign procedure

Behavioral model generationBehavioral model generation

Simulation controller enables fast and automated simulation steps


Mixed signal system sim. for LCD system

ＴＦＴ

Gate Driver

Source Driver

MPU

LCD Cell Modeling by AHDL

DC/DCConverter

Control Logic Gate

Out

put B

uffe

r Arr

ay

Control Logic Gate・Operating Mode Control・Image Processing Control

Output BufferArray

DAC

Analog

AnalogDigital

Analog

Command Instructions

Digital

LCD-PanelAnalog

Original Image

Output images on LCD

We can create output image on LCD panel by Verilog AMS.Effects by analog performance and LCD characteristics can be checked easily.


Issues of mixed signal SoC


Vdd and CMOS scaling limits in analog

アナログ（上限）

アナログ（下限）

デジタル（上限）

デジタル（下限）

テクノロジーノード

‘00 ‘05 ‘100

1

2

3

4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Tech

nolo

gy n

ode

(0.1

um)

Analog (Upper)

Analog (Lower)

Digital （Upper）

Digital (Lower)

Technology node

‘00 ‘05 ‘10

Supp

ly v

olta

ge (V

)

ITRS ‘99

Lowest analog operating voltage must be 1.2V -1.8V.Thus 0.18um – 0.13um must be a scaling limit for analog.This results in salutation of fT and area reduction.


Optimization in channel parameters

Internal capacitanceTransistor area

Output resistanceDC Gain

Frequency characteristics

1/f noiseVT mismatch

Small Large

Log

(Mag

nitu

de)

Log L

Larger gate length is needed for small mismatch and small noise circuit.However, this results in increase of cost and decrease of performance.


Cost up issue by analog & I/O

0

0.1

0.2

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0.35um 0.25um 0.18um 0.13um0

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0.35um 0.25um 0.18um 0.13um

（0.35um : 1）

Chip area Chip cost

I/OAnalog

Digital

The cost of mixed A/D LSI will increase when using deep sub-micron device, due to the increase of the cost of non-scalable analog and I/O parts.

Large analog on SoC must be unacceptable in near future.Wafer cost increases 1.3xfor one generation


Solution 1: Scaled CMOS and use of digital

0.35um0.35um

0.35um TrAccurate passive

Pros

Cons

· Small area (low cost)· High speed· Low power

· Small area (low cost)· High speed· Low power

· Low accuracy· Sensitive to Process· Large 1/f noise

· Low accuracy· Sensitive to Process· Large 1/f noise

· Analog compensation· Digital calibration· System optimization

· Analog compensation· Digital calibration· System optimization

Solution

Use scaled CMOS and not accurate passives.Address the issues by M/S compensation and system optimization.

0.13um0.13um

0.18um_0.13um TrNot accurate passive

(If low Vdd is acceptable)

Scaled CMOS


Example: Analog+ digital calibration tech.

+/- 9 LSB +/- 0.4 LSB

Calibration

Y. Cong and R. L. Geiger, Iowa state university,ISSCC 200314b 100MS/s DAC

1.5V, 17mW, 0.1mm2, 0.13um

0.5 LSB INL,

SFDR=82dB at 0.9MHz, 62dB at 42.5MHz

Area: 1/50

Pd: 1/20

Area and power are reduced drastically, by scaled CMOS and digital tech.


Digital calibration in M/S SoC for DVD

Ana

log

Buf

fers

OffsetAdjustVGA 5th order

Gm-C Filter

DAC

DAC

7bitADC

OffsetControl

Defect

WobbleFilter

Frequency&

PhaseComparator

FIRFilter

LMS

ViterbiDetector

LoopFilters

DACs

VCO

ClockControlSystem

Clocks

1/N

LevelDetector

ExtractedData

PRML Read Channel

WobbleDetect

Pick upOutputs

Analog Front End

ExtractedClock

…

ServoPre-Processor

Servo Error Signals

GainControlDefectDetect

[RF input] [Analog Filter output]

[FIR output]

...

DigitalCalibration

Analog is calibrated by digital automatically.This technology becomes practical.SoC has CPU and digital area becomes smaller.


Solution 2: Advanced packaging technology

Chip On Chip technology

Same capacitanceas on-chip interconnection.No interconnection inductance

LSI A(DRAM)

LSI B(MPU)

area pads

+

bumps

LSI chip A

LSI chip B

AnalogDigital

Some advanced packaging technologies will give the solution.

Analog: using not so much scaled technology.Digital: using scaled technologyConnect with low parasitic cap. and inductance.


Future step: Mixed signal egg.

Analog yolk and white

Digital shell

Ultra-low power signal processingUltra-high speed signal processing

(Weak inversion)

Sustain the analog egg.Calibration and adjustment.

But, very delicate and fancy

Analog helps digital (digital network and storage…).Next step is digital must help analog.

Mixed signal egg ( Analog yolk and white with digital shell)


Future direction: Sensor telemetric SoC

SensorActuatorSensor

ActuatorAnalog

processingAnalog

processingDigital

ProcessingDigital

ProcessingCommunication

NetworkingCommunication

Networking

Power supplyPower supply Digital controlDigital control

RFUWB

Mixed Signal Processing

Sensor telemetric SoC

RF powerNatural energy (Temperature, Gravity, Kinetic, etc)

It will form ubiquitous networkingEverything contains tiny SoC for sensing and telemetry

Outer world


Summary

• Mixed signal (Analog+Digital) SoC becomes a major technology in the LSI world, along with growth of digital consumer products and networking.

• Advanced design methodology with new simulation tools and novel development strategy are vital for this business success.

• CMOS is very powerful technology for analog, as well as digital, but scaling limitation is reaching.

• The collaboration between analog and digital, and advanced packaging technology will bring us effective solutions.

Documents

Mixed signal SoC: Current status and future prospectBoard Level (Disc.+Bip) 20W $ 8,000 Conventional product World 1st Monolithic Bipolar (3um) 2W $ 800 World lowest power CMOS (1.2um)