MMC Hardware and Simulation Comparison

Modular Multilevel Converter Hardware and Simulation Comparison

A thesis submitted to The University of Manchester for the degree of

Doctor of Philosophy

in the Faculty of Science and Engineering

2019

Theodor L Heath

School of Engineering

Department of Electrical and Electronic Engineering

Power and Energy Division

2

Blank page

Table of Contents

3

Table of Contents

Table of Contents .............................................................................................................. 3

List of Figures .................................................................................................................... 6

List of Tables .................................................................................................................... 11

Nomenclature ................................................................................................................. 12

Abstract ........................................................................................................................... 18

Declaration ...................................................................................................................... 19

Copyright Statement ....................................................................................................... 19

Acknowledgements ......................................................................................................... 20

The Author ...................................................................................................................... 20

Introduction ............................................................................................................ 21 1.

1.1. Background ....................................................................................................... 21

1.2. Future Connections .......................................................................................... 23

1.3. Aims and Objectives ......................................................................................... 26

1.4. Main Contributions ........................................................................................... 26

1.5. Thesis Structure ................................................................................................ 27

Modular Multilevel Converter ................................................................................ 30 2.

2.1. Converter Predecessors ................................................................................... 30

2.2. Modular Multilevel Converter Concept ........................................................... 37

2.3. Sub-Module Configuration ............................................................................... 43

2.4. System Control ................................................................................................. 49

Circulating Current Suppression Controller ............................................................ 53

Decoder ................................................................................................................... 55

Nearest Level Controller ......................................................................................... 56

Capacitor Balancing Controller ............................................................................... 58

Control Structure Development .............................................................................. 60 3.

3.1. Comparison of Centralised and Distributed Control Structure ........................ 60

Table of Contents

4

3.2. Objective and Function .................................................................................... 63

3.3. Converter Hardware Prototype Control Structure .......................................... 64

3.4. Summary........................................................................................................... 67

Hardware Development .......................................................................................... 69 4.

4.1. Objective and Function .................................................................................... 69

4.2. System Ratings ................................................................................................. 69

4.3. Sub-Module Design .......................................................................................... 71

Core Components ................................................................................................... 72

Control, Measurement and Communication .......................................................... 74

Sub-Module Power Supply ...................................................................................... 75

Sub-Module Printed Circuit Board .......................................................................... 77

4.4. Auxiliary Circuits ............................................................................................... 81

4.5. Converter Hardware Prototype ........................................................................ 87

4.6. Summary........................................................................................................... 90

Control System Software Development ................................................................. 91 5.

5.1. Distributed Control Unit ................................................................................... 92

5.2. Phase Control Unit ........................................................................................... 94

5.3. Central Control Unit ......................................................................................... 99

FPGA ........................................................................................................................ 99

RT........................................................................................................................... 102

5.4. Human Machine Interface .............................................................................. 104

5.5. Summary......................................................................................................... 105

Simulation Model Development ........................................................................... 107 6.

6.1. Simulation Model Types ................................................................................. 107

6.2. Simulation Model Overview ........................................................................... 109

6.3. Simulation Results .......................................................................................... 113

6.4. Additional Simulation Studies ........................................................................ 121

Table of Contents

5

6.5. Summary ......................................................................................................... 121

Comparison of Simulation and Hardware ............................................................. 122 7.

7.1. Hardware Results ........................................................................................... 122

7.2. Delay Assessment ........................................................................................... 130

7.3. Detailed System Overview ............................................................................. 141

7.4. Summary ......................................................................................................... 144

Conclusion and Future Work ................................................................................ 145 8.

8.1. Conclusion ...................................................................................................... 145

8.2. Future Work ................................................................................................... 147

References ..................................................................................................................... 151

Appendix A – Alternative Converter Topologies ........................................................... 160

A.1. Cascaded Two-Level Converter ......................................................................... 160

A.2. Alternate Arm Converter ................................................................................... 160

Appendix B – Component Calculations and Circuit Design........................................... 163

B.1. Sub-Module Capacitor Calculation .................................................................... 163

B.2. Arm Inductor Calculation ................................................................................... 167

B.3. Discharge Resistor Calculation ........................................................................... 168

B.4. Sallen-Key Filter Circuit Calculation ................................................................... 168

B.5. MOSFET On-Resistance Calculation ................................................................... 169

B.6. Gate-Drive Circuit Calculation ............................................................................ 170

Appendix C – Main Component List .............................................................................. 172

Word count: 34,760 (37,390 with appendix)

List of Figures

6

List of Figures

Figure Title Page

Figure 1.1 Cost comparison between HVAC and HVDC 23

Figure 2.1 Single-phase and three-phase two-level voltage-source

converters

31

Figure 2.2 Operation modes for a single-phase two-level voltage-source

converter

31

Figure 2.3 Pulse-width modulation technique for a single-phase two-level

converter

32

Figure 2.4 Single-phase three-level active neutral-point clamped voltage-

source converter

34

Figure 2.5 Pulse-width modulation technique for a single-phase three-level

converter

35

Figure 2.6 HVDC converter losses since 1990 36

Figure 2.7 Modular multilevel converter overview diagram 37

Figure 2.8 Half-bridge sub-module overview diagram 38

Figure 2.9 Modular multilevel converter equivalent diagram 39

Figure 2.10 Operation modes for a single-phase five-level modular multilevel

converter

42

Figure 2.11 Full-bridge sub-module overview diagram 44

Figure 2.12 Freewheeling DC short-circuit fault topology for HB and FB-SM

MMC

45

Figure 2.13 Clamped double sub-module overview diagram 46

Figure 2.14 T-type sub-module overview diagram 48

Figure 2.15 Generic converter control structure 49

Figure 2.16 Converter inner voltage control structure 50

Figure 2.17 State-block diagrams for dq current control 51

List of Figures

7

Figure 2.18 State-block diagrams for power control 52

Figure 2.19 Converter inner voltage control structure 53

Figure 2.20 Modular multilevel converter three-phase equivalent diagram 53

Figure 2.21 Circulating current suppression control state-block diagram 55

Figure 2.22 Decoder control block diagram 56

Figure 2.23 NLC round function output example 58

Figure 3.1 Centralised control structure 61

Figure 3.2 Distributed control structure 62

Figure 3.3 CHP distributed control structure 65

Figure 3.4 Terasic DE10-Nano DCU 66

Figure 3.5 NI PXI system 67

Figure 3.6 CHP distributed communications structure 68

Figure 4.1 Converter hardware prototype sub-module topology 71

Figure 4.2 Converter hardware prototype sub-module overview 74

Figure 4.3 Sub-module component layout overview 78

Figure 4.4 CHP SM hardware (without capacitor bank) 79

Figure 4.5 CHP SM hardware (with capacitor bank) 80

Figure 4.6 DCU breakout board 81

Figure 4.7 Fibre-optic breakout board 82

Figure 4.8 Power interface board 83

Figure 4.9 BNC analogue interface board 83

Figure 4.10 5 V distribution board 84

Figure 4.11 24 V distribution board 84

Figure 4.12 Auxiliary boards in situ 85

Figure 4.13 CHP system overview 86

Figure 4.14 Populated local controller sub-rack 87

List of Figures

8

Figure 4.15 CHP server rack design 88

Figure 4.16 CHP experimental test rig 89

Figure 4.17 AC resistive load cabinet 90

Figure 5.1 Simplified overview diagram of CHP distributed control

architecture

91

Figure 5.2 Overview diagram of DCU control program 92

Figure 5.3 Packet structure for DCU to SM and DCU to PCU communication 93

Figure 5.4 Overview diagram of PCU control program 95

Figure 5.5 Packet structure for PCU to CCU-FPGA communication 96

Figure 5.6 Overview diagram of CCU-FPGA control program 99

Figure 5.7 Overview diagram of CCU-RT control program 102

Figure 5.8 Front panel of HMI control program 104

Figure 5.9 Overview diagram of control system software and control loop

separation

105

Figure 6.1 Open-loop DEM overview diagram 110

Figure 6.2 CHP-DEM overview diagram 112

Figure 6.3 Capacitor voltage in one sub-module and sum of capacitor

voltages in one arm during a charge cycle in the CHP-DEM

113

Figure 6.4 CHP-DEM under no-load conditions: Converter AC voltage

outputs, external three-phase reference, and reference and

output for one phase

114

Figure 6.5 CHP-DEM under 100 Ω load conditions: Converter AC voltage

outputs and external three-phase voltage reference

115

Figure 6.6 CHP-DEM under 100 Ω load conditions: Converter AC and DC

terminal current, upper and lower arm current, and internal

circulating current

116

List of Figures

9

Figure 6.7 Sub-module capacitor voltages for the upper arm of phase A

using a capacitor balancing frequency of 800 Hz, the resulting

circulating currents and DC terminal current in the CHP-DEM

117

Figure 6.8 Sub-module capacitor voltages for the upper arm of phase A

using a capacitor balancing frequency of 250 Hz, the resulting

circulating currents and DC terminal current in the CHP-DEM

118

Figure 6.9 Impact on DC current for varying CBC trigger frequencies in the

CHP-DEM

119

Figure 6.10 CHP-DEM under 15 Ω load conditions: Converter AC voltage

outputs, AC and DC current outputs, internal upper and lower

arm currents, and sub-module capacitor voltages for the upper

arm of phase A using a capacitor balancing frequency of 800 Hz

120

Figure 7.1 CHP under no-load conditions: Converter AC voltage outputs,

external three-phase reference, and reference and output for

one phase

123

Figure 7.2 CHP under 200 Ω load conditions: Converter AC voltage outputs,

external three-phase reference and converter AC current output

124

Figure 7.3 CHP under 200 Ω load conditions: Converter AC terminal

voltage and reference voltage, and AC terminal current

125

Figure 7.4 CHP under 200 Ω load conditions: Upper and lower arm current

for phase C with a DC link voltage of 40 V, 80 V and 140 V

126

Figure 7.5 CHP under 100 Ω load conditions: AC reference and terminal

voltage, and DC terminal voltage and current

127

Figure 7.6 CHP-DEM with DC voltage fluctuation under 100 Ω load

conditions: DC current and voltage

127

Figure 7.7 CHP-DEM under 200 Ω star-point resistive load: Converter AC

voltage outputs with CBC and without CBC

129

List of Figures

10

Figure 7.8 CHP under no-load conditions: CHP-DEM simulation phase A

voltage reference and output, CHP hardware phase A voltage

reference and output, and magnified sections of the previous

graphs

130

Figure 7.9 Time delay between reference input and voltage output from

system controller

131

Figure 7.10 Histogram of time delay between reference input and voltage

output from system controller over three no-load tests at

different output voltages

132

Figure 7.11 Critical data path in the CHP 133

Figure 7.12 Total system delay overview 134

Figure 7.13 Total system delay breakdown in the converter hardware

prototype

136

Figure 7.14 Best-case total system delay breakdown in the converter

hardware prototype

137

Figure 7.15 State-block diagram for power control with TSD 140

Figure 7.16 CHP under no-load conditions: CHP-DEM simulation with TSD

phase A voltage reference and output, CHP hardware phase A

voltage reference and output, and magnified sections of the

previous graphs

141

Figure 7.17 Detailed equivalent model full overview diagram with no TSD 142

Figure 7.18 Converter hardware prototype full overview diagram with best-

case TSD

143

Figure A.1 Alternate arm converter overview diagram 161

Figure A.2 Operation modes for an alternate arm converter 162

Figure B.1 Sallen-Key low-pass filter circuit 168

Figure B.2 CHP SM gate-driver circuit 170

List of Tables

11

List of Tables

Table Title Page

Table 2.1 Switch modes for half-bridge sub-module configuration 43

Table 2.2 Switch modes for full-bridge sub-module configuration 44

Table 2.3 Switch modes for clamped double sub-module configuration 47

Table 2.4 Switch modes for T-type sub-module configuration 48

Table 4.1 Converter rating specifications 70

Table 4.2 Main component choices and ratings 73

Table C.1 Main component part numbers 172

Nomenclature

12

Nomenclature

List of Acronyms

Acronym Definition

(S)AVM (Simplified) Average Value Model

(T)DM (Traditional) Detailed Model

3LC Three-Level Converter

AAC Alternate-Arm Converter

AC Alternating Current

ACU Arm Control Unit

ADC Analogue-to-Digital Converter

AM Accelerated Model

ANPC Active Neutral-Point Clamped

CB Circuit Breaker

CBC Capacitor Balancing Controller

CCSC Circulating Current Suppression Controller

CCU Central Control Unit

CD (SM) Clamped Double (Sub-Module)

CET Critical Execution Time

CHP Converter Hardware Prototype

CL Control Latency

CMC Cascaded Multilevel Converter

CPU Central Processing Unit

CR Charge Resistor

CTLC Cascaded Two-Level Converter

DAQ Digital Acquisition

Nomenclature

13

DC Direct Current

DCU Distributed Control Unit

DEM Detailed Equivalent Model

DMA Direct-Memory Access

DR Discharge Resistor

DS (SM) Direction Switch (Sub-Module)

DSP Digital Signal Processor

DT Dead-Time

EC Ethernet Controller

EMI Electromagnetic Interference

EMT Electromagnetic Transient

ES Externally Sampled

FB (SM) Full-Bridge (Sub-Module)

FCCU Fully Centralised Control Unit

FG Function Generator

FOB Fibre-Optic Breakout Board

FP Fault-Protection

FPGA Field Programmable Gate Array

FS Firing Signals

FSM Finite State Machine

GHG Greenhouse Gas

HB (SM) Half-Bridge (Sub-Module)

HDL Hardware Description Language

HES Hall-Effect Sensors

HMI Human-to-Machine Interface

HVAC High Voltage Alternating Current

Nomenclature

14

HVDC High Voltage Direct Current

HWTSP Hardware Timed Single Point

I/O Input/Output

IGBT Insulated-Gate Bipolar Transistor

IS Internally Sampled

KVL Kirchoff's Voltage Law

LAN Local Area Network

LC Local Controller

LCC Line-Commutated Converter

LUT Look-Up Table

MEV More-Electric Vehicles

MMC Modular Multilevel Converter

MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor

NLC Nearest Level Controller

NPC Neutral-Point Clamped

OCP Over-Current Protection

OPWM Optimised Pulse-Width Modulation

OVP Over-Voltage Protection

PC Parity Check

PCB Printed Circuit Board

PCC Point of Common Coupling

PCI Peripheral Component Interconnect

PCU Phase Control Unit

PE Power Electronics

PI Proportional-Integral

PIB Power Interface Board

Nomenclature

15

PLL Phase-Locked Loop

POW Point-On-Wave

PSU Power Supply Unit

PWM Pulse-Width Modulation

RCR Ripple Current Rating

RMS Root-Mean Square

RT Real-Time

SM Sub-Module

SMD Surface Mount Device

SM-ID Sub-Module Identification

SoC System-on-Chip

SPI Serial Peripheral Interface

STATCOM Static Synchronous Compensator

TEC Thévenin Equivalent Circuit

TFEC Total Final Energy Consumption

THD Total Harmonic Distortion

TLC Two-Level Converter

TSD Total System Delay

VPL Visual Programming Language

VSC Voltage-Source Converter

Nomenclature

16

List of Symbols

Symbol Definition S.I. Units

C Capacitance F

Csm Sub-Module Capacitance F

D Diode -

DR Discharge Resistance Ω

F Fuse -

f Frequency Hz

fc Carrier Frequency Hz

fr Reference frequency Hz

I Current A

I(abc)la Lower Arm Current A

I(abc)ua Upper Arm Current A

Iac(abc) AC Phase Current A

Iarm Arm Current A

Icirc Circulating Current A

Idc DC Current A

Idiff Difference Current A

Idq dq Current A

L Inductance H

Larm Arm Inductance H

N Number of Sub-Modules per Arm -

N(abc)la Number of Sub-Modules Connected in Lower Arm -

N(abc)ua Number of Sub-Modules Connected in Upper Arm -

P Real Power W

Nomenclature

17

p d/dt -

Q Reactive Power VAr

R Resistance Ω

Rarm Arm Resistance Ω

S Switch or Apparent Power - or VA

s Laplace Operator -

V Voltage V

V(abc)la Lower Arm Voltage V

V(abc)ua Upper Arm Voltage V

Vac(abc) AC Voltage V

Vcap Sub-Module Capacitor Voltage V

Vdc DC Voltage V

Vn(abc) AC Network Voltage V

Vref Reference Voltage V

Wua Energy in Upper Arm J

Vsm Sub-Module Voltage V

x* Set-Point -

x^ Peak -

Z Zener Diode or Impedance - or Ω

ε Percentage Error -

ω Rotational Speed rad/s

Abstract

18

Abstract

Name of University: The University of Manchester

Candidate’s name: Theodor L Heath

Degree Title: Doctor of Philosophy

Thesis Title: Modular Multilevel Converter Hardware and Simulation Comparison

Date: September 2019

Offshore wind generation currently provides 7% of the total installed capacity in the

UK. This is set to increase significantly in the coming decade as the Crown Estate

releases larger swathes of coast and seabed for development. The increasing

penetration of offshore wind and other renewable sources is changing the traditional

energy mix and adding very fast, low inertia power electronic systems to a traditionally

slower, high inertia network. Given the large number of planned voltage-source

converter based high voltage direct current (VSC-HVDC) links, and the rapid scheduled

rollout of the technology, utilities and government have an urgent need for improved

information in this area.

A key weakness is that presently most public domain research and development on

VSC-HVDC is based on simplified simulation models which may not always capture key

hardware complexities and realistic converter operation. The research presented in

this thesis includes the development of a low-power modular multilevel converter

(MMC) with an industrially representative control architecture which has been

designed to investigate these complexities, and provide a platform for future research.

In this thesis, the design, construction, programming and testing of a MMC hardware

prototype (CHP) is discussed in detail, providing a contribution to public-domain

knowledge on the technology and enabling other institutions to bridge the gap into

hardware research. Hardware outputs from the CHP have been compared against

simulation results from a matching detailed equivalent model (DEM) to study the

impact of real internal converter control on power system simulation fidelity. A time

delay associated with the internal control systems has been identified and quantified

as a useful additional element to achieve more accurate models, and this has been

analysed in detail. The time delay indicates a requirement for limits on the bandwidth

of outer controllers and impacts the converter response rate to network transients. A

simple method to incorporate this delay into a PSCAD/EMTDC simulation is then

discussed, assisting in the improvement of power system simulation models.

Declaration and Copyright Statement

19

Declaration

No portion of the work referred to in the thesis has been submitted in support of an

application for another degree or qualification of this or any other university or other

institute of learning.

Copyright Statement

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owns certain copyright or related rights in it (the “Copyright”) and s/he has given The

University of Manchester certain rights to use such Copyright, including for

administrative purposes.

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described in this thesis, may not be owned by the author and may be owned by third

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Intellectual Property and/or Reproductions.

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Library’s regulations (see http://www.library.manchester.ac.uk/about/regulations/)

and in The University’s policy on Presentation of Theses

Acknowledgements and The Author

20

Acknowledgements

Above all, I would like to thank my two brilliant supervisors, Professor Mike Barnes and

Professor Peter R Green. Their expertise, insight and direction have greatly assisted the

research presented in this thesis. Peter and Mike have provided exemplary support,

both professionally and personally during my studies and opened doors to some

fantastic opportunities. It has been an absolute pleasure working with them during the

project and I look forward to many more years of collaboration and friendship.

Financial support under an iCASE sponsorship from the Engineering Physical Sciences

Research Council and National Grid has enabled this research to take place; therefore I

would like to thank both organisations for their assistance in this area. Also, many

thanks to the research project liaisons at National Grid: Dr Paul Coventry, Dr Dechao

Kong and Robin Gupta, for their effort and support.

I would also like to thank my colleagues within the Power Division and the wider

Department of Electrical and Electronic Engineering for the interesting discussions and

technical assistance which were vital for problem solving and debugging. A special

thanks to Sam Ward, who has been critical part of my support network over the last

seven years as Student Welfare Officer.

Last, but by no means least, I would like to thank my wonderfully dynamic family and

friends (including all those already mentioned) for their unwavering support, fantastic

company and valuable encouragement which has kept me afloat and moving forward.

I would especially like to thank Beth for her support, care and patience over the last

seven years, her confidence in me is an endless source of strength which cannot be

overstated.

The Author

Theodor Heath received a first class BEng (Hons) in Electrical and Electronic

Engineering from the University of Manchester in 2015 and has since been studying for

PhD at the same institution under the supervision of Professor Mike Barnes and

Professor Peter R Green. The focus of his research is on voltage-source converters for

high voltage direct current applications the culmination of which is this thesis.

Introduction

21

Introduction 1.

1.1. Background

“Climate change is the defining issue of our time” [1] , a truly global challenge which

has the potential to have a devastating impact on people and the environments in

which they live.

The United Nations Intergovernmental Panel on Climate Change (IPCC) assessment

report in 2013 found that the average global temperature increased by 0.85°C

between 1880 and 2012. More recent measurements from NASA and the IPCC push

this trend to nearer 1°C in 2017 [2, 3]. Both organisations predict temperatures will

continue to rise through the foreseeable future. The IPCC also suggested that

potentially significant and largely irreversible damage to ecosystems and infrastructure

will be caused should this reach 1.5°C above pre-industrial levels [3, 4]. In addition to

the IPCC, close to 97% of publishing climate scientists believe that ‘human activity’ is a

significant cause of climate change [5], and therefore it is human activity that can also

help to limit this rise. “Rapid, far-reaching and unprecedented changes in all aspects of

society” are required to keep to the 1.5°C limit [1].

In 2015 Parties to the United Nations Framework Convention on Climate Change

(UNFCCC) reached an agreement to prioritise the actions and investments needed for

a sustainable low carbon future, in the hope of limiting the average global temperature

rise to the IPCC recommendation of 1.5°C up to a maximum of 2°C [6]. As of August

2019, 185 out of 197 Parties have ratified the Paris Agreement, clearly indicating a

worldwide recognition of, and desire to combat, the issue of climate change [7].

‘Human activity’ refers to the processes which release greenhouse gases (GHGs) into

the atmosphere [2][8]. Electricity and heat production was by far the largest

contributor of GHGs in Europe in 2014, creating an estimated 29.3% of the total [9].

Therefore, it is no surprise that the global energy sector is the target for considerable

reform by the IPCC and Paris Agreement recommendations.

To a small extent the movement away from fossil fuel combustion towards low carbon,

renewable sources of energy had already started in the UK following the Climate

Change Act of 2008 [10], and across the EU, after the Renewable Energy Directive was

enacted in 2009 [11]. The EU is on track to meet one headline target from these

Introduction

22

proposals and fall short on the other; as of 2017, across 28 EU countries, there has

been an average of 21.7% reduction in GHG emissions compared to 1990 levels (above

the 20% target) [12] and an average of 17.5% of total final energy consumption (TFEC)

from renewable sources (below the 20% target) [13]. Despite positive progress, the

International Renewable Energy Agency (IRENA) suggests that a six to seven-fold

increase in the current rate of renewable energy installation is required to meet the

goals set out in the Paris Agreement, increasing the TFEC share of renewables from

15% to 65% by 2050 [14].

Renewables accounted for 33.0% of energy consumed as electricity in the UK in 2018,

up from 29.2% in 2017. However, electricity accounts for just over one sixth of TFEC

[15, 16], clearly indicating that along with a rapid installation of renewable generation

there must also be a huge shift towards the electrification and decarbonisation of the

heat and transport sector to meet climate change targets [17, 18].

Offshore wind energy is one of the most promising technologies available to fill the

renewable energy gap. Potential offshore wind development sites in the UK have been

released by The Crown Estate in a series of rounds, 1 – 3, each increasing in size and

complexity as the required technology and industry advances. All but one project from

Round 1 and Round 2 are operational, with a combined rating of 7.2 GW. A further

3.2 GW is under construction and over 27 GW is in the pipeline [19]. This places the UK

as the world leader for existing installed capacity and future portfolio [20, 21]. This

trend is set to continue with the auction for future offshore wind energy contracts

beginning in autumn 2019, round 4, with an expected increase of 1 – 2 GW each year

throughout the 2020s supported by £557 million of investment for the lowest cost

projects [22, 23].

In 2018 the total installed generation capacity across the UK stood at 105 GW, a slight

drop from 106 GW in 2017, including transmission and distribution level connections

[15, 16]. With a capacity of 7.2 GW, 8% of the total generated electricity in 2018 came

from offshore wind [16]. At predicted rates, offshore wind will be an increasingly

important contributor to the future UK energy mix and therefore the performance and

dependability of these generators, and the systems that support them, will be of

paramount importance in maintaining a reliable supply for millions of consumers.

Introduction

23

1.2. Future Connections

A key component of an offshore wind farm is the connection technology used to

transport generated energy back to the main grid for distribution. This connection can

either be high voltage alternating current (HVAC) or high voltage direct current

(HVDC). HVAC has been technically refined and is a well-understood technology and as

such is often simpler and cheaper to implement than HVDC. HVDC is more efficient for

bulk power transmission but can be considerably more complex and expensive [24].

The distance of transmission is an important consideration in the decision between

HVAC and HVDC. In an HVAC subsea system, a large percentage of the current carrying

capacity is used to charge and discharge the cable capacitance, reducing the amount of

active power which can be transferred using the link, or increasing costs through the

use of reactive compensation [24, 25]. Once charged, a link using HVDC can be utilised

at almost full transmission capacity with high efficiency. The cable cost per kilometre

of an HVAC system is higher than a similarly rated HVDC system. However the

converse is true for the terminal costs where HVAC has small and cheaper substations.

Thus, a break-even point exists based on total cost and connection length. This

relationship is presented in Figure 1.1. The critical distance is typically estimated to be

between 50 and 100 km for offshore connections. For comparison, due to the reduced

capacitance in overhead lines, this is estimated at between 600 and 800 km for

onshore connections [24-26].

Figure 1.1: Cost comparison between HVAC and HVDC

Inve

stm

ent

Co

sts

Distance

DC line cost

AC line co

st

Total AC cost

Total DC cost

DC terminal cost

Critical Distance

AC terminal cost

Introduction

24

A number of consented Round 3 sites will use HVDC for the grid connection with a

distance to shore between 140 and 215 km. These include Creyke Beck A and B,

Teesside A and Sofia (previously known as Teesside B), all located on the Dogger Bank

sandbank off the east coast of England [19]. Hornsea 1, located approximately 120 km

from shore, is using HVAC with reactive compensation for the grid connection, as the

limits for HVAC operation continue to be stretched by industry; the same technology is

planned for Hornsea 2 [25, 27, 28]. While these new advances offer an alternative

solution, HVDC is still seen as the best option for long distance subsea transmission,

either between grids or for offshore generation connections [25, 29, 30].

HVDC converter technology has changed significantly since the first commercial

application of a mercury arc valve line-commutated current source converter (LCC)

based transmission system between the island of Gotland and the mainland of Sweden

in 1954 [31, 32]. Advancements in power electronics in the 1980s, specifically the

development of the insulated-gate bipolar transistor (IGBT), allowed for the design of

self-commutated voltage-source converters (VSCs) [33]. The first industrial application

of a two-level IGBT VSC based transmission system was in 1997 to connect Hellsjön

and Grängesberg, Sweden [34]; this evaluation scheme led to the first commercial VSC-

HVDC transmission link in 1999, also between Gotland and Sweden [24, 35]. VSC-

HVDC is now operational in just over 30 projects globally and this number is expected

to double over the next 5 years [36].

The first LCC-HVDC system designed around thyristor valves was the Eel River scheme

in Canada commissioned in 1972 [37]. Five years later the last mercury-arc system was

installed [31]. Thyristors have dominated the LCC-HVDC market since then and will

continue to do so as improvements in the technology carry on meeting the desire for

improved efficiency, higher reliability and reduced maintenance [38].

To shed light on industrial applications of VSCs, the evolution of ABB’s ‘HVDC Light’

option will be discussed. The 1st Generation, employed on the 1999 Gotland link,

comprised a basic two-level converter (TLC) design with pulse-width modulation

offering approximately 97% efficiency. The 2nd Generation, used for the 2002

Murraylink transmission project between Berri and Red Cliffs in Australia, made use of

a three-level converter (3LC) topology with active neutral-point clamping, increasing

efficiency to around 98%. The Estlink HVDC transmission system between Estonia and

Introduction

25

Finland commissioned in 2006 made use of Generation 3 VSCs; TLCs with optimum

pulse-width modulation, improving efficiency by a further 0.5%. HVDC light is now in

its 4th Generation, the cascaded two-level converter (CTLC), first used on the DolWin1

project in Germany commissioned in 2015, offering close to 99% efficiency [39-42].

The CTLC is one of the main structures of cascaded multilevel converters (CMCs),

another is the modular multilevel converter (MMC), first proposed for HVDC

applications by Marquardt [43, 44] and implemented by Siemens under the name

‘HVDC PLUS’. The Trans Bay Cable project commissioned in 2010 was the first

industrial application of the MMC [45, 46]. A third topology, still in the early stages of

development, is the alternate-arm converter (AAC), proposed by Merlin et al. and

initially considered by Alstom Grid (now GE Grid Solutions) [47, 48].

Currently all major vendors of HVDC systems offer a CMC option [31], however in-

depth knowledge of these systems is presently only held by the manufacturers. The

potential for VSC-HVDC links across the UK, and the plans for rapid adoption of this

technology, brings this lack of knowledge under the spotlight; a significantly better

understanding by utilities and the government is required.

A key weakness in VSC-HVDC research is that presently most public domain research

and development is based on simulation models which can fail to capture key

hardware complexities. The limitations real-time control places on system operation is

a key element, along with nonlinearities in hardware. There is an urgent need for low-

power MMC prototypes that particularly address the real-time control issues in

hardware, in order to further improve simulation models for power system studies. For

these reasons, cascaded multilevel voltage-source converters for high voltage direct

current applications will be the main focus of this research.

The topology chosen to investigate these issues will be the MMC, as it has been the

subject of intensive research and development within academia and industry over the

past decade and therefore is well placed to be a dominating technology for VSC-HVDC

applications [31]. Specifically this research will focus on the internal control and

communication architecture used by MMCs. The findings of the research will help to

determine whether the fidelity of power systems models presently used are suitable

for planning a stable and reliable national power network for consumers.

Introduction

26

1.3. Aims and Objectives

The aim of this thesis is to provide insight into the operation of modular multilevel

converters to inform improvements of power systems simulation models. In order to

achieve this aim, the following objectives have been identified:

1) Design and construct a reduced scale hardware prototype of a modular

multilevel converter with an industrially representative control platform

2) Design and program a real-time representative control and communication

structure

3) Design and construct a detailed equivalent model replica of the reduced scale

hardware prototype

4) Compare, analyse and critically assess control and telecom constraints between

hardware and simulation and identify potential inaccuracies in power systems

simulation tools

1.4. Main Contributions

Thesis

- Construction of a laboratory scale nine-level three-phase modular multilevel

converter with an industrially representative control structure, providing a

future-proofed platform for continued research in the field of voltage-source

converters for high voltage direct current

- Research into the partitioning of total system delay within modular multilevel

converters, which limits outer loop controller bandwidth and transient

response time and a suggested method of adaptation to incorporate the delay

into simulation models

Conference Papers

- T. Heath, P. R. Green, M. Barnes and P. Coventry, “Capacitor Balancing

Controller Voltage Sorting Statistics in Modular Multilevel Converters”, IEEE

Southern Power Electronic Conference (SPEC), Puerto Varas, Chile, December

2017

- T. Heath, P. R. Green, M. Barnes, D. Kong, “Design, Construction and Testing of

a Modular Multilevel Converter with a Distributed Control Architecture”, IET

ACDC Conference, Coventry, UK, February 2019

Introduction

27

Additional

- Contributor to CIGRE Task Force B4.77 on “AC Fault Response Options for VSC-

HVDC Converters” which aims to set out AC system needs as defined by the

European Network of Transmission System Operators for Electricity (ENTSO-E)

and assesses the options achievable with VSC-HVDC technology

- Co-Editor of the “VSC-HVDC Newsletter” alongside M. Barnes, a monthly

release newsletter focussed on developments in, and applications of,

VSC-HVDC converter technology worldwide

- Report “High-Voltage Direct-Current Fault Ride-Through” for National Grid with

a focus on GB to ENTSO-E grid code compliance; report compares LCC and VSC

fault ride-through options and suggests auxiliary systems to support application

of the technologies in different scenarios

Papers in Progress

- T. Heath, P. Judge, G. Chaffey, P. Clemow, P. R. Green, M. Barnes, T. C. Green,

“Designing a Laboratory Scale Modular Multilevel Converter for VSC-HVDC

Investigation”, Magazine

- T. Heath, P. R. Green, M. Barnes, R. Gupta, “Assessment and Breakdown of

Total System Time Delay for a Modular Multilevel Converter with a Distributed

Control Architecture”, Journal

- J. Andrews, T. Heath, P. R. Green and M. Barnes, “A Review and Performance

Evaluation of Sorting Algorithms for Capacitor Balancing Control in Cascaded

Multilevel Converters”, Journal

1.5. Thesis Structure

An overview and summary of each chapter is provided here in order to more easily

navigate the thesis.

Chapter 2 – Modular Multilevel Converter

This chapter covers the concept, design and control of the MMC. Firstly, the early

voltage-source converter topologies are discussed, providing a basis for explaining

MMC operation. This is followed by a description of theoretical behaviour for the MMC

and how the choice of SM design impacts converter operation. Lastly, a brief

explanation of MMC control theory is presented for an industry standard operation

Introduction

28

regime. This chapter provides an important introduction into the MMC technology

underpinning this research.

Chapter 3 – Control Structure Development

In this chapter the different control structures employed on MMCs are discussed.

Initially, the fully centralised control structure, typically used in academic prototypes, is

described and compared against the fully distributed control structure more closely

resembling industrial implementations. This is followed by a description of the chosen

structure for the modular multilevel converter hardware prototype and the

implementation of this architecture in reality, with specific controller hardware.

Chapter 4 – Hardware Development

This chapter provides a comprehensive overview of hardware development for the

converter hardware prototype. The SM design and component selection is discussed in

detail followed by descriptions and images of the required auxiliary circuits supporting

full system functionality. The fully constructed converter hardware prototype is

presented, along with system diagrams and detailed explanation.

Chapter 5 – Control System Software Development

The control system software development for the converter hardware prototype is

presented in this chapter. The theory covered in Chapter 2, the control structure

discussed in Chapter 3 and the hardware detailed in Chapter 4, form the basis for the

control software developed during this research. Each level of controller hardware is

summarised to provide a whole system understanding for the converter hardware

prototype; from the distributed control units to the human machine interface.

Chapter 6 – Simulation Model Development

An overview of the MMC simulation models presently used in academia and industry

are initially provided, followed by a more comprehensive description of the converter

hardware prototype detailed equivalent model which was adapted and developed

during this research. Operation of the simulation model in a number of different test

cases is given to demonstrate nominal converter behaviour.

Chapter 7 – Comparison of Simulation and Hardware

This chapter provides a comparison of simulation model results from the detailed

equivalent model presented in Chapter 6 against experimental hardware results from

Introduction

29

the converter hardware prototype discussed in Chapters 3, 4 and 5. Novel research

into the total system delay is presented, which covers an in depth breakdown of time

delays within a modular multilevel converter with an industrially representative

distributed control architecture. Literature on converter time delays is reviewed and

compared against the findings. A suggested method of incorporating the time delay

into simulation is explained along with a location-based partitioning of the total system

delay.

Chapter 8 – Conclusion and Future Work

A summary of the work contained in this thesis is provided in this chapter, and the

main research outcomes are discussed. Recommendations for a range of different

future research opportunities are also presented.

Appendices and Supplementary Online Repository

Additional technical material, design calculations and component data are provided in

the appendices of this thesis. Printed circuit board designs and written code, both of

which are unsuitable for publication in print, are provided to the reader through a

supplementary online repository hosted by Mendeley Data. This data is accessible

following [49], replicated here for ease.

[49] T. Heath, 2019, "Supplementary Online Repository for Modular Multilevel

Converter Hardware and Simulation Comparison," Dataset published by

University of Manchester, distributed by Mendeley Data, Available:

http://dx.doi.org/10.17632/9sgpn5mdzs.1

Modular Multilevel Converter

30

Modular Multilevel Converter 2.

This chapter provides an introduction to the modular multilevel converter (MMC).

Firstly, the earlier generations of voltage-source converter are discussed, as these

serve as an important basis for explaining MMC behaviour. This will be followed by the

main MMC concept, an overview of sub-module (SM) configurations and an outline of

a typical converter control system.

2.1. Converter Predecessors

The evolution of ABB’s HVDC Light is used as a case-study in this section. This

continues from the overview discussed in Chapter 1. A summary of the earlier

generations is provided as a number of operational principles are shared between

them and the MMC. A grounding in their design and operation is therefore useful to

serve as a basis for explaining the complex design and control of an MMC.

The first generation of HVDC Light was the two-level converter (TLC). The TLC is one of

the most used topologies of voltage-source converter, especially in applications below

1.8 kV. Home appliances, motor drives and domestic generation make wide use of

TLCs due to their simplicity and efficiency [31, 50]. Applications for higher voltage such

as HVDC transmission are relatively recent in comparison, but follow the same

operational principles.

Figure 2.1 shows the schematics for a single and three-phase TLC. A phase comprises

two series connected semiconductor switches (S1, S2) each with an antiparallel diode

(D1, D2) as in Figure 2.1a. The switches are typically metal-oxide-semiconductor field-

effect transistors (MOSFETs) in low power, high switching frequency applications.

Insulated-gate bipolar transistors (IGBTs) are used in high power, low switching

frequency applications. Both allow for bidirectional current flow and controllable

voltage blocking in one direction. Each additional phase is added in parallel across the

DC link along with capacitors to minimise DC voltage ( ) fluctuations during

operation. The AC voltage ( ) terminals, labelled A, B and C in Figure 2.1b, are at the

midpoint of each phase and may make use of an inductor to smooth the current during

switching. For simplicity, the operation of a single-phase will be described, however

the principles can be applied similarly to a three-phase system [24].


31

Figure 2.2 shows the normal operation modes for one phase of a TLC. For each mode

the red lines indicate the positive current path (direction shown by the red arrow) and

the green lines indicate the negative current path. The graph is labelled at each stage

for a corresponding operation mode.

A TLC is so named because the output at the AC terminal can take only two levels. In

mode a, S1 is on, connecting the AC terminal to the positive DC terminal, when in

mode c, S2 is on, connecting the AC terminal to the negative DC terminal. S1 and S2

should not be on simultaneously as this would create a short circuit across the DC link.

A dead-time (or blanking-time) in the order of micro or nanoseconds is set between

one switch turning off and the other turning on.

Figure 2.1: Single-phase (A) and three-phase (B) two-level voltage-source converters

Figure 2.2: Operation modes (a – d) for a single-phase two-level voltage-source converter

D1

D2

Vdc/2

VacVdc/2

S1

S2

D1

D2

S1

S2

D3

D4

S3

S4

D5

D6

S5

S6

A Single Phase B Three Phase

Vdc/2

Vdc/2

AABC

D1

D2

S1

S2

D1

D2

S1

S2

D1

D2

S1

S2

D1

D2

S1

S2

+Vdc2

-Vdc2

+Vdc2

-Vdc2

+Vdc2

-Vdc2

+Vdc2

-Vdc2

A

A A

A

a b

c d

Vo

ltag

e -

Vac

+Vdc2

-Vdc2

a

b

c

d

a

Time


32

During dead-time, the current maintains its original direction due to the AC inductance

and therefore commutates from the switch to the diode. This behaviour is shown in

Figure 2.2. For positive current, as S1 is turned off in mode a, current is forced to flow

through D2 until the AC terminal potential equals the negative DC terminal potential,

as seen in mode b. At this point S2 can be turned on to enable a reversal of current, as

seen in mode c. For negative current, as S1 is turned off in mode a, any current flowing

through S1 commutates to D1, as seen in mode b. At this point S2 can be turned on

connect the negative DC terminal and to enable a reversal of current, as seen in mode

c. This process is similar for mode d when returning back to the positive DC terminal.

The graph in Figure 2.2 plots the voltage from Figure 2.1 for the different operation

modes [37].

By changing the on-time for S1 and S2 during a cycle, the average voltage at A can be

controlled. This method is called pulse-width modulation (PWM) and enables a TLC to

approximate an AC waveform. In Figure 2.3 the PWM process is shown. A sinusoidal

reference (red), corresponding to the desired output voltage and frequency ( ), is

compared against a triangular carrier wave (green).

Figure 2.3: Pulse-width modulation technique for a single-phase two-level converter

, ,


33

When the reference is larger than the carrier, S1 is turned on connecting the AC

terminal to the positive DC terminal, conversely, when the reference is smaller than

the carrier, S2 is turned on connecting the AC terminal to the negative DC terminal,

realising a switching output waveform (blue). Once filtered, the PWM output

represents a good approximation to a sinusoid.

The spectrum, or harmonic content, of a signal is one assessment of power quality and,

where possible, low-frequency harmonic components are avoided through intelligent

control and design. The remaining harmonics can be removed from the waveform

using AC filters comprised of capacitors and inductors, though these can be very large,

lossy and expensive [24, 51]. A larger leads to improved power quality but increased

switching losses [52]. The balance between the effect of harmonics, converter control

and system efficiency for power system applications leads to typical switching

frequencies in the range of 1000 to 2000 Hz [24, 25]. The 1999 Gotland Link TLC had a

switching frequency of 1950 Hz (39 x ) operating at 97% efficiency [42, 53].

As the converter power rating is increased, the balance between harmonics and

efficiency becomes more challenging, as switching and conduction losses increase. In

an effort to mitigate this, and a number of other issues, a few multilevel designs were

proposed. These fall into HVDC Light’s second generation, including the neutral-point

clamped (NPC) three-level converter (3LC) presented in [54], shortly followed by the

improved active neutral-point clamped (ANPC) converter [55].

The NPC is formed of four series connected semiconductor switches (S1–4) each with

an antiparallel diode (D1–4) and two additional diodes (D5-6) arranged as shown in

Figure 2.4. A neutral point, assumed to be at zero-voltage, is formed at the midpoint

between two series connected DC link capacitors and the current path taken for zero-

voltage state is determined by the current polarity, which during normal operation

leads to uneven losses in the semiconductors [31]. The ANPC is formed by merging D5

and D6 with S5 and S6, highlighted red in Figure 2.4. This allows for other zero-voltage

state paths to be formed by controlled switching, spreading the losses more evenly

[31]. The graph of AC voltage terminal output is given in Figure 2.4.


34

The operation of the ANPC is broadly comparable to a TLC in that the AC terminal can

be connected to the positive DC terminal by turning on the top two switches, S1 and

S2 (mode a) and to the negative DC terminal by turning on the lower two switches, S3

and S4 (mode c). However, in addition to these two states the AC terminal can be

connected to the DC neutral point by turning on S2 and S5 (mode b) or S3 and S6,

(mode d). The current polarity determines whether the diodes or the switches are

conducting in all operation modes, similar to Figure 2.2 for the TLC [56].

PWM can also be applied to the ANPC to realise an AC waveform. One method to

achieve this is described in Figure 2.5. In this case two carriers are used to create three

states. Each state can be assigned to an operation mode which matches the waveform

presented. During the positive half cycle the converter switches between the positive

DC terminal and the DC neutral point. During the negative half cycle the converter

switches between the negative DC terminal and the DC neutral point.

In addition to measuring individual harmonic frequencies in a signal, there is an

average measure of harmonic content called the total harmonic distortion (THD). THD

is a ratio (often expressed as a percentage) calculated by square rooting the sum of the

squares of all individual harmonic voltage components and dividing by the

fundamental voltage. A smaller THD percentage indicates a better signal quality and

reduced harmonic content.

Figure 2.4: Single-phase three-level active neutral-point clamped voltage-source converter

D1

D2

Vdc/2

S1

S2

Single Phase

D3

D4Vac

S3

S4

A

Vdc/2

D5

D6

S5

S6

N

Vo

ltag

e -

Vac

+Vdc2

-Vdc2

Time

a

b

c

d

a


35

A basic analysis of the output waveforms in Figure 2.3 and Figure 2.5 conducted using

MATLAB gives THD values of around 99% (~1:1) and 52% (~1:2) respectively, indicating

a significant improvement in power quality with a 3LC in comparison to a TLC. A five-

level converter with the same carrier frequency brings the THD down to 27% (~1:4).

These results show that increasing the number of levels reduces the harmonic content

in the AC waveform [24]; by splitting the DC link with increasing numbers of series

connected capacitors, additional voltage levels can be realised in the ANPC converter.

However, the increased numbers of components and considerable hardware

complexity is not cost-effective at higher power levels [31]. The 2002 Murraylink

ANPC-3LC had a switching frequency of 1350 Hz (27 x ) with 98.2% efficiency [53].

The third generation of HVDC Light returned to the TLC with an improved modulation

technique called optimum pulse-width modulation (OPWM). This strategy enabled

selective harmonic elimination, reduced switching frequencies and improved transient

control capability, therefore increasing efficiency and system economy [57]. The 2006

Estlink TLC with OPWM had a switching frequency of 1050 Hz (21 x ) operating at

98.6% efficiency [42, 53, 58].

Figure 2.5: Pulse-width modulation technique for a single-phase three-level converter


36

The comparable efficiency figure for an LCC HVDC scheme is close to 99.3% including

valve, filter and converter transformer losses [39, 59, 60]. ABB’s Changji-Guquan Ultra-

HVDC link due to be commissioned in 2019 is capable of transporting 12,000 MW of

power, making it the world’s largest LCC link [41]. The difference of 0.7% efficiency

equates to a maximum additional loss of 84 MW on this link. At the UK wholesale price

of £56.70 per MWh (average of last three quarters in 2018) [61] an 84 MW loss

corresponds to a cost of nearly £41 million per year. Efficiency is crucial to delivering

cost effective solutions and while the benefits of VSC technology extend beyond purely

commercial aspects, money plays a significant role in the attractiveness of a

technology.

Cascaded multilevel converter (CMC) topologies such as the fourth generation of HVDC

light, the cascaded two level converter (CTLC) [41], and Siemens’ HVDC PLUS MMC [62]

offer innovative solutions for VSC-HVDC applications, operating at switching

frequencies around 150 Hz (3 x ) and efficiency ratings close to 99% [31, 39].

Figure 2.6 is a graph of HVDC converter losses against time for HVDC Light [39]. The

efficiency gap between VSCs and LCCs is narrowing, indicating steady technological

improvement. There is space in the market for both technologies, as LCCs are favoured

for cost, reliability and power transmission capacity while VSCs are favoured for

controllability, physical size and weak grid support [63].

Figure 2.6: HVDC converter losses since 1990

Loss

es

Year

3%

2%

1%

1990 2000 2010 2020

0%

1st Gen

2nd Gen

3rd Gen

4th Gen

VSC HVDC

LCC HVDC


37

2.2. Modular Multilevel Converter Concept

While Marquardt brought the MMC topology to the attention of the HVDC community

in 2003 [44], the ancestor to the design, the ‘cascaded multilevel inverter’, was initially

proposed for static VAr compensation applications by Peng in 1995 [64, 65]. This

earlier design made use of independent DC sources on each sub-module, rather than

capacitors, which rendered the design unsuitable for high voltage applications. The

MMC for high voltage applications proposed by Marquardt will be explained further in

this section and is the main topology discussed in this thesis. For a description of the

alternate-arm converter and cascaded two-level converter see Appendix A.

Figure 2.7: Modular multilevel converter overview diagram

Vdc

Idc

SM1

SM2

SM3

SMN

SMN

SM3

SM2

SM1

Larm

Larm

SM1

SM2

SM3

SMN

SMN

SM3

SM2

SM1

Larm

Larm

SM1

SM2

SM3

SMN

SMN

SM3

SM2

SM1

Larm

Larm

Va Vb Vc

Arm Phase/Leg

Icu

a

Ibu

a

Iau

a

Icla

Ibla

Iala

IaccIacbIaca


38

A basic structure for a three-phase MMC is shown in Figure 2.7. A converter phase,

also known as a converter leg, is split into two arms with N series connected SMs and a

reactor ( ). Additional phases can be connected in parallel across the DC link. AC

outputs are taken at the midpoint of each phase e.g. phase-to-ground voltages ,

and in Figure 2.7. The basic SM design is a TLC equipped with a DC energy storage

capacitor; this is the half-bridge (HB) topology and is depicted in Figure 2.8 [44].

Similarly to a TLC the HB-SM comprises two series connected semiconductor switches

(S1, S2) each with an antiparallel diode (D1, D2). A capacitor ( ), is connected in

parallel with the switches and acts as an energy storage device. The voltage across

( ), is determined by the stored charge in the capacitor. The SM voltage ( ),

between point A and B on Figure 2.8 can then take two voltage levels; either zero

(bypass), by turning S1 off and S2 on, or (connect), by turning S1 on and S2 off

(neglecting conduction losses). When connected, the capacitor is either charging or

discharging depending on arm current polarity [44].

Unlike two and three-level converters the MMC does not require dedicated capacitors

on the DC network to supress voltage fluctuations; instead, the SM capacitors and DC

cable capacitance provide a similar functionality [56]. Typically SMs also have

integrated circuit protection such as mechanical and electrical bypass switches in

parallel with S2, to disconnect the SM from the arm during a fault [31].

In Figures 2.7 and 2.8, terminal A in SM1 connects to terminal B of SM2, terminal A of

SM2 to terminal B in SM3 and so on, creating a series connected string of SMs which

makes up the arm. By connecting, or bypassing the SMs, the voltage across each arm

can be controlled. This is the basic premise of MMC operation.

Figure 2.8: Half-bridge sub-module overview diagram

D1

D2

Iarm

Vsm

S1

S2

CsmA Vcap

B


39

To analyse this behaviour more closely an ideal equivalent circuit diagram of a single-

phase of the MMC is shown in Figure 2.9. In this diagram and represent the

controllable upper and lower arm voltages respectively. The DC voltage ( ), has been

split equally to create a neutral point. The AC voltage ( ), is taken with respect to

that neutral. is the combined resistance of all conducting elements in each arm.

Figure 2.9: Modular multilevel converter equivalent diagram

By applying Kirchhoff’s voltage law (KVL) to Figure 2.9, Equation 2.1 (left loop) and

Equation 2.2 (right loop) can be derived.

2

dc uaac ua ua arm arm

V dIV V I R L

dt 2.1

2

dc laac la la arm arm

V dIV V I R L

dt 2.2

The upper and lower arm currents, and respectively, are made up of three main

components:

- , a DC component from the DC network split equally across the phases

- , an AC component from the AC network split equally between the arms in

each phase

- , a double frequency AC component created by voltage imbalance between

each phase

Vdc/2

Vdc/2

Larm

Rarm

Larm

Rarm

Vla

Ila

SMN SM3 SM2 SM1

Vua

Iua

Vac

Iac


40

We will take the ideal case for this analysis and assume that all phases are balanced,

removing from the arm currents. This is further explained in Section 2.4. From

Figures 2.6 and 2.8 the upper arm current can be expressed by Equation 2.3 and the

lower arm current by Equation 2.4.

2 3

ac dcua

I II 2.3

2 3

ac dcla

I II 2.4

Combining Equations 2.1 – 2.4 and solving for creates Equation 2.5, which relates

the AC phase voltage to the controllable upper and lower arm voltages and losses.

2 2 2

la ua ac ac armac arm

V V I dI LV R

dt

2.5

In general the voltage drop across the resistance and inductance is much smaller than

the voltage in the two arms; therefore Equation 2.5 can be approximated to Equation

2.6. This represents a main control equation for the MMC.

2

la uaac

V VV

2.6

At any one point half of the SMs in a phase are connected across the DC link, this leads

to Equation 2.7, where N is the total number of SMs in an arm and is the ideal

nominal voltage of each SM capacitor.

* dccap

VV

N 2.7

In reality, capacitor voltages fluctuate during the AC cycle and require active balancing;

this is further explained in Section 2.4. The arm voltages in Equation 2.6 are

determined by the sum of SMs capacitor voltages connected in the string. Assuming all

SM capacitors are charged to the nominal voltage, Equations 2.8 – 2.10 can be used to

calculate AC terminal voltage outputs.

ua ua capV N V 2.8

la la capV N V 2.9

ua laN N N 2.10


41

A single-phase five-level MMC is used as an example to further describe these

principles. Five operation modes, a – e, are shown in Figure 2.10. The lower graphs in

Figure 2.10 are plots of the AC terminal voltage, upper arm voltage and lower arm

voltage for the different operation modes. If a SM is highlighted green it is connected

to the string, conversely if pink, the SM is bypassed.

By applying the equations in the previous page to each mode, the voltage output can

be calculated. The work-through for mode b is provided as an example:

*

4

dc dccap

V VV

N

3

4

dcua ua cap

VV N V

4

dcla la cap

VV N V

2 4

la ua dcac

V V VV

Other than the maximum and minimum voltage output, all other levels can be created

by selecting any matching arrangement of SMs that satisfy Equations 2.8 – 2.10. This

operation principle applies to MMCs with an arbitrary number of SMs.

Commutating from mode a to mode e creates a staircase waveform at the AC terminal.

The number of discrete phase-to-ground voltage levels within the staircase waveform

output of an MMC is equal to the number of SMs in a single arm plus one ( ) [31].

N is influenced primarily by the chosen DC link voltage and the maximum available

switch ratings [56]. For MMCs, IGBT voltage ratings of 3.3 kV and 4.5 kV are most

common, suitable for operational voltage ratings up to 2 kV and 3 kV respectively [31,

66]. DC link voltages of ±320 kV and above are typical in HVDC networks [36, 41, 62],

requiring hundreds of IGBTs to spread the voltage stress to suitable levels [67].

The INELFE link between France and Spain is one of the world’s highest-power MMC

VSC-HVDC connections, employing two independent 1,000 MW links, operating at

±320 kV. At this voltage rating, 400 SMs per arm are used to bring the nominal SM

voltage down to 1.6 kV [68]. A staircase waveform with 401 levels is almost

indistinguishable from a pure sinusoid, removing the need for harmonic filters [56].


42

Figure 2.10: Operation modes for a single-phase five-level modular multilevel converter

SM1

SM2

SM3

SM3

SM2

SM1

VacVla

Vac

+Vdc2

-Vdc2

Time

a

SM4

SM4

VuaVdc/2

Vdc/2

SM1

SM2

SM3

SM3

SM2

SM1

VacVla

SM4

SM4

Vua

SM1

SM2

SM3

SM3

SM2

SM1

VacVla

SM4

SM4

Vua

SM1

SM2

SM3

SM3

SM2

SM1

VacVla

SM4

SM4

Vua

SM1

SM2

SM3

SM3

SM2

SM1

VacVla

SM4

SM4

Vua

b c

d e

D1

D2Zero

S1

S2

CsmA

B

D1

D2

S1

S2

CsmA

Vcap

B

c

b

a

d

e

d

c

b

a

Vu

a

+Vdc

0Time

cb

a

de

dc

ba

Vla

+Vdc

0Time

cb

a

de

dc

ba

Connected

Bypassed

Vcap


43

2.3. Sub-Module Configuration

The SM is a fundamental building block of the MMC. The choice of SM design impacts

converter application, efficiency, functionality and protection. Extensive research into

SM design has led to a number of different configurations, each with benefits and

weaknesses depending on the application. A description of a few of these alternatives

and their suggested uses will be presented in this section. However, for more detailed

reviews of SM configurations see [31] and [69].

The half-bridge SM was briefly described in Section 2.2, and depicted in Figure 2.8. It is

currently the dominant choice for MMC VSC-HVDC applications as it has the lowest

cost and lowest operational losses among all the configurations [31, 70].

Table 2.1 describes the switch patterns for control of this SM. In this table, and

subsequent tables, ‘1’ represents a closed switch and ‘0’ represents an open switch

and the normal operation modes have been highlighted in grey. When both switches

are open, the SM is freewheeling so the output is determined by the arm current; this

state may be used during start-up and charging procedures, but would not be used

during normal operation. At no point should both switches be closed as this would

cause a short circuit across the SM capacitor leading to damaging fault currents. During

normal operation only one switch or diode will be conducting at any one time and,

similarly to the TLC, a dead-time is given between one switch opening and the other

closing to reduce the likelihood of short circuiting the SM capacitor.

Arm Current Switch 1 Switch 2 Vsm Csm

0armI

0 0 Charge

0 1 0 Stable

1 0 Charge

0armI

0 0 0 Stable

1 1 0 Stable

1 0 Discharge

armI x 1 1 Fault Short-Circuit

Discharge

Table 2.1: Switch modes for half-bridge sub-module configuration


44

Cascaded-cell converters such as the one proposed for static VAr compensation make

use of a full-bridge (FB) SM configuration [64, 71] as shown in Figure 2.11. The addition

of two switches (S3 and S4) with anti-parallel diodes (D3 and D4), enable the SM to

produce more than two outputs, in this case zero, or . During normal

operation the FB-SM would only be used to output zero or . The switch patterns to

achieve this can be seen in Table 2.2. In this configuration two switches or diodes will

be conducting at any one time leading to increased losses in comparison to the HB-SM

[31, 70]. Additional devices also increase the cost of construction. The switch modes

with only one switch closed have been omitted from this table, and subsequent tables,

as this would imply an uncontrolled freewheeling state across the anti-parallel diodes.

Figure 2.11: Full-bridge sub-module overview diagram

Arm Current Switch 1 Switch 2 Switch 3 Switch 4 Vsm Csm

0armI

0 0 0 0 Charge

0 1 0 1 0 Stable

0 1 1 0 Discharge

1 0 0 1 Charge

1 0 1 0 0 Stable

0armI

0 0 0 0 Charge

0 1 0 1 0 Stable

0 1 1 0 Charge

1 0 0 1 Discharge

1 0 1 0 0 Stable

armI x 1 1 X X

Fault Short-Circuit

Discharge X X 1 1

Table 2.2: Switch modes for full-bridge sub-module configuration

D1

D2

Iarm

Vsm

S1

S2

CsmA Vcap

D3

D4

S3

S4

C


45

Despite the increase in cost and losses, the FB-SM provides one major advantage over

the HB-SM and this is DC fault blocking capability [72]. Figure 2.12 shows the

behaviour of a single-phase HB and FB-SM MMC during a DC-side short-circuit fault.

Only one SM per arm is necessary to describe the combined freewheeling behaviour of

multiple SMs. The HB-SM MMC behaves as a rectifier using the series connected stack

of D2 diodes. A large fault current, driven by the AC network voltage, flows through

the upper arm during the positive AC cycle (red path) and the lower arm during the

negative AC cycle (green path). Whereas with the FB-SM, the freewheeling path

connects the SM capacitor in reverse through D3 and D2, imposing across the

SM terminals. Equation 2.7 indicates that the combined total voltage of SMs in an arm

is equal to the DC voltage. The peak AC voltage is typically less than half of the DC

voltage and can therefore be comfortably countered by the converter.

The chance of a transient DC fault occurring on cable systems, such as offshore wind

farms, is very low [73]. During more serious faults, the AC-side circuit breakers would

be tripped to allow for the DC network to be repaired; HB-SM designs are considered

to be adequate for these applications. In overhead line systems the chance of a

transient fault occurring is much higher, therefore the FB-SM topology is justified [74].

Figure 2.12: Freewheeling DC short-circuit fault topology for HB and FB-SM MMC

D1

D2

S1

S2

Csm Vcap

D1

D2

S1

S2

Csm Vcap

Va

Vdc

If

Va

Vdc

D1

D2

S1

S2

CsmVcap

D3

D4

S3

S4

D1

D2

S1

S2

CsmVcap

D3

D4

S3

S4

Half-Bridge SM Full-Bridge SM


46

As discussed in Section 2.1, the efficiency of a converter is of paramount importance to

converter design. Increased conduction and switching in the FB-SM due to S3 and S4,

lead to an increase in losses by around 70 – 80% in comparison to the HB-SM [70, 75].

In an effort to mitigate this reduction in efficiency, while maintaining a level of DC fault

protection, the hybrid-MMC was proposed [75]. This system combines HB-SMs and FB-

SMs in each arm of the MMC, balancing functionality and efficiency, but increasing

mechanical complexity. At least half of the SMs in an arm should be FB configuration

to control current during DC faults [76] and through control system design, the HB-SMs

can be utilised at a higher rate than the FB-SMs to limit the increase in losses to nearer

30% [75].

Some configurations seek to enable DC fault blocking capability while reducing the

losses in comparison to FB-SMs. One such topology is the clamped double (CD) SM

[77], which is formed by combining two HB-SMs in an arrangement as in Figure 2.13.

During normal operation of the CD-SM, D6 and D7 are blocking and S5 is closed,

creating a series connection between the two HB-SMs. The behaviour of the CD-SM

then follows the switch patterns in Table 2.3. During a DC fault all switches are

opened, leaving the SM in a freewheeling state. The current path taken depends on

the arm current direction. If the current is positive, the route through D1, D5 and D4 is

taken, connecting both capacitors in series in the circuit. When the current is negative,

two paths are available. One route is through D3, D6 and D2, the other is through D3,

D7 and D2. Theoretically the current splits equally between the two paths, connecting

the capacitors in parallel [69, 77].

Figure 2.13: Clamped double sub-module overview diagram

D1

D2

Iarm

Vsm

S1

S2

CsmiA

D3

D4

S3

S4

CCsmiiD5S5

VcapiiVcapi

D7

D6


47

The losses of the CD-SM are approximately 35% higher than the HB-SM due to

continuous conduction in S5 [31, 70]. However, with the CD configuration, each SM in

the arm is identical, simplifying the mechanical design in comparison to the hybrid

topology consisting of a mix of FB and HB-SMs.

While progress has been made to incorporate dc-fault blocking into SM design with

high efficiency, other researchers have focussed their attention on increasing the

number of levels a SM can produce. Many three-level SM topologies are derivations of

the MMC predecessors described in Section 2.1, including SM variations of the NPC

converter and the flying capacitor converter, described by Solas [78, 79]. Others, such

as the T-type topology proposed by Sahoo [80, 81], depicted in Figure 2.14 and

described by Table 2.4, are adaptations of HB-SMs.

In the T-Type SM, the output can take three voltage levels: 0, or

with reduced losses in comparison to two HB-SMs, the CD-SM or other three-

level configurations [80]. However, by considering Figure 2.13 and Table 2.4 it is clear

that in order to charge or discharge , must also be connected. Balancing

sub-module capacitor voltages is a key issue in MMC control, the T-Type SM adds

Arm Current Switch 1 Switch 2 Switch 3 Switch 4 Vsm Csm

0armI

0 0 0 0 Charge

0 1 0 1 Charge (ii)

0 1 1 0 0 Stable

1 0 0 1 Charge

1 0 1 0 Charge (i)

0armI

0 0 0 0 0 Stable

0 1 0 1 Discharge (ii)

0 1 1 0 0 Stable

1 0 0 1 Discharge

1 0 1 0 Discharge (i)

armI x 1 1 X X

Fault Short-Circuit

Discharge X X 1 1

Table 2.3: Switch modes for clamped double sub-module configuration


48

complication to an already challenging task without significant benefits [31, 56].

Capacitor balancing control is covered in more detail in the following section.

The choice of which SM topology to use in an MMC is down to a balance of cost,

losses, functionality (such as DC-fault blocking) and physical volume. The SM capacitor

takes up around half the size of a commercial SM design and therefore topologies

which reduce the required capacitance are also being investigated [31].

While some of the designs presented in this section may have potential applications,

very few can compare to the low cost, high efficiency and simple physical design of the

HB-SM. For this reason nearly all MMC vendors currently offer an HB-SM based

solution [31, 69].

Arm Current Switch 1 Switch 2 Switch 3 & 4 Vsm Csm

0armI

0 0 0 Charge

0 0 1 Charge (ii)

0 1 0 0 Stable

1 0 0 Charge

0armI

0 0 0 0 Stable

0 0 1 Discharge (ii)

0 1 0 0 Stable

1 0 0 Discharge

armI x

X 1 1

Fault Short-Circuit

Discharge 1 X 1

1 1 X

Table 2.4: Switch modes for T-type sub-module configuration

Figure 2.14: T-type sub-module overview diagram

D1

D2

Iarm

Vsm

S1

S2

Csmi

A

Vcapi

B

D4

S4

Csmii

D3

S3Vcapii


49

2.4. System Control

The MMC has multiple levels of cascaded control from multi-terminal system

behaviour down to semiconductor switching. This enables the control of hundreds of

independently fired switches within the converter, while maintaining desired

behaviour on the AC and DC networks. The control system chosen depends on the

application requirements. Figure 2.15 represents a classic nested control loop

structure for an MMC connected to an active network.

When a VSC-HVDC system is used to connect an offshore wind farm to an active

network, the onshore converter typically controls the DC link voltage, and the reactive

power fed into the main grid. The offshore converter controls the AC voltage, and

frequency of the wind farm network. This constitutes the power loop (purple) as these

parameters are controlled by varying the real (P) and reactive (Q) power output of the

converters. Set-points for these control parameters can be chosen by an operator

directly or by another control loop, such as in a multi-terminal scheme.

The real and reactive power flow between two AC sources is determined by the AC

voltage magnitude and angle difference between both ends. Therefore the power set-

points can be converted into a reference voltage magnitude and angle and fed straight

into the voltage loop (green). This is called direct control (not shown in Figure 2.15).

This type of control, while simplest in implementation is limited in bandwidth by

various AC resonance frequencies and does not have current limit capability [82]. An

alternative form of control, as depicted in Figure 2.15, makes use of a current loop

(blue) between the power and voltage loops to manipulate the ac current in a dq

rotating reference frame, this is called vector control. The final stage, referred to as

voltage control, represents the inner MMC control systems which translate the AC

voltage references into switch control outputs, in order to generate the desired

converter voltage. This section will provide an overview of each control loop.

Figure 2.15: Generic converter control structure

MMC PlantLocal

NetworkControllerController

Power Current

Voltage

Idq* Vac* Vac Idq

Vdc* Q* Vac* f*

P, QΣ Σ


50

Figure 2.16: Converter inner voltage control structure

Consider a single-phase network as in Figure 2.16. is the AC output at phase A of

the converter, is the network voltage at the converter point of common coupling

(PCC). Z is the impedance between the terminal and the PCC, which includes the arm

and, where used, transformer resistance and inductance. Equation 2.11 can be derived

using KVL for phase A.

acaaca na za aca

dIV V V RI L

dt 2.11

The equation for the three phases can then be expressed in Equation 2.12. The

derivative function has been replaced by the operator p.

( )

za aca

zb acb

zc acc

V I

V R Lp I

V I

2.12

By applying the power-invariant Clarke transformation, described in Equation 2.13, to

Equation 2.12 we can switch reference frame from the abc to the αβ0 domain. Then

assuming the three-phase system is balanced, and by applying the sine-based Park

transformation, depicted in Equation 2.14, to the resulting equation, the reference

frame is changed again from αβ0 to dq respectively. For a full derivation of the abc to

dq transformation see [83].

Vaca Vna

LR

Iaca

Z

PCC

1 11

2 2

2 3 30

3 2 20

1 1 1

2 2 2

a

b

c

2.13

sin( ) cos( )

cos( ) sin( )

d

q

2.14


51

Equation 2.12 can then be expressed in the rotating dq synchronous reference frame

as in Equation 2.15.

0 1

1 0

d d d d

q q q q

V I I IR Lp L

V I I I

2.15

Applying the Laplace transformation, with zero initial conditions, to Equation 2.15,

results in Equation 2.16 and Equation 2.17.

As the rotational speed ω and the dq currents and can be measured, the cross

coupling terms of and can removed through feed-back nulling;

solving the resulting equations for and then leads to Equations 2.18 and 2.19.

( ) ( )( )cd nd

d

V s V sI s

Ls R

2.18

( ) ( )( )

cq nq

q

V s V sI s

Ls R

2.19

Equations 2.18 and 2.19 can be represented by the decoupled state-block diagrams in

Figure 2.17; symbolising the MMC current control loop. The (s) notation has been

removed for simplicity. Feed-forward nulling [84] can be used to eliminate the network

disturbance voltages and as shown. In addition, a proportional – integral (PI)

feedback controller is used to control the dq currents. For a derivation of PI gain tuning

equations for a similar scenario see [56].

( ) ( ) ( ) ( ) ( )cd nd d d qV s V s RI s LsI s LI s 2.16

( ) ( ) ( ) ( ) ( )cq nq q q dV s V s RI s LsI s LI s 2.17

Figure 2.17: State-block diagrams for dq current control

MMC=1PI

VoltageId* Vcd* Vcd Id

Σ Σ

Vnd

1Ls+R

Σ

Vnd

MMC=1PI

VoltageIq* Vcq* Vcq Iq

Σ Σ

Vnq

1Ls+R

Σ

Vnq


52

In Figure 2.17 the voltage control loop is represented as a unity gain block. This

assumption is only valid if the output is accurate and the bandwidth at which the

voltage loop operates is significantly higher than the current control loop; a key area of

interest for this research. In order to accurately study system behaviour and decouple

interactions between controllers in a cascaded control system, each loop should be at

least four to ten times quicker than the encompassing layer [85]. The power control

loop can be built around the current control loop using Equation 2.20 and Equation

2.21 [56, 83], which relate the real and reactive power transmitted to the dq-axis

currents.

The Clarke and Park transformations performed earlier aligned the q-axis voltage to

zero, therefore the terms containing can be neglected.

3

2nd d nq qP V I V I 2.20

3

2nq d nd qQ V I V I 2.21

The state-block diagram representing this power control can be seen in Figure 2.18. In

this case, both the current and inner voltage loops are assumed to be unity gain blocks.

For details on other outer loop control schemes see [31, 56].

For stability in the state-block diagram depicted in Figure 2.18, PI gains in the q-axis

loop should be negative.

Figure 2.18: State-block diagrams for power control

MMC=1=1PI

CurrentVoltage

Id* IdP* Σ 3Vnd2

P

MMC=1=1PI

CurrentVoltage

Iq* IqQ* Σ 3Vnd2

Q


53

The voltage control loop comprises the internal control systems of the MMC. It is made

up of four main controllers as depicted in Figure 2.19; the circulating current

suppression controller (CCSC), decoder, nearest level controller (NLC) and capacitor

balancing controller (CBC). These internal control systems and their supplementary

control blocks will be described in more detail in the following section.

Circulating Current Suppression Controller

In Section 2.2 it was assumed that all phases in the MMC were energy balanced,

removing from the upper and lower arm currents in each phase. However, in

reality, uneven charging of SM capacitors and hardware nonlinearities lead to different

energies stored in the upper and lower arms of each phase, which result in different

voltages across each phase. This voltage imbalance causes current to circulate within

the converter, increasing electrical losses and wear on system components [86, 87].

Figure 2.20: Modular multilevel converter three-phase equivalent diagram

Figure 2.20 is a simplified three-phase equivalent diagram for the MMC. The

equivalent upper and lower arm voltages in each phase are adjustable therefore this

imbalance can be reduced using a circulating current suppression controller.

Vdc/2 Vdc/2

Larm RarmLarmRarm

VlaIla

VuaIua

Vac

IacIdc

VblaVbua

VclaVcua

Icirc

Figure 2.19: Converter inner voltage control structure

CCSC CBC

NLCDecoder MMC=1Vdq* VdqFS

Vdif* [Vsm]Icirc*

ω, Idif Vsm, Iarm


54

Equation 2.3 and Equation 2.4 from Section 2.2 can be rewritten as Equation 2.22 and

Equation 2.23 respectively to include the circulating current terms.

2 3

ac dcua circ

I II I 2.22

2 3

ac dcla circ

I II I 2.23

Combining Equations 2.1, 2.2, 2.22 and 2.23 and solving for gives Equation 2.24.

The derivative function has been replaced by the operator p.

2

3

dcdc ua la circ arm arm

IV V V I R pL

2.24

The combination of and is referred to as the difference current ( ) which

from Figure 2.22 can be expressed as Equation 2.25.

2 3

ua la dccirc diff

I I II I

2.25

The losses associated with this current are called the difference voltage ( )

therefore Equation 2.24 can be rewritten and simplified to Equation 2.26.

2 2

dc ua ladiff diff arm arm

V V VV I R pL

2.26

If the circulating current is zero then the voltage drop in the phase is determined by

the DC current through , which should be small. Therefore by reducing , the

circulating current can be supressed. The right-hand side of Equation 2.26 rewritten for

the three phases can then be expressed by Equation 2.27.

( )

diff a diff a

diff b arm arm diff b

diff c diff c

V I

V R L p I

V I

2.27

Equation 2.27 is similar in form to Equation 2.12 for the current control and the same

transformation is therefore applied to change from the abc to dq reference frame,

noting that has been replaced by , as has no impact on the dq values. In

this case the circulating current is a negative sequence double frequency component

[31, 86].


55

Equation 2.28 represents the dq difference voltage equation.

0 12

1 0

diff d circ d circ d circ d

arm arm

diff q circ q circ q circ q

V I I IR L p L

V I I I

2.28

The Laplace transform can then be applied to Equation 2.28, with feed-back nulling to

eliminate the cross-coupled terms, to create the state-block diagram for the d-axis

shown in Figure 2.21. The same system is used for the q-axis variables. The references

and

are set to zero, as the control system is designed to supress the

circulating currents. L and R represent the arm inductance and resistance respectively.

Decoder

The decoder exists to covert the reference inputs from the current controller and CCSC

into usable references for the NLC before translation into firing signals (FS). The core

function of this block is to satisfy the simultaneous equations for the upper and lower

arm voltages as a function of AC voltage and DC voltage as in Equation 2.29 and

Equation 2.30, derived from Equation 2.6 and Equation 2.24 respectively.

2la ua acV V V 2.29

2la ua dc diffV V V V 2.30

In Equation 2.29 and Equation 2.30, is the phase reference voltage set by the

current controller, is the difference voltage calculated by the CCSC and is the

DC voltage set point. The outputs and are the reference voltages for the upper

and lower arms fed into the NLC. This process is shown in Figure 2.22 which represents

the decoder control blocks for the MMC. Note that inputs from the CCSC and current

controller are in the dq reference frame and therefore require transforming back to

the abc reference frame using the inverse Park and Clarke transformations.

Figure 2.21: Circulating current suppression control state-block diagram (d-axis)

= 1PI

Decoder - MMCIcircd* = 0 Vdiffd* Vdiffd Icircd

Σ 1Ls+R


56

In Figure 2.22 the symbols and

are the upper and lower arm reference

voltages for phase A, B and C respectively. When the phases are balanced and the

difference voltage is zero, the outputs from the decoder are two equal, but opposite,

sinusoidal signals equivalent to the AC voltage set point offset by half the DC link

voltage.

Nearest Level Controller

The NLC is tasked with converting the sinusoidal upper and lower arm references from

the decoder into firing signals for the switches. The NLC therefore represents the

modulation block for the converter, and could be replaced by a PWM controller similar

to the two described in Section 2.1. The choice between a PWM controller and NLC is

determined primarily by harmonic requirements and the complexity of

implementation.

In order to meet the harmonic standards of a transmission network, without the use of

AC filters, an MMC using NLC would need to be able to output a minimum of 31 levels

[56]. Distribution networks are inherently more damped, reducing this requirement to

even fewer levels. For example, the 24 MW VSC demonstrator constructed by Alstom

Figure 2.22: Decoder control block diagram

Vdiff-dq*

= 1

NLC - MMC

Vabc-ua* VdqΣ

Vdq*

abcdq

Vdiff-abc*

abcdq

Vabc*

0.5

Vdc

ω

2

Vdiff-dq*

= 1

NLC - MMC

Vabc-la* VdqΣ

Vdq*

abcdq

Vdiff-abc*

abcdq

Vabc*

0.5

Vdc

ω

2

Upper Arm

Lower Arm


57

Grid (now GE Grid Solutions) required only 15 levels to connect to an 11 kV distribution

network without the need for filters [88]; PWM would reduce this even further.

As mentioned previously, the number of SMs chosen for a system is primarily

determined by the DC link voltage and switch voltage ratings, which for HVDC

applications leads to hundreds of SMs per arm. The number of carriers is proportional

to the number of levels in a PWM scheme; as a result systems with hundreds of levels

render PWM a computational challenge to implement. The simplicity of NLC

implementation makes it the favoured modulation method for industrial scale

converters [31].

Consider the nominal capacitor voltage of a SM described by Equation 2.7 in

Section 2.2 (replicated here for ease). By connecting a SM to the arm, the voltage of

the arm increases by a discrete step of . Each discrete step is referred to as a level.

The NLC block samples the upper and lower arm voltage references from the decoder

and calculates the closest discrete step to the desired voltage [31]. Equation 2.31

describes this calculation.

* dccap

VV

N 2.7(2)

*

*

ref

on

cap

VN round

V

2.31

is

or from Figure 2.22. The round function in Equation 2.31 brings

the division to the nearest integer, providing the number of SMs which need to be

connected in the arm to reach the desired voltage ( ). An example of Equation 2.31

for one arm of a 15 level MMC can be seen in Figure 2.23.

In the example shown in Figure 2.23, the MMC has a DC link voltage ±14 kV,

corresponding to a nominal capacitor voltage of 2 kV per SM. This staircase plot is

similar to the upper and lower arm graphs in Figure 2.10.

All of the SMs in the arm would then be issued turn-on or turn-off orders, with the

number set to turn-on equal to . The same applies for the remainder of the arms in

the converter, altering the AC terminal voltage while maintaining the DC link voltage.


58

Capacitor Balancing Controller

For the NLC to work effectively, and to protect the SM switches from over-voltages, all

the capacitors should ideally be balanced and be at the nominal capacitor voltage. If

this is the case, the choice of which SMs to connect would be arbitrary, most likely

following a pre-determined list which balanced the on-time and semiconductor

switching to spread use throughout the converter. However, this assumption is not

valid as the capacitors charge unevenly due to alternating current in the arms as

described by the switching modes in Tables 2.1 – 2.4. A secondary controller is

therefore used to ensure that the SMs are kept within a narrow margin of the nominal

voltage; this is called the capacitor balancing controller [44].

In order to achieve energy balancing, the capacitor voltage at each SM is measured

and placed into a list of values for each arm. These lists are then sorted in order of

magnitude. When the arm current is positive, the SMs are ordered from smallest to

largest, and subsequently the lowest voltage capacitors are first selected to be

connected. Conversely when the arm current is negative the SMs are sorted from

largest to smallest so that the highest voltage capacitors are first selected to be

connected. In the most efficient case, only one SM in each arm will be connected or

disconnected at each transition. In practice multiple SMs are switched at each

transition to maintain capacitor voltage balance throughout the MMC.

Figure 2.23: NLC round function output example


59

Sorting large lists is not a trivial task, requiring significant computational resource and

time. For the best performance, the rate at which the lists are sorted by the CBC

coincides with voltage transition orders from the NLC. For example, for a converter

with 14 SMs per arm, the output changes 28 times in a 50 Hz cycle requiring an

effective sorting frequency of 1.4 kHz. In this case the effort required to sort six lists of

14 values is low, and the time between transitions is more than adequate. When the

number of SMs per arm approaches 400, an effective frequency of 40 kHz is needed

but the computational effort required has increased significantly. Lower sorting

frequencies are chosen to mitigate this challenge, leading to worse performing

balancing control [89]. A more detailed discussion on the challenges of sorting,

including algorithm choice and implementation, is discussed in Chapter 5 and [67].

In summary, the real and reactive power set-points provided to the power controller

(Figure 2.18) lead to a dq current reference for the current controller (Figure 2.17). The

voltage references calculated by the current controller are used alongside the voltage

references from the CCSC (Figure 2.21) to provide a dq voltage to the decoder (Figure

2.22). The abc references for the upper and lower arms are calculated by the decoder

and issued to the CBC and NLC. These controllers work together to ensure that the

correct number of SMs are connected to the arm to meet the desired voltage

magnitude and angle. This produces the required output power, while maintaining

energy balance across the SM capacitors.

The control systems presented in this section provide one common method of

managing the behaviour of an MMC. For extensive discussions on additional methods

see [31, 90].

Control Structure Development

60

Control Structure Development 3.

The control of an MMC with hundreds, or potentially thousands, of sub-modules (SMs)

is not a trivial task. Due to commercial reasons, the precise details of how industry has

implemented this complicated process are not available in the public domain. The

need for hardware models to understand the behaviour of this technology is ever

growing and so a number of solutions for system control have been found by academic

institutions and discussed in the open literature. Reduced scale hardware prototypes

developed by academia have also been constructed, typically with considerably fewer

SMs and reduced power ratings. In some cases this has led to unrepresentative control

structures based on a single centralised controller.

In reality, the control of an industrial scale converter with a single centralised

controller would be infeasible due to processing speed and input/output (I/O)

requirements. A single-point of failure would also be created which has a significant

risk and cost associated with it. Industrial scale converters typically spread the

computational burden of system control across a number of different controllers in a

distributed control structure to increase processing capability and system reliability.

This chapter will discuss the differences between centralised control and distributed

control, providing examples from literature for both arrangements. The control system

architecture and hardware for the MMC prototype will then be presented.

3.1. Comparison of Centralised and Distributed Control Structure

In the context of MMCs, a centralised controller brings together the entire control

system into one device. This centralised system, referred to here as the station

controller or fully centralised control unit (FCCU), is typically made up of an integrated

combination of field programmable gate array (FPGA) or digital signal processor (DSP)

resource alongside a soft-core central processing unit (CPU). The station controller

typically also facilitates the human-to-machine interface (HMI) and development

software to enable very fast control system prototyping and deployment.

Figure 3.1 [91] presents a high-level overview diagram for a centralised control

structure. All the control tasks described in Section 2.4 are processed at the station

control level. The FCCU is therefore omniscient and performs the complete

measurement, calculation and firing cycle within the required timescales.


61

The station controller is optically or galvanically isolated from the power electronics

(PE). In some cases, low level control is delegated to SMs; this may include converter

protection, dead-time management, switch signal decoding and the analogue-to-

digital conversion of SM capacitor voltages. However, most FCCU solutions make use

of ‘dumb’ SMs and rely on the central controller to perform these duties. In these

cases, a voltage-to-frequency converter or high linearity optocoupler will transmit the

analogue SM capacitor voltage to the FCCU for digital conversion and processing.

This method of MMC control requires the FCCU to have a large quantity of digital and

analogue I/O and very powerful computational hardware. This could be something

similar to the Opal RT OP5600 used by [92, 93]. The centralised control structure is

suitable for reduced scale prototypes and simplifies the control system development

significantly in comparison to a distributed structure. Literature discussing hardware

examples using the centralised control structure include [79, 81, 94-97]. As the number

of SMs increases, the physical I/O requirements become much greater and the time

available to perform calculations reduces, placing significant computational strain on a

single processing unit. This renders the centralised structure impractical in industrial

scale MMCs and thus exhibits unrepresentative behaviour.

Figure 3.1: Centralised control structure (adapted from [91])

Valve HallSubmodule

PEPEPEPE

FPGA/DSP & CPU Station Controller and

Human Machine Interface

Server Room

Fibre-Optic/ Galvanically

Isolated Interface

Centralised Structure

x6N

FCCU


62

The control structures most frequently adopted by industry take the form of a

distributed control structure, Figure 3.2 [91]. This separates the control process into

distinct levels, each with a part to play in the overall control of the MMC. The power

electronics on each SM are now supported by a dedicated distributed control unit

(DCU), often FPGA based, creating a ‘smart’ SM.

In the most basic distributed control mode, the DCUs handle the SM capacitor voltage

measurement, switch signal control, dead-time management and local protection

mechanisms. The DCU reads and writes data across an optically isolated

communication link to the FPGA-based arm controller.

Figure 3.2: Distributed control structure (adapted from [91])

Valve HallSubmodule

Fibre-Optic Interface

PEPEPEPE

Wired/PCB Trace Interface

High Speed Wired Interface

FPGA Arm Controller x6

RT CPUStation Controller x1

Server Room

x6N

Distributed Structure (Industry)

Control Room

Ethernet Network Interface


DCU FPGA

CCU

ACU


63

The arm control unit (ACU) then manages the capacitor balancing control, nearest level

modulation and switch signal allocation. The ACU reads and writes data across a high-

speed wired interface to a real-time (RT) CPU based central control unit (CCU). Two

ACUs may be governed by, or contained within, a single phase control unit (PCU).

The CCU acts as the overall system co-ordinator and contains the decoder, circulating

current controller, dq current controller and power controller. Power set-points may

then be set by a supervisory controller or an HMI communicating with the system over

a wired local area network (or similar).

The distributed control structure parallelises vast amounts of the basic control tasks

and significantly reduces the physical I/O requirements for a single controller. The ACU

still requires substantial processing power to perform capacitor balancing control.

FPGAs offer extremely fast mathematical computation capabilities and parallel sorting

techniques, ideal for this process. Literature discussing hardware prototypes using the

most basic form of distributed control include [98-101]. This is also the method

presently used by industry [31].

The more complex form of distributed control makes use of the same structure in

Figure 3.2, but delegates more tasks to the ‘smart’ DCUs, reducing the computational

requirements on the ACU. For example, enabling the DCUs to communicate with one

another could allow for capacitor balancing and nearest level control to be performed

at the SM level; the ACUs would then only need to provide supervisory control. So far

these methods have either been tested on bespoke prototypes which do not reflect

the hardware used in industry, or are in very early stages of prototyping [102-105].

The converter constructed during this research has the capability to compare the basic

and complex distributed control methods and assess the implications of both on

system control. The following sections will describe the research control structure

chosen for the MMC hardware prototype developed during this research.

3.2. Objective and Function

The development and testing of a hardware prototype is a critical stage in the

verification and validation process of a product or system. While simulation tools are

becoming better at replicating actual behaviour, their fidelity is improved by validation

against a real system [106].


64

Simulating state-of-the-art hardware like an MMC is non-trivial. Models of varying

fidelity have been constructed to suit different simulation applications; these are

discussed further in Chapter 6. In order to condense a high fidelity model into a low

fidelity model many assumptions are made. One assumption is that the MMC internal

control is instantaneous, with zero communication delay, and can therefore be

disregarded in the simulation. So far this assumption has been based on

computationally powerful hardware in a centralised control structure, Figure 3.1,

which may not accurately reflect the behaviour of an industrial scale system [107].

A goal of this research was to design, build and test a reduced-scale converter

hardware prototype (CHP) of an MMC capable of implementing an industrially

representative distributed control structure, Figure 3.2. The industrial relevance of the

distributed control structure described has been verified through discussions with

technical experts from Siemens and GE Grid Solutions, leading manufacturers of HVDC

systems. The outputs from the hardware system have been used to investigate the

behaviour and bandwidth requirements of internal current and voltage control loops,

enabling the validation of, and improvements to, power systems models.

3.3. Converter Hardware Prototype Control Structure

In this thesis the design and construction processes for the CHP have been presented

in a logical order that the author believes will ease understanding. In reality, the

processes were intertwined. Decisions which seem unclear may have been made in

parallel with hardware development or control system development and will be

explained more thoroughly in the following chapters. The first instance of this is that

the chosen system ratings include a total of 48 sub-modules in the converter, equating

to eight per arm. This is the basis on which the CHP control structure was developed.

The control structure chosen for the CHP is based on the distributed control structure

presented in Figure 3.2. However, a few changes have been made to bring the system

within budget and to enable additional functionality for future research. Figure 3.3

shows an overview diagram for the CHP distributed control structure.

In the CHP structure the FPGA based DCU has been replaced with a system-on-chip

(SoC) based DCU, which combines the benefits of a hard micro-processor with an

FPGA. Each DCU now acts as the master to four SM slaves. This controller can behave


65

as four independent parallel partitions (to closely match Figure 3.2) or can work as a

single aggregated local control unit to investigate alternative control methods.

The CHP is made up of eight SMs per arm, requiring two DCUs per arm and therefore

twelve in total for the six arms per converter. Each DCU controls a serial peripheral

interface (SPI) to an on-board analogue-to-digital converter (ADC) on each SM for

capacitor voltage sampling. The DCUs in Figure 3.3 have a similar set of communication

channels to those in Figure 3.2, including a wired interface to the SMs and a fibre-optic

interface to the phase control unit (PCU). These are essential for the basic form of

distributed control. However, in addition, the DCUs are capable of communicating with

one another across a local area network (LAN) to explore the more complex

distributed control methods briefly discussed in Section 3.1.

Figure 3.3: CHP distributed control structure (adapted from [91])

Valve HallSubmodule

PEPEPEPE

High Speed Wired interface

FPGAPhase Controller x1

FPGA & RT CPUStation Controller x1

Server Room

Wired/PCB Trace Interface

x6N/4

Fibre-Optic Interface

Distributed Structure (Academia)

To SoC

x6N

Control Room

Ethernet Network Interface


DCU

CCU

PCU


66

Each PCU is partitioned into three sections with a total of six parallel processes,

representing all six arm controllers. The PCU handles switching control, capacitor

balancing control and acts as a master to twelve DCUs. Communication to the CCU is

facilitated by a high speed wired link. Due to hardware limitations, the nearest level

control is split between the PCU and CCU. This represents a very minor change in

control system partitioning.

The remainder of the internal control systems are processed by the CCU. As the CHP is

a research tool, the CCU has a number of additional tasks such as start-up control, data

recording and the control of auxiliary devices. Due to these additional tasks, and

limitations in computational power, the RT CPU based CCU makes use of an additional

FPGA. A different PC then runs the HMI to the CHP, allowing for control of the system

over a LAN.

The hardware solution for Figure 3.3 is summarised into the following devices:

- DCU: Terasic DE10-Nano Intel Cyclone V SoC [108], Figure 3.4

- PCU: NI PXI-7851(R) Xilinx Virtex-5 LX30 FPGA [109], Figure 3.5

- CCU-FPGA: NI PXIe-7857(R) Xilinx Kintex-7 160T FPGA [110], Figure 3.5

- CCU-RT: NI PXI-8102 Intel Celeron T3100 RT CPU [111], Figure 3.5

- Additional: NI PXIe-6363 digital acquisition (DAQ) board [112] and an NI PXIe-

1071 chassis to house the PCU, CCU and DAQ boards [113], Figure 3.5

Figure 3.4: Terasic DE10-Nano DCU


67

The DCU units, Figure 3.4, are programmed in Verilog and VHDL using the Intel Quartus

Prime interface. The National Instruments (NI) PXI system, Figure 3.5, allows for

efficient and simplified control system design on the CCU and PCU using LabVIEW

(HMI, RT and FPGA). The control system development for the CHP applied to this

control structure will be discussed further in Chapter 5.

Figure 3.6, on the following page, is an overview diagram for the communication

structure based on a hardware implementation of Figure 3.3. In Figure 3.6 the

communication interface between each device is described by the protocol, number of

parallel lines, conductor medium and link bandwidth. A brief summary of the

information passing between each controller is presented along with data flow

direction. The programming language used is listed to the right of each device group.

This communication structure describes the implementation of the basic distributed

control method on the CHP and therefore does not make use of the potential

communication link between DCUs. Future research opportunities for the CHP will be

discussed further in Chapter 8.

3.4. Summary

This chapter has compared the centralised and distributed control structures and

described the chosen distributed control structure for the converter hardware

prototype. The control hardware used to create this structure is also discussed, along

with an overview of the interfaces used to pass data between control levels.

Figure 3.5: NI PXI system, slots from left to right: CCU-RT, DAQ, PCU and CCU-FPGA


68

Figure 3.6: CHP distributed communications structure (adapted from [91])

CC

U (R

T CP

U)

PC

U

DA

Q

- System measurements- Relay control

- Set points- Reference voltages- DAQ data

DA

T

ERR

DA

T Optical Fibre5 MHz UART- State Signals- Capacitor voltages- Fault Codes

3x12D

CU

20

CLK CS

VSM S1 S2 S3 S4

SM

X4

Wired (isolated)12.5 MHz SPI/UART- Switch signals - Capacitor voltage

Verilog&

VHDL

LabVIEW RT

LabVIEWFPGA

Valve Hall

Server Room

CLK – SPI ClockCS – SPI Chip SelectVSM – SPI DataS1-4 – SM Switch SignalsDAT – 32-bit Control DataERR – Critical Error

CC

U (FP

GA

)

Wired5 MHz UART- NLC variables- Current polarity

- State machine control

Control Room

HM

I

LabVIEW UI

Wired1 Gbps Ethernet- User controls and interface

32

Wired33 MHz PCIe Bus

Ma

ster Co

ntro

ller

Hardware Development

69

Hardware Development 4.

Chapter 2 covered the theoretical basis behind the operation and control of a modular

multilevel converter (MMC). Chapter 3 then introduced the concept of centralised and

distributed control structures and the chosen structure for use on the converter

hardware prototype. The implementation of this theory in hardware and integration

with the research control structure is described in this chapter.

4.1. Objective and Function

The main purpose of the converter hardware is to demonstrate and analyse the

behaviour of an MMC controlled using a representative distributed control structure.

Studies on the internal converter dynamics consider the impact on converter

performance following changes to the control system, the introduction of

communication delays and data loss, and nonlinearities in hardware.

The converter hardware prototype (CHP) has been designed to be reconfigurable and

flexible. This enables research into a wide range of different converter topologies, sub-

module configurations and control methods. Additional functionality has been

carefully weighed against impacts to the internal structure, so as to avoid diluting the

main research theme.

4.2. System Ratings

As the focus of the research was on how limitations in hardware affected control and

communication within an MMC, rather than power level, the ratings of the CHP could

be reduced significantly. Low ratings enable control behaviour to be observed without

the cost and complexity of high power devices. The control signals to the switching

device gate drivers are the same regardless of power level therefore the choice of

power electronics hardware does not limit the scalability of this research.

The route taken to select system ratings for a reduced scale prototype is largely

arbitrary, as there are very few restrictions on component availability in the low power

range. In order to build a set of specifications for the CHP, the DC link supply was

chosen first and the remaining ratings were selected around it.

The CHP has been designed to operate in an engineering laboratory environment with

a dedicated mains supply. The DC network connecting to the CHP is represented by a


70

B and K Precision PVS60085MR programmable DC power supply. This supply has an

output power rating of 3 kW (input 3.5 kVA), suitable for connection to a single-phase

mains laboratory supply. The DC power supply provides an output voltage up to 600 V

or output current up to 8.5 A. As the behaviours of the AC and DC power systems

connected to the converter are beyond the scope of this research, the AC side is a star-

point resistive load and the DC supply was kept as a fixed DC voltage.

In Section 2.2 it was mentioned that the number of sub-modules (SMs) is primarily

determined by the DC voltage rating of the converter and the available IGBT switch

ratings. This would usually lead to hundreds of SMs per arm. In this case, the DC link

voltage is very low and therefore the number of levels can be selected based on

desired performance. Initially the CHP was designed with 16 SMs per arm, allowing for

17-level three-phase AC outputs. However, once designed, the cost of building a

system with 96 SMs proved to be outside the budget. A reconfigurable system using a

total of 48 SMs fell within budget, allowing for a 25-level single-phase and nine-level

(phase to ground) or 17-level (line-to-line) three-phase MMC to be constructed.

From Equation 2.7, with a DC link voltage of 600 V and 24 SMs per arm, the nominal

voltage rating of a SM in the single-phase setup is 25 V. The three-phase system, with

eight SMs per arm and a nominal SM voltage of 25 V, can therefore operate with a DC

link voltage of 200 V. The SMs are designed to an absolute maximum rating of 60 V.

Description Single-Phase Rating Three-Phase Rating

DC Voltage ±300 V ±100 V

AC Voltage (phase to ground RMS)

210 V 71 V

SMs/arm 24 8

No. Levels 25 (line to ground) 9 (line to ground)

17 (line to line)

SM Voltage 25 V

Apparent Power 1.8 kVA (peak), 1.0 kVA (nominal)

AC Current (per phase RMS)

8.5 A (peak), 4.7 A (nominal)

DC Current (per phase)

3.0 A (peak), 1.7 A (nominal)

Table 4.1: Converter rating specifications


71

To keep within the 8.5 A current capability of the DC power supply, it was decided that

the SMs would have a nominal operating current of 5 A and a peak rating of 9 A. The

SMs are designed to an absolute maximum rating of 15 A.

These specifications and the resulting power ratings for the CHP are provided in Table

4.1. Two power ratings are listed; a 1 kVA nominal rating and a 1.8 kVA peak rating.

The absolute maximum rating of 7.2 kVA is unachievable, as over-voltage and over-

current protection will activate at 57 V and 9 A per SM respectively, this is by design to

protect the CHP from human error and described further in the following section.

4.3. Sub-Module Design

A SM was designed based on the ratings of Table 4.1. A selection of SM configurations

was discussed in Section 2.3. It was noted that the half-bridge (HB) SM is the most

widely used configuration in industry as it has the advantage of lowest overall losses

and a simpler hardware design in comparison to the alternatives. The full-bridge (FB)

SM enables DC fault blocking capability at a cost of increased switching and conduction

losses. Other configurations, while providing efficiency improvements, added no

significant functionality to FB or hybrid (converter arms comprising HB and FB-SMs)

systems. For this reason it was decided that the CHP SM would be based on a flexible

FB configuration, enabling investigations into HB, FB and hybrid operation.

Figure 4.1 is the overview diagram of the CHP SM design. The HB configuration can be

used by disconnecting the physical jumper cable between points RSa and RSb and

series connecting the SMs via point A and B. The FB configuration can be used by

connecting the physical jumper cable and series connecting the SMs via point A and C.

A jumper cable is used, rather than a semiconductor switch to provide a clear visual

galvanic isolation between the HB and FB sides.

Figure 4.1: Converter hardware prototype sub-module topology

D1

D2

CsmA

D3

D4

C

B

RSa RSb

DR

Z1

Z2

S1

S2 S4

S3

F1


72

Core Components

In comparison to industrial systems, the ratings of the CHP SM are very low. For an

industrially sized SM designed to operate at 2 kV the forward voltage across an IGBT

(estimated at 3 V during conduction) represents a 0.15% voltage drop at the SM

terminal. For the same technology at 25 V this is a 12% voltage drop. In order to have

more representative behaviour the voltage drop across the switches must be much

smaller. Low on-resistance MOSFETs were therefore more suitable for the CHP SM

design than IGBTs, as the voltage drop could be selected based on current ratings.

While the turn-on/off characteristics of MOSFETs are different to IGBTs, the frequency

at which switching occurs and the dead-time given between switch commands is

within the capability of both technologies. In addition, the rise and fall times of SM

output are not of interest in this research and therefore the behavioural differences

can be disregarded. An N-channel MOSFET with an on resistance of 6 mΩ, current

rating of 75 A, and a drain-to-source voltage of 60 V was chosen. Internal anti-parallel

body diodes are inherent in commercial MOSFET structures. However, to ensure ample

protection, dedicated anti-parallel diodes are used. A Schottky rectifier with a current

rating of 15 A, and blocking voltage of 100 V was chosen for this task.

A bank of electrolytic capacitors with a total capacitance of 3 mF ensures that the

ripple current rating of the converter is met while ensuring the ripple voltage error is

less than ±10% of the nominal. Two ceramic 1 µF capacitors are placed in parallel with

three electrolytic 1 mF capacitors to provide improved high frequency performance.

Three additional protection mechanisms are also included on the CHP SM design:

- A quick-blow current-limiting fuse (F1) for over-current protection (OCP)

- Back-to-back zener diodes (Z1 and Z2) for over-voltage protection (OVP)

- A discharge resistor (DR) for SM capacitor discharge

Fuses require no control signals and therefore provide an OCP mechanism

independent of the control system. However, they do not break the circuit sufficiently

quickly to protect sensitive power electronic components from damage. The fuses on

the CHP-SMs are designed to work alongside the current-limitation settings of the DC

link power supply and the fast breaking controllable relays discussed in Section 4.4, to

provide a complete OCP scheme for the CHP.


73

OVP of the SM devices can be provided by setting the combined threshold of the back-

to-back zener diodes to be below the absolute maximum voltage rating of the lowest

rated component. Should the threshold voltage be exceeded during operation, the

zener diodes enter the breakdown (avalanche) region, effectively creating a short

circuit. Once the voltage is below the threshold the zener diodes very quickly return to

behaving as an open-circuit. This effectively clamps the maximum voltage to the

threshold voltage. Two zener diodes with a 56 V blocking voltage and 1.2 V forward

voltage provide a 57.2 V avalanche breakdown rating with 5 W power dissipation.

A discharge resistor in each SM, parallel to the capacitor bank, allows the capacitors to

discharge to safe voltage levels before mechanical work or inspections are carried out.

The DR does not noticeably impact the system during normal operation. A 47 kΩ

resistor has been chosen, providing a 10 minute discharge window. Additionally, the

DC link power supply has a bleed resistor of approximately 250 Ω in parallel with the

output terminals. If the supply is turned off and the SMs are still connected and in the

output state, the bleed resistor offers a faster alternative discharge path.

Industrial SM designs typically include a hardware bypass switch and thyristor in

parallel with S2 to mechanically disconnect the SM from the circuit and to protect the

SM from DC side faults respectively [56]. The MOSFETs chosen for the CHP SM are

capable of handling fault currents, removing the need for the thyristor. The hardware

design of the CHP allows for SMs to be physically bypassed by rearranging connectors.

The main devices have been summarised in Table 4.2.

Component Part Name Main Ratings Notes

S1 – S4 N-Channel MOSFET

60V, 75A, 6mΩ Overrated for current to

remove protection thyristor

D1 – D4 Schottky Rectifier

100V, 15A (150A peak) Provides dedicated path in

addition to body diode

Z1 – Z2 Zener Diode

56V, 5W (180W peak) Two devices back-to-back for

57.2V avalanche

Csm Electrolytic

Capacitor Bank 63V, 3mF

Three 1mF electrolytic and two 1uF ceramic in parallel

DR Resistor 47kΩ 10 minute discharge

Table 4.2: Main component choices and ratings


74

All of the devices chosen for the core components shown in Figure 4.1 and listed in

Table 4.2 meet the desired converter ratings. For calculations behind device choice and

rating in the CHP see Appendix B. For a list of the main components and the specific

manufacturer part numbers see Appendix C.

The core components depicted in Figure 4.1 and listed in Table 4.2 require additional

supporting circuitry in order to function. Figure 4.2 provides an overview diagram for

the CHP SM and the main supporting components. In Figure 4.2 the core topology

from Figure 4.1 has been reduced to the components of interest for control. This is in

the green shaded area labelled ‘CHP SM Core’. The following sections will explain the

need for the additional components and details of the chosen devices.

Control, Measurement and Communication

In Section 2.4 the capacitor balancing controller was described. This type of CBC

requires a capacitor voltage measurement from each SM in order to maintain balance

between SMs. One of the simplest and cost effective solutions for accurate

measurement is built around an ADC. A 10-bit, 1 mega-sample per second (MSps) ADC

Figure 4.2: Converter hardware prototype sub-module overview

CsmA C

B

S2

S4

S3

CHP SM Core

Switch SignalsS1 – S4 SolidFloating Dashed

ADC SignalsCLK, CS, Data SolidFloating Dashed

Power5V Solid5V Floating Dashed

Power24V Solid15V Floating Dashed

CHP SMGD3

Sallen-K

eyADC

DC DC

DC DC

DC DCA

B

C

OP1

S1

CLK

CS

Data

5V

24V

24V

24V

24V

S1

S2

S3

S4

GD1

GD2

GD4

OP2

OP3

DC DCB5

Key

Floating Digital Region

Control Isolated Region

Floating Analogue Region


75

was chosen, with an input from the SM capacitor scaled and filtered by a second order

Sallen-Key filter with a 3 dB cut off frequency of 19.3 kHz. This circuit provides just over

0.03 V per bit resolution over the full 30 V scale. A 20% margin on the nominal 25 V SM

voltage allows for at least double the calculated capacitor voltage ripple to occur

within the measurement window at the maximum rated operational voltage. Two

additional measurement circuits of the same design are available on the SM for future

research.

SMs in an MMC are connected in series and subsequently the voltage with respect to

ground on each SM is determined by the sum of capacitor voltages connected below it.

This varies in real-time as SMs are connected and disconnected from the circuit during

modulation; therefore each SM is taken to be floating at a voltage anywhere between

0 and 600 V determined by the DC link supply. Digital optical isolation provides the

galvanic separation between the control system and the high voltage electronics. A

combination of single and dual-channel 15 mega-bit per second (Mbps) optocouplers

are used to communicate between the ADCs and main control hardware (OP1 – 3 in

Figure 4.2). Inverters are used at the optocoupler outputs to ensure the incoming

signals match the driving signals seen by the control components. The MOSFETs are

driven by optocoupler gate-drivers (GD1 – 4 on Figure 4.2). The gate drive circuit

design is provided in Appendix B. The optical isolation is rated at 3.75 kV, much higher

than any voltage anticipated in the CHP.

In Figure 4.2 the purple shaded area is the isolated region on the SM. Signals and

power supplies in this area are taken with respect to a 0 V ground. The blue and green

shaded areas are the floating regions; components in these areas are referenced to

points A, B or C, which vary in potential during switching.

Sub-Module Power Supply

In a typical industrial SM design, energy will be harvested from in order to power

the local auxiliary systems. The auxiliary systems on an industrial IGBT based SM are

estimated to require 15 W of power including gate-drivers and local control units [31].

INELFE, the 401-level MMC between France and Spain, has close to 4,800 SMs across

two converters in one 1,000 MW point-to-point link [114]. At 15 W per SM this is equal

to 72 kW of auxiliary supply requirement, less than 0.01% of the total power rating of

the link. The SM capacitors in INELFE store around 12,800 J of energy and are kept


76

within a nominal voltage range by the capacitor balancing controller thereby providing

a suitable power source for the auxiliary systems [115].

Constructing the CHP following the same principles creates some challenges. Firstly the

CHP requires an average of approximately 2 W of power for the auxiliary systems on

each SM, including the shared distributed control units discussed in Section 3.3. This

equates to around 100 W for the whole system, just over 10% of the nominal rating.

Less than 1 J of energy is stored within the CHP SM capacitor and as the auxiliary

system power requirements are high, energy harvesting from the SM capacitors

becomes a more significant factor in the converter operation. This would negatively

impact capacitor balancing control and power control response. Secondly, the start-up

and shut-down procedures for an industrial system are more complicated as the

auxiliary systems do not become operational until the capacitors are charged above a

certain threshold. This would limit the potential of the CHP as a research tool because

ideally data collection should continue during charge and discharge cycles to observe

converter performance.

For these reasons the auxiliary systems on CHP SMs and shared local control units are

powered by two independent programmable DC power supplies, a B and K Precision

BK1900B at 5 V for the local control units and a TENMA 72-2540 at 24 V for the SM

circuitry. As each SM is floating, the power is delivered via 1 kV galvanically isolated

DC/DC converters on the CHP SMs.

Four isolated DC/DC converters are required on each SM. One converter provides a 5 V

supply, with respect to point B, to the measurement and communication circuit

including the ADC, Sallen-Key filter and optocouplers (DCB5 in Figure 4.2). The

remaining three provide dedicated isolated 15 V supplies to the gate drivers of:

- S1, with respect to point A (DCA in Figure 4.2)

- S2, with respect to point C (DCC in Figure 4.2)

- S3 and S4, with respect to point B (DCB in Figure 4.2)

In addition to the devices listed in this section, over 100 passive components such as

resistors, capacitors and connectors are required to ensure full functionality. These

components will not be discussed in any further detail.


77

Sub-Module Printed Circuit Board

After selecting suitable devices for each component, a detailed schematic and printed

circuit board (PCB) design was produced using an industrial design tool, Altium

Designer. The PCB is designed to fit on the standardised Eurocard format of 100 mm x

160 mm, for easy mounting in a 3U sub-rack. A PCB layout diagram of the CHP SM V5.1

is provided in Figure 4.3. In Figure 4.3 the shaded areas correspond to the same

isolated areas shown in Figure 4.2.

Five previous iterations of SM design informed the layout and component choices. The

CHP SM V5.1 PCB design files (layout and schematic) are freely available from the

thesis supplementary online repository [49]. In summary, SM V5.1:

- Improved general digital and analogue routing for reduced cross-coupling

- Improved component layout to minimise distance and inductance loops

- Increased ground and power planes and increased isolation distances

- Reduced heat-sink space allocation to add expansion for future research

- Improved utilisation of surface mount devices (SMDs) for space saving

- Changed wire-to-board connector technology to reduce signal degradation

- Changed optocouplers to increase maximum communication frequency

In order to provide additional flexibility in the design, and to ensure the ease of

replacement of malfunctioning devices, the SM capacitor bank is populated on a

separate board. The device is therefore not shown on Figure 4.3. The capacitor bank is

mounted above the gate driver circuits using four 3-pin board-to-board connectors. A

fully populated CHP SM V5.1 is shown without the capacitor bank in Figure 4.4, and

with the capacitor bank in Figure 4.5.

The V5.1 PCBs were manufactured externally. The manufacturer also populated the

PCB with SMDs using pick-and-place technology. All the remaining through-hole

components were populated by the author. Previous iterations of the SM were fully

fabricated and populated in house.

In Figures 4.4 and 4.5, the red and black four-way Molex KK series connector is the

jumper cable used to reconfigure between HB and FB configuration. The black two-

way Molex KK series connector acts as a star-point grounding between the analogue

and digital floating regions in order to eliminate ground loops.


78

Figure 4.3: Sub-module component layout overview

24V In

BHB

ACOM

CFB

GD3

GD4

GD1

GD2

DC DCA

DC

DC

B

DCA

DC DCC

DCC

DC

B

DC DCB5

DCB5

OP1 OP2 OP3

OPa1 OPa2 OPa3 OPa4 OPa5

AD

C

S-K

AD

Ca1

S-Ka1

AD

Ca2

S-Ka2

D3

S3

D4

S4

Heat SinkKeepout

D1

S1

D2

S2

DR

Z1

Z2 F1

Wire-to-Board Wire-to-Board

I1 I2

I3

Ia1

Ia2

Ia3

Ia4

Ia5

Heat SinkKeepout

160mm

100 mm

RSa RSb


79

Figure 4.4: CHP SM hardware (without capacitor bank)


80

Figure 4.5: CHP SM hardware (with capacitor bank) from two angles


81

4.4. Auxiliary Circuits

A number of other PCBs have been designed, fabricated and populated during the

research for the CHP. This section will briefly cover each board and its functionality but

will not go into detail about device selection and design iterations. The designs and

schematics for all the PCBs described in this section are available from the

supplementary online repository [49]. For a list of the main components and the

specific manufacturer part numbers see Appendix C.

Distributed Controller Breakout Board

The distributed controller breakout board, Figure 4.6, is used to facilitate

communication between the PCU, DCU and SMs.

Eight 20-way TE Connectivity Micro-MaTch series connectors enable critical and

additional communication mechanisms to four SMs per breakout, making up a local

control unit. These connectors are routed to I/O pins on the DCU board. Two 5 Mbps

fibre-optic receivers (general data and fault error receiver) and a 5 Mbps fibre-optic

transmitter (general data) are used to pass information between the DCU and the PCU

via the fibre-optic breakout board discussed in the following section. A one-input-four-

output 24 V distribution circuit supplies the adjacent SMs with power. For future

expansion or additional requirements, two four-way Molex KK series connectors

provide access to spare reconfigurable I/O and the power rails of the local controller.

Figure 4.6: DCU breakout board


82

Fibre-Optic Breakout Board

In order to ensure a clear isolation barrier, and to replicate the technology used by

industry, a fibre-optic breakout board (FOB) is used to facilitate communication

between the PCU and DCUs, Figure 4.7.

A group of two 5 Mbps fibre-optic transmitters (light grey) and one 5 Mbps fibre-optic

receiver (dark grey) is used for each DCU. A 68-pin high density D-SUB connector is

used to communicate between the FOB and the PCU. A power supply from the 5 V

distribution board, via the green and blue banana connectors, is used for the fibre-

optic drivers and fibre-optic receiver circuits.

Power Interface Board

Each arm is made up of a stack of series connected SMs and an arm inductor. Two

arms connect in series to make a phase. The three phases are all connected in parallel

across the DC link to create a three-phase CHP. The AC outputs are taken at the

midpoint between the two arms in each phase. All of these connection points are

facilitated on the power interface board (PIB), Figure 4.8.

Arm current measurement is carried out using linear isolated Hall-Effect sensors (HES).

Relays allow for controlled charging of the CHP and provide a circuit-breaker

functionality to protect the CHP from faults. Galvanic isolation between the high

voltage circuit and sensitive control circuit is provided by the relays and HES, with

ratings of 5 kV and 2.1 kV respectively.

Banana connectors are used to connect the SMs together and to the PIB. Banana

connectors simplify reconfiguration within the CHP and allow for isolating and

bypassing different sections of the circuit during testing. The screw terminals enable

Figure 4.7: Fibre-optic breakout board


83

different charging resistors to be used and provide the connection point for the arm

inductors. A power supply from the 5 V distribution board is used for the relays. Two

additional fuses are provided at the positive and negative DC rails for OCP. A 68-pin

high density D-SUB connector is used to communicate between the PIB and DAQ.

BNC Analogue Interface Board

A number of additional analogue signals from differential probes require digitisation

for use by the control systems in the CHP. A BNC analogue interface, Figure 4.9,

provides the physical connections for the differential probes and a communication

interface over a 68-pin high density D-SUB connector to the DAQ.

5 V Power Distribution Board

A DC power supply is used to provide 5 V to the DCUs in the CHP. The connector on the

devices is a standard barrel connector. The 5 V power distribution PCB, Figure 4.10, is

used to provide twelve outputs from one input to distribute power throughout the

Figure 4.8: Power interface board (partially populated)

Figure 4.9: BNC analogue interface board


84

CHP. Each connector is individually switched and clearly indicates, using an LED, when

power is supplied to a DCU. The 5 V connection points to the PIB and FOB are provided

by two additional banana connector pairs.

24 V Power Distribution Board

A second DC power supply is used to provide 24 V to the SMs in the CHP. Molex Ultra-

fit connectors are used between the SMs and the distribution board. The 24 V power

distribution PCB, Figure 4.11, is used to provide twelve outputs from one input. The

twelve outputs are subsequently split between four outputs by the distributed

controller breakout boards to reach the full 48 SMs.

Figure 4.10: 5 V distribution board

Figure 4.11: 24 V distribution board


85

Figure 4.12: Auxiliary boards in situ; FOB (upper), PIB (middle), multiple (lower)


86

Figure 4.12 shows a selection of auxiliary boards installed in the CHP. Figure 4.13 is an

overview diagram for the CHP describing how the auxiliary boards are used in the

system to facilitate communication and power distribution throughout the converter.

The devices are referenced back to their respective figures in Chapters 3 and 4.

Figure 4.13: CHP system overview

CC

U (R

T CP

U)

DCU x12

SM x48

Valve Hall

Server Room

Control Room

Figure 4.5

Figure 3.4

LCB

Figure

4.6

DC

U B

reako

ut x1

2

FOB

Figure

4.7

Fibre

Bre

akou

t x1

PIB

Figure

4.8

Po

we

r Inte

rface x1

BNC

Figure

4.9

BN

C In

terface

x1

To MMCTo MMC

Figure

3.5

Supply Room

CC

U (FP

GA

)Figu

re 3

.5

PC

UFigu

re 3

.5

DA

QFigu

re 3

.5

HM

I

5V

Figure

4.1

05

V D

ist. x1

5V Supply

BK1900B

24V

Figure

4.1

12

4V

Dist. x1

24V Supply

72-2540

To DCUFOB, PIB

To SM via DCU Breakout


87

4.5. Converter Hardware Prototype

The hardware discussed in Chapter 3 and Chapter 4 is housed within a single 19-inch

43U server rack. The DCUs are grouped into a local controller (LC) with four SMs.

Figure 4.14 shows one LC (LC10) from the front, side and back. Communications and

auxiliary power is fed into the back of the SMs. The power system side is accessible

from the front of the SMs, allowing for simple system reconfiguration and probing.

Different connectors have been used throughout the build for different purposes, to

reduce the chance of operator error when making hardware changes.

Figure 4.14: Populated local controller sub-rack front (upper), side (middle) and back (lower)


88

Prior to populating the full rack, a layout design was produced to visualise the

equipment arrangement and check space requirements. Figure 4.15 is the annotated

rack design.

When the rack walls and back are installed, forced air cooling from six 120 mm fans

ensures hot air is ventilated out of the rig to keep operational temperatures low. These

fans are powered from an additional 24 V fixed power supply which connects to a

three-phase mains distribution box installed at the base of the CHP rack. This

distribution box also provides mains power to the DC link PSU from one phase, and the

auxiliary PSUs, NI PXI system and the network router on a different phase. This splitting

across phases ensures the mains supply is not overloaded during testing.

Figure 4.15: CHP server rack design

Full CHP Rack

RT Monitor

Keyboard Tray

DC PSU

Front View

LC1

LC2

LC3

LC4

LC5

LC6

Rear View

NI PXI System

Fibre Breakout

LC7

LC8

LC9

LC10

LC11

LC12

Router

Auxiliary PCBsAuxiliary PSUs

Arm Inductors


89

The populated rack, consisting of the complete CHP, is shown in Figure 4.16 from the

front and back. During normal use, the front door, side-walls and back plate are

installed to reduce the risk of shock. An AC star-point resistive load cabinet, shown in

Figure 4.17, is mounted to the side of the rack.

Figure 4.16: CHP experimental test rig front (left) and back (right)


90

4.6. Summary

This chapter has covered the hardware development for the converter hardware

prototype. System ratings have been detailed and the subsequent SM design

presented and discussed. The auxiliary PCBs required to enable CHP functionality are

described and shown (independently and in situ). Decisions on design and component

selection for all boards have been justified either in this chapter or in Appendix B. An

overview diagram of system interaction between the control hardware and converter

hardware details the CHP assembly and the final constructed CHP is shown.

The circuit diagrams and PCB layouts presented in this chapter have been wholly

developed by the author of this thesis. Each PCB has been populated and tested by the

author (except SMDs on the SMs). The converter hardware prototype three-phase

mains distribution box, 3U sub-racks, back-plate (with fan-driven air cooling) and

internal shelving have been designed and/or assembled by the author, along with over

300 different copper, fibre-optic and multi-way connectors which have been cut to size

for the CHP during rack population.

The work presented in Chapter 3 and Chapter 4 forms part of a conference paper

presented at the 15th IET international conference on AC and DC Power Transmission

(ACDC 2019) titled “Design, Construction and Testing of a Modular Multilevel

Converter with a Distributed Control Architecture” by T Heath, P R Green and M

Barnes from the University of Manchester, and D Kong from National Grid [91].

Figure 4.17: AC resistive load cabinet

Control System Software Development

91

Control System Software Development 5.

In this chapter the MMC control theory presented in Chapter 2 is applied to the

converter hardware prototype (CHP) described in Chapters 3 and 4. The control system

software is partitioned across the different levels of hardware in the CHP. Due to the

complexity and size of the programs developed during this research, an overview into

the function of each controller is given, rather than code extracts or pseudocode. The

most recent versions of the control system programs are available from the

supplementary online repository [49].

The control system software was developed using a bottom-up approach; starting with

the distributed control units and ending at the human-machine interface. This

approach mirrored hardware progression. Figure 5.1 is a simplified diagram of the

distributed control and communications architecture of the converter. This diagram is

presented for clarity and serves as a reference point for this chapter.

Figure 5.1: Simplified overview diagram of CHP distributed control architecture

CCU-RT

PCU DAQ

DCU SM

CCU-FPGA

HMI

PCI 33 MHz Bus

5 MHz UART

12.5 MHz SPI

5 MHz UART

PXI Chassis

CCU Central Control Unit DAQ Digital Acquisition

BoardDCU Distributed Control UnitFPGA Field Programmable

Gate ArrayHMI Human Machine

InterfaceLAN Local Area NetworkPCI Peripheral Component

InterconnectPCU Phase Control UnitRT Real-time ControllerSM Sub-moduleSPI Serial Peripheral

Interface UART Universal Asynchronous

Receiver/Transmitter

100 Mbit/s LAN


92

5.1. Distributed Control Unit

Twelve Terasic DE10-Nano development boards with Intel Cyclone V System-on-Chips

(SoCs) are used for the distributed control units (DCUs), the lowest level of control

hardware. As shown in Figure 5.1, these devices communicate directly with four sub-

modules (SMs) per board and to the phase control unit (PCU). The DCU forms part of

the inner voltage control loop.

The DCUs all run an identical program written in Verilog using the Quartus Prime FPGA

development software. Figure 5.2 provides an overview of the DCU control program.

The universal asynchronous receiver/transmitter (UART) is aggregated for the four

SMs, whilst the serial peripheral interfaces (SPIs) operate as four independent, parallel

modules. The main functions for the DCU, in order of execution, are:

- Receive switch signals and configuration data from the PCU via UART

- Determine the validity of the data by performing a parity check

- Issue firing signals with dead-time to the gate drivers on each SM

- Drive the serial peripheral interface (SPI) to the ADCs on each SM to acquire

capacitor voltages

- Transmit capacitor voltage measurements and recorded errors back to the PCU

via UART

Figure 5.2: Overview diagram of DCU control program

DCU

DA

T

ERR

DA

T

CLK CS

VSM FS CLK CS

VSM FS CLK CS

VSM FSCLK CS

VSM FS

TO S

M

TO P

CU

SPI SPI SPI SPI

DT and FP

DT and FP

DT and FP

DT and FP

UARTParity Check

Parity Calculation

Packet Builder/Translator

ErrorHandler

CLK ClockCS Chip SelectDAT DataDT Dead-timeERR ErrorFP Fault

ProtectionFS Firing SignalsVSM SM Capacitor

Voltage


93

Figure 5.3 shows the packet structure for communication links handled by the DCU.

The data received from the ADC over SPI takes the form of a 16-bit transfer (VSM IN)

which contains ten bits of measurement data. The SPI is driven by a 12.5 MHz clock

derived from the 50 MHz FPGA clock. This is equivalent to a theoretical communication

delay of 1.28 µs per sample (not including propagation delays though opto-isolators or

inverters). The communication link to the PCU is a bespoke 5 MHz UART over single-

mode fibre-optic cable. The 32-bit packet sent by the PCU (DAT IN) contains four sets

of switch signals for the SMs and control settings. Once a packet has been received,

the DCU program is executed. Upon completion, the DCU transmits two 32-bit packets

back to the PCU (DAT OUT) containing the SM capacitor voltage measurements and

any errors met during operation (such as switching or parity errors). Each packet takes

6.4 µs to transmit (not including fibre driver or receiver delays). The total theoretical

execution time for the program, including UART and SPI delay is just over 21 µs.

The fault protection (FP) and dead-time (DT) blocks in Figure 5.2 ensure that the

correct firing signals are transmitted to the SMs and that the firing signals to each

switch on the SM are always delayed by a dead-time of 100 ns. This control block

eliminates the potential for the SM capacitor to be short circuited due to controller or

communication errors.

For the purposes of this research, only the FPGA portion of the SoC is used. The FPGA

alone is sufficient to meet the control requirements. Future work will make use of the

hard-processor portion of the SoC to explore more complex forms of distributed

control on the CHP.

Figure 5.3: Packet structure for DCU to SM and DCU to PCU communication

15 0

STARTSTOP SM VOLTAGE

4102

STOP PAR SW4-1 SW4-1- CONTROL STARTSW4-1- SW4-1-

2 1 4 1 4 1 4 1 4 7 2

-

1

DATIN

DATOUT

STOP PAR SM VOLTAGE SM VOLTAGE0

- ERROR START

2 1

31

10 1 10 26

031

SMVSM

IN

PCU

STOP PAR SM VOLTAGE SM VOLTAGE0

- ERROR START

2 1

31

10 1 10 26


94

FPGAs are parallel processing units made up of thousands of flip-flops and configurable

combinatorial logic, each of which is latched at every clock cycle, or ‘tick’. Programs are

written in hardware description languages (HDLs) such as Verilog or VHDL; text-based

programming languages suited to describing digital logic. The code is then synthesised

into logic circuits comprising flip-flops and look-up-tables (LUTs). As all the code is

executed at every tick, one of the challenges in FPGA program development is ensuring

code is executed in the correct order. This is typically achieved using a finite-state

machine (FSM). In an FSM, all the processes are still executed in parallel, but each

state remains in an idle condition until the previous state issues a ‘ready’ command,

indicating a transition; providing predictable sequential behaviour from parallel logic.

The DCU is developed using an FSM. This ensures the execution of the main functions

follow a predefined sequential path, for controlled operation. In the case of the DCU,

the FSM remains in the idle state until it detects incoming data from the PCU, after

which it transitions to the UART state, followed by the parity check state and so on

until the FSM has returned to the idle state and awaits further instructions. This

behaviour is similar to master/slave communication between the PCU and DCU.

5.2. Phase Control Unit

One NI PXI-7851(R) card with a Xilinx Virtex-5 LX30 FPGA is used for the PCU. This card

is housed in a NI PXIe-1071 chassis and communicates directly with the twelve DCUs,

the central control unit (CCU) FPGA and the CCU real-time (RT) system, Figure 5.1. The

PCU forms part of the inner voltage control loop.

The PCU program is written in LabVIEW FPGA using the National Instruments LabVIEW

development software. Figure 5.4 provides an overview of the PCU control program.

The main functions for the PCU are:

- Receive configuration data and state machine controls from the CCU-RT

- Receive nearest level controller (NLC) data and arm current polarity from the

CCU-FPGA

- Host the UART to each of the twelve DCUs to send switch signals and receive

capacitor voltage measurements

- Determine the validity of the data packets by performing parity checks

- Implement the capacitor balancing controller (CBC) to sort voltages in each arm

- Handle SM switch selection using the NLC with sorted lists from the CBC


95

Ideally, six parallel processes, one for each arm, would be used in this device to more

closely represent industrial control hardware. The parallel processes would handle

UART, parity checks, packet translation and CBC for each arm. However, due to limited

FPGA resource, the latter three of these operations were partially or fully serialised to

reduce FPGA utilisation. After optimisation and compression the code utilises 99% of

the FPGA resource. The program overview is shown in Figure 5.4.

The incoming data to the PCU from the twelve parallel DCU UARTs undergoes a parity

check (PC) before the capacitor voltages are separated into individual values and

assigned an identification number (SM-ID), representing the physical location of the

corresponding SM in the CHP. These measurements are then available to the capacitor

balancing controller (CBC) for each arm. The 5 MHz UART between the CCU-FPGA and

the PCU is only used as a receiver at this end. The packet structure for this

communication link is shown in Figure 5.5; a 35-bit packet containing NLC references

(NuC to NlA), indicating the number of SMs to be switched on in the upper and lower

arms of each phase, and the current polarity for each arm (ArmIPol), is sent by the

CCU-FPGA. This information is also checked for parity prior to being released for the

NLC module. This packet takes approximately 7 µs to transmit.

Figure 5.4: Overview diagram of PCU control program

PCU

TO D

CU

TO C

CU

-FPG

A

TO C

CU

-RT

Parity Check

UA

RT

UA

RT

UA

RT

UA

RT

UA

RT

UA

RT

UA

RT

UA

RT

UA

RT

UA

RT

Error Handler

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DA

T

ERR

DA

T

DMA

NLD

UART

UA

RT

UA

RT

BU

S

Phase A

NLC

Phase B Phase C

Configuration Control

State Machine Control

Parity Check and Packet Translator

Packet Builder and Parity Calculator

CBC

CBC

CBC Capacitor Balancing Control

DMA Direct Memory Access

NLC Nearest Level Control

NLD Nearest Level Data


96

A direct-memory access (DMA) LabVIEW FPGA block is used to implement the

communication link between the CCU-FPGA and the CCU-RT host. This allows the CCU-

RT host to read/write specific variables stored in the FPGA. These variables govern and

monitor the FPGA FSM for safe, controlled operation. The communication delay

between the FPGA and the CCU-RT is unspecified. However, it can be estimated by

considering that the data transfer is over a 32-bit 33 MHz peripheral component

interconnect (PCI) bus. This results in a delay of just over 30 ns. In practice, set-up

times for the DMA interface and arbitration of the PCI bus will lead to an increased

delay for each transmission. Additionally, the data transferred via the DMA interface

from the CCU-RT is only sampled by the FPGA at a frequency of 1 kHz.

Once the capacitor voltages have been assigned a SM-ID they are placed into six arrays

of eight values, one array for each arm. The CBC executes an FPGA implementation of

the bubble-sort algorithm to sort the measurements from largest to smallest. Two

bubble-sorts are completed in parallel i.e. one phase at a time. These sorted arrays are

then transferred to the NLC, which determines the SMs to connect and disconnect

based on the arm current direction and the position of the SM-ID in the sorted list.

Switch signals are assigned to each SM and placed into twelve 32-bit packets to be

transmitted to the DCUs; DAT IN in Figure 5.3. Parallel implementation of the DCU

UARTs ensures that all twelve packets are transmitted simultaneously. However,

variation in component performance and different length optical fibres result in

unsynchronised switching at the DCUs. The difference in propagation delay across the

fibre-optic devices can be as much as 100 ns [116], causing discrepancies between

firing signals issued by DCUs. For the purposes of this research, the lack of

synchronisation and the associated time delay between switching events is mitigated

by the fact that only a small number of SMs are switching in or out at any level change.

Should the system encounter a critical error during operation, or if power is lost to the

CCU, the error line will be driven low, placing the DCUs in a fault state which

Figure 5.5: Packet structure for PCU to CCU-FPGA communication

NLCIN

CCU FPGA

STOP PAR NuC0

START

2 1

35

4 2

NlC NuB NlB NuA NlA

4 4 4 4 4

ArmIPol

6


97

disconnects all SMs from the circuit. As the AC network connected to the CHP is not

active there is no risk of entering freewheel diode rectification operation. The error

path is a critical fault control, allowing for a blocking response time of around 1 µs,

including fibre-optic driver rise time, fibre-optic link propagation delay, switch driver

fall time and switch turn-off time.

National Instruments LabVIEW is traditionally a dataflow visual-based programming

language (VPL). In response to demand for high speed data processing, LabVIEW FPGA

was developed, which merges LabVIEW with parallel programming techniques.

Sequential execution is forced inherently by the language; therefore the use of FSMs is

reduced in comparison to Verilog or VHDL. In LabVIEW FPGA, parallel processes are

drawn in separate loops, each of which can be triggered at a particular frequency with

specific start conditions based on local or global variables.

From a control system perspective these execution rates limit bandwidth, determine

loop delays and sampling frequency and directly impact the response time of the

system. In the PCU program, the trigger frequencies for the parallel loops are set

depending on the control function. The CBC module and NLC module work in parallel

executing at nominal frequencies of 500 Hz and 5 kHz respectively. The UART receivers

continuously poll the input pins and the remainder of the modules run when called

and execute their respective process as fast as possible.

During a full cycle at the 50 Hz network frequency, the CHP operating in nine-level

three-phase mode will require 16 level changes, with an average of 1.25 ms between

each change (from 0.8 ms to 3.2 ms). A nearest level controller with a 5 kHz execution

frequency ensures that the minimum time between level changes is 200 µs. This also

allows sufficient time for the DCU communication and measurement loop to complete

before sending new firing signals. In practice, the maximum frequency of this loop on

the CHP is closer to 40 kHz; decreasing the minimum time between level changes to 25

µs. Alternatively, the CBC could be executed as soon as the NLC has completed;

creating a data dependent path.

The ideal sorting frequency is equal to the number of level changes per second, for

example in the CHP, 16 level changes in a 50 Hz cycle suggests an ideal sorting

frequency of 800 Hz [56]. With no SM switching limitation, the sorting frequency


98

would lead to an equivalent effective SM switching frequency. The effective converter

switching frequency is equal to the number SMs per phase multiplied by the effective

SM switching frequency i.e. the potential for 16 switching events per level change, or

12.8 kHz for the CHP. Performing a sort before every level change allows for the best

performance in capacitor balancing. However, it leads to increased SM switching and

therefore increased switching losses.

In industrial practice the sorting frequency and SM switching frequency are decoupled,

and the effective SM switching frequency is limited to nearer 150 Hz in order to keep

losses low. The effective converter switching frequency in this case would be 150 Hz

multiplied by the number of SMs in a phase. The sorting frequency used in industry is

not discussed in open literature for commercial reasons [31].

A number of reduced switching frequency techniques have been investigated [87, 117-

119]. A variation of the slow-rate capacitor voltage-balancing strategy proposed by

[120] has been used on the CHP, with a loop frequency of 500 Hz. In Chapter 6, it was

identified that sorting above 500 Hz provided no significant benefit to CHP operation.

The sampling frequency of capacitor voltages is set by the NLC using the master/slave

UART. CBC execution can therefore run at the same frequency as NLC.


99

5.3. Central Control Unit

The CCU is formed of an FPGA and an industrial PC with a conventional CPU running a

real-time (RT) operating system. The main tasks for these devices are distinct and

therefore software development is discussed separately.

FPGA

One NI PXIe-7857(R) card with a Xilinx Kintex-7 160T FPGA is used for FPGA section of

the CCU. This card is housed in a NI PXIe-1071 chassis and communicates directly to

the PCU and the CCU-RT controller, Figure 5.1. The CCU-FPGA forms part of the inner

voltage and current control loops.

This program is written in LabVIEW FPGA using the National Instruments LabVIEW

development software. Figure 5.6 is an overview diagram of the CCU-FPGA control

program. The main functions for the CCU-FPGA are:

- Receive configuration data and state machine controls from the CCU-RT

- Phase-locked loop (PLL) and dq current control calculation

- Nearest level control calculation

- Host the UART to the PCU to transmit NLC and arm current polarity data

Figure 5.6: Overview diagram of CCU-FPGA control program

CCU-FPGA

TO P

CU

TO C

CU

-RT

Parity Calculation

State Machine Control

NLC

PLLABC

to dq

dq to ABC

PI

Decoder

Packet Builder

NLD

UART

BU

S

DAQ Data Translator

Ref Gen

DMAPI Proportional

Integral ControlPLL Phase-locked

Loop


100

The CCU-FPGA controller receives data from the CCU-RT controller from a second DMA

interface. The data includes system measurements taken by the NI PXI-6363 digital

acquisition (DAQ) card, reference control and a variable used for state-machine

control. System measurements include three-phase AC reference voltages, AC

converter currents, upper and lower arm currents, DC current and DC voltage. The

DAQ data translator converts the incoming data into a usable form and calculates the

arm current polarity for use by the CBC in the PCU.

Two control modes have been implemented on the CHP. The first, grid-following

mode, forces the converter to track the voltage of an external three-phase AC source.

The second, grid-forming mode, forces the CHP to track an internal AC reference.

Grid-forming control uses an AC reference generator (Ref Gen) controlled from the

HMI (via the CCU-RT) to generate the desired converter voltage reference for the

voltage control loop. Voltage magnitude and angle for each of the phases can be

varied through the program during run-time to change the CHP output voltage.

Grid-following control uses the AC network voltage to generate the voltage reference

for the voltage control loop. Since there is not an active AC network connected to the

CHP, an external three-phase function generator (FG) is used to represent the AC grid.

The FG output waveform for each phase is sampled by the DAQ and transmitted to the

CCU-FPGA. Voltage magnitude, frequency and angle for each of the phases can be

physically varied during run-time.

In both cases the desired voltage reference could be sent directly to the decoder which

calculates the upper and lower arm voltage references for the NLC. This is similar to

direct control discussed in Chapter 2. The main difference is that the AC side of the

CHP is connected to a three-phase resistive load, rather than an active network. Power

flow is therefore determined by the magnitude of the converter output voltage only

and a power control loop is not required. For grid-forming control, this is the process

used by the CHP. For grid-following control, additional control loops are added to bring

the CHP in-line with industrial converter control.

A PLL uses the FG voltage measurements to calculate the frequency and angle of the

reference. The angle is used to transform the measured data from the abc reference

frame to the dq reference frame, as discussed in Chapter 2. At this point a closed loop


101

dq current controller would usually be used to create the converter voltage reference.

However, the functionality of this controller requires power transfer to occur between

two AC sources which is not the case for the CHP. For the research in this thesis the

performance of the internal current controllers is less important than the time it takes

to execute the control calculations.

To this end, the abc-to-dq and dq-to-abc transformations are carried out for all the

necessary measurements on the CCU-FPGA, but the proportional-integral (PI) loop is

bypassed and the voltage reference to the decoder is not affected by the output

current. The circulating current suppression controller (CCSC) is also placed on the

CCU-FPGA, however in the CHP, the outputs from this module are not used by the

decoder when calculating the upper and lower arm voltage references for each phase.

Designing the CHP in this way simplifies future system development, especially

regarding the introduction of an active AC network, as only minor changes are

required to the decoder and PI modules to close the dq current and circulating current

control loops.

Six references are fed into the CCU-FPGA side of the NLC. A round function, as

discussed in Chapter 2, is used to translate the continuous AC references into discrete

steps, representing the number of SMs to be connected in the upper and lower arms

of each phase. This information is bundled into a packet along with arm current

polarity and sent to the PCU using the 5 MHz UART described in Section 5.2.

Similarly to the PCU, the CCU-FPGA is developed in LabVIEW FPGA. Control loop trigger

rates can be chosen by the programmer. For the CHP, the current control loop and the

CCSC are triggered at a frequency of 40 kHz. However, the bandwidth of the

controllers would be set by tuning the PI gains around desired performance. UART

communication with the PCU occurs at a frequency of 20 kHz and the DMA link to the

CCU-RT is polled at a frequency of 20 kHz, as the DMA is hosted by the CCU-RT the

data update frequency is 4 kHz; a faster polling frequency ensures the new data is used

within a maximum of 50 µs. The remainder of the modules run when called and

execute their respective processes as fast as possible.


102

RT

One NI PXI-8102 card with an Intel Celeron T3100 RT CPU is used for RT section of the

CCU. This device is housed in a NI PXIe-1071 chassis and communicates directly to the

PCU, CCU-FPGA, NI PXIe-6363 DAQ card, DC link power supply and human-machine

interface (HMI), Figure 5.1. The CCU-RT forms part of the current and power control

loops and is the highest level controller with deterministic timing in the CHP.

The CCU-RT program is written in LabVIEW RT using the National Instruments LabVIEW

development software. Figure 5.7 is an overview diagram of the CCU-RT control

program. The main functions for the CCU-RT are:

- Ensure system control timing is met across CHP

- Data transfer and state-machine control for the PCU and CCU-FPGA

- Configuration and timing of digital acquisition for system measurements

- Hosting network published variables for HMI control

- DC link and circuit breaker control

- Initialisation and start-up management

Figure 5.7: Overview diagram of CCU-RT control program

TO P

CU

BU

S

TO C

CU

-FPG

A

BU

S

BU

S

TO D

AQ

NET

TO H

MI

TO D

C P

SU

DMA DMA

Setup

PCU ControlCCU-FPGA

ControlDAQ

Control

EC

FPGA State Machine Control

CCU-RT

Error Handler

EC Ethernet Controller

NET Network


103

The CCU-RT is the master for the PCU and CCU-FPGA controllers. It handles the 32-bit

33 MHz PCI bus used for DMA transfers between both FPGA cards and the RT

controller, and for configuration and data collection using the DAQ. The CCU-RT also

handles the Ethernet controller (EC) for communication over a local-area network

(LAN) to the HMI and the DC link power supply unit (PSU).

When the CCU-RT program starts it sets all variables to a predefined default state and

prepares the FPGA operation chains; downloading and initialising the FPGA bitfiles. A

data acquisition task and a digital output task are created to configure the DAQ. The

DC PSU is set to a nominal voltage with the output disabled (Setup). Once complete

the program enters the real-time control loops (PCU Control and CCU-FPGA Control)

governed by the FSM controller (FPGA State Machine Control).

The CCU-FPGA timed loop is triggered at a frequency of 4 kHz and has the highest

priority within the CCU-RT. This loop handles the hardware-timed single-point (HWTSP)

sampling of the system variables and data transfer to the CCU-FPGA. HWTSP sampling

is when a data acquisition task is triggered by hardware, in this case triggered by the

CCU-RT system, and allows for a very fast controlled throughput of data. Only the most

recent sample of each measurement is sent to the controller. The nominal execution

time for this loop is close to 200 µs. A sampling rate of 4 kHz, providing 80 samples per

cycle, enables effective system control and suitable timing performance. A faster

central processing unit (CPU) would enable this loop, and therefore hardware data

acquisition, to be executed at greater frequencies. The data acquisition forms the

feedback loop for the current controller. A power controller has not been developed

for the CHP because it is not connected to an active AC network.

The PCU timed loop is triggered at a frequency of 100 Hz and has the lowest priority.

This loop handles control of the PCU FSM and updates HMI front-panel variables for

the CCU-FPGA, both of which require user interaction. A faster PCU loop frequency

would offer no significant benefits for CHP control. This loop also drives digital outputs

on the DAQ to control circuit breakers for controlled turn-on and turn-off cycles.

Critical errors during run-time lead to the program being aborted. This drives the

critical fault line at the PCU low, placing the SMs into blocking mode. Non-critical

operation errors are gathered at shut-down (Error Handler) and reported to the HMI.


104

5.4. Human Machine Interface

The HMI is hosted on a separate computer and communicates to the CCU-RT over a

LAN. Any computer with the appropriate LabVIEW software can be used to host the

HMI. The HMI would form part of the power control loop.

The HMI program is written in LabVIEW using the National Instruments LabVIEW

development software. Figure 5.8 depicts the front-panel for the HMI. The main

functions of which are:

- System charge cycle control

- Hosting a graphical user interface

- AC reference generator control

The HMI takes user input and transmits the information via network-published

variables accessible by the HMI and the CCU-RT device over a LAN. In addition a charge

cycle process has been programmed to remove the need for user interaction during

pre-sequenced turn-on and turn-off cycles. This automation reduces the chance of

operator error and speeds up the process.

Control of the CHP is handled using the user interface shown in Figure 5.8.

Figure 5.8: Front panel of HMI control program


105

5.5. Summary

Chapter 5 has provided an overview of the control system software development for

the converter hardware prototype. Each level of controller programming has been

discussed, with specific detail regarding communication and calculation delays found

throughout the system. The control theory presented in Chapter 2 has been

implemented and adapted to the converter hardware discussed in Chapters 3 and 4.

An overview diagram detailing how the different controllers presented in this chapter

form the control system on the distributed architecture of the CHP is shown in

Figure 5.9. Key data exchanges and the location of control loops are indicated, along

with where each controller sits within the voltage, current and power control loops.

Figure 5.9: Overview diagram of control system software and control loop separation

CC

U (R

T CP

U)

PC

U

DA

Q

DC

U SM

CC

U (FP

GA

)

HM

I

Round

Decoder

CCSC

CBC

NLC ii

FS w/DT

Vsm

FS

Vsm

dq/ABC

IarmVabcIabcVdcIdc

PLL

CB

SC

Iarm

Vabc

Iabc

Vdc

IdcSC

Non

SC

BC

DCSC

PI

FS – Firing SignalsDT – Dead-Time SC – State ControlCB – Circuit BreakersBC – Bus ControlDC – Direct Control

Voltage

Current

Power

MMC

dq/ABC


106

Figures 7.17 and 7.18 at the end of Chapter 7 are more detailed diagrams of the

control loops and delays which further support the discussion presented in this

chapter.

Each level of control programming has been designed, developed and tested by the

author of this thesis. The pre-existing hardware including the National Instruments

PXI-1071 chassis, PXI-8102 RT controller, PXI-6363 DAQ card and PXI-7851R FPGA card

were provided with no usable code extracts and therefore were effectively received as

new. This remains true for the hardware purchased as part of this research including

the Terasic DE10 SoCs and National Instruments PXI-7857R FPGA card. Code

development started with the DCUs in Verilog HDL and was logically verified using test-

benches written in Verilog by the author. The PCU and CCU-FPGA code was developed

in LabVIEW FPGA, followed by the CCU-RT in LabVIEW RT and the HMI in standard

LabVIEW.

The entirety of the code has been written by the author other than: the phase-locked

loop (PLL) control block on the CCU-FPGA, which is an intellectual property core

provided by National Instruments, and the universal asynchronous receiver transmitter

(UART) on the DCU which was adapted for the converter hardware prototype from

[121].

Programs developed during this research will not be discussed in any further detail in

this thesis. The most recent versions of code are available from the supplementary

online repository [49].

Simulation Model Development

107

Simulation Model Development 6.

The primary objective of this research is to assess the fidelity of simulation models

presently used in power system studies. In order to present this information clearly, an

overview of the different types of simulation model are covered in this chapter,

followed by a description of the simulation model used during this research. The

developed model replicates the converter hardware prototype (CHP) for comparison

and analysis, presented in Chapter 7.

6.1. Simulation Model Types

Simulating state-of-the-art hardware such as an MMC is non-trivial. Models of varying

fidelity have been developed to suit different simulation applications. In this thesis

these are categorised into seven distinct types and two sub-types following the

categorisation developed by Cigré and others [122-125].

Type 1: Full Physics Model

MMC components (IGBTs and diodes) in the Type 1 model are described by partial

differential equations and can accurately represent switching losses and low level

system behaviour [126]. Very small time-steps are required, typically in the order of

nanoseconds, which make them ideal for internal converter dynamics but unsuitable

for power system analysis [124]. Parameterising the components is also a significant

challenge for larger full physics models.

Type 2: Full Detailed Model (DM)

In the Type 2 model, nonlinear IGBT and diode models are used to provide accurate

simulation of switching transients and sub-module (SM) conduction paths, but cannot

be used to accurately calculate switching losses [123, 124]. The voltage-current

characteristics of the semiconductors are represented as nonlinear resistors [114]. This

model is suitable for electromagnetic transient (EMT) simulation programs, such as

SPICE, to provide a high level of fidelity and is therefore typically used to tune lower

fidelity models. Similarly to the Type 1 model, very small time-steps are required.

Type 3: Traditional Detailed Model (TDM)

The Type 3 model, or TDM, simplifies the IGBT and diode models to use fixed on and

off resistances determined by the capacitor voltage, firing signals and arm current

direction. This may reduce the simulation time in comparison to a Type 2 model


108

depending on the simulation tool used [123]. EMT programs such as PSCAD are ideal

for TDM simulation. A Type 3 model can simulate arm currents and SM capacitor

voltages and provide access to low level MMC components. Time-steps in the order of

microseconds are required. Type 3 simulations are computationally inefficient and are

therefore typically only used to validate simplified models [107, 123, 124].

Type 3.5: Accelerated Model (AM)

The accelerated model (AM) is a hybrid between the DEM and TDM [125, 127]. MMC

arms are represented as controllable voltage sources and the individual SMs are

separated from the series connected circuit and calculated independently with a

current source equal to the arm current [107]. For this model SM components are

accessible by the user and reconfiguring between HB and FB SMs is more intuitive

[127]. The AM reduces some of the drawbacks of the DEM without the simulation

inefficiencies of the TDM. The integration time is in the order of microseconds [125].

Type 4: Detailed Equivalent Model (DEM)

In each arm of the Type 4 model the SMs are lumped together into a single Thévenin

equivalent circuit, significantly reducing the number of electrical nodes in the

simulation model in comparison to the TDM [124]. The resistance and voltage of the

equivalent circuit is determined by the firing signals, arm current direction and the

sum of connected SM capacitor voltages. Individual SM capacitor voltages are

accessible but the semiconductor elements are not. Similarly to the Type 3 model,

time-steps in the order of microseconds are required, but in this case the simulation is

computationally efficient, making it suitable for EMT power system studies [123].

Type 5: Average Value Model (AVM)

The AVM reduces the MMC simulation model further by representing the AC and DC

sides of the converter as controllable voltage and current sources respectively [123].

Voltage sources simulate converter output based on switching behaviour at the AC

side to ensure harmonic content is modelled; these are staircase waveforms as

described in Chapter 2 [128]. The DC-side model is derived around power balance

principles and is represented as two current sources, one for the DC link and the other

for converter losses [129]. In typical Type 5 models there is no access to MMC

components, therefore circulating current suppression control and capacitor balancing

control is assumed to be behaving ideally [114, 124]. Additional detail has sometimes


109

been added to the Type 5 model to include repetitive capacitor voltage ripple and

circulating currents, to improve model fidelity [130, 131]. AVMs are computationally

efficient and larger time-steps in comparison to Type 4 models can be used, leading to

much shorter simulation times within the EMT simulation tool. AVMs can be used for

transient studies, simplified harmonic analysis and faster tuning of high level control

systems [123].

Type 5.5: Simplified Average Value Model (SAVM)

Type 5 MMC models can be simplified within the EMT tool by replacing the staircase

waveforms with pure sinusoids, removing the harmonic content and therefore the

ability to perform harmonic studies. For Type 5.5 models, the integration time can be

in the order of milliseconds, reducing the simulation time even further [123, 124].

Type 6: Phasor Model

Type 5.5 models can be characterised in the phasor domain by a Type 6 phasor model

[132, 133]. For the phasor model the three-phase network is assumed to be harmonic

free and balanced. These models are typically used for time-domain transient stability

analysis over medium (seconds) and long term (minutes) studies. Root mean square

(RMS) or phasor simulation tools are usually used with Type 6 models. Time-steps are

in the order of milliseconds [123].

Type 7: Power Flow Model

Type-7 is a power-flow model where the MMC is represented by an ideal controllable

voltage source based on a sequential or unified algorithm [123, 134]. An RMS

simulation tool is used for power flow simulations. Type-7 models are usually used to

calculate the power flow in multi-terminal systems with time-steps in the order of

seconds, which make them ideal for long term power system studies [125].

6.2. Simulation Model Overview

A Type 4, 31-level three-phase MMC DEM was developed by Dr. Antony Beddard [56]

using PSCAD/EMTDC. An open loop version of this DEM will be summarised in this

section, for further detail see [56, 125]. A discussion on how this MMC DEM model has

been adapted for this research will then be presented.

As mentioned in Chapter 6.1, the DEM is constructed using Thévenin equivalent

circuits (TECs) for the upper and lower arms in each phase, based on IGBTs modelled


110

as linear two-state resistances. The subroutine for the calculation of a TEC for a series

connected stack of SMs is provided by PSCAD. Figure 6.1 provides an overview of the

open-loop DEM. In the open-loop DEM, TECs of thirty half-bridge SMs are placed in

series with an additional arm resistance of 0.6 Ω ( ), to account for copper

conduction losses in the converter, and an arm inductance of 45 mH ( ), used to

suppress circulating currents and limit fault current. The SMs are taken to have a

capacitance of 1150 µF with a leakage resistance of 10 MΩ. IGBT on and off resistances

and diode conducting and blocking resistances are 10 mΩ and 1 MΩ respectively.

The MMC is connected directly to a ± 320 kV DC link (DC) modelled as an infinite bus.

A number of 25 Ω charging resistors (CR) controlled by circuit breakers (CB) limit inrush

currents from a 400 kV line-line RMS AC link ( , , ), also modelled as an infinite

bus. Power flow between the converter and AC link is measured over the per-phase

network resistance of 1 mΩ ( ) and inductance of 1 mH ( ).

Figure 6.1: Open-loop DEM overview diagram

MMC DEM31-Level 3-Phase

DC

CR

CB

CR

CB

CR

CB

Rnet

Rnet

Rnet

DC Link

DC-side AC-side

A

B

C

P

N

A

P

N

Thevenin Equivalent

Arm (30 SMs)

Thevenin Equivalent

Arm (30 SMs)

Rarm

Larm

Rarm

Larm

B

Thevenin Equivalent

Arm (30 SMs)

Thevenin Equivalent

Arm (30 SMs)

Rarm

Larm

Rarm

Larm

C

Thevenin Equivalent

Arm (30 SMs)

Thevenin Equivalent

Arm (30 SMs)

Rarm

Larm

Rarm

Larm

Veq

Req

D1

D2

S1

S2

C

R1

R2Veq

Rc

Vsm

Iarm

Ic

Vc

Vsm

Iarm

Ic

Thevenin Equivalent

VaLnet

Lnet

Lnet

Vb

Vc

AC LinkAC Network


111

Direct control of the voltage magnitude and angle of the converter output (and

therefore the power flow) is employed in the open-loop DEM. Internal voltage control

including the decoder, capacitor balancing control (CBC) (using bubble sort), and

nearest level control (NLC) is built into the model as a bespoke Fortran PSCAD block,

written by Beddard. The CBC is triggered at a frequency of 1500 Hz. The decoder and

NLC execute on every 20 µs time-step, an effective trigger frequency of 50 kHz.

The open-loop DEM model has been adapted to match the CHP constructed during this

research; system parameters have been taken from the CHP where possible. Figure 6.2

gives an overview of the CHP-DEM. The CHP-DEM simulates a nine-level three-phase

MMC in a test network. The MMC is connected to a ± 100 V DC link modelled as an

infinite bus. The CHP is charged from the DC supply via two 100 Ω CRs controlled by

CBs to limit inrush currents. A star-point passive load on the AC side is formed of three

100 Ω resistors. CRs of 15 kΩ also limit current to the AC load during charging.

TECs of eight half-bridge SMs are placed in series with an additional arm resistance of

0.45 Ω ( ), based on estimated resistances of conductors and connectors in the

CHP, and an arm inductance of 10 mH ( ). The SMs are taken to have a SM

capacitance of 3000 µF with IGBT on and off resistances of 6 mΩ and 60 MΩ

respectively and diode conducting and blocking resistances of 35 mΩ and 1 MΩ

respectively. In the CHP, an anti-parallel diode and MOSFET body diode are in parallel.

The nominal peak CHP arm current leads to a forward voltage drop on the anti-parallel

diode which is below the threshold voltage of the body diode. Therefore, in normal

circumstances the anti-parallel diode will be the only device conducting; the

characteristics for this device have been used for the CHP-DEM.

Similarly to the CHP, the simulation model can swap between grid-following and grid-

forming control using an external and internal three-phase reference. The bespoke

Fortran block containing the internal voltage control has been adapted to work with a

nine-level system. The general functionally of the driver is the same as the original

developed by Beddard [56]. The CBC is triggered at a frequency of 500 Hz. The decoder

and NLC are triggered at a frequency of 50 kHz, set by the simulation time-step.

The CHP-DEM runs through the same start-up procedure as the CHP to simulate the

converter charging process. In summary this process starts by connecting all eight SMs


112

in the upper and lower arms in all three phases. The capacitors charge to half the

nominal voltage using the DC link via the charging resistors. During the charge process

it is important to ensure that the phases remain in energy balance to avoid high levels

of circulating current. To achieve this, the upper and lower arms from each phase of

the converter are instructed to bypass one SM from their circuit, leaving seven SMs per

arm connected. This is repeated in 400 ms steps until four SMs per arm are connected,

half of the total. At this point the capacitors are charged to the nominal voltage.

Synchronous switching of SMs between phases is considerably simpler to achieve in

simulation than in hardware, though requires careful control in both cases. During the

charge process, the CBC ensures that all the SMs remain in balance. A short period

after the capacitors have reached nominal charge, the AC and DC circuit breakers open

and the system enters normal operation.

Figure 6.2: CHP-DEM overview diagram

MMC DEM9-Level 3-Phase

DC

CR

CB

CR

CB

CR

CB

AC LoadCharge Current

LimitationDC Link

External 3-Phase AC Reference

DC-side AC-side

A

B

C

P

N

A

P

N

Thevenin Equivalent

Arm(8 SMs)

Thevenin Equivalent

Arm(8 SMs)

Rarm

Larm

Rarm

Larm

B

Thevenin Equivalent

Arm(8 SMs)

Thevenin Equivalent

Arm(8 SMs)

Rarm

Larm

Rarm

Larm

C

Thevenin Equivalent

Arm(8 SMs)

Thevenin Equivalent

Arm(8 SMs)

Rarm

Larm

Rarm

Larm

Veq

Req

D1

D2

S1

S2

C

R1

R2Veq

Rc

Vsm

Iarm

Ic

Vc

Vsm

Iarm

Ic

Thevenin Equivalent

Circuit Breaker (CB)

Charge Resistor (CR)

CB


113

The two graphs in Figure 6.3 show the capacitor voltage for one SM and the sum of

capacitor voltages in one arm during the charging cycle. The DC link is 200 V and with 8

SMs per arm, the nominal SM voltage is 25 V; both set-points are reached before the

CBs are closed to bypass the charging resistors.

In addition to the CHP-DEM, a hybrid simulation model has been constructed by the

author as part of the research presented in this thesis. For the hybrid model, one

phase of the DEM has been replaced with a replica phase developed following Type 3

TDM principles, allowing for comparison between the two different models in the

same simulation. Limitations in low voltage operation of IGBTs in PSCAD/EMTDC

require this model to be a higher voltage than the CHP, which limits the comparability

with hardware and therefore will not be discussed further in this thesis.

6.3. Simulation Results

Graphs of steady state operation for the CHP-DEM with no load and a star-point

resistive passive load are provided in Figure 6.4. These results demonstrate that the

simulation model behaviour matches the theoretical operation of the MMC and can be

used for comparative analysis with the CHP. Figures 6.4 to 6.7 are simulation results

from the CHP-DEM without circulating current suppression control enabled.

Figure 6.3: Capacitor voltage in one sub-module (upper) and sum of capacitor voltages in one

arm (lower) during a charge cycle in the CHP-DEM


114

This first set of figures depicts operation of the CHP-DEM with no load connected to

the AC terminals of the MMC. The results are taken at an arbitrary time after the MMC

has fully charged (between 6.48 s and 6.52 s). The DC voltage is set at 200 V and the AC

voltage reference is set to 100 V peak phase-to-ground (amplitude modulation ratio of

1). For these results the converter is operating in grid-following mode and ground is

taken to be at the midpoint of the DC link.

The upper graph in Figure 6.4 shows an ideal nine-level three-phase output from the

CHP-DEM, following an external voltage reference which is depicted in the middle

graph. The lower graph overlays the voltage reference to the corresponding converter

voltage output to demonstrate tracking.

Figure 6.4: CHP-DEM under no-load conditions: Converter AC voltage output (upper),

external three-phase reference (middle), and reference and output for one phase (lower)


115

Returning to the theory presented in Chapter 2, the graphs in Figure 6.4 match the

expected output for an MMC with eight SMs per arm. A staircase waveform with nine

levels closely tracks and approximates the reference voltage input. As there is no load

connected to the MMC, the SM capacitor voltages remain at the nominal set-point.

Capacitor voltage ripple is caused by capacitor leakage and current flow through the

discharge resistor, both of which are negligible. Therefore, all three phases remain

very well balanced and no circulating currents flow in the converter.

Operation of the CHP-DEM with a star-point resistive passive load connected to the AC

terminals of the MMC is depicted in Figures 6.5 to 6.9. The DC voltage is set at 200 V

and the AC voltage reference is set to 100 V peak phase-to-ground. For these results

the converter is operating in grid-following mode and ground is taken to be at the

neutral point of the resistive load. Converter output voltages are measured with

respect to the ungrounded neutral point of the three-phase 100 Ω load.

The upper graph in Figure 6.5 shows the nine-level three-phase output from the CHP-

DEM under load conditions, following an external reference, in the lower graph.

Figure 6.5: CHP-DEM under 100 Ω load conditions: Converter AC voltage outputs (upper) and

external three-phase voltage reference (lower)


116

The clear staircase waveform seen in Figure 6.4 now has notches caused by switching

events on different phases, Figure 6.5. The ungrounded star-point resistive load

creates a path for current to flow between converter phases, creating a cross coupling

effect. Voltage steps at the AC terminal output of one phase, caused by nearest level

modulation, lead to a step change to the current flowing across the load resistors and

between phases. In Chapter 2 it was explained that the arm currents in an MMC are

made up of direct current, circulating current and AC current components. The AC

current is split between the upper and lower arms and flows through the arm

inductors. A step change in arm current induces a voltage across the inductor to

oppose the current change, which presents as a notch on the AC output voltage. Cross-

coupling effects are less evident is systems with higher numbers of levels because the

nominal SM capacitor voltage, representing the maximum voltage step, is a smaller

proportion of the total AC output voltage.

Figure 6.6 shows two graphs for one phase of the MMC: the upper graph is of the AC

and DC terminal currents, the lower graph is of the upper and lower arm currents and

circulating current.

Figure 6.6: CHP-DEM under 100 Ω load conditions: Converter AC and DC terminal current

(upper), upper and lower arm current, and internal circulating current (lower)


117

The upper and lower arm currents in Figure 6.6 are not sinusoidal due to the double

frequency circulating current component. If this is successfully supressed then the arm

currents are near sinusoidal with a magnitude equal to half the converter AC current

plus a DC offset.

Capacitor balancing control (CBC) ensures that the SM capacitor voltages are kept

close to the nominal voltage, 25 V in the case of the CHP. The frequency at which the

capacitor voltages are sorted impacts the capacitor voltage ripple and subsequently

wider MMC behaviour. Figure 6.7 shows the capacitor voltages for the upper arm of

phase A over two fundamental cycles. A CBC frequency of 800 Hz is used, equal to the

effective switching frequency of the nine-level converter. In this case, the SMs are well

balanced, the circulating currents are sinusoidal and the DC current is stable.

Figure 6.7: Sub-module capacitor voltages for the upper arm of phase A using a capacitor

balancing frequency of 800 Hz (upper), the resulting circulating currents (middle) and DC

terminal current (lower) in the CHP-DEM


118

In Figure 6.8, the CBC frequency has been reduced to 250 Hz. Capacitor voltage ripple

has increased to ±1.6% in comparison to ±1% using an 800 Hz balancing frequency. The

frequency of sorting changes the point-on-wave (POW) at which the sort is carried out,

which alters the effectiveness of CBC. At low frequency sorting, CBC trigger

discrepancies between phases can lead to significant variation in stored charge in the

converter arms. Circulating current increases and distorts due to this variation, which

in turn causes DC current to fluctuate. An example of this is provided in Figure 6.8. The

circulating currents are no longer free from harmonics and vary significantly in

magnitude. In a closed loop system the circulating current suppression control (CCSC)

would be used to minimise the circulating currents to reduce losses, improve capacitor

balancing control and reduce the observable effect on the DC link [87, 120].

Figure 6.8: Sub-module capacitor voltages for the upper arm of phase A using a capacitor

balancing frequency of 250 Hz (upper), the resulting circulating currents (middle) and DC

terminal current (lower) in the CHP-DEM


119

A study into the impact of CBC sorting frequency on the DC link current is shown in

Figure 6.9 for integer multiples of the fundamental frequency on the CHP-DEM. This

study identifies that for best performance on a balanced three-phase system, low rate

sorting should be carried out at an integer multiple of three times the fundamental

frequency so that sorting occurs at the same POW for each phase. It is evident from

Figure 6.9 that the fluctuation in DC current is at a frequency equal to the CBC trigger

rate. At higher sorting rates the variation of DC current reduces significantly.

Figure 6.10 shows the behaviour of the CHP-DEM under 1 kW resistive loading

conditions; the nominal rated operating point for the CHP. The voltage steps now lead

to larger steps in current flowing between phases. For a 1 kW load, the RL circuit

created by the load resistance and arm inductor has a larger time constant, slowing the

current rise and fall times at the output. This effect can be seen as smoother voltage

transitions across the load resistors. Slowed voltage transitions lead to phase and

magnitude error between the reference and converter output, as seen in Figure 6.10A.

Figure 6.9: Impact on DC current for varying CBC trigger frequencies (800 Hz to 150 Hz) in the

CHP-DEM


120

The increase in load from 150 W (100 Ω) to 1000 W (15 Ω) increases the upper and

lower arm currents proportionally, Figure 6.10C, which in turn leads to an increased

variation in SM capacitor voltage ripple, Figure 6.10D. In Figure 6.7, with the MMC

feeding a 150 W load, the capacitor voltage error is ±1% from the nominal. In Figure

6.10D, with the MMC feeding a 1000 W load, the capacitor voltage error is ±6%.

Appendix B provides an analytical method to calculate the capacitor voltage ripple for

a particular SM capacitance and MMC power rating. An estimate of ±4.6% ripple was

calculated for a 1 kW load. The discrepancy between these figures exists because the

Figure 6.10: CHP-DEM 15 Ω load conditions: Converter AC voltage outputs (A), AC and DC

current outputs (B), internal upper and lower arm currents (C), and sub-module capacitor

voltages for the upper arm of phase A using a capacitor balancing frequency of 800 Hz (D)


121

analytical method makes a number of assumptions, one of the more significant of

which is that the CCSC works perfectly. When using a non-ideal CCSC on the CHP-DEM

the capacitor voltage ripple reduces to ±4.7%, much closer to the analytical value.

6.4. Additional Simulation Studies

A study into the impact of sorting algorithm choice on capacitor balancing control

voltage sorting statistics was carried out using data from the original DEM model

developed by Dr. Antony Beddard [56]. Capacitor voltage data for the upper arm of

one phase was collected over ten seconds of steady state and transient operation. The

data was then passed through variations of bubble sort and merge sort to analyse how

different algorithms impact the number of swaps and comparisons required while

sorting the data from largest to smallest. The difference in sorting complexity

depending on the POW at which the sort is carried out is also investigated.

The capacitor voltage sorting poses a significant challenge for industrial converters

with hundreds of SMs per arm. Therefore the choice of sorting algorithm impacts the

frequency at which the CBC can be triggered, and the computational power required

to carry out the algorithm.

This work forms part of a conference paper presented at the IEEE Southern Power

Electronics Conference (SPEC 2017) titled “Capacitor Balancing Controller Voltage

Sorting Statistics in Modular Multilevel Converters” by T Heath, P R Green and M

Barnes from the University of Manchester, and P Coventry from National Grid [67].

Studies are on-going to provide a side-by-side analysis of sorting performance for

algorithms presented in literature in the field of VSC-HVDC.

6.5. Summary

This chapter has provided an overview of modular multilevel converter simulation

models with varying degrees of fidelity. A Type-4 detailed equivalent model of an MMC

described and validated in [56] has been adapted to closely represent the converter

hardware prototype described in Chapters 3, 4 and 5. Simulation results from the

converter hardware prototype detailed equivalent model for a few different operating

modes have been provided and explained. In general the CHP-DEM results match the

expected behaviour following the theory presented in Chapter 2. This simulation data

will be compared against hardware results in the following chapter.

Comparison of Simulation and Hardware

122

Comparison of Simulation and Hardware 7.

In this chapter a number of the simulation studies presented in Chapter 6 are repeated

on the nine-level three-phase converter hardware prototype (CHP) constructed during

the research. Differences between the simulation and hardware results are discussed,

especially regarding the time delays caused by measurement systems and internal

converter control loops. Whole system diagrams for the CHP and detailed equivalent

model are used to clearly describe where the time delays exist and how these delays

could impact control of the converter. Literature discussing time delays within an MMC

is also reviewed and used to support the findings presented in this thesis.

7.1. Hardware Results

Graphs of steady state operation for the CHP with no load and a star-point resistive

load are provided in this section. The results presented are to demonstrate how the

converter hardware prototype compares to the theoretical operation of the MMC and

the simulation results obtained from the detailed equivalent model.

The first set of graphs, presented in Figure 7.1, depict operation of the CHP with no

load connected to the AC terminals of the MMC. The DC voltage is set at 200 V and the

AC voltage reference is set to 100 V peak phase-to-ground (amplitude modulation ratio

of 1). For these results the converter is operating in grid-following mode and ground is

taken to be at the midpoint of the DC link.

A three-phase external reference is generated by two synchronised function

generators. The three references are then sampled by the NI PXI-6363 digital

acquisition (DAQ) card for use by the phase-locked loop (PLL) in the CHP. The reference

for phase A from the function generator is also sampled by an oscilloscope which is

used to measure the CHP AC terminal outputs. This enables measurements taken by

the NI system to be matched with samples taken by the oscilloscope. A measurement

taken by the oscilloscope will be labelled as externally sampled (ES) and a

measurement taken by the DAQ will be labelled as internally sampled (IS).

The upper graph in Figure 7.1 shows the nine-level three-phase output waveform from

the CHP (ES) following the three-phase reference (IS) (neglecting sampling delay)

depicted in the middle graph. The lower graph overlays the voltage reference (ES) to

the corresponding converter voltage output (ES) to demonstrate tracking.


123

Returning to the theory presented in Chapter 2, the graphs in Figure 7.1 match the

expected output for an MMC with eight SMs per arm. A staircase waveform with nine

levels closely tracks and approximates the reference voltage input. As there is no load

connected to the MMC, the SM capacitor voltages remain close to the nominal set-

point of 25 V, discharging slightly due the resistor in parallel with the SM capacitors

and inherent capacitor leakage. Distortion in the reference voltages, Va*, Vb* and Vc*,

are due to synchronisation problems between the external function generators.

In Figures 7.2 and 7.3 the CHP is operating with a star-point resistive load connected to

the AC terminals of the MMC. The DC voltage is set at 140 V and the AC voltage

reference is set to 70 V peak phase-to-ground. For these results, the converter is

operating in grid-following mode. Converter output voltages in Figure 7.2 are

measured with respect to the ungrounded neutral point of the 200 Ω per phase

resistive load.

Figure 7.1: CHP under no-load conditions: Converter AC voltage outputs (upper), external

three-phase reference (middle), and reference and output for one phase (lower)


124

The upper graph in Figure 7.2 shows the nine-level three-phase voltage output from

the CHP under load conditions (ES), following an external reference depicted in the

middle graph (IS) (neglecting sampling delay). The AC output current through the load

is shown in the lower graph (IS). The output voltages from the hardware, shown in

Figure 7.2, exhibit similar notching to the output voltages from simulation, shown in

Figure 6.5. This further demonstrates the cross coupling effect within MMCs with small

numbers of levels when using an ungrounded star-point load.

Measurements of SM voltages, dc current, upper and lower arm currents and phase

currents need to be accurate to effectively to control an MMC. A number of Hall-Effect

sensors (HES) have been used in the CHP to measure the internal converter currents.

HES measure the magnitude of the magnetic field caused by current flow through a

conductor, and output a low magnitude voltage linear to the current for analogue-to-

Figure 7.2: CHP under 200 Ω load conditions: Converter AC voltage outputs (upper), external

three-phase reference (middle) and converter AC current output (lower)


125

digital conversion. HES require a stable supply voltage for accurate measurements and

are sensitive to electromagnetic interference (EMI). The power supply used for the HES

is also supplying the fibre-optic breakout board and the distributed control units

(DCUs). Common mode noise from the other devices leads to fluctuation on the supply

rail which is subsequently interpreted as current variation. Power electronic converters

create significant EMI due to semiconductor switching which couples to the sensors,

degrading measurement accuracy. Examples of this noise can be seen in the lower

graph of Figure 7.2. A regulated or independent power supply and EMI shielding

gaskets for the HES would significantly improve the accuracy of current measurement.

The test for Figure 7.2 has been repeated using an external current probe for phase

current measurement to reveal the significance of noise on the HES output voltage.

This is shown in Figure 7.3 for phase A in the CHP. In Figure 7.3 the phase A output

voltage and reference voltage are plotted on the left y-axis (ES), and the phase current

is plotted on the right y-axis (ES). The phase current very closely tracks the phase

voltage as the star-point load is purely resistive (neglecting parasitic inductance). In

comparison to the current measurements taken by the HES, shown in Figure 7.2, the

measurements using the current probe, shown in Figure 7.3, contain significantly less

noise and demonstrate expected converter behaviour.

Figure 7.3: CHP under 200 Ω load conditions: Converter AC terminal voltage and reference

voltage (left axis), and AC terminal current (right axis)


126

Figure 7.4 shows the CHP measurements of arm currents for phase C under load when

subject to three different DC link voltages (ES). In general the arm currents match the

expected behaviour from theory and simulation with a clear double frequency

circulating current component, and an increasing network frequency current

component and increasing DC current component as the power level increases.

However, the arm currents become more distorted as the power level rises due

increasing circulating currents and a varying DC current, due to DC supply dynamics.

The upper graph in Figure 7.5 shows the nine-level AC voltage reference and output for

phase A of the CHP under load conditions (ES) and the lower graph is of DC terminal

voltage and current (ES). High frequency transients in the DC current correspond to SM

switching in the converter. Figure 7.6 is the DC terminal voltage and current for the

CHP-DEM after an AC supply has been added in series with the DC supply; this exhibits

the impact of minor voltage fluctuations (less than 1%) on DC current.

Figure 7.4: CHP under 200 Ω load conditions: Upper and lower arm current for phase C with

a DC link voltage of 40 V (upper), 80 V (middle) and 140 V (lower)


127

Unlike simulation, the DC link for the converter hardware prototype is not an infinite

bus. As the CHP draws current from the supply, the bus voltage drops and the DC

supply internal regulator actuates to maintain control of the DC voltage, this causes

voltage ripple at the supply terminals which then leads to a change in current drawn by

the converter. Very small fluctuations in voltage can cause significant DC current

Figure 7.5: CHP under 100 Ω load conditions: AC reference and terminal voltage (upper), and

DC terminal voltage and current (lower)

Figure 7.6: CHP-DEM (replica simulation model) with DC voltage fluctuation under 100 Ω

load conditions: DC current and voltage


128

variation between the supply and the CHP as seen in Figure 7.6. Connecting the CHP to

a DC supply with an improved regulator, or the addition of a DC link capacitor, may

help to alleviate this voltage fluctuation, and potentially damp this dynamic.

Capacitor balancing control (CBC) is implemented on the PCU of the CHP. The CBC is

triggered at 500 Hz in the CHP; faster trigger rates will result in reduced capacitor

voltage error, but will increase the frequency of SM switching. The CBC implemented

on the CHP has no limit to the number of SMs that can be swapped at a level change.

As discussed in Chapter 5, the PCU FPGA is limited in space and the core control

program requires almost all of the FPGA resource. This limitation means that there is

insufficient spare FPGA resource to implement a direct-memory access module

between the PCU FPGA and the real-time central control unit (CCU-RT). SM capacitor

voltages which are balanced by the CBC are not directly accessible, or stored, and

therefore cannot be compared against the simulation results presented in Chapter 6.

In order to demonstrate the functionality of the CBC implemented on the CHP, two

graphs of AC voltage output with and without CBC are presented in the upper and

lower graphs of Figure 7.7 respectively (ES). The CHP is tested using a DC link voltage of

30 V and a 200 Ω star-point resistive load. Without CBC, the SM capacitors become

unevenly charged and the AC output voltage is heavily distorted. Given enough time,

one SM in the upper and lower arm of each phase will charge to the DC link voltage

and the converter will behave like a two-level converter modulated at low frequency.

There are a number of other differences in the converter hardware prototype to the

detailed equivalent model. One difference is that in simulation all of the SMs are

switched simultaneously; as one SM turns off, another turns on, constantly

maintaining DC and AC voltage balance. Whereas in the CHP, while the phase control

unit (PCU) transmits switch signal data to all the DCUs simultaneously, a number of

time delays exist between the PCU sending the signals and the SM switches receiving

them. There are differences in the propagation delays through the electro-optical

interfaces of fibre-optic communication and MOSFET gate-driver hardware. Packets

sent from the PCU along multiple paths therefore encounter varied propagation

delays, and as the DCUs do not share a clock, there is no mechanism to synchronise

the switch outputs. In practice the theoretical maximum delay between SMs switching

in the CHP is close to 250 ns and therefore has very little effect on MMC performance.


129

Converters with a small number of levels, such as the CHP constructed during this

research, would not normally operate using nearest level modulation, as the AC

voltage output has considerable harmonic content when using less than 15-levels in a

distribution network [88], or 31-levels in an HVDC network [56]. Instead, alternative

strategies such as level-shifted pulse-width modulation, phase-shifted pulse-width

modulation or space-vector modulation would synthesise an AC output with improved

harmonic performance [31]. This research focusses on industrially representative

control and therefore nearest level modulation is used to provide comparable results.

Any future research which requires the CHP to be connected to an active AC network

will need development time to redesign the modulation strategy. Additionally, the

circulating current suppression control (CCSC) loop and dq current control loop will

need to be closed and tuned to ensure stable operation of the converter.

It is important to note that the CHP was designed to assess industrially representative

internal control and communication within a modular multilevel converter, in order to

improve power systems models for network operators.

Figure 7.7: CHP-DEM under 200 Ω star-point resistive load: Converter AC voltage outputs

with CBC (upper) and without CBC (lower)


130

7.2. Delay Assessment

Typical power systems simulation tools, such as those described in Chapter 6, simplify

operation of modular multilevel converters by overlooking detailed timing effects. In

reality, time is taken for control calculations to be made and data to be communicated

between controllers. The principal output from this research is the characterisation of

the delays caused by internal converter controllers in an industrially representative

distributed control architecture, such as the one used on the CHP.

The upper and middle graphs in Figure 7.8 are the AC voltage output against the

reference input in simulation (CHP-DEM) and hardware (CHP) respectively. The lower

two graphs are magnified sections of the simulation (left) and hardware (right) results.

Figure 7.8: CHP under no-load conditions: CHP-DEM simulation phase A voltage reference

and output (upper), CHP hardware phase A voltage reference and output (middle), and

magnified sections of the previous graphs (lower-left and lower-right respectively)


131

The theory presented in Chapter 2 described the nearest level modulation used for the

modular multilevel converter. Equation 2.29 (replicated here for ease) is the function

used to discretise the reference voltage into a staircase waveform with level changes

equal to the nominal capacitor voltage.

*

*

ref

on

cap

VN round

V

2.29(2)

Ideal transitions occur halfway between each discrete step following Equation 2.29.

Therefore, a nine-level converter with a 200 V peak-to-peak AC reference will have a

nominal capacitor voltage of 25 V and level changes at ±12.5 V, ±37.5 V, ±62.5 V and

±87.5 V, this ideal behaviour is demonstrated in the upper graph of Figure 7.8. A

maximum time delay equal to the solution time-step exists in simulation; for the CHP-

DEM this is 20 µs. For the hardware results in the middle graph, with a 70 V peak-to-

peak AC reference, the level changes should occur at ±8.75 V, ±26.25 V, ±43.75 V and

±61.25 V. However, in reality, there is an observable time delay between the ideal level

change and actual level change. This delay is the total system delay (TSD) for the MMC,

combining different sampling, communication, calculation and control loop delays. The

lower-right graph in Figure 7.8 has been enlarged for Figure 7.9; with two

measurements for the TSD identified at the level changes of 8.75 V and -8.75 V.

Figure 7.9: Time delay between reference input and voltage output from system controller


132

As the CHP is operating in open-loop, there is no controller to bring the MMC output

exactly in phase with the reference. Open-loop operation is required to be able to

identify the TSD clearly. An initial analysis of data from the CHP provided 120

measurements for TSD. For these tests the CHP was subjected to three different DC

link voltages of 40 V, 80 V and 120 V and measurements of time delay were taken by

eye from the raw data at every expected level change following the technique shown

in Figure 7.9. The graph in Figure 7.9 shows two measurements for TSD that have

coincidentally aligned the reference input and voltage output, this is not by design.

A histogram of this data is plotted in Figure 7.10. A mean average TSD of 426 µs was

calculated for these measurements with a maximum delay of 1030 µs and a minimum

of 100 µs. The midpoint between quantisation values was taken as the ideal level

change time as this was a clear measurement point. However, this point could be

100 µs away from the first recorded measurement of the desired voltage. Therefore

the results shown in Figure 7.10 have an error 0 to +100 µs.

A further set of tests using the oscilloscope to identify the desired voltage, compared

the expected level change time from the reference voltage input (ES) to the actual

level change time at the converter voltage output (ES). The tests acquired statistics for

a total of 2,500 measurements. Each test measured the TSD at a specific level change

Figure 7.10: Histogram of time delay between reference input and voltage output from

system controller over three no-load tests at different output voltages


133

for 500 cycles while the CHP was subjected to a DC link voltage of 40 V. The level

changes used for the test were at ±6.25 V and ±1.25 V. A minimum and maximum TSD

of 142 µs and 1159 µs respectively, and an average of 440 µs were measured using this

technique. The raw measurements (with error) and the oscilloscope statistics are

closely matched and show a significant range of over 1000 µs.

A number of different time delays combine to form the TSD. The delays exist along the

critical data path in the CHP, from measurement of the voltage reference though to

firing of the switches; a diagram depicting the critical path is shown in Figure 7.11. In

order to better understand the TSD and the variation exhibited by the CHP, it needs to

be broken down into constituent parts. Figure 7.12 provides an overview diagram to

show this separation. Delays t_rt through t_d represent the individual delays which

form the TSD, taken between the ideal level change, t0, and actual level change, t1.

Figure 7.11: Critical data path in the CHP

CC

U (R

T CP

U)

DC

U

SM

Valve Hall

Server Room

LCB

DC

U B

reako

ut

FOB

Fibre

B

reako

ut

MMC Reference

CC

U (FP

GA

)

PC

U

DA

Q

Switch Modulation

DAQ Trigger

DAQ Data

NLC

DCU Data

Switch Signals


134

t_rt: CCU-RT control loop latency and execution time which relies on data from the

digital acquisition (DAQ) card. The DAQ sampling time, DAQ to CCU-RT data transfer

delay and CCU-RT to CCU-FPGA DMA access time is also included in this time delay.

Control loops (naming convention from Chapter 5) on the critical path include:

- CCU-FPGA Control: A timed-loop trigger rate, referred to as control latency (CL),

of 250 µs, with a critical path execution time (CET) of 100 µs.

The LabVIEW real-time controller timed-loop is not completely deterministic,

finishing late approximately 3% of the time. This is likely due to limited

computational resource and data access arbitration. When late, the timed-loop

discards missed periods and maintains the original execution phase, leading to

an additional latency delay in multiples of 250 µs. The highest execution time

for over 1 million loop iterations was 745 µs, i.e. indicating a maximum CL of

750 µs.

t_cf: CCU-FPGA control loop latency and execution time which relies on updated data

from the CCU-RT. The calculation time for the PLL, abc to dq and dq to abc

transformations, reference decoding, nearest level control and packet building is

included in this delay. Control loops on the critical path include:

- DMA: CL of 100 µs and a CET of 200 ns

- PLL. abc to dq and dq to abc: CL of 25 µs and a CET of 8.8 µs

- NLC and Decoder: CL of 50 µs and a CET of 1.2 µs

- Packet Builder: CET of 200 ns

Figure 7.12: Total system delay overview

t_rt t_cf t_cf2p t_p t_d

Total System Delay (TSD)

Ideal Level Change

t0 t1

t0 t1

TSD

Vo

ltag

e

TimeActual Level

Change

t_p2d


135

t_cf2p: CCU-FPGA to PCU packet communication delay, including copper and hardware

propagation time. The critical path includes:

- Packet transfer time: 7 µs

- Signal propagation time: 5 ns

t_p: PCU control loop latency and execution time which relies on updated data from

the CCU-FPGA. The calculation time for UART receivers, nearest level control and

packet building is included in this delay. Control loops on the critical path include:

- UART receiver: CET of 200 ns.

- NLC: CL of 200 µs and a CET of 7.8 µs.

- Packet Builder and Parity Calculator: CET of 2.3 µs.

t_p2d: PCU to DCU packet communication delay, including copper, fibre and hardware

propagation time. The critical path includes:

- Packet transfer time: 6.4 µs.

- Signal propagation time: ~175 ns

t_d: DCU program execution time which relies on control data and switch signals from

the PCU. The DCU data input to switch signal output and hardware propagation delays

are included in this delay.

- Parity Check, Translator, DT and FP: CET of 160 ns.

- Signal propagation time: 600 ns

Figure 7.13 provides a scaled plot of time delays constituting the TSD; it is clear that a

significant portion of TSD is formed of control loop latency, rather than execution time.

The best-case TSD includes the critical execution time for each loop without any

latency; this assumes that updated data at the output of one loop is immediately used

by the following loop on the critical execution path. The calculation for the best-case

TSD is shown in Equation 7.1. The nominal worst-case assumes that the loops all

execute within the allocated time but the data output of one loop is ready immediately

after the data dependant loop has checked for new data, leading to maximum control

loop latencies. The calculation for the nominal worst-case TSD is given in Equation 7.2.

The timed-loop fails to complete within the allocated 250 µs in approximately 3% of

loop iterations. The actual loop latency can increase to 750 µs, leading to the absolute

worst-case TSD calculated using Equation 7.3.


136

2 2b rt cf cf p p p d dTSD t t t t t t 7.1

2 2w rt rtcl cf cfcl cf p p pcl p d dTSD t t t t t t t t t 7.2

2 23aw rt rtcl cf cfcl cf p p pcl p d dTSD t t t t t t t t t 7.3

Following Equations 7.1, 7.2 and 7.3 the best-case TSD is 135.1 µs, the worst-case TSD

is 760.1 µs and absolute worst-case is 1260.1 µs. These analytical values for TSD match

the measured response from the CHP hardware seen in Figure 7.10 and from the

oscilloscope statistics.

To further demonstrate how control loop latency impacts TSD, the nearest level

control (NLC) loop in the PCU, forming part of the critical execution time t_p and the

control latency t_pcl, was increased from a trigger rate of 5 kHz to 20 kHz; reducing

t_pcl from 200 µs to 50 µs. The oscilloscope was used to analyse 500 TSD

measurements between the ideal level change and actual level change at 1.25 V. A

minimum and maximum TSD of 137 µs and 870 µs respectively, and a mean of 341 µs

were measured using this technique. In comparison to NLC at 5 kHz the minimum TSD

remains largely unchanged from 142 µs, whereas the average TSD with NLC at 20 kHz

is 100 µs lower than the TSD with NLC at 5 kHz, an expected drop following a reduction

in the worst-case by 150 µs. The maximum TSD with NLC at 20 kHz was also lower,

however, the absolute worst-case may not have presented in the smaller sample size.

Figure 7.13: Total system delay breakdown in the converter hardware prototype

t0

t1

0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300

Time (µs)

t_rt

t_rtcl x 3

t_cf

t_cfcl

t_cf2p

t_p

t_pcl

t_p2d

t_d

Time-Delay (µs)t_rt = 100.0t_rtcl = 250.0t_cf = 10.4t_cfcl = 175.0t_cf2p = 7.0t_p = 10.3t_pcl = 200.0t_p2d = 6.6t_d = 0.8


137

Substantial reductions in the average and worst-case delay can be made through

controller redesign in the CHP. Presently the controller hardware operates multiple

concurrent control loops, enabling independent control of trigger frequency for each

loop. However, the addition of data dependency paths between controllers, or specific

timing design for control loop execution, would ensure that updated data is used as

soon as it is available. This would significantly reduce, or completely remove the t_fcl

and t_pcl time delays.

More powerful CCU-RT hardware would also enable a reduction in t_rtcl, and t_rt

delays; especially if more deterministic operation is guaranteed. These changes to the

CHP could potentially limit the absolute worst-case TSD to around 250 µs and the best-

case TSD to 100 µs (assuming a CCU-FPGA Control trigger rate of 10 kHz). If an internal

reference is used, the TSD is reduced even further by removing t_rt and t_rtcl delays

from Equations 7.1, 7.2 and 7.3, leading to a best-case TSD of 35 µs. Improved

telecommunication hardware could reduce this to below 25 µs. Currently a data

dependant path through the CHP would leave only the critical execution path and

digital acquisition latency, determined by the sampling period, leading to a TSD

between 135.1 µs and 385.1 µs, as shown in Figure 7.14.

Figure 7.14: Best-case total system delay breakdown in the converter hardware prototype

0 100 200 300 400

Time (µs)

t0

t_cf

t_rtclsampling period

t_cf2p

t_p

t1

t_p2d

t_d

t_rt

Time-Delay (µs)t_rt = 100.0t_rtcl = 250.0t_cf = 10.4t_cf2p = 7.0t_p = 10.3t_p2d = 6.6t_d = 0.8

50 150 250 350


138

An industrial scale converter is likely equipped with significantly more powerful

hardware which is programmed for highly deterministic behaviour using greater levels

of parallelism; this would enable faster communication rates and reduced program

execution times. However, an industrial converter also has significantly more data to

communicate between controllers on the critical path, and a larger computational

requirement for additional controllers such as capacitor balancing control. The digital

acquisition system, PLL design and computational hardware for industrial MMCs is not

documented in the public domain and therefore industrial data on TSD is limited.

The book, “Design, Control, and Application of Modular Multilevel Converters” written

by employees of ABB and Statoil and leading researchers in MMC design at Sweden’s

KTH Royal Institute of Technology, discusses TSD in the context of industrial converter

design [31]. In [31] the TSD (referred to as total time delay) is identified as equal to, or

“in the same order of magnitude as” the period set by the sampling frequency. The

example given in Chapter 3, page 154 in [31] assumes a sampling frequency of 10 kHz,

leading to an estimated critical execution time in the order of 100 µs. When including

the sampling period at 10 kHz, this is equal to a TSD between 100 µs and 200 µs. A 10

kHz sampling rate on the CHP would reduce t_rtcl to 100 µs, leading to TSD between

135.1 µs and 235.1 µs. The values to TSD gathered from [31] corroborate the findings

of this research and highlight that the best-case TSD of 135 µs from the CHP is a

reasonable representation of industrial converter behaviour. The authors in [31] go on

to state that the TSD is “not generally negligible” in the selection of closed loop system

bandwidth, clearly highlighting the need for a more detailed breakdown of this delay

to be provided, as presented in this thesis.

Very little public-domain research into time delays within MMCs has been undertaken,

despite the potentially significant impact on transient performance and limitations on

control loop bandwidth. In [135], methods to compensate TSD (referred to as system

time delay) are considered. A suggested solution involves setting a minimum sampling

frequency based on the maximum switching frequency of the converter. For MMCs

with 200 SMs per arm, with a conservative SM switching frequency of 150 Hz, an

effective switching frequency of 60 kHz is observed, requiring a minimum sampling

frequency of equal magnitude or higher for the optimal design method. This paper also

based the TSD analysis on a centralised control structure, neglecting additional


139

communication and control delays when using a distributed architecture. The

equivalent measurement for t_rt and t_cf in [135] (STD-AC and STD-DSP respectively)

are similar and further corroborate the overall findings in this thesis. The method

presented in [135] reduces the latency in digital acquisition. However, it will not

reduce or mitigate the impact of critical execution time, especially during transients.

The paper “Modeling and Current Control of Modular Multilevel Converters

Considering Actuator and Sensor Delays” written by researchers from the Technical

University of Kaiserslautern and Siemens, consider TSD (referred to as actuator and

sensor delays) in the modelling and control of MMCs [136]. In [136] a sampling

frequency of 25 kHz is assumed, equal to a sampling loop latency of 40 µs. In the

analysis two sampling instants are considered for actuator delay and four sampling

instants for sensor delay, equal to 80 µs and 160 µs respectively. A method to

compensate for the sensor delays in steady state is proposed, but transient behaviour

is still subject to response time limited by the TSD [136]. In the CHP, system voltages

are measured using high-frequency differential probes which respond to input changes

in approximately 20 ns; this is a small sensor delay and is therefore omitted from the

TSD analysis for the CHP. The measurement of extra-high voltages in the 400 kV power

transmission range, is not generally negligible as additional delay is introduced from

the instrument transformer and digital interfaces [136]. Any potential sensor delays

should be incorporated into the TSD under t_rt.

The authors in [137] incorporate a time delay block into a continuous simulation model

for an MMC similar to the Type 4 DEM discussed in Chapter 6. A TSD of 125 µs is

included to improve model fidelity. A 125 µs delay is also used in [138]. Both of which

closely match the results gained from the CHP in this thesis.

In wider research, such as [139], time delays associated with an 201-level MMC using a

fully distributed architecture are discussed. The communication architecture is based

on an EtherCAT ring network running between all the DCUs in an arm. The DCUs

handle capacitor balancing control and modulation locally, using data cycled between

controllers. A 1000 µs cycle time for the EtherCAT network is required to pass data

between the 400 SMs in a phase. Therefore the TSD in this case is a minimum of

1000 µs, plus reference sampling time and analogue to digital conversion.


140

In general the open access publications discussing TSD in an MMC discuss the impact

of TSD on MMC control but provide no specific breakdown or detail about how the

delay is formed. An initial breakdown is provided by [135], but the architecture used

for the assessment does not fully reflect industrial converter design and proposes

unrealistic sampling frequencies for mitigation.

The measured values for time delay components of TSD from the CHP may not be an

entirely accurate reflection of industrial converter performance. However, the

breakdown does identify where the time delay components exist in an MMC. It also

confirms the existence of a total system delay significant enough to be included in

power systems simulation models. In a nested control structure, such as the one used

for an MMC described in Chapter 2, an outer control loop should be four to ten times

slower than the loop that it feeds in to [85]. In the case of the CHP, with controller

redesign, the current and internal voltage control loops would require between 135 µs

and 385 µs to complete. Considering the best-case, with a 10 kHz sampling frequency,

surrounding control loops would be limited to a bandwidth of 425 Hz (if ten times

slower). Steady state operation will not be significantly impacted by this controller

limitation, or the total-system delay, however, transient performance will be affected.

It is important to know the TSD of a particular converter design before performing

power system studies to accurately simulate converter performance. The TSD should

form part of the model delivered by the manufacturer, or be explicitly provided, to be

incorporated into the power system simulation tool, as in Figure 7.15.

A 140 µs delay has been added at the output of the decoder in the CHP-DEM (140 µs is

the closest integer multiple of the critical execution time in Figure 7.15 using a 20 µs

simulation time-step) and a 4 kHz sampler, equal to the sampling frequency used for

digital acquisition on the CHP, provides a representative voltage measurement. This

results in a fixed critical execution time delay and a variable sampling delay.

Figure 7.15: State-block diagram for power control with TSD

MMC ≠ 1e-sT = 135 µs

≈1PI

CurrentVoltage

Idq* IdqPQ*Σ 3Vnd

2PQ

±


141

Figure 7.16 is an adapted version of Figure 7.8; in Figure 7.16 the simulation graphs

have been replaced with results including TSD, the hardware results remain the same.

By following this simple method to include TSD in the model, the simulation results

now largely match the output waveform of the hardware.

7.3. Detailed System Overview

An overview diagram describing the detailed equivalent model from Chapter 6 is

presented in Figure 7.17. A matching diagram is presented for the converter hardware

prototype constructed during this research in Figure 7.18. The TSD breakdown has

been included in Figure 7.18 to further demonstrate the location of time-delays within

a converter.

Figure 7.16: CHP under no-load conditions: CHP-DEM simulation with TSD phase A voltage

reference and output (upper), CHP hardware phase A voltage reference and output (middle),

and magnified sections of the previous graphs (lower-left and lower-right respectively)


142

Figure 7.17: Detailed equivalent model full overview diagram with no TSD

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143

Figure 7.18: Converter hardware prototype full overview diagram with best-case TSD

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144

7.4. Summary

In this chapter the nine-level three-phase converter hardware prototype constructed

during the research has been compared against a corresponding detailed equivalent

simulation model built in PSCAD/EMTDC. In general the CHP operation matched the

theoretical and simulation results. There are many improvements which would further

increase the usefulness of the CHP for future power systems research, some of these

will be discussed in the future work section of Chapter 8. The time delay associated

with a control and communication structure representative of industrial scale

converters has been investigated. Open literature supports the findings presented in

this thesis and shows that the breakdown and analysis of total system delay has not

previously been carried out in public research, clearly highlighting the novelty in this

research. Overview diagrams comparing the simulation and hardware help to locate

the delays and provide far greater clarity on the internal workings of modular

multilevel converters.

Conclusion and Future Work

145

Conclusion and Future Work 8.

In this chapter the main outcomes from the research will be summarised. Future work

identified during the course of the research will be discussed along with potential

future research avenues.

8.1. Conclusion

The aim of this thesis was to provide insight into modular multilevel converter control

and operation, especially with regards to recommending improvements to power

systems models for more accurate simulation studies. In order to achieve this aim, the

following objectives were identified:

1) Design and construct a reduced scale hardware prototype of a modular

multilevel converter with an industrially representative control platform

2) Design and program a real-time representative control and communication

structure

3) Design and construct a detailed equivalent model replica of the reduced scale

hardware prototype

4) Compare, analyse and critically assess control and telecom constraints between

hardware and simulation and identify potential inaccuracies in power systems

simulation tools

All of these objectives have been met during this project.

For commercial reasons, very little information is available in the open-literature about

the internal control and communication within industrial scale modular multilevel

voltage-source converters. This lack of public-domain knowledge is a risk for utilities,

when often the main priority is the security and stability of power supply. Without

accurate simulation and testing prior to introducing new technology to the National

Grid, the network may become unstable. The fidelity of these studies relies on the

fidelity of simulation model used to represent the converter, which presently only

model hardware nonlinearities and realistic converter behaviour to a degree.

There was therefore an urgent need for the development of a low-power reduced-

scale hardware model of a modular multilevel converter with an industrially

representative control architecture. This system would open up the opportunity for


146

internal converter dynamic investigations and pave the way for future VSC-HVDC

research. This potentially improves the accuracy of power network simulation and

helps to ensure that future connections are appropriately and accurately tested before

commissioning.

To this end, a nine-level three-phase laboratory scale modular multilevel converter

hardware prototype (CHP) has been designed, constructed, programmed and tested as

a fundamental part of this research. The CHP is controlled using a variety of equipment

which forms a distributed control architecture which is representative of industrial

scale converters. The CHP control system architecture was informed by open literature

and face-to-face conversations with industry. Very few hardware models exist in

academia and even fewer incorporate distributed control. The CHP therefore provides

an excellent platform for continued novel research into MMCs. Details on the

development of the CHP were published at conference, providing support to other

researchers keen on improving or replicating the experiments, and all designs and

code is available to the public from the supplementary online repository [49].

A nine-level three-phase CHP-DEM was created using a verified 31-level three-phase

DEM developed by Antony Beddard [56]. Parameters from components used in the

CHP were incorporated into the simulation model to provide a suitable replica model

for comparison against hardware. Comparison between the hardware and simulation

identified a delay between the timing of ideal level changes in simulation and the

actual level changes observed in hardware. The measured TSD for the CHP fell

between 140 and 1100 µs, but a control system redesign would bring this between 135

– 385 µs. Similar values for TSD are given in literature, corroborating these findings and

suggesting that an industrial scale MMC would have a TSD in a similar range in the

order of 100-200 µs.

MMC models should incorporate sampling delays and control system computational

delay for accurate results, especially when carrying out studies on transient

performance and fault response. In higher fidelity simulation models (such as DEMs)

the sampling delays can be incorporated as fixed frequency sampler blocks and the

computational delays as either distributed or aggregated blocks depending on the

detail required by the simulation. Models with lower fidelity (such as AVMs) should

take into consideration system delays when setting outer loop controller bandwidths.


147

This is to ensure that the hardware system has adequate time to respond to set-points

and network transients for system stability.

Utilities performing MMC simulations should query the manufacturers on specific

sampling rates and critical execution delays prior to running system studies. The

research presented in this thesis provides a guide for identifying and quantifying

sources of delay so they can be more easily understood and implemented into power

systems simulation tools.

A partitioning of this delay for an industrially representative control architecture

provides a novel insight into the control and telecom constraints in hardware modular

multilevel converters, supporting the development of improved power systems

simulation models and adding to knowledge in the field of VSC-HVDC.

8.2. Future Work

A significant contribution from this research was the development of a laboratory scale

modular multilevel converter (MMC), referred to in this thesis as the converter

hardware prototype (CHP). The CHP provides a platform for continued novel research

into MMCs and other cascaded multilevel converters (CMCs). The CHP is suitably

designed for the studies carried out in this thesis, and a wide range of other studies.

However, a number of improvements could be made to the CHP to open up even more

avenues of research. A few of these improvements, and suggested areas of future

investigation, have been summarised and categorised below as: hardware

development, control architecture development, simulation studies and other

research opportunities.


Currently the CHP connects to an active DC network provided by a controllable DC

supply and feeds a three-phase resistive star-point load. In reality, an MMC would be

connected to an active AC and DC network and power flow between the two networks

would be controlled by increasing or decreasing the magnitude and phase of the

converter voltages. The next stage of development for the CHP would be to connect an

active AC network provided by a controllable three-phase supply to the AC side of the

converter. A transformer could be used to step-up voltages to three-phase mains

voltage or to another voltage level of interest.


148

An active AC network would be used for the PLL references and power flow could be

set using a closed loop power controller as discussed in Chapter 2. In order to achieve

this, the CCSC loop and dq current control loop would need to be closed with feedback

from the sensors; enabling traditional converter control and further research into

power system dynamics and power flow control.

The DC network could then be replaced or supported by a battery storage device or a

capacitor bank to investigate auxiliary service provision from MMCs. Studies into the

behaviour of static synchronous compensators (STATCOMs) could also be carried out.

There is also potential for research which makes use of the full-bridge capability of the

SMs, which has not been required for this project.

The CHP has a voltage rating of ±100 V, this magnitude is well suited for connecting to

a small motors and generators. Prior to the development of MMCs for HVDC

applications they were used for motor drive applications due to their reduced

electromagnetic interference (EMI) and improved harmonic performance [140].

Previously, the computationally intensive control and operation of MMCs restricted

the application to larger drives. While the control challenge still exists, systems with a

small number of levels can now be controlled with much smaller devices, increasing

the opportunities for application. One application tying into current research interests

may be for motor-drive improvements for more-electric vehicles (MEVs).

The addition of an over-rated direction switch (DS) to replace one of the sub-modules

in each arm of the CHP would create an alternate arm converter (AAC) with 7 SMs per

arm, providing a platform for research into alternative CMC topologies.

Control Architecture Development

The CHP has been constructed with a distributed control architecture, as described in

Chapter 3. For this research a representative industrial control system has been

implemented on the CHP, enabling studies into the telecommunication and controller

delay of internal converter control systems. Control systems making better use of the

distributed architecture could be investigated using the CHP with very little additional

hardware.

As part of another EPSRC PhD research project titled “Computation and

Communication Architectures for Modular Multilevel Converter Construction” an


149

investigation into more distributed control and alterative control architectures will be

made using the CHP. For example, the functionality of the distributed control units

(DCUs) will be extended, potentially enabling local capacitor balancing control. This

would reduce the telecommunication and computational requirements of the phase

control unit (PCU) (or arm control unit for industrial converters). Reducing the

bottleneck at the PCU would free-up computational resource and enable a wide

variety of additional functionality on the CHP.

Simulation Studies

The findings from this research identified a clear delay caused by communications and

internal converter control systems. A sensible progression from this research would be

to incorporate the suggested improvements to power systems models with the

addition of total system delay. This may involve adding delays to a detailed

electromagnetic transient (EMT) simulation model in a program such as PSCAD/EMTDC

as suggested in this thesis, or by limiting the control loop bandwidths in a root-mean

square (RMS) simulation model such as PowerFactory.

A research project with accurate data from manufacturers would ensure that any

adaptations to the models represent actual converter behaviour, rather than relying

on representative data from a laboratory scale prototype. Operational limitations

caused by time delay is likely to significantly impact the performance of high-frequency

auxiliary control systems or fault response options which are often suggested for

MMCs; while power electronics offer exceptional response rates, they are not

instantaneous. This will become more apparent with the increased penetration of

power electronic converters.

Other Research Opportunities

During the design of the CHP a number of choices were made to ensure the system

was flexible and reconfigurable to enable a wide range of future research; this was

partly described in Chapter 4.

The CHP is made up of twelve DCUs which each control four SMs. These devices can be

rearranged to create up to a 25-level single-phase MMC or up to a nine-level three-

phase MMC. However, the system is not limited to creating a single converter. A group

of three DCUs can be configured as a three-level three-phase converter, with


150

supervisory control from the PCU. Therefore, four individual converters can be created

and connected together, enabling research into multi-terminal DC grids. Additional

measurements would be required for the individual converter AC outputs, acquired by

the remaining analogue inputs on the central control unit (CCU) FPGA or DCUs. A back-

to-back link can also be configured, with two seven-level three-phase converters.

The findings of this research and the development of the distributed control

architecture for the CHP has potential applications in other power electronic systems,

such as multiphase machines, multi-machine systems, other multi-level converter

topologies, battery management systems and more. In all of these cases the

coordination of many smaller devices is critical for full system stability and therefore

understanding the limitations in control and communication are equally as important

as in an MMC. As the penetration of power electronic converters in UK infrastructure

continues to rise, the coordination of these high speed systems will also become

increasingly important; forming a distributed control structure, on a massive scale.

Reconfiguration of the CHP for these avenues of research is non-trivial and would

require a detailed understanding of the system and considerable additional hardware,

however, a large part of the design and documentation of the test rig has been

undertaken to enable such future research to be carried out as straightforwardly as

possible.

References

151

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Alternative Converter Topologies

160

Appendix A – Alternative Converter Topologies

A.1. Cascaded Two-Level Converter

The CTLC topology is almost identical to that of an MMC. The main difference between

the two topologies is that the MMC SMs have individual IGBTs whereas the CTLC SMs

use TLC valves.

This means that SM ratings are typically much higher in a CTLC than an MMC. For a

±320 kV system such as DolWin 1, the first commercial application of the CTLC [41],

only 38 SMs per arm are required. This results in a nominal SM voltage of 16.8 kV

[141]. The ±320 kV INELFE link between France and Spain was commissioned in the

same year and uses an MMC topology with 400 SMs per arm. This results in a nominal

SM voltage of 1.6 kV, ten times smaller than the CTLC [141].

In summary the CTLC topology has simpler control requirements than a similarly rated

MMC at the expense of reduced dynamic performance [56].

A.2. Alternate Arm Converter

The AAC combines an MMC and a TLC to create a converter which is capable of

blocking DC-faults with reduced switching and conduction losses in comparison to an

MMC.

Figure A.1 shows the AAC overview diagram. The AAC structure is similar to that of an

FB-SM MMC with one fundamental change, in series with the stack of FB-SMs is a TLC

valve referred to as a direction switch (DS). During normal operation only one arm

conducts per half AC cycle. The upper DS is closed during the positive half-cycle,

connecting the upper arm to the AC terminal. The lower DC is closed during the

negative half cycle connecting the lower arm to the AC terminal. The stack of FB-SMs

is then modulated to produce a staircase output waveform, thus referred to as the

wave-shaping converter [92].

The required voltage withstand capability of the stack of FB-SMs in the AAC

configuration is equal to half the DC link. This is half the required rating of a similarly

rated MMC. The FB-SMs are capable of applying , zero and to the SM

terminals. Unlike the MMC, outputting is desirable during normal operation, not

just dc-fault scenarios. In fact, the ideal operating point for the AAC is when the peak


161

AC voltage output is 27% higher than half the DC link voltage, requiring the SM

capacitors to be connected in reverse [47, 92, 142]. The minimum rating of the DS

must then be 27% higher than half the DC link voltage.

Figure A.2 shows a number of operation modes for a 20 kV rated AAC. In Figure A.2,

SMs highlighted green are connected, red are bypassed and blue are reversed. In

mode a the upper DS is conducting and the FB-SMs in the arm are all connected

producing 10 kV, a voltage equal to half the DC link. The voltage at the AC terminal is

therefore zero. In mode b the upper DS is still conducting but the SMs have been

connected to produce a -2.7 kV voltage; this represents the peak output voltage for

the converter at 12.7 kV. The lower DS in mode b is withstanding this peak voltage. In

mode c the upper DS has been opened and the lower DS has been closed. The SMs in

the arm have been connected to produce an AC output voltage of – 5kV which is

reflected in the upper DS voltage.

Figure A.1: Alternate arm converter overview diagram

Vdc

Idc

DS

SM1

SM2

SMN

SMN

SM2

SM1

DS

Larm

Larm

DS

SM1

SM2

SMN

SMN

SM2

SM1

DS

Larm

Larm

DS

SM1

SM2

SMN

SMN

SM2

SM1

DS

Larm

LarmVa Vb Vc

Arm Phase/Leg

Icu

a

Ibu

a

Iau

a

Icla

Ibla

Iala

IaccIacbIaca

DNSN

DiiSii

DiSi

DS

D1

D2

Iarm

S1

S2

Csm

D3

D4

S3

S4

FB-SM


162

The ideal operating point for the AAC limits the operational range of the converter.

Operating the AAC outside of this boundary causes energy imbalance between the AC

and DC side leading to capacitor voltage drift. Ultimately this would lead to the

converter blocking for protection. One solution is to provide an overlap time during

the transition between the upper and lower arm DS conduction. This enables current

to flow through the entire phase, enabling energy sharing between the arms as a

means of balancing. However, this creates other challenges such as additional losses

and increased DC-side harmonic distortion [31, 143].

Figure A.2: Operation modes for an alternate arm converter

DS = 0

SM1

SM2

SM2

SM1

DS = 1

Vac0 V

Vla10 kV

a

SMN

SMN

Vua10 kVVdc/2

10 kV

Vdc/210 kV

b c

0 V DS = 0

SM1

SM2

SM2

SM1

DS = 1

Vac12.7 kV

Vla10 kV

SMN

SMN

Vua2.7 kVVdc/2

10 kV

Vdc/210 kV

12.7 kV DS = 1

SM1

SM2

SM2

SM1

DS = 0

Vac-5 kV

Vla5 kV

SMN

SMN

Vua10 kVVdc/2

10 kV

Vdc/210 kV

5 kV

D1

D2

S1

S2

CsmA Vcap

D3

D4

S3

S4

C

Connected

D1

D2

S1

S2

CsmA Vcap

D3

D4

S3

S4

C

Bypassed

D1

D2

S1

S2

CsmA Vcap

D3

D4

S3

S4

C

Reversed

Vsm Vsm Vsm

SMNSMN SMN

Component Calculations and Circuit Design

163

Appendix B – Component Calculations and Circuit Design

B.1. Sub-Module Capacitor Calculation

The method outlined below is used to calculate the value of SM capacitance required

for a given ripple voltage by determining the variation in the converter arm energy.

This approach assumes that the output voltage and current is sinusoidal, that the DC

voltage is smooth and split equally between the SMs, and that the converter is

symmetrical i.e. identical across all six arms.

This analytical approach to calculating the SM capacitance for a given set of ratings

was initially presented by [43] and derived in full by [56]. A value of 40 kJ/MVA of

stored energy per MVA of converter rating was given by [141] as an appropriate

estimate and is used for comparison.

Equations B.1 to B.4 on the following page can be used to calculate the appropriate SM

capacitance for the chosen system ratings. Where is the energy stored in the

upper arm of one phase, is the power rating of the converter, is the rotational

speed, is the peak AC current, is the DC current, is the network frequency,

is the SM capacitor, is the number of SMs in an arm, is the ripple voltage error and

is the nominal capacitor voltage.

Table 4.1 from Section 4.2 describes the converter rating specifications of interest and

has been replicated here for simplicity.

Description Single-Phase Rating Three-Phase Rating

AC Voltage (L-L RMS) 360 V 120 V

DC Voltage ±300 V ±100 V

Apparent Power 1.8 kVA (peak)

1 kVA (nominal)

1.8 kVA (peak)

1 kVA (nominal)

SM Voltage 25 V 25 V

SMs/arm 24 8

Table 4.1(2): Converter Rating Specifications


164

Key equations:

1.5

2

11

3

dua

PW m

m

B.1

3

2

a

dc

Im

I

B.2

2 f B.3

22

uasm

cap

WC

N V

B.4

For 1 kVA and a voltage ripple error of

314 /rad s

5d

dc

dc

PI A

V

1.67

3

dcdcp

II A

2 24.71

3

da rms

dc

PI A

V

3 22

10

a rmsIm

1.52000 3

1.38942.5 4

uaW J

2

1.381.38

16 0.1 25smC mF

By comparison, the 40 kJ/MVA estimate gives , significantly higher than

the analytical method.


165

For 1.8 kVA and a voltage ripple error of

314 /rad s

9d

dc

dc

PI A

V

3

3

dcdcp

II A

2 28.48

3

da rms

dc

PI A

V

3 22

18

a rmsIm

1.53600 3

2.48942.5 4

uaW J

2

2.482.48

16 0.1 25smC mF

By comparison, the 40 kJ/MVA estimate gives .

As the analytical method is more frequently used, the smaller capacitance values will

be implemented in the CHP. For 1 kVA the SM must have a minimum capacitance

1.38 mF to keep voltage ripple below 10% during operation. For 1.8 kVA a minimum of

2.48 mF is required.

According to Equations 2.20 and 2.21 in Section 2.3, replicated below, the arm current

is made up of three components; a DC component, a network frequency AC

component and a double frequency circulating component.

2 3

ac dcua circ

I II I 2.20(2)

2 3

ac dcla circ

I II I 2.21(2)

The AC current flowing through the SM capacitors in each arm must be accounted for

when choosing an appropriate device, the AC components are referred to as the ripple

current in DC capacitor datasheets. The chosen SM capacitor is a Panasonic

EEUFC1J102 [144]; a 1 mF electrolytic with an rms ripple current rating (RCR) of 2.77 A.

From Equations 2.20 and 2.21 the ripple current flowing through the capacitors is


166

equal to one half of the ac current calculated for the two examples above i.e. RCR of

2.35 A for 1 kVA and 4.24 A for 1.8 kVA. Allowing for a 25% margin to cover circulating

currents, uneven current distribution through the parallel capacitor bank and to

extend the lifetime of the capacitors gives a maximum required RCR of 5.3 A.

Placing three SM capacitors in parallel to create a capacitor bank increases the total

RCR to 8.31A and increases the total capacitance to 3 mF. The device datasheet

recommends a correction factor of 0.7 for 60 Hz frequency. It is assumed that this

correction factor is also suitable for 50 Hz, bringing the total RCR down to 5.8 A; this

meets the RCR requirement for both the 1 kVA and 1.8 kVA designs.

The 3 mF bank changes the expected voltage ripple for both designs. Rearranging B.4

gives B.5.

22

ua

cap sm

W

NV C

B.5

For 1 kVA and

2 3

1.374.57%

16 25 3 10

For 1.8 kVA and

2 3

2.488.27%

16 25 3 10

Both designs during operation should exhibit less than 10% of ripple voltage with a

3 mF SM capacitor bank. Two additional 1 µF ceramic capacitors are placed in parallel

to improve the high frequency performance of the DC capacitors; the increase in

capacitance is negligible in the above calculations.

Working the CHP below the nominal power rating will lead to reduced voltage ripple

on the SM capacitors, which may lead to unrepresentative power system outputs, but

requires no change to the capacitor sizing to operate safely.


167

B.2. Arm Inductor Calculation

The method outlined below is used to calculate the SI unit arm inductor value based

on a pre-defined per-unit value of 0.2 based on [56, 87, 94, 99, 145]. The arm inductor

can be calculated using Equation B.6. Where is the arm inductor in SI units, is

the arm inductor in per-unit equivalent and , and are the per-unit

voltage, current and inductor bases respectively. Table 3.1 lists the specifications of

interest. Values calculated in Section B.1 are also used.

2

pu base

arm pu base

base

L VL L L

fI B.6

For 1 kVA and

70.71base a rmsV V V

4.71base a rmsI I A

0.2 70.719.6

2 4.71armL mH

f

For 1.8 kVA and

70.71base a rmsV V V

8.48base a rmsI I A

0.2 70.715.31

2 8.48armL mH

f

An arm inductor between 5 mH and 10 mH was therefore preferred as it fell within the

per-unit rating of 0.1 and 0.2 for the 1 kVA and 1.8 kVA operating points. However, the

CHP will usually be operated below the nominal power rating, indicating a larger

inductor may be beneficial to maintain representative power system outputs.

The availability of inductors suitable for the required DC current and inductance rating

within the desired price range is limited. Given that the nominal rating, or below, is the

preferred operating point for the CHP, a Hammond 546-159ZJ 10 mH arm inductor was

chosen, close to 0.2 p.u. for the 1 kVA design.


168

B.3. Discharge Resistor Calculation

The RC discharge equation is given by Equation B.7.

RC

c sV V e

B.7

Where is the capacitor voltage of a device with capacitance at a time constant ,

based on a start voltage discharging across a resistor .

The specifications of interest are:

- The SM capacitance,

- When the capacitor is charged to its maximum,

Rearranging Equation B.7 for and calculating based on a discharge from the

maximum capacitor voltage of 57 V to 1 V in 600 s gives

3

60049.5

13 10 ln

57

R k

47 kΩ is a common value that falls close to the desired resistance and will therefore be

used for the CHP.

B.4. Sallen-Key Filter Circuit Calculation

A Sallen-Key design, shown in Figure B.1, was used as a unity gain low-pass filter to

remove unwanted high frequency components and decouple the power electronic

circuit from the capacitor voltage measurement circuit.

The maximum expected observable frequency in the system is determined by the

modulation method. As both NLC and PWM methods are explored, a maximum

switching frequency of 9.6 kHz was chosen, equivalent to NLC switching at 600 Hz. A

filter with a 3 dB cut-off frequency of 19.2 kHz therefore allows for higher than Nyquist

Figure B.1: Sallen-Key low-pass filter circuit

VinVout

R1 R2

C1

C2


169

sampling rates and attenuates high frequency noise. The nominal switching frequency

for NLC is between 50 and 150 Hz per SM which represents a 2.4 kHz effective

switching frequency. This is well within the low-pass filter range.

The design was specified for an of 19.2 kHz and a Q factor close to 0.6. A Q factor

between 0.5 and 0.7 provides a damped frequency response with a smooth transition

between the pass band and stop band. For simplicity , leading to

Equation B.8 and B.9 which describe the cut-off frequency and Q factor with respect to

, and .

To provide high impedance input R is selected as 100 kΩ. and can therefore be

calculated by solving B.8 and B.9 as simultaneous equations.

The resulting equations give and , the nearest available

components are 68 pF and 100 pF respectively. The Sallen-Key filter therefore has R1

and R2 at 100 kΩ, at 68 pF, and at 100 pF, providing a 3 dB cut-off frequency of

19.3 kHz and a Q factor of 0.61.

B.5. MOSFET On-Resistance Calculation

The forward voltage of an IGBT in a 2000 V nominal sub-module is usually close to 3 V.

The nominal voltage proposed for the prototype MMC is 25 V. A representative

voltage drop for the CHP SM will better represent realistic system operation.

Where is the representative forward voltage and is the desired on-resistance

for the MOSFET. For the 1 kVA and 1.8 kVA operating points the desired was

9.3 mΩ and 5.2 mΩ respectively. A value of 6 mΩ was chosen as this allows margin for

any additional voltage drop caused by resistances throughout the circuit.

0

1 2

1

2f

R C C B.8

1 2

22

C CQ

C B.9

3 2

MM

dc a rms

VR

I I

B.10

325 0.0375

2000MV V


170

B.6. Gate-Drive Circuit Calculation

The gate driver circuit, Figure B.2, was chosen based on experimental trial and error

with an early SM version. The combination of on and off resistance (via return diode)

provided a smooth turn-on and turn-off transition which reduced voltage oscillations

at the SM terminals and provided adequate switching times. The bleed resistor

ensures there is a stable gate-to-source voltage should a high-impedance output occur

at the gate-driver.

The gate driver circuit specifications of interest are:

-

-

The HCPL-3120-300E gate-driver specifications of interest (from [146]) are:

- Output gate-to-source voltage,

The IRFB7546PBF MOSFET specifications of interest (from [147]) are:

- Input capacitance,

- Gate resistance,

- Threshold voltage,

- Plateau voltage,

- Gate-to-drain charge,

Equation B.11 [148, 149] can be used to calculate the time taken to reach the end of

the Miller plateau region, where the drain current is at its maximum and the drain-to-

source voltage is at its minimum. This is called the turn-on time ( ). The total gate

resistance, , can be calculated by summing the MOSFET gate resistance, , and

gate driver external on resistance, .

Figure B.2: CHP SM gate-driver circuit

D-return

R-g(on)100

R-g(off)10 R-bleed

100k

G

S

D

Gate-DriverMOSFET


171

Therefore the turn-on time for the MOSFET, , is 387 ns

Equation B.12 [148, 149] can be used to calculate the time taken to turn off, when the

gate-to-source voltage is less than the threshold voltage and no drain current is

flowing. The total gate resistance, , can be calculated by summing the MOSFET gate

resistance, , with the gate driver external on resistance, , in parallel with the

off resistance, .

Therefore the turn off time for the MOSFET, is 98.7 ns when = 2.1 V and 80.6 ns

when is 3.7 V. A minimum dead-time of 100 ns is therefore suitable to ensure

devices turned off prior to turning on other devices.

ln

G gdGSon G iss

GS gp GS gp

R QVt R C

V V V V

B.11

ln ln

gp G gdGSoff G iss

gp TH gp

V R QVt R C

V V V

B.12

Main Component List

172

Appendix C – Main Component List

A list of manufacturer part numbers for the main components used in the MMC is

provided in Table C.1. This list is non-exhaustive and excludes passive components.

PCB Part Name Mfr. Part # Location

S1 – S4 N-Channel MOSFET IRFB7546PBF Sub-Module (V5.1)

D1 – D4 Schottky Rectifier MBR15100CT Sub-Module (V5.1)

Z1 – Z2 Zener Diode 1N5370BG Sub-Module (V5.1)

OO_1, OI_3 1-Channel Optocoupler HCPL-060L-

000E Sub-Module (V5.1)

OI_1 – 2 OO_2

2-Channel Optocoupler HCPL-063L-


GD1 – 4 Optocoupler Gate-Driver HCPL-3120-


OA1 – 4 Operational Amplifier MCP601T-I/OT Sub-Module (V5.1)

ADC1 – 4 Analogue to Digital Converter ADCS7477AIM

F/NOPB Sub-Module (V5.1)

15V_X 24/15V Isolated DC/DC Supply TME 2415S Sub-Module (V5.1)

5V_B 24/5V Isolated DC/DC Supply TME 2405S Sub-Module (V5.1)

Choke Inductor 546-159ZJ 19” Server Rack

C1 – 3 Electrolytic Capacitor EEUFC1J102 Capacitor Bank (V4)

Rx_D, Rx_Er

Fibre-Optic Receiver HFBR-2521Z Fibre-Optic Breakout (V3)

FPGA Breakout Board (V3)

Tx_D Tx_Er

Fibre-Optic Transmitter HFBR-1521Z Fibre-Optic Breakout (V3)


Driver Fibre-Optic Driver SN75451BP Fibre-Optic Breakout (V3)


HES_IXu HES_IXl

5A Isolated Current Sensor ACS712ELCTR

-05B-T Power Interface (V3)

HES_dcn HES_dcp

20A Isolated Current Sensor ACS712ELCTR

-20A-T Power Interface (V3)

Relay_acX Relay_dcX

Controllable Relay RZ01-1A4-

D005 Power Interface (V3)

Table C.1: Main component part numbers

173

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