MMDAQ Content – Overview – Case study – adding support for VMM1 chips – Drawings (data flow, concurrency, error reporting, scalability, monitoring) 13

Marcin Byszewski, MMDAQ overview 1

MMDAQ

Content– Overview– Case study – adding support for VMM1 chips– Drawings (data flow, concurrency, error reporting,

scalability, monitoring)

13 Feb 2013

MMDAQ is the data acquisition software used by Micromegas ATLAS upgrade R&D during test beam periods and in the laboratories. Apart from what is presented here it also has satellite programs like offline event browser, data preparation (filtering, clusterisation).


MMDAQDuring the design of the MMDAQ no assumptions were taken on electronics type or readout configuration.• Any combination of data sources (Chips, FEC , SRU)

– (multithreading, dynamic dispatch)• Event building on available variables

– (Trigger#, SRS Time Stamp, EoE FAFA frame)• Client - Server and Detached GUI

– (by interprocess communication)• Scalability

– (multithreading, data buffering design limiting locking)• XML Configuration

13 Feb 2013

Marcin Byszewski, MMDAQ overview 313 Feb 2013

Data validation and monitoring requires that we understand data format.Each new electronics type requires its own class representationNetwork Device, Chip, Channel


Case study: integration of VMM1 During 2012 test beam runs we have acquired data from a heterogeneous readout system using the MMDAQ. It had to be adapted from reading SRS-FECs with 16 APV25 chips each (UDP protocol) to being able to read tracking information from VMM1 chips connected to BNL-DAQ boards and VMM1 trigger data from BNL-FPGA evaluation board.

Challenges and solutions were:• Synchronisation mechanism of data sources, and event building

– Trigger number embedded in data

• Handling of multiple sources of data - each VMM1 board is a UDP data source (= SRS-FEC), albeit with relatively low data rate– MMDAQ-FEC (MMDAQ representation of SRS-FEC) support multiple data sources to limit thread use

for low rate data sources

• VMM1 trigger evaluation board uses TCP protocol– Special MMDAQ-FEC for TCP protocol

13 Feb 2013


Case study: integration of VMM1 • Multiple data sources support for MMDAQ-FEC classes

– Option 1: Each VMM1 board represented as MMDAQ-FEC in MMDAQ (many treads)

– Option 2: MMDAQ-FEC serves multiple VMM1 (one thread for many VMM1s)

13 Feb 2013

Configuration file Option 1:<fec id = "16"> <name>BNL16</name>

<ip>10.0.0.16</ip> <chip id = "0" type = "VMM1"> <name> VMM1.16.00 </name> </chip> </fec><fec id = "17"> ...

Configuration file Option 2:<fec id = "3"> <name>BNL</name> <ip>10.0.0.16</ip> <chip id = "16" type = "VMM1"> <name> VMM1.16.00 </name> </chip> <ip>10.0.0.17</ip> <chip id = "17" type = "VMM1"> <name> VMM1.17.00 </name> </chip>...


Case study: integration of VMM1

13 Feb 2013

FEC APV25processing

FEC BNLprocessing

CSrsChipApv

NICUDPReceiver

Identify data sourceVerify data source

CSrsChipVmm

RootWriter

APV treeVMM tree

ApvChannel(processing)

VMMChannel(processing is no-op)

UDP packets

Support VMM1-BNL-DAQ:By providing 3 derived classes:CSrsChipBnl : public CSrsChipCSrsChannelBnl : public CSrsChannelCRootTreeFillerBnl: public CRootTreeFillerand implementing functions for chip-specific data handling (mostly none for VMM1)

TCPReceiver(For VMM1 trigger

analysis)

TCP packets

(…)


DRAWINGS concurrency, scalability

13 Feb 2013


Receiver

SRS data

source

NICInput buff

De codeUDP

FEC

FEC

UDP Buffer

Process data(ZS)

ChipEvID,

channelsEvID, channelsEvID, channels

ChipEvID,


Processed data (channels)

eventID

Writer (RootWriter)

eventID

Data Flow

Event BuilderChip type -> Timeout,

completeness

EvIDEvIDEvID

Timeout / ready

13 Feb 2013

UDP packets with RAW data

RAW

Processed data (channels)Receiver, FEC, Chip, Writer are designed to be extensible by inheritance.


UDPReceiver

SRS data

source

NICInput buff

De codeUDP

FEC

FEC

UDP Buffer

Process data(ZS)

ChipEvID,


ChipEvID,


Data (channels)

eventID

RootWriter

eventID

Concurrency


completeness

EvIDEvIDEvID

Timeout / ready

1

pool

pool

1

13 Feb 2013

Threads / thread pools are represented by distinct colouring.


UDPReceiver

SRS data

source

NICInput buff

De codeUDP

FEC

FEC

UDP Buffer

Process data(ZS)

ChipEvID,


ChipEvID,



completeness

Data (channels)

eventID

RootWriter

eventID

EvIDEvIDEvID

Error reporting

Timeout / ready Timed-out/missing fragment

Queue overflow

Bad ipQueue overflow

Bad dataBad chip idQueue overflow

13 Feb 2013


NIC

FEC

FEC

ChipEvID,


ChipEvID,


Data (channels)

eventID

RootWriter

eventID

Scalability


completeness

EvIDEvIDEvID

Timeout / ready

1

pool

1

NIC UDPReceiver

UDPReceiver

1+1

1+1

lock

13 Feb 201340MB/s(300Hz)

15MB/s per NIC(1.8kHz,16x 520B) Very preliminary


UDPReceiver

SRS data

source

NICInput buff

De codeUDP

FEC

FEC

UDP Buffer

Process data(ZS)

ChipEvID,


ChipEvID,


Data (channels)

eventID

RootWriter

eventID

Monitoring


completeness

EvIDEvIDEvID

Timeout / ready

13 Feb 2013

Publisher request

statsstats

stats

stats

stats

Monitoring based onExisting event display program

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MMDAQ Content – Overview – Case study – adding support for VMM1 chips – Drawings (data flow, concurrency, error reporting, scalability, monitoring) 13