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VLSI TECHNOLOGY
Refrences
1. Integerated Circuits - K.R Botkar
2. Basic VLSI Design Douglas Pucknell3. VLSI Technology S M Sze
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INTRODUCTION & HISTORY
19th Century - Solid-State Rectifiers
1907 - Application of Crystal Detector inRadio Sets
1947 - BJT Constructed by Bardeen and
Brattain
1959 Integrated Circuit Constructed by
Kilby
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Integrated Circuits
An integrated circuit is a collection of discrete
elements created by means of a single
construction process in which all elements are
formed.
Components and wiring are all integrated parts of
chip and cannot be separated from each other
Helping keys to IC manufacturing are1. Planar transistor
2. Batch Processing
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1958: First integrated circuit Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2003 Intel Pentium 4 Qprocessor (55 million transistors) 512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years No other technology has grown so fast so long
Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power consumption
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Moores Law:
Fit straight line on semilog scale Transistor counts have doubled every 26 months
Year
Transisto
rs
40048008
8080
8086
80286Intel386
Intel486Pentium
Pentium ProPentium II
Pentium III
Pentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
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Integration: Levels
SSI: 10gates/ chip: Small signal integration
MSI: 1000gates/ chip: Medium Signal Integration
LSI: 10,000 gates/chip: Large Signal Integration
VLSI: higher that 10K gates/ chips
ULSI: higher that 1Million gates/ chips
Choice of scale of integration depends on
1)production volume & flexibilty
2) complexity of required ckt and3) yield and cost for a particular scale ofintegeration
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In 1971, minimum dimensions of 10 um in 4004
In 2003, minimum dimensions of .18um in Pentium4.
Scaling down forever ? (No, transistors cannot be
less than atoms) Many predictions of fundamental limits to scaling
have already proven wrong
We believe that scaling will continue for at least
another decade. What is the future?
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VLSI electronics, the most advanced state of
SC electronics forms the basis of 2nd industrial
revolution and is the key technology for
information age
- Microprocessor in 4th gr computers is
using LSI/VLSI technology
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Advantages of ICs over Discrete
Components
Reduced size & weight
Increased reliability
Reduction in circuit cost Reduction in power consumption
Improved speed
Quick designing by use of MSI/LSI/VLSIpackages
ICs facilitates new product development
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Si is a better semiconductor material
than Ge bcoz
Si can withstand temp
up to 150degree Celsius
Grows a stable oxide Intrinsic resistivity is
high(230000 OhmCm)
Electronic grade Si ischeaper than Ge
Ge can withstand only
100degree Celsius
Ge oxide is unstable 47OhmCm
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Classification of ICs
Based on fabrication1. Monolithic IC:- ICs which are included entirely in a
single chip of SemiConductor( usually Si)
100s of identical can be built simultaneously on a Si wafer
using batch processing2. Hybrid IC :- It may contain one or more monolithic
ckts or individual transistors bonded to an insulatingsubstrate with resistors, capacitors or other ckt
elements with appropriate inter connections Hybrid ckts offer excellent isolation b/w components &
allow the use of more precise resistors & capacitors
Less expensive to build in small numbers
Again classified in to Thick Film & Thin Film ICs
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Based on operation performed
1. Analog IC:- Perform analog or linear operation
like amplification, integaeration etc. It deals with
analog quqntities like pressure, temp etc2. Digital IC:- Perform digital operations like AND,
OR , NOT etc
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MODULE1
Monolithic IC Process
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Sorenson14
Semiconductor Manufacturing Processes
Design
Wafer Preparation
Front-end Processes
Photolithography
Etch
Cleaning
Thin Films
Ion Implantation
Planarization Test and Assembly
Thin Films
Photo-lithography
Cleaning
Front-End
Processes
EtchIon
Implanta
tion
Planarizatio
n
Test &
Assembly
Design
Wafer
Preparation
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Sorenson15
Design
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
EtchIon
Implantation
Planarization
Test &
Assembly
DesignWafer
Preparation
Establish Design Rules
Circuit Element Design Interconnect Routing
Device Simulation
Pattern Preparation
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A logic circuit diagram is drawn to determine theelectronic circuit required for the requested function.
Once the logic circuit diagram is complete,simulations are performed multiple times to test thecircuits operation.
Logic Circuit Design / Layout Design
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Sorenson17
Wafer Preparation
Thin Films
Photo-
lithography
Cleaning
Front-End
Processes
EtchIon
Implantation
Planarization
Test &
Assembly
DesignWafer
Preparation
Polysilicon Refining
Crystal Pulling & Crystalstructure
Wafer Slicing & Polishing
Epitaxial Silicon Deposition
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drain
IC device
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Sorenson23
Polysilicon Refining
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Czochralski Growth Process
Czochralski Process is a
Technique inMaking Single-
Crystal Silicon
A Solid Seed Crystal isRotated and Slowly
Extracted from a Pool of
Molten Si
Requires Careful Control to
Give Crystals Desired Purity
and Dimensions
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Parts Of Apparatus
a) Furnace: Crucible, Susceptor or supporter,
rotation mechanism, heating element ,
power supply & control s/m
b) Crystal pulling mechanism: seed shaft or
chain, rotation mechanism & seed chuck
c) Ambient control: Gas source, flow control,
purge tube &exhaust or vaccum mechanism
d) Control system: microprocessor, sensors &
outputs
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CYLINDER OFMONOCRYSTALLINE
The Silicon Cylinder is Knownas an Ingot
Obtained Single crystal Si is of
99.99999999% purity
Typical Ingot is About 1 or 2
Meters in Length
Can be Sliced into Hundreds of
Smaller Circular Pieces Called
Wafers
Each Wafer Yields Hundreds or
Thousands of Integrated
Circuits
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Comparisaon
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Wafer Shaping, Slicing & polishing
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Wafer Shaping
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Wafer Slicing & polishing
The Silicon Crystal is Sliced by Using a Diamond-Tipped Saw into Thin Wafers
Sorted by Thickness
Damaged Wafers Removed During Lapping Etch Wafers in Chemical to Remove any RemainingCrystal Damage
Polishing Smoothes Uneven Surface Left by Sawing
Process
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Wafer Lapping
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Wafer Shaping, Slicing & polishing
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Diffusion of Dopant Impurities
Diffusion - Mass transport by atomic motion
Mechanisms
Gases & Liquids random (Brownian) motion
Solids vacancy diffusion or interstitial diffusion
In Semiconductors diffusion means the process of Junctionformation
There are different methods for junction formation. Butselective diffusion is an important technique in itscontrollability, accuracy & versatility
Impurity atoms are introduced on to the surface of Si waferand diffuse in to the lattice bcoz of their tendency to movefrom regions of high concentration to low concentration
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Diffusion is a result of random motion and particles
diffuse in the direction of decreasing concentrationgradient
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Glass tube filled with water. At time t = 0, add some drops of ink to one end
of the tube.
Measure the diffusion distance, x, over some time.
Compare the results with theory.
to
t1
t2
t3
xo x1 x2 x3time (s)
x (mm)
Simple Diffusion
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1. Substitutional Diffusion
2. Interstitial Diffusion
Diffusion Mechanisms
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Substitution-diffusion
applies to substitutional impurities like boron. Phosphorus and
arsenic
dopant atoms exchange with vacancies left by parent atom
rate depends on (1) number of vacancies;
(2) activation energy to exchange.
Vacancy Diffusion:
increasing elapsed time
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smaller atoms diffuse between atoms( interstitialvoids) eg: gold, copper, nickel etc
More rapid than substitutional diffusion and not stable.
Usefull in fabrication of digital ICs
Interstitial diffusion
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Ficks Laws Governing Diffusion
Process
Diffusion rate of impurities in to the SCdepends on following
1. Mechanism of diffusion
2. Temperature
3. Properties of lattice environment
4. Physical properties of impurity
5. Concentration gradient of impurities and
6. The geometry of the parent SC
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Diffusion Profiles
Depending on boundary conditions, Ficks 2nd lawhas two type of solutions. These solutions
represent two types of impurity distribution
profiles.
1. Constant source diffusion following
complementary error function( erfc)
2. Limited source diffusion following Gaussian
distribution function
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Constant Source(erfc) Diffusion
Impurity concentration at the surface is maintainedconstant throughout the diffusion cycle
i.e N(0, t) = constant = Ns
The boundary conditions areN(0, t) = constant = Ns and N(x, t) = 0 initialy
When Ficks 2nd law is solved using above
boundary condittions we get a solution whichfolows a complementary error function distribution
Commonly used for isolation and emitter
diffusion bcoz it maintains a higher surface
on entration
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Limited Source ( Gaussian) Diffusion
A pre determined amount of impurity is introducedin to the crystal unlike the constant source
diffusion
Diffusion takes place in two steps
1. Predeposition Step: fixed no:of impurity atoms
are deposited on Si wafer during a short time
2. Drive in Step: Impurity source is turned off and
impurities deposited already are allowed to
diffuse
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When Ficks 2nd law is solved with boundary
conditions we get
which is a Gaussian distribution
Used when
moderately high sheet resistivity is require
multiple diffusions are needed
Transistor bases are made
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Parameters Affecting Diffusion Profile
Solid solubility
Diffusion temperature
Diffusion time Surface cleanliness and defects in Si crystal
pn junction formed using erfc diffusion ismodeled as a Step junction and Gaussian
diffusion as a linear graded junction
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Ion Implanatation System
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Properties of Ion Implantation
The depth of penetration of any particular
type of ion will increase with increasing
accelerating voltage
The accelerating voltage may be from 20 kV to
250kV
The penetration depth will generally be in the
range of 0.1 to 1.0micrometre
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Annealing
It is done after ion implantation
Annealing is performed
to restore the surface region of Si which is
heavily damaged due to the ion implantation
process back to a well ordered crystalline state
To allow the implanted ions in interstitial sites
to go in to the substitutional sites in the crystal
structure
Annealing involve heating of the wafers to a
temp range of 600 to 1000degreeCelsius for
around 30 minutes
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Advantages
- At low temp also implantation can be done without disturbing
previously diffused regions
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Thermal Oxidation
Oxidation of Silicon
The role of SiO2 in IC fabrication is as follows
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The role of SiO2 in IC fabrication is as follows
It acts as a diffusion mask permitting selective diffusi
in to the wafer It protects the junction from moisture and other
atmospheric contaminants
It serves as an insulator on the wafer surface SiO2 acts as the active gate electrode in MOS structu
To isolate one device from another
It provides electrical isolation of multilevelmetallization used in VLSI
Sacrificial layers are grown and removed to clean up surface
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The simplest method of producing an oxide layer
consists of heating a silicon wafer in an oxidizing
atmosphere.
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The thickness of oxide layer depends on temp
of the furnace, length of time wafer are in the
furnace and flow rate of oxygen
Rate of oxidation can be significantly
increased by adding water vapour to the
oxygen supply to the oxidizing furnace
Layer thickness in the range 0.1 to
5microMeter are commonly produced at
temps b/w 1000 & 1200degreeCelsius
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Dry oxide - Pure dry oxygen is employedDisadvantage
- Dry oxide grows very slowly
- oxide thickness is small
Advantage
- Oxide layers are very uniform.
- Relatively few defects exist at the oxide-silicon interface (These defects interfere with
the proper operation of semiconductordevices)
- dielectric strength is high and thus makeideal dielectrics for MOS transistors.
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Wet oxide - In the same way as dry oxides,but steam is injected
Disadvantage
- Hydrogen atoms liberated by thedecomposition of the water molecules produce
imperfections that may degrade the oxidequality.
Advantage
- Wet oxide grows fast.( four times faster
than dry oxide)- Useful to grow a thick layer of field oxide
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Key Variables in Oxidation
Temperature
- reaction rate
- solid state diffusion
Oxidizing species- wet oxidation is much faster than dry oxidation
Surface cleanliness
- metallic contamination can catalyze reaction
- quality of oxide grown (interface states)