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MODELING ANALOG CIRCUITRY WITH VHDL
A Thesis
Submitted to the Graduate School
of the University of Notre Dame
in Partial Fulfillment of the Requirements
for the Degree of
Master of Science
in Computer Science and Engineering
by
Mark D. Mueller, B.S.E.E.
Eugene W. Henry, Co-Director
Robert J. Minniti, Co-Director
Department of Computer Science and Engineering
Notre Dame, Indiana
April 1994
MODELING ANALOG CIRCUITRY WITH VHDL
Abstract
by
Mark Dean Mueller
With the increasing use of mixed signal analog and digital technologies in circuit
design, there becomes a growing need for a method to simulate such circuits quickly, eas-
ily and accurately. Modeling the components structurally with an analog simulation tool is
a common technique. A more powerful method would be to behaviorally model both
types of components at a higher level. The VHSIC Hardware Description Language
(VHDL) includes a REAL data type that allows continuous quantities to be represented in
its models. Modeling analog components in VHDL is done by determining a constant
lumped-parameter transfer function for each component and using REAL data types as
signals. Euler’s method can then be used to approximate the value of a quantity after a dis-
crete time step. The analog portion of a mixed signal circuit modeled in VHDL can be
connected to digital instances much as any other VHDL component.
TABLE OF CONTENTS
ii
LIST OF FIGURES ........................................................................................................iv
ACKNOWLEDGEMENTS..............................................................................................v
CHAPTER 1 INTRODUCTION................................................................................1
1.1 Background..................................................................................................1
1.2 Organization.................................................................................................3
CHAPTER 2 ANALOG AND DIGITAL SIMULATION .......................................4
2.1 Analog Simulators .......................................................................................4
2.1.1 SPICE Analyses ............................................................................5
2.1.2 Netlist Description ........................................................................8
2.1.3 Simulation Stability ......................................................................9
2.1.4 Simulator Procedure....................................................................11
2.2 VHSIC Hardware Description Language (VHDL)....................................12
2.2.1 Basic Modeling Concepts ...........................................................12
2.2.2 Basic Syntax and Structure of VHDL.........................................14
2.2.3 Basic VHDL Modeling Techniques............................................16
2.3 Mentor Graphics and Simulation...............................................................17
2.3.1 Accusim Analog Simulator.........................................................18
2.3.2 System-1076 VHDL Compiler ...................................................18
2.3.3 QuickSimII Digital Simulator.....................................................19
CHAPTER 3 METHODOLOGY ............................................................................21
3.1 VHDL as a Mixed Mode Simulator...........................................................22
3.1.1 Behavioral and Structural Description........................................23
3.1.2 Transfer Function Modeling .......................................................24
3.1.3 Time Approximation...................................................................26
3.1.4 Use of VHDL Constructs............................................................28
TABLE OF CONTENTS
iii
3.2 Modeling Analog Components ..................................................................30
3.2.1 Passive Filter Modeling ..............................................................31
3.2.2 Modeling Operational Amplifiers...............................................32
3.2.2.1 Ideal Opamp Models....................................................33
3.2.2.2 Non-Ideal Opamp Models............................................35
3.2.3 Active Filter Modeling................................................................38
CHAPTER 4 IMPLEMENTATION AND RESULTS ...........................................40
4.1 Implementation ..........................................................................................41
4.1.1 VHDL Structures ........................................................................41
4.1.2 Transfer functions for behavioral components ...........................45
4.1.3 Opamp Implementation ..............................................................53
4.2 Example Circuit: Synchronous Detector ...................................................54
4.3 Results........................................................................................................56
CHAPTER 5 CONCLUSION AND FUTURE WORK .........................................61
5.1 Conclusion .................................................................................................61
5.2 Future Work ...............................................................................................62
CHAPTER 6 REFERENCES...................................................................................63
APPENDIX ..................................................................................................................... 66
iv
LIST OF FIGURES
Figure 1 : Ideal opamp inverter..................................................................................34
Figure 2 : Non-ideal opamp inverter..........................................................................36
Figure 3 : Opamp model with offset voltage .............................................................37
Figure 4 : Summing Bus Resolution Function ...........................................................42
Figure 5 : Data Structures Package.............................................................................43
Figure 6 : Package header for passive functions.........................................................44
Figure 7 : Circuit and transfer function for passive high-pass filter...........................46
Figure 8 : Circuit and transfer function for active low-pass filter (2nd order) ...........47
Figure 9 : Circuit and transfer function for active low-pass filter (1st order).............48
Figure 10 : VHDL component for 1st-order active low-pass inverting filter ...............49
Figure 11 : VHDL component for analog switch .........................................................50
Figure 12 : VHDL component for function generator..................................................51
Figure 13 : Circuit and VHDL component for inverting amplifier...............................52
Figure 14 : Block Schematic of LSC............................................................................55
Figure 15 : Input to LSC Simulations...........................................................................57
Figure 16 : LSC Simulation Results: Accusim vs. VHDL ...........................................59
Figure 17 : LSC Simulation Results for Different Values ofVpeak.............................60
v
ACKNOWLEDGEMENTS
I am indebted to Miles Laboratories and Dr. Gary Bernstein, who supported this
master’s thesis through funding during the Summer of 1993. I am also grateful to Steve
Detwiler of Miles for his assistance.
I would also like to acknowledge my reader, Dr. Jay Brockman, and my advisors,
Mr. Robert J. Minniti and Dr. Eugene W. Henry, for their technical support and guidance
throughout the project.
Finally, I would like to thank my family, especially my parents, Mary and Michael,
and my fiance, Carrie, for all the love and understanding they have shown me.
1
CHAPTER 1
INTRODUCTION
1.1 Background
With the increasing use of mixed signal analog and digital technologies in circuit
design, there is a growing need for a method to simulate such circuits quickly, easily and
accurately. A common technique used to simulate such circuits is modeling the compo-
nents structurally with an analog simulation tool such as SPICE or Accusim using built-in
digital constructs. This type of structural modeling often introduces problems due to a
primitive interconnection between the analog and digital components. It introduces added
complexity into digital models that is usually unnecessary. Because of this the time
required to simulate SPICE type circuits increases such that it is impractical for simulating
VLSI circuitry. Behavioral modeling avoids these complications by modeling both types
of components at a higher level, while allowing verification of the functionality of the cir-
cuits. The VHSIC Hardware Description Language (VHDL) is a well-established digital
description language and a government standard that was adopted by the IEEE as a stan-
dard. VHDL, however, includes a REAL data type that allows continuous quantities to be
evaluated and represented in its models. The modeling of analog components in VHDL is
2
accomplished by determining a constant lumped-parameter transfer function for each
component and using REAL data-type signals. The continuous-time domain of the analog
circuit is mapped to the discrete-time domain of VHDL using Euler’s method to approxi-
mate the value of a quantity after a periodic time step. In this fashion, the analog portion of
a mixed signal circuit is modeled in VHDL and can be connected to digital instances as
any other VHDL component. Various types are defined by the user to represent the time
step, voltage, resistance, reference levels, and other quantities associated with analog
design.
The example used to demonstrate this technique is a synchronous detector and
noise filter circuit. Results of the VHDL simulation compare very well with those
obtained by simulating a structural model of the circuit in Accusim. The VHDL models
used for operational amplifiers in the circuit were ideal, which makes the accuracy of this
simulation very good. Another advantage of simulating analog circuits with VHDL has
become apparent in the simulation of complex circuits such as this detector. The behav-
ioral description used in VHDL provides simulations that evaluate comparable results in a
much shorter time. Thus the simplicity of modeling these circuits in VHDL not only con-
tributes to the brevity of the description, but also reduces the amount of calculation neces-
sary to achieve a quality simulation. This allows the use of VHDL for simulating large
scale mixed-mode integrated circuits.
3
1.2 Organization
The remainder of this thesis describes modeling the analog portion of circuits in
VHDL. Chapter 2 discusses analog and digital simulation using SPICE and VHDL,
respectively. It also describes the Mentor Graphics Accusim analog simulator and Quick-
sim II digital simulator. Chapter 3 explains the general technique used to describe the ana-
log portion of circuit in VHDL. Application-specific modeling for active filters is also
introduced. The implementation of these techniques for specific analog components is dis-
cussed in Chapter 4. Also, the functionality of the example circuit is described and the
results of standard analog and VHDL simulations are compared. Finally, Chapter 5 pre-
sents a summary of the project and draws several conclusions. Topics for future research
are also provided.
4
CHAPTER 2
ANALOG AND DIGITAL SIMULATION
2.1 Analog Simulators
Analog simulators were developed to aid circuit designers in the analysis of tran-
sistor circuitry and have become a significant tool in the design of analog integrated cir-
cuits (ICs). The experimental method of implementing a proposed circuit on a breadboard
with discrete components became increasingly inaccurate in predicting the behavior of the
same circuit fabricated on a single IC. This is due to the great disparity between the para-
sitics of a breadboard and those on a chip. It is also undesirable to manufacture an IC and
attempt to test and subsequently modify it. Measuring voltages on an IC is a very delicate
procedure requiring high skill and complicated equipment, and measuring currents is vir-
tually impossible. Modifications to the IC must be made by changing the fabrication
masks and fabricating a new circuit, which means that several weeks will pass and many
dollars will be spent before a measurement of the modified circuit can be taken. In modern
industry, this is unacceptable.
5
Simulators such as SPICE (Simulation Program with Integrated Circuit Emphasis)
were developed to emulate the electronic behavior of circuits so that designers could see if
the circuits performed as expected. Circuit simulators also provide a way to rapidly study
design changes and optimizations. The SPICE circuit simulator was developed in the early
1970’s at the University of California at Berkeley. It is widely used in industry and aca-
demia throughout the country. SPICE was originally limited to main-frame computers.
Now, different versions of SPICE can be purchased for use on personal computers and it is
also commercially available for workstations. The description of SPICE found here fol-
lows that found in [18], [14], and [10]. Accusim is a SPICE-like analog simulator that is
part of the Mentor Graphics tools, which run on a client/server network. Accusim per-
forms many of the same analyses as SPICE, while incorporating that capability into a
large set of tools with a user-friendly interface.
2.1.1 SPICE Analyses
The SPICE program performs three basic types of analyses: DC analysis, AC anal-
ysis, and transient analysis. The specific analyses are invoked using “dot-keywords”, such
as “.TRAN”. The group of DC analyses is used to solve for the DC values of requested
voltages and currents in a circuit. All capacitors in the circuit are assumed to be open cir-
cuits, and all inductors are considered short circuits. The most basic DC analysis is the
.OP analysis which calculates the operating or quiescent point (Q-point) of a circuit. This
is useful for determining whether transistors and other active devices are properly biased.
This analysis is also performed automatically at the beginning of most other analyses. The
6
.DC analysis is a sophisticated version of .OP in that it calculates a series of operating
points found by sweeping 1 or 2 DC sources (voltage or current). This analysis provides a
simple method for generating device transfer curves. Another DC analysis is the .TF anal-
ysis, which computes a DC transfer function for a desired output quantity with respect to a
specified source and the corresponding input and output impedances. This is used to deter-
mine voltage and current gain, transconductance, and transimpedance. The final DC anal-
ysis is the .SENS sensitivity analysis. This analysis determines the effect a small change in
each element individually has on the specified output. The sensitivity of the output is com-
puted in both output units per absolute element change (e. g. Volts/Farads) and output
units per percent element change (e. g. Volts/%).
The AC analysis group performs analyses for small-signal sinusoidal steady-state
solutions of circuits. The basic analysis is .AC, which sweeps a designated source over a
given frequency range to determine frequency response. A DC operating point is calcu-
lated at the beginning of this analysis so that linearized models of the various elements can
be created for that operating point. There are two other analyses that can be associated
with the .AC analysis frequency sweep: noise and distortion analysis. The .NOISE analy-
sis calculates the output and input-referred thermal noise generated in semiconductors in a
normalized root-mean-square sum. The .DISTO analysis provides information about the
harmonic and intermodulation distortion within the circuit.
The final analysis group is transient analysis. This group focuses on determining
the circuit solution over time. The chief analysis in this group is the .TRAN analysis. This
analysis calculates the full time domain response over a designated time period. The simu-
7
lator controls the internal simulation time step based on how fast the state variables of the
circuit system are changing. A maximum time step can be specified by the user to limit the
size of the internal time step. Along with the time interval, the user specifies the output
time step; i. e. how often the output values are recorded. The effect of these parameters are
addressed in Section 2.1.3. A Fourier analysis is performed with the regular transient anal-
ysis if the .FOUR statement is used. The DC component and first 9 harmonic components
are determined for designated signals at a given primary frequency, and the total harmonic
distortion is calculated.
The .TRAN analysis begins in a DC state at time t=0 determined in one of three
ways. If the UIC (Use Initial Conditions) flag is specified by the analysis, initial voltages
for capacitors and initial currents for inductors indicated in their respective element state-
ments are used as the initial operating values. All unspecified initial conditions are
assumed to be zero. If the UIC flag is not used, the .IC statement can be used to assign
node voltages to some nodes. The remaining nodes will not default to zero, but their initial
states will be calculated via an operating point analysis which takes the assigned nodes
into account. If both the UIC flag and .IC statement are present, the .IC statement is
ignored and the state is determined using solely initial conditions. If neither the UIC flag
nor the .IC statement is used, the entire initial state for the .TRAN analysis will determin-
ined by a full DC operating point analysis.
8
2.1.2 Netlist Description
The connectivity of elements for a circuit is passed to the SPICE simulator pro-
gram by a netlist description file. This file also indicates which analyses to perform and
which quantities to record. Elements are entered into this file in a basic format which dif-
fers slightly for passive and active elements, and independent and dependent sources. The
basic format for a circuit element is:
element_name nodes (values | parameters | model)
The element name identifies the element in two ways. The first character must be a letter
which indicates the element type, such as resistor, current source, or MESFET. The
remaining 7 characters may be any alphanumeric characters to identify it as a unique ele-
ment of the indicated type. Some examples include RE, IIN1, and B3, corresponding to
the element types previously mentioned.
The next set of fields defines how the element is connected in the circuit. Nodes in
a SPICE circuit description are identified by positive numbers. All circuits must have a
node 0 which is the reference node in the circuit. The node fields define at which nodes the
indicated element is connect. The nodes must be specified in an order indicated by the
description format of each element. The nodes of all circuit elements are polarized to indi-
cate a current and voltage convention. This is useful when assigning initial conditions to
capacitors and inductors.
The final fields in an element description designate the value of the element or the
name of the model used for an active device. The values for passive elements are specified
in the base unit for that device (ohms, farads, henries) with engineering scale factors if
9
desired. Models for semiconductor devices are defined with the .MODEL statement which
names a model and assigns values to the device’s SPICE-model parameters. For other ele-
ments, such as sources, there are parameters to indicate the various quantities associated
with that element, such as amplitude, damping and frequency for a transient sinusoidal
source. An example line for a resistor in a netlist description would be:
R2 11 21 100000
2.1.3 Simulation Stability
The transient analysis in SPICE is possibly the most important of the analyses that
the program performs. The time domain response is equivalent to what is seen on an oscil-
loscope and is usually very difficult to determine by hand analysis for most complex cir-
cuits. It can also be even more difficult to visualize. For these reasons, the time domain
analysis of any analog simulator is the most used part of the simulator. Unfortunately, it is
also often misunderstood. There are many different simulator and analysis options that can
be adjusted to provide stability and accuracy. One of these is the method of integration.
There are 2 different integration methods that SPICE can use to solve the system of differ-
ential equations that represents the time response of the circuit. The default method is
trapezoidal integration, but other types of circuits, such as power circuits or those contain-
ing inductors, switches, and diodes, simulate better using Gear integration. Gear integra-
tion is recommended to provide increased stability in these circuits.
The difference between the output time step specified in the .TRAN analysis state-
ment and the internal simulation time step is very confusing and can be the cause of much
10
frustration. The output time step (tstep) determines how often the output is sampled. The
simulation time step is changed by the simulator to get accurate results with a time step
that is as large as possible. The range of the time step is determined by the maximum time
step parameter (tmax) that can be specified in the .TRAN statement. If unspecified, this
limit is assigned to be 2% of the simulation interval. The minimum allowable time step
(tmin) is defined as 1.0e-9• tmax.
These analysis quantities and the simulation relative tolerance (reltol) are vital to
proper simulation. The reltol tolerance defines the maximum relative error necessary to
reach a solution for the current time step via the chosen iterative integration method. The
default value of reltol is 0.1%. A description of how these quantities interact during a sim-
ulation follows. The tstep must be small enough that high frequency waveforms are not
aliased. If tstep is too large than the simulation results will be inaccurate, but if it is too
small the simulation will take too long to run. A value for tstep that provides 10 to 20
points per period for the highest frequency waveform is usually sufficient. When a small
tstep is used, then it is often necessary to make tmax smaller than tstep. One reason for this
is to guarantee that there will always be at least 1 calculation between each output time
point. Another is that if tmax is larger than tstep, then the value for tmin may be too close
in magnitude to tstep. Recall that tmin is determined by tmax. If tmax is larger than neces-
sary, then tmin may also be too large. This can cause the simulator to crash because the
tmin is unnecessarily high. Reducing tmax will reduce tmin. The simulator may still return
an error of “time step too small” if the time step required to achieve the accuracy indicated
by reltol is smaller than tmin. The solution in this case is to increase reltol to 0.5% or 1%.
11
This may be necessary especially in large and complex circuits. Thus it often takes fine
adjustment of the 3 controllable parameters (tstep, tmax, reltol) to ensure that a simulation
achieves sufficient efficiency and accuracy. This is a very time consuming effort and many
times leads to incomplete analysis.
2.1.4 Simulator Procedure
SPICE and similar analog simulators perform analyses by mapping the circuit into
a system of linear equations. For transient analysis, the follow procedure describes the
method used to reach a solution [12]. At the initial starting point, the DC solution is found
via estimating non-linear elements through an iterative linearization such as Newton-
Raphson. At each iteration of the non-linear method, the resulting system of linear equa-
tions is solved using methods such as Gaussian elimination or LU-factorization to check
for convergence. Once convergence is achieved, the results for that time point are saved.
At time points beyond the starting point, a numerical integration method such as the afore-
mentioned trapezoidal method is used to quantize time into discrete time steps. At each
successive time point, the iterative non-linear method is used to find the approximation of
the system at the present time step. If the solution has not converged after a predefined
number of iterations or the solution is converged but the next time step is computed to be
smaller than the present step, the time step is reduced and non-linear method is attempted
with the reduced time step. Once convergence is achieved and an appropriate time step is
calculated, the simulation time is incremented by the new time step. This routine repeats
until the required simulation time is reached.
12
2.2 VHSIC Hardware Description Language (VHDL)
In general, hardware description languages (HDLs) are used as design aids for the
structured process used in digital VLSI design. They have two main applications. First,
they are useful for documentation, which provides accuracy and portability for designs.
Second, nearly all HDLs are coupled with simulators to provide a means of modeling and
validating designs. The VHSIC (Very High Speed Integrated Circuit) Hardware Descrip-
tion Language, or VHDL, is special historically because no standard HDL existed before
it was developed by the Department of Defense (DoD). The DoD released version 7.2 of
VHDL in 1985. VHDL eventually became an IEEE standard in 1987 with the goal of
developing it further. It has since become a very popular commercial tool for modeling.
For a more thorough discussion of VHDL see [4] and [5].
2.2.1 Basic Modeling Concepts
One of the most important concepts addressed by the designers of VHDL is that of
abstraction hierarchy, which can be broken down into two types or domains. This abstrac-
tion hierarchy is used in the breakdown of the design to various levels of detail and func-
tionality. The domains of abstraction are thestructural domain, which describes the
system as the interconnection of more primitive components, and thebehavioral domain,
which describes the system by defining I/O response through a procedure. Each domain is
further broken down into six levels, each level having different representations in each
domain. The different levels and their representations are shown in Table 1.
13
System level models are models designed at the chip or PMS (processor-memory-
switch) level. A system model, or a model at nearly any level, is usually composed of
interconnections of primitives. Behavior can be specified at many different levels in the
model. In other words, there is not one level that is behavioral which all subsequently
higher levels rely on, but there may be a mix between behavioral and structural domain in
each level. The one exception to this is the silicon level, for which no behavioral represen-
tation exists in this abstraction hierarchy.
In the design and use of simulators in the modeling process, scheduling mecha-
nisms are of great importance due to the need to maintain a time queue and order of
events. Also, the simulation efficiency is important to simulator design. It is defined as the
ratio of the real logic time to the host CPU time. Real logic time is the time required to
complete an activity sequence in a real circuit, and host CPU time is that to simulate the
sequence on a host CPU. For accurate comparisons, the CPU time must be normalized
TABLE 1 : HIERARCHY AND DOMAIN BREAKDOWN [4]
Level Structural Domain Behavioral Domain
PMS CPUs, Memories Performance specs
ChipRAMs, ROMs,
MicroprocessorsAlgorithms,I/O response
RegisterCounters, ALUs,
RegistersTruth tables,State tables
Gate Flip-flops, Gates Boolean expressions
CircuitActive devices,
R, L, and CDifferential equations
Layout Geometric Objects None
14
against the speed of the host. This efficiency is determined by the programming technique,
computer architecture, and modelling level. Simulators using a multiprocessor will exe-
cute faster than a uniprocessor. Finally, SPICE and other gate-level simulations are fre-
quently far too inefficient to use for system models, and chip level simulation is usually
more efficient.
2.2.2 Basic Syntax and Structure of VHDL
The basic features of VHDL are introduced in [4] as well. All design models in
VHDL are calleddesign entities. These are comprised of aninterface description and a
number ofarchitectural bodies. The interface descriptions define the direction and nature
of the external signals in the model. The architectural bodies define the behavior of the
model, which can be defined as a direct behavior or an interconnection of structural primi-
tives. Only one architectural body is invoked per simulation. There are two major VHDL
structures used within architectural bodies to group statements. These areblocks andpro-
cesses. Blocks define sequences of code that are active when the block’s guard condition
is true. They may be nested to add extra conditions to code within an outer block. Pro-
cesses define sequences of code that are active when specified signals change in value (i.e.
are unstable). Processes also may be nested.
There are various data types in VHDL, which can be broken down into logical
types, arithmetic types and character types. The predefined logical types are BOOLEAN,
BIT, and BIT_VECTOR (an array of BIT). The predefined arithmetic types are INTE-
15
GER, POSITIVE, NATURAL, and REAL. The predefined character types are CHARAC-
TER, and STRING (an array of CHARACTER). These data types may be applied to any
of the three classes of objects in VHDL: constants, variables, and signals. Constants can-
not have their values changed in the model. Variables may have their values changed, but
they have no direct relation to hardware. This is because they have no time dimension in
the simulation. Signals are non-constants with a time dimension, and this means that they
are related to actual “signals” in the physical implementation of the model. Signals
assume their values after a time designated in the signal assignment statement, or after a
delta (minimal) time if none is specified. Signals also have multiple containers (drivers),
that can contribute to the value of a single signal. Drivers are created for a signal for each
process that assigns it a value. The signal value is determined as a function of the drivers
in a bus resolution function. All of the many named entities in VHDL have attributes asso-
ciated with them, the most useful of which are signal and array attributes. Attributes tell
what the previous value was, whether or not the signal is stable, and so forth.
Functions and procedures are present in VHDL, the main differences being in what
is passed and what is returned. Functions pass only inputs, are of the same type as the
value returned, and usually appear on the right hand side of an assignment statement when
called. Procedures pass both inputs and outputs, are usually untyped, and do not appear in
an assignment statement. Packages used in VHDL are header files that contain declara-
tions of types, objects, functions, and procedures. They may be created by users so a com-
mon set of declarations can be repeated in various entities. Finally, the control statements
available in VHDL involve conditional statements and loop statements. The conditionals
16
are IF and CASE. The loop statements are LOOP, NEXT, and EXIT, with optional control
expressions WHILE and FOR. RETURN is a control statement that transfer control of the
execution from a subroutine to the calling routine, and the WAIT statement is used to sus-
pend execution for a period of time or until a condition is true.
2.2.3 Basic VHDL Modeling Techniques
The most important thing to understand when studying VHDL modeling tech-
niques is the difference between concurrent and sequential assignment of values. Sequen-
tial assignment is what takes place with variables: they assume their values in the order in
which they appear, in series, just like other computer languages. Signal assignments, how-
ever, are concurrent: they assume their values at the same time, in parallel, just like circuit
elements. Thus a signal assignment that uses the result of an immediately preceding signal
statement does not use the new value, but the original value that was computed during the
last simulation cycle. Each signal can have only 1 driver per signal per process. If there are
multiple assignments to the same signal within a process, all but one maybe overwritten.
Modeling combinational logic is fairly straightforward. Delays between gates can be mod-
eled, or an overall process delay can be used alternatively. Other methods include a ROM
array that is indexed by the inputs, or a multiplexer approach that simply passes a value
for a given set of inputs. Modeling sequential logic is more involved. The major difference
between synchronous and asynchronous modeling is the delay involved with signal
assignments for each. The delay for synchronous networks is defined by the clock period,
while the delay for asynchronous networks is defined by a propagation delay, but the feed-
17
back implementation for both is modeled the same. Clocked flip-flops are modeled in
blocks that containguarded assignment statements which are on standby until the guard
condition (e. g., a clock edge) is met. These statements take on different values under dif-
ferent conditions, thus functioning like a latch.
Finite state machines are modeled using a block for the entire machine and a
nested block for each state. They can also be modeled using processes containing CASE
statements defining state transition and output. Each state block assigns a new state to the
state register, but only one of these will be an unguarded block, and thus the only valid
driver. The bus resolution function assigns the value of this driver to the state register.
Finally, the WAIT statement is very useful in that it implies sequential logic and state stor-
age. When the model reaches a WAIT statement, it will wait for a named condition, until
named signals change, or for a given total time. The statement may include any combina-
tion of these conditions, but if no conditions are named the model may be suspended
indefinitely.
2.3 Mentor Graphics and Simulation
Mentor Graphics is the tool environment available for analog and VHDL simula-
tion. The three tools that are most pertinent to this project are the Accusim analog simula-
tor, the System-1076 VHDL Compiler, and the QuickSim II digital simulator. For a more
detailed explanation of these tools, see [1], [2], [15], [17], and [20].
18
2.3.1 Accusim Analog Simulator
Accusim is the Mentor Graphics analog circuit simulator. As mentioned earlier,
many of the same analyses performed with SPICE can be performed with Accusim. How-
ever, Accusim has an elaborate graphical user interface that many other analog simulators
do not. The analyses and other options can all be set by a variety of menus and dialog
boxes. Instead of entering a program-like netlist, the circuit is described by means of a
schematic creation tool known as Design Architect. Using this tool, the circuit is “drawn”
using elements selected from various menus, and the values and models are entered
directly on this schematic. The model for an active device is entered in a text file in the
same fashion as the SPICE model of the same device. When simulating the model in
Accusim, user-specified voltages and currents are retained as data. The data may be
viewed in a graphing window known as achart. There is also an extensive list of measure-
ments that is used to recover additional data from the simulation, such as rise and fall
times. Additional information can also be found by creating new plots that are a function
of the original, such as its derivative or Fourier transform.
2.3.2 System-1076 VHDL Compiler
System1076 is the VHDL interface tool in Mentor. It is technically part of Design
Architect, but has its own tutorial and manuals. Models using VHDL can be created in
numerous ways. System1076 has some predefined packages for use in VHDL that permit
the code to be used with other Mentor tools, primarily QuicksimII. Mentor makes use of
19
standard VHDL in its own format. The syntax is the same for the language, but the file
organization is structured, as is always the case in Mentor. It is recommended that a
VHDL model in System1076 consists of at least 2 distinct source files. The standard
VHDL design descriptions, namely the entity and the architecture(s) are kept in separate
source files. The System1076 compiler can compile separately and link all the necessary
files of a model. Compile options include a location map for any package libraries, and
other switches. The standard Mentor package library,mgc_portable , is always
mapped. An interesting facet of the System1076 VHDL is that it contains syntax tem-
plates for virtually every VHDL construct. They are loaded into the source file at a desired
location, and the user simply tabs through the allowable fields and enters appropriate
names. Fields that are required by the construct are denoted as such. VHDL models also
require design viewpoints, as do many Mentor Graphics components. The models may
then be simulated in QuickSimII, as can all models created in the Design Architect with
specific viewpoints.
2.3.3 QuickSimII Digital Simulator
QuickSimII is a powerful multilevel simulator. QuickSimII (QSim) is loaded with
a particular model and viewpoint, which to defines the simulation parameters. Any
selected nets, internal or external (ports), may be observed during the simulation. The
input of the simulation can be defined in 2 ways: an external force file or interactively
defined stimuli. The force file is simply a text file written in a specific format that defines
the duration of the simulation and the inputs at various times. This requires preparation
20
before entering QSim, but in some cases it can be quicker to use than the interactive stim-
uli method. Using this method, the user selects an input, and defines, in a popup window,
the values of the inputs at various times. This doesn’t require a file to be written ahead of
time, but it requires a great deal of time to enter the forces in the simulator. The result of
the simulation can be viewed in a trace window or in a listing over time. It can also be
viewed with a chart in the same fashion that curves are displayed in Accusim.
Because QuickSim II processes circuit activity based onevents, it is anevent-
driven simulator. An event is a change of state for any signal. They serve as flags to the
simulator indicating when components need to be evaluated for their affect on the circuit.
Evaluation of components can result in new events which must be scheduled in future
time steps or the current time step (indicating no delay). The mechanism that keeps track
of the events is called atiming wheel. The timing wheel is comprised of individualslots;
one for each time step. A slot contains all of the events scheduled to occur at its designated
time step. The events of the current time step, calledmature events, are read and processed
by the simulator and the affected components are evaluated. This constitutes oneiteration
of the simulator. A single time step can contain multiple iterations if mature events result
in new events with no delay. These events become immediately mature and are addressed
in the next iteration for the current time step. Iterations are performed until the present slot
is empty of events. The timing wheel then advances to the slot corresponding to the next
time step to repeat the process for the duration of the simulation.
21
CHAPTER 3
METHODOLOGY
This chapter discusses the methodology in using VHDL to simulate analog and
mixed analog-digital circuits. Primarily, it addresses the analog rather than the digital por-
tion of a given circuit. Although digital description is not trivial, its standardization was
the express purpose for which VHDL was designed and created, and thus it will not be
discussed in detail. For a more complete treatment of digital modeling with VHDL, see [4]
and [5]. Analog description, was not the primary the intent of the designers of VHDL,
however, it is the focus of much of this chapter. Other techniques have been developed for
analog and mixed-mode simulation, such as using Asymptotic Waveform Evaluation to
model linear RLC interconnects in VLSI circuits [11], and the SPECS piecewise approxi-
mate simulation algorithm [21]. Other VHDL methods have been developed to perform
switch-level modeling [19]. The method discussed here, corresponding to that which is
found in [8], involves a behavioral description of analog components based on their trans-
fer functions. These models are implemented in the discrete time domain of VHDL using
a relatively small time step and various VHDL constructs.
22
Analog modeling techniques for filter circuits and operational amplifiers will also
be described in this chapter. These modeling techniques can be easily used in VHDL to
describe various analog components at a fairly high level. The designer has the power to
describe a component to whatever degree is necessary to achieve a particular accuracy.
Filter circuits, both passive and active, are easily adapted to description based on their
transfer functions, and thus are easily used in such a description in VHDL. Operational
amplifiers can be characterized within the confines of an active filter to an appropriate
degree of accuracy, using both ideal and non-ideal models.
3.1 VHDL as a Mixed Mode Simulator
The inclusion of “real” numbers as a type in VHDL allows floating point calcula-
tions within a description. It is this flexibility that permits the computation necessary to
model analog components. The procedure for implementing these models is contained in
this section. First, the concepts of behavioral and structural description are discussed, as
this method is in reality a hybrid of both. Second, the form and style of the models built
for simulation with VHDL is introduced. Third, the time approximation used with this
method is described. Fourth, the application of many VHDL constructs to analog descrip-
tion is elaborated.
23
3.1.1 Behavioral and Structural Description
All tools used for circuit simulation have varying degrees of behavioral and struc-
tural description.Behavioral description is the lowest level of a fixed model hierarchy. A
fixed model hierarchy is a hierarchy such that all components at a given level are com-
prised of components from the previous level, except for the lowest, foundation level.
Since behavioral models in this case are at the lowest level, there are no models beneath
them. A behavioral description is commonly comprised of a set of physical or logical
equations that describe how a device operates via mathematical relationships among the
currents and/or voltages at the terminals and within the device. Examples of such are the
Ebers-Moll and Gummel-Poon [12] models for the bipolar junction transistor (BJT), the
Level 1, Level 2, and Level 3 models for the metal-oxide-semiconductor field-effect tran-
sistor (MOSFET) used in SPICE, and algorithmic and Boolean models for various levels
of logic circuits. A transfer function representing a device is also a behavioral model, and
a technique which will be explored in more detail later in this chapter.
Structural descriptions are, in a fixed model hierarchy, all models created beyond
the behavioral level. Without structural models, there are only the lowest-level behavioral
descriptions. Structural models are those which are comprised of other models. The mod-
els that are integrated into a structural description can be either behavioral or structural.
The models used to create structural descriptions are generally simpler than the models
they are collected to form, thus lower in the model hierarchy. In SPICE terminology, struc-
tural descriptions are often referred to as subcircuits and macromodels. Examples of struc-
tural descriptions are macromodels for many analog circuits such as operational
24
amplifiers, thyristors, voltage regulators, and zener diodes [12] and [3]. Any digital circuit
can be modeled structurally, either through a logic technology such as CMOS or TTL, or
from a functionally complete set of logic gates (the basic set of AND, OR, and NOT, for
example).
According to [8], this method of describing analog circuits in VHDL is a behav-
ioral method. However, examples found therein demonstrate that there is structural con-
tent and therefore there exists a hierarchy to this method of modeling mixed analog and
digital circuits. Behavioral description is emphasized in order to show that the level at
which the modeling hierarchy begins is relatively high compared to that of most analog
simulation tools. Tools such as SPICE and Accusim model behaviorally at the device
level, while this method uses behavioral models on the circuit level. This is done for three
reasons. First, structural models can present difficulties caused by the connection and
interaction of the analog and digital circuits that behavioral models avoid. Second, behav-
ioral models described in VHDL are less complex than their structural counterparts
designed in SPICE, but they allow verification of functional and system requirements.
Third, a common hardware description language improves portability of descriptions and
communication among designers.
3.1.2 Transfer Function Modeling
Since VHDL provides a REAL data type, it is possible to represent analog and
continuous quantities within a VHDL description. Also, VHDL is a simulation language
25
which evaluates in a sequential fashion, from input to output. This does not contradict ear-
lier statements that VHDL signals are determined concurrently. At a given time instance,
signals are evaluated “simultaneously” by using the signal values from previous time steps
or scheduled signal events for the current time. The new values are used at the next time
step. Logically and physically, however, stimuli applied at input signals propagate sequen-
tially through the described circuit, ending at the output. These properties allow us to rep-
resent analog devices within VHDL if we can model them with distinguishable inputs and
outputs. Therefore, an obvious method to model analog devices within this constraint is to
use Laplace transform transfer functions.
The transfer functionH(s) of a circuit or system is defined as the ratio of the output
to the input, , in the Laplace domain. In effect, a signal assignment statement in
VHDL describes a digital transfer function by describing the output signal in terms of
other signals, variables, and constants [8]. This property is simply applied to signals of
type REAL instead of BIT or some other digital type. This method is matched very well
with the concept of behavioral modeling that was previously suggested. Certain passive
components, such as resistors, capacitors, and inductors cannot be modeled individually
with a voltage transfer function because they have no unique output or input port. How-
ever, a network of these components comprises a passive filter which can be modeled as a
behavioral component by forming the transfer function of the network.
In order to use the transfer function as a VHDL model, it must be described in time
and not complex frequency (s) as it is determined in the Laplace domain. Conversion from
complex frequency to time is easily achieved by performing an inverse Laplace transform
Vout s( )Vin s( )--------------------
26
on the transfer function for the circuit. The inverse transform may be determined from
tables or computed directly by substituting the time derivative for the complex fre-
quency variables. The power ofs translates to the order of the derivative. This method
analytically yields a differential equation describing the output quantity in terms of the
input quantity. The resulting differential equation describes the behavior of the analog cir-
cuit or component in the time domain with no initial conditions. This is because transfer
functions acquired with the Laplace transform have no initial conditions associated with
them. The differential equation can show transient analysis in the sense of showing the cir-
cuit response over time, but the effect of initial conditions is not included in this analysis.
3.1.3 Time Approximation
The model thus far, for a circuit with unique input and output ports, is a differential
equation in the continuous time domain. In order to represent this model in VHDL, it is
necessary to convert the time domain from continuous to discrete, i. e. perform a quantiza-
tion of time. Digital VHDL models are simulated by the scheduling of events in a discrete
time environment that cause a change in any signal value. Analog descriptions in VHDL
must be able to perform in that same environment. The values for many analog waveforms
with non-zero time derivatives are constantly changing, and thus constantly “scheduling
new events” in the continuous time domain. These values are represented using the VHDL
type REAL for the signals magnitude. It only remains now to obtain a discrete time
approximation. A piecewise-linear approximation can be used to accurately represent
tdd
27
waveforms in this discrete time domain with no discontinuities while allowing the deriva-
tive to be approximated by the simple Euler techniques of numerical integration.
The Euler method used by this technique is known asbackward Euler. The Euler
methods are derived from first order Taylor series approximations. For this reason, the
order of load impedances and filters will be limited to second order. A fair amount of
accuracy may be maintained approximating second derivatives, but accuracy and compu-
tation time degrade considerably for higher order circuits. The backward Euler method
assumes that the current valuev1 is determined by the previous valuev0 and the derivative
of v at the current time step,v1′ [22]. If the time between each approximation is given by
T, then the derivativev1′ is given by Eq. (1):
(1)
If the variables in Eq. (1) are given as a function of time,t can be set equal toNT, whereN
is an integer representing the number of time steps since starting timet0, then the back-
ward Euler approximation is given by Eq. (2):
(2)
The backward Euler formula can now easily be substituted into a differential equation,
yielding a discrete time approximation of the continuous time waveformv(t) using a dis-
crete time stepT. Solving the finite difference equation forv(NT) will yield the result of
the discretized transfer function forv(t). For example, the resulting equation for a single-
pole high pass RC filter is given by Eq. (3):
v1′v1 v0–
T----------------=
tdd
v t( )t NT=
v NT( ) v NT T–( )–T
--------------------------------------------------=
28
(3)
The truncation error of this approximation is determined by the next higher order
term in the series, in this case the second order term. The magnitude of the truncation error
coefficient for this and other first order Euler methods (such as forward Euler) is
[22]. This shows that the truncation error depends heavily on the choice ofT, the time step.
If the time step is less than the smallest time constant (or 1/|p|max, where |p|max is the larg-
est pole magnitude) the truncation error is workable [8]. The stability of the approxima-
tion is guaranteed for all stable functions (Repi < 0 for all poles) [22]. Even for unstable
functions a converging sequence is found (though the true response does not converge) for
the approximation if the product ofTpi is outside a unit circle in the Laplace domain cen-
tered at 1 + j0 for all pi [22]. The choice of the time step is crucial in determining the accu-
racy of the simulation; the smaller the time step, the more accurate the simulation. The
trade off for small time steps is longer simulation time due to the increased amount of cal-
culation necessary over a fixed time period. Thus a compromise must be reached that
yields accurate results without extensive calculation.
3.1.4 Use of VHDL Constructs
Now that the model is complete, it must be implemented in VHDL using the lan-
guage’s constructs. In many programming languages, various constructs can be used to
achieve the same effect or functionality; it is often a question of what is the most efficient
Vout NT( )Vin NT( ) Vin NT T–( )– Vout NT T–( )+
1 TRC--------+
-----------------------------------------------------------------------------------------------------=
T2
2⁄
29
construct to attain that desired result. Many of the same constructs and methods can be
used to describe analog circuits with few modifications. The entity declarations are used to
define the ports of the component and the parameters passed to it at instantiation. The
GENERIC list passes the constant parameters such as timing requirements, gains, and
clamp limits. The PORT list defines the type and direction of component’s ports. Also,
ASSERT statements are frequently used in entity declarations to check the generics for
errors in passed values; negative element values, for instance.
The architecture of a component describes its structural and / or behavioral compo-
sition. Any signals or variables contained within the component are declared in the archi-
tecture. The description of the component can use component instantiations, signal-
connected function calls, and simple signal assignment statements. In analog descriptions,
function calls are frequently used to determine the value of a signal from a network finite
difference equation obtained via backward Euler. The passive components in such a net-
work have their values passed into the component by the generics and then to the function
by the function call. One finite difference equation may be accessed by many components.
For example, a simple RC low-pass filter could be used as a passive filter and also as the
dominant-pole frequency roll-off model for an operational amplifier.
Also, the various data types necessary for analog circuit description must be
defined. Two types of signals are considered: reference signals and varying signals. Refer-
ence signals are signals that do not change, or that aren’t supposed to change, such as
ground. Varying signals are the vital signals used in this modeling technique. Both current
and voltage signals are defined. These signals are updated as appropriate as the simulation
30
progresses. Other types that are defined are types for the three major passive components:
resistors, capacitors, and inductors. Types that describe clamping threshold levels and
gains are defined. General parameters such as frequency and amplitude also have defined
types. These types are all subtypes of the REAL data type, except for the varying signals,
which are subtypes of a bus resolution function type. Finally, the time step must be
assigned. It is assigned as two different types: once as type TIME for use in signal assign-
ments, and again as a REAL for use in computing the finite difference equations. Where
and how these signals are explicitly defined will be addressed in Chapter 4.
3.2 Modeling Analog Components
Once a useful modeling technique is determined and the proper use of the VHDL
constructs is explained, it is necessary to know how to arrive at transfer functions for the
circuits or groups of circuits that are to be modeled. The major focus of modeling in this
thesis is modeling filters, both active and passive. Filters are used to selectively block or
pass components of signals which have frequencies above or below a specific critical fre-
quency, or those which have frequencies inside or outside a set range. First, the method for
modeling simple passive filters is described. These filters are comprised of resistors,
capacitors, and inductors. Second, the behavioral properties of operational amplifiers
(opamps) is detailed for ideal and non-ideal models. Third, active filter modeling is dis-
cussed. Active filters are filters that use passive components and opamps achieve the
desired bandpass characteristics.
31
3.2.1 Passive Filter Modeling
The procedure for finding the transfer functions of passive filters is the same as
that for determining the transfer function of any passive network. The values for the vari-
ous passive components in an electric circuit are replaced by the Laplace domain values.
The values of the elements in the Laplace domain are determined by taking the Laplace
transform of the voltage-current relationship for each element. For the resistor, this is very
simple, as shown in Eq. (4a) below. The capacitor and inductor relationships are differen-
tial equations, and have the complex frequency variable s as part of their Laplace circuit
element value. These are shown in equations Eq. (4b) and Eq. (4c), respectively. Note that
no initial conditions are taken into account.
(4a)
(4b)
(4c)
These voltage-current relationships in the Laplace domain represent the impedance Z(s) of
each element in ohms.
v t( ) i t( ) R= V s( ) I s( ) R=( )
V s( )I s( )------------- R=
⇔
ZR s( )=
i t( ) Ctd
dv t( )= I s( ) CsV s( )=( )
V s( )I s( )------------- 1
sC------ ZC s( )= =
⇔
v t( ) Ltd
di t( )= V s( ) LsI s( )=( )
V s( )I s( )------------- sL=
⇔
ZL s( )=
32
By replacing elements with their appropriate impedance values, circuit analysis in
the Laplace domain can be easily performed. Of specific interest to the aforementioned
modeling technique is analysis of the circuit to determine its transfer function between
two ports designated as input and output ports. By convention, the input port is on the left
of the circuit and the output port is on the right for passive filter networks. The transfer
functionH(s) is most easily obtained using node voltage analysis techniques to describe
the circuit behavior in terms of its voltages. The internal node voltages can be eliminated
by substitution or by multiplication of node to node transfer functions to obtain the final
function . Details on node voltage Laplace circuit analysis can be found in [13] and
[16].
3.2.2 Modeling Operational Amplifiers
Operational amplifiers (opamps) are important building blocks in many analog cir-
cuit applications, such as adding waveforms, differentiating and integrating waveforms,
and also serving as simple inverters or multiplying buffers. They are also used in filtering
as the key difference between active and passive filters. Opamps are circuits that are usu-
ally very complex in structure to achieve a simple behavior; this complexity reflects how
difficult is to obtain this behavior accurately. The functional stage of the opamp is the
input stage: a high input impedance differential amplifier. Level shifting circuits and out-
put stages are frequently used to massage and drive the differential amplifier output. The
Vout s( )Vin s( )--------------------
33
ideal behavior and ideal model of an opamp will be discussed, then more accurate non-
ideal modeling of opamps will be addressed.
3.2.2.1 Ideal Opamp Models
Modeling opamp circuits with an ideal opamp model is done because it is a simple
method which can be used to analyze an active circuit independent of the opamp technol-
ogy with reasonable accuracy. The ideal behavior for opamps is based on the concept of a
null port (also called virtual ground); a pair of terminals at which the voltage and current
are both zero [9]. The input terminals of the ideal opamp represent a null port. The proper-
ties of the null port approximation can be explained through two other properties of the
ideal opamp; gain and input resistance. If the gain A of the opamp is extremely high (105
or above), an infinite gain is generally a good approximation for the opamp. However, the
output of the opamp is limited to the supply voltage, usually 5 to 15 volts, not nearly infi-
nite. Thus the input voltage approaches zero, as shown in Eq. (5), where a finite gain is
used to demonstrate the minuscule input.
(5)
Since this input voltage is many orders of magnitude less than other voltages in the
circuit, such as the output and power supply, it is assumed to be zero in the ideal model.
The other property that allows the null port approximation is the input resistance Ri. This,
like the gain, is very high (on the order of 1MΩ or higher) thus the input current can be
Vin
Vout
A----------– 15V
100000------------------– 150µV–= = =
34
considered negligible. The final approximation made when using ideal opamps is that the
output impedance Ro is also zero, i.e. no internal resistance at the output. A summary of
the characteristics for the ideal opamp is found in Eq. (6a), Eq. (6b), and Eq. (6c).
(6a)
(6b)
(6c)
A simple example of circuit analysis using the ideal opamp is the opamp inverter
in Figure 1. The key analysis tool when dealing with ideal opamps is the virtual ground
concept based on the null port at the input. Since there is no voltage drop between the
input terminals, their voltages are equal, but there is also no current flow between the ter-
minals [6].
Vin 0 Iin, 0= =
Ri ∞ Ro, 0= =
A ∞=
Vi ≈ 0
I i ≈ 0
+
- Vo
R1
R2
+
Vs
+
-
-
Figure 1 : Ideal opamp inverter
I ≈ 0
35
When using virtual ground, node voltage equations are formulated for each node except
the output node (Vo in this case). This is because the output impedance is zero, which
translates to shorting the current at this terminal to ground makes its node equation unnec-
essary [9]. The transfer function for this circuit is Eq. (7).
(7)
This demonstrates the ease of modeling with ideal opamps. The use of the virtual ground
technique eliminates any specifics of the internal properties of the opamp and effectively
removes it from the circuit for analysis.
3.2.2.2 Non-Ideal Opamp Models
Non-ideal opamp models are improvements on the ideal opamp model that emu-
late the behavior of real opamps more accurately. The first improvement on the ideal
model eliminates the approximations that made the null port assumption possible. The
gain and input resistance are now assumed to be finite and the output resistance is non-
zero. In Figure 2, an opamp with this approximation is shown in an inverting configura-
tion.
The transfer function of this circuit can be determined using the internal properties of the
non-ideal opamp model to yield the expression in Eq. (8).
(8)
H s( )Vo s( )Vs s( )---------------
R2–
R1---------= =
H s( )Vo s( )Vs s( )---------------
Ri Ro A– R2( )Ri R1 R2 Ro+ +( ) R1 R2 Ro+( ) ARiR1+ +--------------------------------------------------------------------------------------------------------= =
36
Note that if the ideal opamp assumptions are applied to this transfer equation, the result is
the same as that in Eq. (7) for the ideal opamp inverter.
Another non-ideality that can be added to the opamp model is that which is caused
by DC errors. The amplifier stages within the opamp are often DC coupled, which can
cause errors in the overall amplifier characteristics. The two main sources of these errors
are bias current and offset voltage. For modeling using voltage transfer functions with the
prescribed VHDL technique, the offset voltage is of greater importance and is much sim-
pler to represent. The offset voltage is the voltage output that is measured from an opamp
output that has no differential input at all; it is usually a small DC value. This can be mod-
eled as shown below in Figure 3 with a DC source (Vos) in series with the negative input
port of a non-ideal opamp with no DC error modeling.
RoRi
Vi
I i
AV i
+
- Vo
R1
R2
+
Vs
+
-
-
Figure 2 : Non-ideal opamp inverter
37
Most operational amplifiers also have high frequency limitations related to those
of the transistor circuits in the opamp. These limitations can be modeled with a simple RC
low pass filter between the input resistance and dependent voltage source of an opamp
model without frequency consideration. The dependent source is altered to amplify the
voltage from the filter. This models the dominant pole of the frequency response [13].
Many opamps have other poles at higher frequencies, but these can be ignored because
their effect is minimal. The dominant pole can be modeled where the critical roll-off fre-
quency . The gain of the opamp can then be modeled as in Eq. (9):
(9)
+
+
--
Vos
-
+
Opamp withDC errors
Opamp withno DC errors
Figure 3 : Opamp model with offset voltage
ωc 1 RC⁄=
A s( )Adcωc
s ωc+---------------=
38
The gain at zero frequency, also referred to as the DC gain, isAdc. The product in the
numerator of Eq. (9) is the gain bandwidth product (GB) of the amplifier. This gain func-
tion can be substituted for the constant gainA in Eq. (8) and other transfer functions for
which frequency modeling is desired. There are other non-linear effects, such as slew rate
and noise, which are not addressed here but can also be included in non-ideal opamp mod-
els [9].
3.2.3 Active Filter Modeling
Active filters are filter circuits that use opamps and passive components to perform
filtering. The passive components used with active filters are resistors and capacitors only;
inductors are not used. This allows active filters to be fabricated on integrated circuits, and
they are often less in weight and consume less space than their passive counterparts.
Active filters can be mass produced at a low cost compared to passive filters, which are
very expensive due to their discrete inductor components. The major structural difference
between active and passive filters is the presence of opamps. Thus the analysis of active
filters depends on the opamp model chosen. Once the opamp model is included in the
active filter circuit, analysis of active filters is simply a hybrid of passive network and
opamp analysis.
For finding the transfer function of circuits with an ideal opamp model, the node
voltage method is used to determine node equations. The equations for the network are
then adjusted using the virtual ground method to set the voltage at the opamp input port to
zero, eliminating one node equation. A second equation is omitted corresponding to the
39
output node. The transfer function may then be directly determined [13]. When non-ideal
opamp models are used, the circuit corresponding to the model is inserted in place of the
opamp in the circuit. This produces a network of passive components including resistors,
capacitors, and various dependent and independent voltage sources from which a transfer
function may be determined in standard fashion. Note that the more complex and accurate
the opamp model is, the more complex the transfer function is relative to the transfer func-
tion determined with an ideal opamp model. For the VHDL modeling technique, it is wise
to keep track of the order of each function determined. It should be possible to cascade
functions of higher order so that each is at most second order. This would produce 2 or
more finite difference equations which individually represent nodal transfer functions but
together model the entire filter.
40
CHAPTER 4
IMPLEMENTATION AND RESULTS
This chapter discusses the implementation of the mixed signal method described in
Chapter 3, provides an example of the using this technique, and compares the results
against those of an analog simulation performed with Accusim. The discussion of the
implementation explains the basic types and structures necessary to describe analog cir-
cuits in VHDL. This includes many of the data types described in Section 3.1.4, VHDL
functions representing transfer functions, and opamp approximations. The example circuit
is a synchronous level-detector circuit. The functionality of this circuit is detailed later in
this chapter. The final portion of this chapter discusses the results of the VHDL simulation
of the example and compares them to the results obtained by simulating an analog model
using the Mentor Graphics Accusim simulator. The results are very good in accuracy and
speed.
41
4.1 Implementation
In order to implement the VHDL mixed-mode simulation technique, several things
must be in place first. Foremost of these are the bus resolution functions and the data type
definitions. The bus resolution function is used to resolve signals for which multiple val-
ues have been assigned. The data types are mostly subtypes of the REAL type and are
used to differentiate between quantities such as resistance, voltage, frequency, and so
forth. Transfer functions for the different components that could be modeled are also
determined and coded before the descriptions of the analog components are entered. These
functions are put in a PACKAGE that can be accessed by all components. Finally, the use
of opamp models is discussed, both ideal and non-ideal, and methods for implementing
them are suggested.
4.1.1 VHDL Structures
The first structure is a package used to define a function, as detailed in [8]. This
function is used as the resolution function for the type that will define the current signal
type. The package and the function definition of the summingbus resolution function
(brf), summing_brf_val .,can be found in Figure 4. This function creates an array
(data_array ) that has one element for each of the given signal’s drivers. The value of
the signal will be the sum of the values assigned by each driver, which is the value of each
42
element in the array. This effectively sums the currents at a node. If only one driver exists,
than the value assigned by that driver will be the signal value.
The next structure analyzed is the data structure package which defines the types
and constants used in the analog simulation. This is based on the package given in [8].
This file is only a package header since there are no function definitions, only type defini-
tions. The package is shown in Figure 5 on page 43. The only constants assigned in this
package refer to the analog time step. The time step is represented in two data types: the
physical data type TIME and the floating point data type REAL. This is so the time step
can be used in the scheduling portion of a signal assignment statement and as part of cal-
PACKAGE summing_bus_res_function ISTYPE summing_val IS ARRAY ( integer RANGE <> ) OF real ;FUNCTION summing_brf_val ( data_array : summing_val )
RETURN real ;SUBTYPE brf_real IS summing_brf_val real ;
END summing_bus_res_function ;
PACKAGE BODY summing_bus_res_function ISFUNCTION summing_brf_val ( data_array : summing_val )
RETURN real ISVARIABLE i : integer ;VARIABLE result : real := 0.0;
BEGINFOR i IN data_array’RANGE LOOP
result := result + data_array(i) ;END LOOP ;RETURN result ;
END summing_brf_val ;
END summing_bus_res_function;
Figure 4 : Summing Bus Resolution Function
43
culations needed in solving a finite difference equation. The value of the time step must
matchexactly the time step, or resolution, of the digital simulator. Otherwise the results
will be invalid. The next definitions are those which identify the varying signals voltage
USE work.summing_bus_res_function.all ;
PACKAGE my_data_structure IS---- analog time step--
CONSTANT analog_time_delta : time := 100 ps ;CONSTANT analog_time_delta_real : real := 1e-10;--s
---- analog signal--
SUBTYPE voltage IS brf_real ;SUBTYPE current IS brf_real ;
---- analog reference--
SUBTYPE analog_reference_aref IS real ;---- analog component--
SUBTYPE res IS real ;SUBTYPE cap IS real ;SUBTYPE ind IS real ;
---- analog threshold levels--
SUBTYPE analog_v_level IS real ;---- analog gain--
SUBTYPE analog_vv_gain IS real ;---- general parms--
SUBTYPE frequency IS real ;SUBTYPE amplitude IS real ;
--END my_data_structure ;
Figure 5 : Data Structures Package
44
and current. Thecurrent type uses thebrf_real bus resolution function defined in
Figure 4. The reference signal types and parameter types are defined. The analog reference
signal is defined to be a subtype of the REAL type, as are most of the reference signals and
parameter types. The passive analog components have type definitions for resistors,
capacitors, and inductors as shown in Figure 5. The threshold level type is used to set sat-
uration and clamping limits on circuits. The gain type is used to define the gain of an
amplifier. The general parameters include types for frequency and amplitude. These types
are used mostly in descriptions of analog sources, such as function generators.
The transfer functions for the various circuits are defined in a passive behavior
package. The package header defines the headers for all functions which will be further
USE work.my_data_structure.all ;
PACKAGE my_passive_behaviors IS
FUNCTION phpf1 (CONSTANT c : cap;CONSTANT r : res ;SIGNAL von_1, vin_1, vin : voltage
) RETURN voltage ;
FUNCTION alpf2ni (CONSTANT rf, rs, r : res;CONSTANT c : cap ;SIGNAL vn_1, vn_2, vin : voltage
) RETURN voltage ;
FUNCTION alpf1i (CONSTANT r1, r2 : res;CONSTANT c : cap;SIGNAL vn_1, vin : voltage
) RETURN voltage ;
END my_passive_behaviors ;
Figure 6 : Package header for passive functions
45
defined in the package body. The function headers establish the parameters that will be
passed to the function and the data type that the function returns. The package header for
these functions is shown in Figure 6 on page 44. The transfer functions will be analyzed in
Section 4.1.2. All functions were named by the same convention.The first letter denotes
either apassive oractive filter. The next three letters indicate whether the filter is low-
pass (lpf) or high-pass (hpf). Other acronyms could be generated for band-pass and
band-stop filters. The number following the filter type indicates the order of the filter;1st,
2nd, and so forth. Finally, a suffix is added for active filters to illustrate whether the filter
configuration isinverting ornon-inverting. Thus, the function calledalpf2ni models
an active, low-pass filter that is second order and non-inverting.
4.1.2 Transfer functions for behavioral components
All the transfer functions discussed in this section are built assuming ideal models
for all opamps. The first transfer function listed in the passive behaviors package is the
transfer function for a passive high-pass filter (Figure 7 on page 46). The value oftau is
the RC time constant of the circuit. The constantsr andc correspond to the elements
shown in Figure 7. Note that previous values for both the input (vin_1 ) and the output
(von_1 ) are needed because the derivative of each voltage appears in the continuous time
differential equation.
46
The second transfer function listed in Figure 6 on page 44 is for a non-inverting
active low pass filter of second order shown in Figure 7. Again, the passive components
rf , rs , r , andc correspond to those indicated in the circuit diagram. The differential
equation for this filter contains a second order derivative (as indicated by the filter order),
and thus the values of the output voltage vout at the previous two time stepsvn_1 and
vn_2 are used. The variablek denotes the gain due to the non-inverting configuration of
the circuit.
FUNCTION phpf1 ( CONSTANT c : cap;CONSTANT r : res ;SIGNAL von_1, vin_1, vin : voltage)
RETURN voltage ISVARIABLE tau : real;VARIABLE vout : voltage;
BEGIN
tau := c * r;vout := ( vin - vin_1 + von_1) / (1.0 +
analog_time_delta_real / tau);RETURN vout;
END phpf1;
Figure 7 : Circuit and transfer function for passive high-pass filter
+
-
+
-
voutvin r
c
47
The third transfer function described is for an inverting, first-order, low-pass filter.
This function is shown in Figure 7. The constant function parameters map to the circuit
elements as indicated in the figure. Note that in the numerator of the equation, the input
voltage is subtracted from the previous state of the output voltage. This demonstrates the
inverting property of this filter, because as the input increases, the output decreases. The
FUNCTION alpf2ni ( CONSTANT rf, rs, r : res;CONSTANT c : cap ;signal vn_1, vn_2, vin : voltage)
RETURN voltage ISVARIABLE tau, k, t : real;VARIABLE vout : voltage;
BEGIN
tau := r * c;k := 1.0 + rf / rs;t := analog_time_delta_real;vout := ( k*((t/tau)**2)*vin +
(3.0 - k)*(t/tau)*vn_1 + 2.0*vn_1 - vn_2 ) /( (t/tau)**2 + (3.0 - k)*(t/tau) + 1.0 );
RETURN vout;END alpf2ni;
Figure 8 : Circuit and transfer function for active low-pass filter (2nd order)
+
-
+
-
voutvin
rs
c
+
-
c
r r
rf
48
shunt resistorrs is not included in the function, indicating that it is unnecessary. This is
because the ideal opamp model is assumed, thus there is no current throughrs and the
voltage across it is zero.
To see how these functions are accessed in a VHDL component architecture, the
first-order, low-pass inverting filter is examined in Figure 4. The passive components of
the circuit are passed to the VHDL component in the entity via theGENERIC list. The
FUNCTION alpf1i (CONSTANT r1, r2 : res;CONSTANT c : cap;SIGNAL vn_1, vin : voltage)
RETURN voltage ISVARIABLE tau1, tau2, t : real;VARIABLE vout : voltage;
BEGIN
tau1 := r1*c;tau2 := r2*c;t := analog_time_delta_real;vout := ( vn_1 - (t/tau1)*vin ) / (1.0 + t/tau2);RETURN vout;
END alpf1i;
Figure 9 : Circuit and transfer function for active low-pass filter (1st order)
+
-
+
-
voutvin
c
+
-
r1
r2
rs
49
ASSERT statement guarantees that these component values are positive and non-zero. The
PORT list for this entity includes the input and output signals, and could also list reference
signals if needed. The architecture of this component declares a signalVn_1 that repre-
sents the value of the previous state of the output voltage. The TIME typed constant
analog_time_delta appears to schedule the present voltagev_out to become the
old valueVn_1 AFTER the next iteration. Without scheduling, the signal assignment of
the present value would be attempted simultaneously with that of the previous value, caus-
ing the simulator to constantly update both values during a single time step until they con-
verged. This usually does not happen, and the simulation would be incorrect or would
most likely fail.
ENTITY active_lpf_1_inv ISGENERIC ( CONSTANT r1 : IN res;
CONSTANT r2 : IN res;CONSTANT c2 : IN cap);
PORT ( v_in : IN voltage := 0.0;v_out : BUFFER voltage := 0.0);
BEGIN
ASSERT ( (r1>0.0) AND (r2>0.0) AND (c2>0.0) )REPORT “ERROR: R and C values must be > 0.0”SEVERITY FAILURE;
END active_lpf_1_inv;
ARCHITECTURE lpf_1_i_behavior OF active_lpf_1_inv ISSIGNAL Vn_1 : voltage := 0.0;
BEGIN
v_out <= alpf1i(r1, r2, c2, Vn_1, v_in);Vn_1 <= v_out AFTER analog_time_delta;
END lpf_1_i_behavior;
Figure 10 : VHDL component for 1st-order active low-pass inverting filter
50
There are other analog components that can be useful in a VHDL analog model.
One of these is the analog switch shown in Figure 11. This component uses theBLOCK
construct to guard the subsequent signal assignment statement. The value ofv_in is
passed tov_out only when the guard condition is satisfied, which in this case is that
sel1 is a logic ‘1’. This switch is a directional switch with a unique input and a unique
output. TheBUS identifier in the entity description is necessary to allowv_out to be
assigned with a guarded signal assignment. It means that there is no driver from this com-
ponent forv_out when the guard condition is false, so the signal value is assigned in
another component or the value is indeterminate.
Other components that prove useful are function generating components. A VHDL
component that generates a sinusoidal function is listed in Figure 12. The generics deter-
mine the characteristics of the sine wave generated. There is no input to the generator
ENTITY analog_switch ISPORT ( v_in : IN voltage := 0.0;
v_out : BUFFER voltage BUS:= 0.0;sel1 : IN qsim_state);
END analog_switch;
ARCHITECTURE switch_behavior OF analog_switch ISBEGIN
B1 :BLOCK ( sel1 = ‘1’ )BEGIN
v_out <= GUARDED v_in;END BLOCK B1 ;
END switch_behavior;
Figure 11 : VHDL component for analog switch
51
other than these generics. The two output signals for this generator are a sine wave
(v_sine ) and its inverse (v_sine2 ) at the same dc offset. Variables declared in the
architecture represent the pure sinusoidal value (temp_v ), and the time elapsed in the
present period (simtime ). TheIF statement is used to resetsimtime to the time step
value if it is within one time step of the period. Other generators, such as the square wave
generator in the Appendix, can be modeled with this same technique.
Finally, there are useful opamp circuits that have only resistive elements, such as
inverting amplifiers and voltage followers. These components can be represented in
ENTITY func_gen ISGENERIC ( CONSTANT amp : IN amplitude := 1.0 ;
CONSTANT offset : IN analog_v_level := 0.0 ;CONSTANT freq : IN frequency := 0.001 );
PORT ( SIGNAL v_sine , v_sine2 : OUT voltage := 0.0 );END func_gen ;
ARCHITECTURE func_gen_behavior OF func_gen ISBEGIN
P1 :PROCESS
VARIABLE temp_v , simtime : real := 0.0 ;CONSTANT period : real := 1.0/freq;
BEGINtemp_v := amp * sin(6.2832*freq*simtime) ;v_sine2 <= -temp_v + offset ;v_sine <= temp_v + offset ;WAIT FOR analog_time_delta ;IF ( (simtime <= period) and (simtime > (period -
analog_time_delta_real)) ) THENsimtime := analog_time_delta_real ;
ELSEsimtime := simtime + analog_time_delta_real ;
END IF ;END PROCESS P1 ;
END func_gen_behavior;
Figure 12 : VHDL component for function generator
52
VHDL without function calls, because the output equation for the component is so simple.
The example listed in Figure 7 is the description code for an opamp inverter. The entity
description for this component passes the component values in the generic list and
declares the input and output signals in the port list, just as the entity description of the
active filter in Figure 4 on page 42. In the architecture, the simplicity of the ideal opamp
inverter model is obvious. For this reason, a separate function is not used to describe the
output signal.
ENTITY opamp_inverter ISGENERIC ( CONSTANT r1 : IN res ;
CONSTANT r2 : IN res);PORT ( v_in:IN voltage := 0.0 ;
v_out:BUFFER voltage := 0.0) ;BEGIN
ASSERT ( (r1 > 0.0) AND (r2 > 0.0) )REPORT “ERROR: R and C values must be > 0.0” SEVERITY FAILURE ;
END opamp_inverter ;
ARCHITECTURE inverter_behavior OF opamp_inverter ISBEGIN
v_out <= (-r2 / r1) * v_in ;END inverter_behavior;
Figure 13 : Circuit and VHDL component for inverting amplifier
+
-
+
-
voutvin+
-
r1
r2
53
4.1.3 Opamp Implementation
As seen in the previous section, ideal opamp models are easily implemented in
VHDL, since this model does not add any complexity to the circuit transfer function
model. However, non-ideal opamps with custom parameters may be added to these mod-
els. Quantities such as offset voltage, and input and output impedance that are introduced
in Section 3.2.2.2 can be included in VHDL functions and have specific values passed to
the component models as generics. For example, the opamp inverter of Figure 7 can be
made non-ideal by implementing Eq. (8) on page 35 in the output signal assignment state-
ment. This could be further improved by adding the offset voltage as a DC error. The
equations in Eq. (10a) and Eq. (10b) represent the output voltage for this case via superpo-
sition. Note that Eq. (10a) reduces to Eq. (8) forVos = 0.
(10a)
(10b)
The frequency characteristics of the opamp gain described by Eq. (9) can be substituted
for the constant gain in these equations. This will result in first-order differential equa-
tions. Note that ifVos is constant with respect to time, which it is for most opamp models,
all occurrences ofsVos will be equal to 0. In both models which useVos, the totalVo is
found by adding the components ofVo due toVos andVs.
Vo
Vs------
Vos 0=
Ro AR2–( ) Ri
Ri R1 R2 Ro+ +( ) R1 R2 Ro+( ) ARiR1+ +--------------------------------------------------------------------------------------------------------=
Vo
Vos--------
Vs 0=
Ro AR2–( ) R1
Ri R1 R2 Ro+ +( ) R1 R2 Ro+( ) ARiR1+ +--------------------------------------------------------------------------------------------------------=
54
4.2 Example Circuit: Synchronous Detector
The circuit that has been simulated to demonstrate these VHDL analog description
techniques is the Light Suppression Circuit (LSC). It is a synchronous detector and filter
circuit design by Miles Laboratories, Inc. A block diagram of the circuit appears in
Figure 14. The input to the LSC is a signal from a photodetector. Contained in this signal
is theideal signal: a square wave at frequencyf with a peak voltage level ofVpeak. This is
due to an LED that flashes at frequencyf. The voltage levelVpeak conveys information
about a specific property of the light that we wish to measure. Also contained in this input
signal are noise signals: sinusoidal voltage waveforms at various frequencies contributed
by ambient light. Some sources of ambient light include fluorescent lights, television, and
sunlight. This light contains the same property measured by the photodetector, and thus
adds unwanted noise to the ideal signal. The magnitude of this noise is higher than the
magnitude of the ideal signal [7].
The output signal of the LSC settles to an approximately DC voltage levelVo
which is proportional to the input levelVpeak by some gainK. This levelVo is the input to
an analog-to-digital converter which in turn feeds a digital processing circuit. Thus, the
LSC effectively filters out the noise produced by the ambient light while detecting the
peak voltage of the square wave produced by the LED. Such a filter can be used for other
applications requiring level detection and noise filtering. The circuit from which the
VHDL description is derived is fabricated on a breadboard with discrete components. The
models used in the VHDL description are ideal for all opamps in the circuit.
55
Figure 14 : Block Schematic of LSC
56
4.3 Results
Two models of the LSC were built and simulated. One model was constructed
from analog components contained in the Mentor Graphics AccuParts library. These com-
ponents model the discrete components used in the breadboard version of the circuit built
at Miles. These models are provided in most cases by the component manufacturers for
use with various SPICE-like simulators.They are complex models, sometimes containing
more than 50 circuit elements. An example of one such model is included in the Appen-
dix. The other model is a VHDL model of the LSC using many of the components listed in
Section 4.1 and in the Appendix. The components were all created by the method
described in Chapter 3, and are ideal models of the circuit components they represent.
As mentioned earlier, the LSC is both a synchronous detector and a noise filter. In
order to demonstrate the effectiveness of this circuit as a noise filter, it was necessary to
simulate both models with a compound waveform as the input to the circuit. This input
signal is shown in Figure 15. It is the sum of 5 voltage waveforms: the ideal signal and 4
external noise sources. These noise sources represent the three largest frequency compo-
nents caused by ambient room light and television light. These frequencies and their mag-
nitudes, estimated from RMS measurements performed at Miles, are shown in Table 2.
The ideal input signal used in simulating both models is also listed. This frequency range
provides a unique case that requires a small time step (high frequency) and a long simula-
tion interval (long settling time).
57
TABLE 2 : LSC INPUT COMPONENTS
Signal Frequency Magnitude
Ideal Signal 8 kHz 0 to -15 mV
Noise Signal 1 0 Hz (DC) 0.7 V
Noise Signal 2 60 Hz 0.15 V
Noise Signal 3 120 Hz 0.15 V
Noise Signal 4 17 kHz 89 mV
Trace
Input Signal
Figure 15 : Input to LSC Simulations
58
The results of simulating the Accusim and VHDL models of the LSC appear
below in Figure 16. Several observations can be made from this graph. First, the differ-
ence between the two waveforms is approximately 0.01 volts, or a relative error of 6.67%.
Considering the complexity of the opamp models used in the Accusim models and the
simplicity of the ideal models used by the VHDL circuit model, this is a good result. In
this case, the final DC value of the response is considered the most important part of the
result. Second, the effects of the more complex models are evident in the entire response.
There is much more damping that takes place with the Accusim models, and these effects
could be added to the VHDL model in the form of RC poles. Also, there are frequency
compensation effects in some of the Accusim opamp models (those that model frequency
compensated opamps) which are not included in ideal opamp models. The “X” points in
Figure 16 represent scaled experimental data measured from the breadboard version of the
LSC that indicate that the complex Accusim model accurately simulates the LSC. It is
important to note that although these additional non-idealities dampen the response, they
do not severely affect the final DC value of the result.
Third, close observation reveals that the curve indicating the Accusim response
begins at -4mv, while the VHDL response begins at 0V. This is due to the offset voltage
present in the Accusim models and not included in the ideal VHDL opamp models. Thus
one non-ideality accounts for 40% of the discrepancy between the final values of the 2
responses. Fourth, the time necessary to perform the two simulations differed drastically.
Table 3 shows the time measurements for the simulation of both models over a 50 ms sim-
ulation time. Note that the output time step for Accusim is longer than that of the VHDL
59
model. The VHDL time step is both the output and the simulation time step, so it is proba-
ble that the simulation time for the Accusim model was shorter at various times. Yet the
VHDL simulation produces output for each time step. The real time period for the VHDL
simulation is 6.1% that of the Accusim.
TABLE 3 : SIMULATION TIMES FOR LSC OVER 50ms INTERVAL
Model Real Time (s) CPU Time (s) Time Step (µs)
Accusim 2.61e+4 2.48e+4 2.35
VHDL 1.59e+3 N/A 0.50
Figure 16 : LSC Simulation Results: Accusim vs. VHDL
60
Now that the accuracy of the VHDL simulation has been validated, it can be used
to check the operation of the LSC. Figure 17 shows the results of VHDL simulations using
the same noise sources indicated in Table 2, but using different values ofVpeak for the
ideal signal. The values ofVpeak for the input of each response are indicated in the figure.
The VHDL model used for this is the same as that used for the Accusim comparison. The
final DC level of the response for this circuit is indeed proportional toVpeak by a constant
approximately equal to 9.5. It is also interesting to note that the circuits settle faster for
lower values ofVpeak, but the overshoot of those transient responses is higher. This dem-
onstrates the ease of using VHDL to quickly model and analyze the analog portion of a
circuit.
LSC Simulation-5mv
-10mv
-15mv
-20mv
Figure 17 : LSC Simulation Results for Different Values ofVpeak
61
CHAPTER 5
CONCLUSION AND FUTURE WORK
5.1 Conclusion
In conclusion, this thesis has shown the feasibility of using VHDL to model analog
circuits. This can be very useful for mixed-mode circuits. By combining standard digital
modeling techniques with the analog modeling techniques discussed in Chapter3, accurate
and effective mixed-mode simulation can be achieved. The high level models for analog
circuits in VHDL are easy to write and easy to modify. The results illustrated in Chapter4
show that even simple ideal VHDL models can produce accuracy comparable to that of
complex SPICE-like models. For complex circuits and long simulation periods, the
VHDL models simulate much faster than the analog models. The simplicity of the higher-
level behavioral models used in VHDL provide fewer calculations for the simulators than
the structural models used in SPICE-like simulation. Thus the simulations of the VHDL
model are faster.
62
5.2 Future Work
There is a great deal of future work available in this area. A complete library could
be developed that models an entire range of 1st and 2nd order filters in terms of the circuit
elements. Other libraries could be generated that use compnents that are not directed
towards application, but towards simulation and study. One such library would be a library
of transfer functions where the parameters are simply the coefficients ofs in the numerator
and denominator of the transfer function. Other libraries could be generated that model an
analog circuit in one component, but have multiple VHDL architectures for that compo-
nent that vary in complexity. A more advance project could entail coupling a VHDL
library of components to a library of IC layouts. This kind of mapping between tool librar-
ies could result in a design process that involves automated layout based on the connectiv-
ity of the VHDL models. Such a tool would be very powerful for circuit designers.
63
CHAPTER 6
REFERENCES
[1] AccuParts User’s Manual, Software Version 8.2, 1993.
[2] Analog Simulators User’s Manual, Software Version 8.2, 1993.
[3] Analog Simulators Reference Manual, Software Version 8.2, 1993.
[4] James Armstrong.Chip-Level Modeling with VHDL. Prentice Hall, Englewood
Cliffs, New Jersey, 1989.
[5] James R. Armstrong and F. Gail Gray.Structured Logic Design with VHDL. PTR
Prentice Hall, Englewood Cliffs, New Jersey, 1993.
[6] Robert Boylestad and Louis Nashelshy.Electronic Devices and Circuit Theory. 4th
Edition. Prentice Hall, Englewood Cliffs, New Jersey, 1987.
[7] Steve Detwiler, Personal Communications, July 1993.
[8] Randolph E. Harr and Alec G. Stanculescu, ed.Applications of VHDL to Circuit
Design. Kluwer Academic Publishers, Boston, 1991.
[9] Lawrence P. Huelsman.Active and Passive Analog Filter Design: An Introduction.
McGraw-Hill, Inc., New York, 1993.
[10] IsSpice3 User’s Guide, Intusoft, 1992.
64
[11] Seok-Yoon Kim, Nanda Gopal, and Lawrence T. Pillage. AWE Macromodels of
VLSI Interconnect for Circuit Simulation.1992 IEEE International Conference on
Computer-Aided Design. IEEE Computer Society Press, Washington, 1992.
[12] Guiseppe Massobrio and Paolo Antognetti.Semiconductor Device Modeling with
SPICE. 2nd Edition. McGraw-Hill, Inc., New York, 1993.
[13] Don A. Meador.Laplace Circuit Analysis and Active Filters. Prentice Hall,
Englewood Cliffs, New Jersey, 1991.
[14] Lawrence G. Meares and Charles E. Hymowitz.Simulating With SPICE. Intusoft,
San Pedro, California, 1988.
[15] Mentor Graphics VHDL Reference Manual, Software Version 8.2, 1993.
[16] James W. Nilsson.Electric Circuits. 2nd Edition. Addison-Wesley Publishing Co.,
Reading, Massachusetts, 1987.
[17] QuickSim II User’s Manual, Software Version 8.2, 1993.
[18] Gordon W. Roberts and Adel S. Sedra.SPICE for Microelectronic Circuits. 3rd
Edition. Saunders College Publishing, Fort Worth, 1992.
[19] Alec G. Stanculescu, Andy S. Tsay, Alexandru N. D. Zamfirescu, and Douglas L.
Perry. Switch-Level VHDL Descriptions.1989 IEEE International Conference on
Computer-Aided Design. IEEE Computer Society Press, Washington, 1989.
[20] System-1076 Design and Model Development Manual, Software Version 8.2,
1993.
[21] Chandramouli Visweswariah and Ronald A. Rohrer. Piecewise Approximate
Circuit Simulation.1989 IEEE International Conference on Computer-Aided
Design. IEEE Computer Society Press, Washington, 1989.
65
[22] Jiri Vlach and Kishore Singhal.Computer Methods for Circuit Analysi and
Desgin. 2nd Edition. Van Nostrand Reinhold, New York, 1994.
66
APPENDIX
The code for all VHDL models developed during this project are included here.
Following the VHDL models is an example of an Accuparts opamp model.
PACKAGE summing_bus_res_function IS
TYPE summing_val IS ARRAY ( integer RANGE <> ) OF real ;
FUNCTION summing_brf_val ( data_array : summing_val )RETURN real ;
SUBTYPE brf_real IS summing_brf_val real ;
END summing_bus_res_function ;
PACKAGE BODY summing_bus_res_function IS
FUNCTION summing_brf_val ( data_array : summing_val )RETURN real IS
VARIABLE i : integer ;VARIABLE result : real := 0.0;
BEGINFOR i IN data_array’RANGE LOOP result := result + data_array(i) ;END LOOP ;
RETURN result ;
END summing_brf_val ;
END summing_bus_res_function;
67
USE work.summing_bus_res_function.all ;
PACKAGE my_data_structure IS---- analog time step--
CONSTANT analog_time_delta : time := 0.5 us ;CONSTANT analog_time_delta_real : real := 5.0e-7;--s
---- analog signal--
SUBTYPE voltage IS brf_real ;SUBTYPE current IS brf_real ;
---- analog reference--
SUBTYPE analog_reference_aref IS real ;---- analog component--
SUBTYPE res IS real ;SUBTYPE cap IS real ;SUBTYPE ind IS real ;
---- analog threshold levels--
SUBTYPE analog_v_level IS real ;---- analog gain--
SUBTYPE analog_vv_gain IS real ;---- general parms--
SUBTYPE frequency IS real ;SUBTYPE amplitude IS real ;
--END my_data_structure ;
68
USE work.my_data_structure.all ;
PACKAGE my_passive_behaviors IS
FUNCTION phpf1 (CONSTANT c : cap;CONSTANT r : res ;SIGNAL von_1, vin_1, vin : voltage
) RETURN voltage ;
FUNCTION alpf2ni (CONSTANT rf, rs, r : res;CONSTANT c : cap ;SIGNAL vn_1, vn_2, vin : voltage
) RETURN voltage ;
FUNCTION alpf1i (CONSTANT r1, r2 : res;CONSTANT c : cap;SIGNAL vn_1, vin : voltage
) RETURN voltage ;
END my_passive_behaviors ;
PACKAGE BODY my_passive_behaviors IS---- High Pass RC Function--
FUNCTION phpf1 (CONSTANT c : cap;CONSTANT r : res ;SIGNAL von_1, vin_1, vin : voltage
) RETURN voltage ISVARIABLE tau : real;VARIABLE vout : voltage;
BEGINtau := c * r;vout := ( vin - vin_1 + von_1) / (1.0 +
analog_time_delta_real / tau);RETURN vout;
END phpf1;---- Active Non-Inverting LPF - 2nd Order--
FUNCTION alpf2ni (CONSTANT rf, rs, r : res;CONSTANT c : cap ;signal vn_1, vn_2, vin : voltage
69
) RETURN voltage ISVARIABLE tau, k, t : real;VARIABLE vout : voltage;
BEGINtau := r * c;k := 1.0 + rf / rs;t := analog_time_delta_real;
vout := ( k*((t/tau)**2)*vin +(3.0 - k)*(t/tau)*vn_1 + 2.0*vn_1 - vn_2 ) /( (t/tau)**2 + (3.0 - k)*(t/tau) + 1.0 );
RETURN vout;
END alpf2ni;---- Active Inverting LPF - 1st Order--
FUNCTION alpf1i (CONSTANT r1, r2 : res;CONSTANT c : cap;SIGNAL vn_1, vin : voltage
) RETURN voltage ISVARIABLE tau1, tau2, t : real;VARIABLE vout : voltage;
BEGINtau1 := r1*c;tau2 := r2*c;t := analog_time_delta_real;
vout := ( vn_1 - (t/tau1)*vin ) / (1.0 + t/tau2);RETURN vout;
END alpf1i;
END my_passive_behaviors;
70
LIBRARY std ;USE work.my_data_structure.all;USE work.my_passive_behaviors.all;USE std.standard.all;
ENTITY active_lpf_1_inv ISGENERIC (
CONSTANT r1 : IN res;CONSTANT r2 : IN res;CONSTANT c2 : IN cap);
PORT (v_in : IN voltage := 0.0;v_out : BUFFER voltage := 0.0);
BEGIN
ASSERT ( (r1>0.0) AND (r2>0.0) AND (c2>0.0) )REPORT “ERROR: R and C values must be > 0.0”SEVERITY FAILURE;
END active_lpf_1_inv;
ARCHITECTURE lpf_1_i_behavior OF active_lpf_1_inv IS
SIGNAL Vn_1 : voltage := 0.0;
BEGIN
v_out <= alpf1i(r1, r2, c2, Vn_1, v_in);Vn_1 <= v_out AFTER analog_time_delta;
END lpf_1_i_behavior;
71
LIBRARY std ;USE work.my_data_structure.all;USE work.my_passive_behaviors.all;USE std.standard.all;
ENTITY active_lpf_2_ninv ISGENERIC (
CONSTANT rf : IN res;CONSTANT rs : IN res;CONSTANT r : IN res;CONSTANT c : IN cap);
PORT (v_in :IN voltage := 0.0;v_out :BUFFER voltage := 0.0);
BEGIN
ASSERT ( (rf>0.0) AND (rs>0.0) AND (r>0.0) AND (c>0.0) )REPORT “ERROR: R and C values must be > 0.0”SEVERITY FAILURE;
END active_lpf_2_ninv;
ARCHITECTURE lpf_2_ni_behavior OF active_lpf_2_ninv IS
SIGNAL Vn_1, Vn_2 : voltage := 0.0;
BEGIN
v_out <= alpf2ni(rf, rs, r, c, Vn_1, Vn_2, v_in);Vn_1 <= v_out AFTER analog_time_delta;Vn_2 <= Vn_1 AFTER analog_time_delta;
END lpf_2_ni_behavior;
72
LIBRARY std, mgc_portable ;USE work.my_data_structure.all;USE mgc_portable.qsim_logic.all;USE std.standard.all;
ENTITY analog_switch ISPORT (
v_in : IN voltage := 0.0;v_out : BUFFER voltage BUS:= 0.0;sel1 : IN qsim_state);
END analog_switch;
ARCHITECTURE switch_behavior OF analog_switch IS
BEGIN
B1 :BLOCK ( sel1 = ‘1’ )BEGIN
v_out <= GUARDED v_in;END BLOCK B1 ;
END switch_behavior;
73
LIBRARY std ;USE work.my_data_structure.all ;USE std.math.all ;
ENTITY func_gen ISGENERIC (
CONSTANT amp : IN amplitude := 1.0 ;CONSTANT offset : IN analog_v_level := 0.0 ;CONSTANT freq : IN frequency := 0.001 );
PORT ( SIGNAL v_sine , v_sine2 : OUT voltage := 0.0 );
END func_gen ;
ARCHITECTURE func_gen_behavior OF func_gen IS
BEGIN
P1 :PROCESS
VARIABLE temp_v , simtime : real := 0.0 ;CONSTANT period : real := 1.0/freq;
BEGINtemp_v := amp * sin(6.2832*freq*simtime) ;
v_sine2 <= -temp_v + offset ;
v_sine <= temp_v + offset ;
WAIT FOR analog_time_delta ;IF ( (simtime <= period) and (simtime > (period -
analog_time_delta_real)) ) THENsimtime := analog_time_delta_real ;
ELSEsimtime := simtime + analog_time_delta_real ;
END IF ;
END PROCESS P1 ;
END func_gen_behavior;
74
LIBRARY std ;USE work.my_data_structure.ALL ;USE std.standard.all ;
ENTITY opamp_inverter ISGENERIC (
CONSTANT r1 : IN res ;CONSTANT r2 : IN res);
PORT (v_in: IN voltage := 0.0 ;v_out:BUFFERvoltage := 0.0 ) ;
BEGIN
ASSERT ( (r1 > 0.0) AND (r2 > 0.0) )REPORT “ERROR: R and C values must be > 0.0” SEVERITY FAILURE ;
END opamp_inverter ;
ARCHITECTURE inverter_behavior OF opamp_inverter IS
BEGIN
v_out <= (-r2 / r1) * v_in ;
END inverter_behavior;
75
LIBRARY std ;USE work.my_data_structure.all;USE work.my_passive_behaviors.all;USE std.standard.all;
ENTITY passive_HPF_1 ISGENERIC (
CONSTANT c1 : IN cap;CONSTANT r2 : IN res);
PORT (v_in :IN voltage ;v_out :BUFFER voltage := 0.0);
BEGIN
ASSERT ( (c1 > 0.0) AND (r2 > 0.0) )REPORT “ERROR: R and C values must be > 0.0”SEVERITY FAILURE;
END passive_HPF_1;
ARCHITECTURE HPF_1_behavior OF passive_HPF_1 IS
SIGNAL Von_1, Vin_1 :voltage := 0.0;
BEGIN
v_out<= phpf1(c1, r2, Von_1, Vin_1, v_in);Vin_1<= v_in AFTER analog_time_delta;Von_1<= v_out AFTER analog_time_delta;
END HPF_1_behavior;
76
LIBRARY std ;USE work.my_data_structure.all ;USE std.standard.all ;
ENTITY square_gen ISGENERIC (
CONSTANT del : IN time := 0 ms ;CONSTANT v1, v2 : IN analog_v_level := 0.0 ;CONSTANT period : IN time := 1us);
PORT (SIGNAL v_sqr , v_sqr2 : OUT voltage := 0.0);
END square_gen ;
ARCHITECTURE sqr_gen_behavior OF square_gen IS
BEGIN
P1 :PROCESS
VARIABLE delayed : boolean := TRUE;
BEGINIF (delayed) THEN
delayed := FALSE;WAIT FOR del ;
END IF ;v_sqr <= v1;v_sqr2 <= -v1;WAIT FOR period/2 ;v_sqr <= v2 ;v_sqr2 <= -v2 ;WAIT FOR period/2 ;
END PROCESS P1 ;
END sqr_gen_behavior;
77
LIBRARY std ;USE work.my_data_structure.all ;USE std.standard.all ;
ENTITY sum_node ISGENERIC (
CONSTANT w1 , w2 : IN analog_vv_gain := 1.0);PORT (
SIGNAL v1 , v2 : IN voltage := 0.0;SIGNAL v_o : BUFFER voltage := 0.0);
END sum_node;
ARCHITECTURE sum_behavior OF sum_node IS
BEGINv_o <= w1 * v1 + w2 * v2;
END sum_behavior;
LIBRARY std ;USE work.my_data_structure.all;USE std.standard.all;
ENTITY voltage_follower ISPORT (
v_in :IN voltage := 0.0;v_out :BUFFER voltage := 0.0);
END voltage_follower;
ARCHITECTURE buffer_behavior OF voltage_follower IS
BEGIN
v_out <= v_in;
END buffer_behavior;
78
* Copyright (c) Mentor Graphics Corporation,1988,1989,1990,1991 All Rights Reserved.
* UNPUBLISHED, LICENSED SOFTWARE.* CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE* PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.** CREATED using AccuPARTner sim_6.1a (12-09-91) on Thu Jan 9
17:55:24 1992* 5 PIN OPAMP MODEL.SUBCKT LT1013ACH 30 22 3 17 13* USAGE: XNAME INV NINV OUT VCC VEE $LT1013ACH*********************************** INPUT STAGE ************************************ INPUT GAIN STAGERC1 19 13 6889.39RC2 20 13 6889.39Q1 19 30 29 Q1Q2 20 27 28 Q2RE1 15 29 2411.03RE2 15 28 2411.03* THIRD POLEIEE 17 15 1.15507E-05REE 15 11 2.59724E+07* NEGATIVE INPUT COMMON MODE VOLTAGE CLAMPINGD1 15 24 DD2 15 23 DECLMP1 24 17 30 17 0.7 1ECLMP2 23 17 22 17 0.7 1* TEMPERATURE MODELING OF IB AND VOSGIB1 0 30 POLY(2) 10 0 40 0 0 1.18011E-08 7.5E-11GIB2 0 22 POLY(2) 10 0 40 0 0 1.18011E-08 -7.5E-11IIBTC 0 10 1RIBTC 0 10 1 TC=2.00286E-19 1.15107E-21IIOSTC 0 40 1RIOSTC 0 40 1 TC=-0.00745921 2.91375E-05IVOSTC 0 4 1RVOSTC 0 4 1 TC=0.25EVOS 27 22 4 0 4E-05*********************************** MID STAGE ************************************ ZERO FOR THE CMRRRZERO1 2 1 2E+08RZERO2 11 1 10CZERO 1 2 1.59155E-14EZERO 25 11 POLY(2) 30 11 22 11 0 0.5 0.5GCM 21 11 1 11 0.000887524RCM 25 2 1DCM1 2 11 DCMDCM2 11 2 DCM* GAIN STAGE DOMINANT POLE
79
GDM 21 11 19 20 3.14159E-05C2 18 21 5E-12R2 11 21 100000GB 18 11 21 11 0.0314159RO2 11 18 8.40966E+07* GAIN STAGE CLAMPINGECLMP 100 0 17 0 1DCLMP 18 100 DECLMN 101 0 13 0 1DCLMN 101 18 D* SECOND POLE AND ZEROG3 11 38 18 11 0.0001R3A 38 11 10000R3B 38 31 101.01C3 31 11 1.05042E-11* OUTPUT VOLTAGE CLAMPINGEVEE 12 11 13 11 1 1EVCC 16 11 17 11 -1 1* QUIESCENT CURRENT AND VIRTUAL GROUNDISPTC 0 9 1RISPTC 0 9 1 TC=0.00120064 -3.32661E-06GISP 17 13 POLY(2) 9 0 17 13 0 -6.40655E-06 1E-06EGND 11 0 POLY(2) 17 0 13 0 0 0.5 0.5*********************************** OUTPUT STAGE ***********************************IFP 16 7 0.000344856QP1 12 38 7 QP1VP 17 5 1QNO 5 7 3 QNO*IFN 8 12 0.000344856QN1 16 38 8 QN1VN 6 13 1QPO 6 8 3 QPO.MODEL Q1 PNP IS=0.8E-16 BF=29030.1 KF=1.00905E-06 AF=1.MODEL Q2 PNP IS=0.8E-16 BF=29030.1 KF=1.00905E-06 AF=1.MODEL D D.MODEL DCM D IS=1E-14 N=0.1 XTI=0.MODEL QN1 NPN BF=72.4941 RC=0.1 RB=1.MODEL QP1 PNP BF=72.4941 RC=0.1 RB=1.MODEL QNO NPN BF=72.4941 RC=0.1 RB=1.MODEL QPO PNP BF=72.4941 RC=0.1 RB=1.ENDS LT1013ACH
