Modeling and Simulation of Single-Event Effects in Digital Devices and ICs

1854 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 55, NO. 4, AUGUST 2008

Modeling and Simulation of Single-EventEffects in Digital Devices and ICs

D. Munteanu, Member, IEEE, and J.-L. Autran, Senior Member, IEEE

Abstract—This paper reviews the status of research in modelingand simulation of single-event effects (SEE) in digital devicesand integrated circuits, with a special emphasis on the currentchallenges concerning the physical modeling of ultra-scaled de-vices (in the deca-nanometer range) and new device architectures(Silicon-on-insulator, multiple-gate, nanowire MOSFETs). Afterintroducing the classification and the terminology used in thispaper, we firstly present the basis of the different transport modelsused in device-level simulation (drift-diffusion, hydrodynamic,Monte-Carlo and some approximated and exact quantum-me-chanical based approaches). We also focus on the main emergingphysical phenomena affecting ultra-short MOSFETs (quantumeffects, tunneling current, ballistic operation) and the methodsenvisaged for taking them into account at device simulation level.Several examples of device simulation are given at the end ofthis first part, including recent results on fully-depleted SOI andmultiple-gate devices. In the second part, we briefly survey thedifferent circuit-level modeling approaches (circuit-level simu-lation, Mixed-Mode, 3-D simulation of portions of circuits) ofsingle-event effects in integrated circuits. The SEU in advancedSRAM and SEE mechanisms in logic circuits are reminded. Theproduction and propagation of digital single-event transients(DSETs) in sequential and combinational logic, as well as thesoft error rate trends with scaling are particularly addressed.Recent bibliographical examples of simulation in SRAMs andlogic circuits are presented and discussed to illustrate these topicsat circuit-level.

Index Terms—Circuit simulation, compact models, device mod-eling and simulation, digital circuits, digital single-event transient,double-gate, FinFET, gate-all-around, multiple-gate MOSFET,nanowire MOSFET, omega-gate, quantum-mechanical effects,radiation effects, single-event effects, soft error rate, transportmodels, triple-gate.

I. INTRODUCTION

T HE phenomenal success of CMOS technology, and, byconsequence, the progress of the information technology,

can be attributed without any doubt to the scaling of the MOStransistor, which has been pushed during more than thirty yearsto increasing levels of integration and performances.Then,MOSFETs have been fabricated always smaller, denser, faster

Manuscript received October 30, 2007; revised May 21, 2008. Current versionpublished September 19, 2008.

D. Munteanu is with the L2MP-CNRS, UMR CNRS 6137, 13384 MarseilleCedex 13, France (e-mail: [email protected]).

J.-L. Autran is with the L2MP-CNRS, UMR CNRS 6137, Bât. IRPHE,49 rue Joliot Curie, BP 146, 13384 Marseille Cedex 13, France, and alsowith the Institut Universitaire de France (IUF), Paris, France (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNS.2008.2000957

and cheaper in order to provide ever more powerful productsfor digital electronics. Recently, the scaling rate has acceler-ated, and the MOSFET gate length is now less than 40 nm,with devices entering into the nanometer world [1], [2]. Theso-called “bulk” MOSFET is the basic and historical key-deviceof microelectronics: its dimensions have been reduced morethan times during the three past decades. However, thebulk MOSFET scaling has recently encountered significantlimitations, mainly related to the gate oxide SiO leakagecurrents [3], [4], the large increase of parasitic short channeleffects and the dramatic mobility reduction [5] due to highlydoped Silicon substrates precisely used to reduce these shortchannel effects. Technological solutions have been proposedin order to continue to use the “bulk solution” until the 45 nmITRS node. Most of these solutions envisage the introductionof high-permittivity gate dielectric stacks (to reduce the gateleakage, [4], [6]), midgap metal gate (to suppress the Silicongate polydepletion-induced parasitic capacitances) and strainedSilicon channel (to increase carrier mobility, [7]). However,in parallel to these efforts, alternative solutions to replace theconventional bulk MOSFET architecture have been proposedand studied in the recent literature. These options are numerousand can be classified in general according to three main di-rections: (i) the use of new materials in the continuity of the“bulk solution”, allowing increasing MOSFET performancesdue to their dielectric properties (permittivity), electrostaticimmunity (SOI materials), mechanical (strain), or transport(mobility) properties; (ii) the complete change of the devicearchitecture (e.g., multiple-gate devices, Silicon nanowiresMOSFET) allowing better electrostatic control, and, as a result,intrinsic channels with higher mobilities and currents; (iii) theexploitation of certain new physical phenomena that appearat the nanometer scale, such as quantum transport, substrateorientation or modifications of the material band structure indevices/wires with nanometer dimensions [2], [8].

As the MOSFET is scaling down, the sensitivity of integratedcircuits to radiation, coming from the natural space or presentin the terrestrial environment, has been found to seriouslyincrease [9]–[12]. In particular, ultra-scaled memory ICs aremore sensitive to single-event-upset (SEU) and digital devicesare more subjected to digital single-event transient (DSETs).Single-event-effects (SEE) are the result of the interaction ofhighly energetic particles, such as protons, neutrons, alpha par-ticles, or heavy ions, with sensitive regions of a microelectronicdevice or circuit. These SEE may perturb the device/circuitoperation (e.g., reverse or flip the data state of a memory cell,latch, flip-flop, etc.) or definitively damage the circuit (e.g.,gate oxide rupture, destructive latch-up events).

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MUNTEANU AND AUTRAN: MODELING AND SIMULATION OF SINGLE-EVENT EFFECTS IN DIGITAL DEVICES AND ICs 1855

Modeling and simulating the effects of ionizing radiation haslong been used for better understanding the radiation effects onthe operation of devices and circuits. In the last two decades, dueto substantial progress in simulation codes and computer perfor-mances which reduce computation times, simulation reached anincreased interest. Due to its predictive capability, simulationoffers the possibility to reduce radiation experiments and to testhypothetical devices or conditions, which are not feasible (or noteasily measurable) by experiments. Physically-based numericalsimulation at device-level presently becomes an indispensabletool for the analysis of new phenomena specific to short-channeldevices (non-stationary effects, quantum confinement, quantumtransport), and for the study of radiation effects in new device ar-chitectures (such as multiple-gate, Silicon nanowire MOSFET),for which experimental investigation is still limited. In thesecases, numerical simulation is an ideal investigation tool for pro-viding physical insights and predicting the operation of futuredevices expected for the end of the roadmap.

A complete description of the modeling and simulation ofSEE, including the history and the evolution of this researchdomain, have been presented in the reference survey papersby Dodd [9]–[11] and Baumann [12]. In this paper we wouldlike to review the current status of modeling of digital devicesand circuits, with a special emphasis on the current challengesconcerning the physical modeling of the ultra-scaled devicesand new device architectures. The paper is organized as fol-lows. Sections II-A and B of this introductive part present theclassification and the terminology used in the paper, as wellas the basic mechanisms of SEE, their impact on microelec-tronic devices, and the interest of modeling and simulation.The introduction is followed by Section II which discussesdevice modeling approaches and Section III which deals withcircuit level simulation. In Section II, we firstly present thetransport models used in device simulation (drift-diffusion, hy-drodynamic, Monte-Carlo and quantum approaches). Next theemerging physical phenomena in ultra-short MOSFETs are de-scribed in detail and the methods envisaged for taking them intoaccount in device modeling are presented. Two other importantissues of SEE simulation are discussed: the necessity of con-sidering a 3-D (real space) domain approach for device-levelsimulation and a realistic ion track as input in simulation.Several examples of simulation at device level are given at theend of Section II, based on our recent results on fully-depletedSOI and multiple-gate devices. In Section III, we briefly surveythe different circuit-level modeling approaches (circuit-levelsimulation, Mixed-Mode, 3-D simulation of full cells or por-tions of circuit) of single-event effects in integrated circuits.The SEU in advanced SRAM and SEE mechanisms in logiccircuits are reminded. Digital single-event transient (DSETs)production and propagation in sequential and combinationallogic, as well as the soft error rate trends with scaling are partic-ularly addressed. Three masking effects (logical, temporal andelectrical masking) which naturally reduce the soft-error ratein combinational logic are reminded. A few typical examplesof simulation in SRAM (bulk and SOI Double-Gate) and logiccircuits (inverter chains) are finally presented and discussed toillustrate these circuit-level approaches.

A. Classification and Terminology

As defined by the JEDEC standard JESD89A [13],single-event effects (SEE) indicate any measurable or ob-servable change in state or performance of a microelectronicdevice, component, subsystem, or system (digital or analog)resulting from a single energetic particle strike. We precise inthe following the most important terms and related definitions:

• Soft error: An erroneous output signal from a latch ormemory cell that can be corrected by performing one ormore normal functions of the device containing the latchor memory cell. As commonly used, the term refers to anerror caused by radiation or electromagnetic pulses and notto an error associated with a physical defect introducedduring the manufacturing process. Soft errors can be gener-ated from SEU, SEFI, MBU, MCU, and or SET. The termSER has been adopted by the commercial industry whilethe more specific terms SEU, SEFI, etc. are typically usedby the avionics, space and military electronics communi-ties. Historically, the term “soft error” was first introduced(for DRAMs and ICs) by May and Woods of Intel in theirApril 1978 paper at the IRPS and the term “single eventupset” was introduced by Guenzer, Wolicki and Allas ofNRL in their 1979 NSREC paper (SEU of DRAMs by neu-trons and protons).

• Single-event upset: A soft error caused by the transientsignal induced by a single energetic particle strike.

• Single-event upset cross-section: The number of events perunit fluence. For device SEU cross-section, the dimensionsare sensitive area per device. For bit SEU cross-section, thedimensions are area per bit.

• Single-event upset rate: The rate at which single event up-sets occur.

• Single event transient (SET): A momentary voltage excur-sion (voltage spike) at a node in an integrated circuit causedby a single energetic particle strike.

In addition to the previous terminology, we mention here, formemory, the following definitions:

• Hard error: An irreversible change in operation that is typ-ically associated with permanent damage to one or moreelements of a device or circuit (e.g., gate oxide rupture, de-structive latch-up events). The error is “hard” because thedata is lost and the component or device no longer func-tions properly even after power reset and re-initialization.

• Linear energy transfer (LET) of a particle: The energy lostby unit of length, which is expressed here in MeVcm mg(1 pC m MeVcm mg in Silicon). The magnitudeof the disturbance an incident particle causes primarily de-pends on the LET of that particle.

B. Basic Mechanisms of Single-Event Effects onMicroelectronic Devices

The physical mechanisms related to the production of SEE inmicroelectronic devices consist in three main successive steps:(1) the charge deposition by the energetic particle striking thesensitive region, (2) the transport of the released charge into thedevice and (3) the charge collection in the sensitive region of thedevice. In the following we succinctly describe these different


mechanisms, for a detailed presentation we invite the reader toconsult ref. [9]–[12].

Charge deposition (or generation): When an energetic par-ticle strikes the device, an electrical charge can be deposited byone of the following mechanisms: direct ionization by the inter-action with the material or indirect ionization, by secondary par-ticles issued from nuclear reactions with the atoms of the struckmaterial. Direct ionization typically characterizes heavy ions

of the space environment. They interact with the targetmaterial mainly by inelastic interactions and transmit a largeamount of energy to the electrons of the struck atoms. Theseelectrons produce a cascade of secondary electrons which ther-malize and create electron-hole pairs along the particle path. In asemiconductor or insulator, a large amount of the deposited en-ergy is thus converted into electron-hole pairs, the remaining en-ergy being converted into heat and a very small quantity in atomsdisplacement. It was experimentally shown that the energy nec-essary for the creation of an electron-hole pair depends on thematerial bandgap. In a Silicon substrate, one electron-hole pairis produced for every 3.6 eV of energy lost by the ion. Otherparticles, such as the neutrons of the terrestrial environment, donot interact directly with target material since they do not ionizethe matter on their passage. However, these particles should notbe neglected, because they can produce SEE due to their prob-ability of nuclear reaction with the atoms of materials whichcompose the microelectronic devices. This mechanism is calledindirect ionization. The products resulting from a nuclear reac-tion can deposit energy along their traces, in the same manneras that of direct ionization. Since the creation of the column ofelectron-hole pairs of these secondary particles is similar to thatof ions, the same models and concepts can be used.

Charge transport: When a charge column is created in thesemiconductor by an ionizing particle, the released carriers arequickly transported and collected by elementary structures (e.g.,

- junctions). The transport of charge relies on two main mech-anisms: the charge drift in regions with an electric field and thecharge diffusion in neutral zones. The deposited charges canalso recombine with other mobile carriers existing in the lattice.

Charge collection: The charges transported in the device in-duce a parasitic current transient, which could induce distur-bances in the device and associated circuits. The devices mostsensitive to ionizing particle strikes are generally devices con-taining reversely-biased - junctions, because the strong elec-tric field existing in the depletion region of the - junctionallows a very efficient collection of the deposited charge. The ef-fects of ionizing radiation are different according to the intensityof the current transient, as well as the number of impacted cir-cuit nodes. If the current is sufficiently important, it can inducea permanent damage on gate insulators (gate rupture, SEGR) orthe latch-up (SEL) of the device. In usual low power circuits, thetransient current may generally induce only an eventual changeof the logical state (cell upset).

C. Interest of Modeling and Simulation

The continuous reduction of the feature size in microelec-tronics requires increasingly complicated and time-consumingmanufacturing processes. At the same time, the fabrication of

emerging devices with alternative architecture, such as mul-tiple-gate or Silicon nanowire transistors, is very expensive andnot yet mature. This renders difficult and expensive a systemat-ical experimental investigation of the radiation effects on thesenew ultra-scaled devices. Since computers are today consider-ably cheaper resources, simulation is becoming an indispens-able tool for the device engineer, not only for the device opti-mization, but also for specific studies such as the device sensi-tivity when submitted to ionizing radiation. In addition, as theMOSFET dimensions are reduced in the nanometer scale, thedevice behavior becomes increasingly complicated while newphysical phenomena specific to the ultra-short channels appear(such as quantum confinement, quasi-ballistic transport or pa-rameter fluctuations). It becomes now mandatory to understandthe mechanisms of these emerging phenomena and their impacton the device sensitivity to radiation. Then, the growing interestin modeling and simulation of single-event effects in microelec-tronic devices relies on unique capabilities, summarized below:

(a) Simulation provides useful insights into device operationsince all internal physical quantities that cannot be mea-sured on real devices are available as outputs in simula-tion. Several quantities in real devices are sometimes toosmall or too fast and cannot be measured.

(b) “What if” studies, which are not feasible by experiment,can be performed in simulation [11].

(c) The predictive capability of simulation studies makes pos-sible the reduction of the radiation experiments [11].

(d) Emerging phenomena appearing in ultra-scaled devicescan be taken into account in simulation. The influence ofthese phenomena on the sensitivity to radiations of futuredevice can be investigated in simulation studies.

(e) Simulation offers the possibility to test hypothetical de-vices which have not yet been manufactured.

II. DIGITAL DEVICES MODELING

In this section, we survey the different device modeling ap-proaches of single-event effects at device-level. We begin bypresenting the transport models used in device simulation (drift-diffusion, hydrodynamic, Monte-Carlo and quantum models).Next, the emerging physical phenomena in ultra-short MOS-FETs (quantum confinement, ballistic transport, tunneling) aredescribed in detail and the methods envisaged for taking theminto account in simulation at device level are presented. Twoother important issues of SEE simulation are discussed: (i) thenecessity of using 3-D codes for the simulation of the actual de-vices and (ii) the ion track structure to be used as input in simu-lation. Several examples of simulation at device level are givenat the end of this section, mainly based on our recent results onfully-depleted SOI and multiple-gate devices.

A. Device Modeling Approaches

1) Transport Models: Historically, the first models used incarrier transport simulation describe the physical phenomenataking place in the device as functions of the electric field, evenif these phenomena depend on carrier energy [14]. This is pos-sible when considering that carrier energy is in permanent bal-ance with the electric field. Carrier transport in MOSFET de-vices is mainly due to electrostatic potential gradients and/or


gradients of carrier concentration [14]. The current density in abiased device is then usually modeled by the sum of a conduc-tion component (drift) and a diffusion component, as follows(for electrons):

(1)

where is the carrier mobility, is the thermal diffusion co-efficient, is the electric field and is the electron density.and depend on material and electric field and are connectedby the Einstein’s equation:

(2)

with the lattice temperature. Similar equations are consid-ered for holes (see the paragraph “Drift-Diffusion” below).

This traditional description of electronic transport constitutesthe “Drift Diffusion” (DD) model, the basic model used inCMOS devices simulation [14], [15]. This modeling level isgenerally adapted for long devices, with either weak or strongelectric fields (except for the modeling of impact ionization;see below in this paragraph). When the device feature size isreduced, the electronic transport becomes qualitatively differentfrom the traditional transport model since the average carriervelocity does not depend on the local electric field. Average car-rier velocity is a function of the carrier energy which dependson the variations in time and space of the electric field. In shortdevices steep variations of electric field take place in the activearea of the devices. Then, non-stationary phenomena (suchas velocity overshoot [16], [17]) occur following these rapidspatial or temporal changes of high electric fields. In smalldevices, non-stationary phenomena play an important role andmay dominate the device operation. Since DD model neglectsnon-stationary effects, new advanced transport models becomemandatory for accurate transport simulation in ultra-shortdevices [18]–[20].

A second important issue is related to impact ionization phe-nomenon, particularly relevant to the operation of Silicon-on-In-sulator (SOI) MOSFET with partially-depleted films. The im-pact ionization is an energy threshold phenomenon which di-rectly depends on the carrier energy. The physical mechanismof impact ionization consists in the generation of electron-holepairs in the device regions where a strong electric field exists(like in the vicinity of the drain regions). An electron with asufficient energy in the conduction band yields its energy to anelectron of the valence band. This last electron then jumps inthe conduction band and leaves a hole in the valence band. Itthus results a carrier multiplication in the device and the en-ergy threshold necessary for the phenomenon release is roughlythe semiconductor bandgap energy. In the case of MOSFET de-vices, the impact ionization phenomenon becomes important fordevice operation at high drain biases. The electrons generatedby impact ionization go into the channel and amplify the draincurrent. The holes are pushed back towards the substrate andare then evacuated or not, depending on the type of device. Inbulk MOSFETs they are collected by the substrate electrode andcreate a substrate current. In partially depleted SOI MOSFETs,the existence of the buried oxide prevents the hole evacuation

by the substrate electrode; they generally accumulate in the neu-tral region (body without external contact) of the Silicon film,and increase the body potential leading to drain current kinkphenomenon. Modeling approaches of impact ionization basedon the electric field (such as in the traditional “Drift-Diffusion”model) causes important quantitative and qualitative errors [21];in particular an over-estimation of the impact ionization rate isobserved even for long devices. An energy dependent advancedmodel is then mandatory for a more accurate modeling of theimpact ionization [22].

A large majority of the advanced models used in physics andengineering for the description of carrier transport is based onthe solution of the semi-classical approach of the BoltzmannTransport Equation (BTE). The most accurate approach is thenumerical solving of the BTE by the Monte Carlo (MC) method[16], [23]. Although very accurate results and valuable insightsare obtained with this method, MC approach is not routinelyused for simulation studies due to considerably time-consumingsimulation. An intermediate modeling level relies on hydrody-namic (HD) and energy-transport model (such as Energy Bal-ance) [18]–[20]. These models are obtained from deterministicsolutions of the BTE and provide a more accurate description ofthe carrier transport than the DD model.

However, the hydrodynamic model fails in the ballistic limit[24]. One therefore needs to move downward to the quantumtransport area in which, different approaches have been devel-oped such as the quantum hydrodynamic model, the quantumMonte-Carlo, the Wigner–Boltzmann approach and Green’sfunction approach. The latter is the most exact, but at the sametime the most difficult of all in terms of physical understandingand computational burden [25].

Fig. 1 illustrates the various levels of approximation de-scribing charge transport in semiconductor devices. Thishierarchical classification highlights the order of increasinglevel of model accuracy and complexity. In this figure, thetransport models range from the one-dimensional compact oranalytical modeling used in circuit-level simulation (top) to theexact numerical quantum-mechanical solution given by the NonEquilibrium Green’s Function (NEGF) method (bottom) [25].In the following we succinctly present the different numericaltransport modeling approaches; the compact and analyticalmodels will be discussed in Section III.

Drift-Diffusion: The drift-diffusion (DD) model was formany years the standard level of solid-state device modeling,mainly due to its simple concept and short simulation times.This approach is appropriate for devices with large featurelengths. This model considers that carrier energy does notexceed the thermal energy and carrier mobility is only a localfunction of the electric field (mobility does not depend oncarrier energy). As noted before, these assumptions are accept-able as long as the electric field changes slowly in the activearea, as is the case for long devices. All simulation softwarepackages for MOSFETs [26]–[28] are based on the solutionof the basic semiconductor equations consisting of Poisson’sequation coupled with DD transport model. The simulationcode initially solves the Poisson’s equation:

(3)


Fig. 1. Illustration of the hierarchy of transport models. Adapted after Vasileska and Goodnick [25].

where is the charge density, is the potential and is theSilicon permittivity. Laplace equation is solved in oxides. DDmodel is described by the following continuity equations:

(4)

(5)

where is the generation-recombination rate. Electron and holecurrent densities are given by:

(6)

(7)

In (6)–(7) the first term of the right-hand side is the drift com-ponent and the second term represents the diffusion component(which gives the name Drift-Diffusion to this model). Theseequations are discretized and solved on a meshed domain usingfinite-element technique.

The DD model considers that carriers gain maximum en-ergy instantaneously balanced with the electric field [15]. Then,non-stationary effects (velocity overshoot and carrier transportby thermal diffusion processes associated with electronic tem-perature gradients) specific to short devices are neglected inDD model, as well as the dependence of impact ionization onthe carrier energy. However, DD model is able to assimilatemodels describing quantum-mechanical confinement effects inshort-channel MOSFETs [see paragraph 2) in this section].

Hydrodynamic model: In reality, the carrier energy does notimmediately respond to changes in electric field. Mobility anddiffusion coefficients are tensor quantities that depend on sev-eral parameters besides electric field [29]. In nano-MOSFETs,the high internal electric fields result in substantial electronheating. The hydrodynamic model, obtained by taking the firstthree moments of the Boltzmann Transport Equation (BTE),represents the carrier transport effects in short devices more

accurately than the DD model. The hydrodynamic model is amacroscopic approximation to the BTE taking into account therelaxation effects of energy and momentum. In this model, thepropagation of electrons in a semiconductor is treated as theflow of a charged, thermally conducting gas subjected to anelectric field. This model removes several limiting assumptionsof DD: the carrier energy can exceed the thermal energy and allphysical parameters are energy-dependent. The current densityand the energy flow are modeled in HD model by the followingequations (given here for electrons [27]):

(8)

(9)

(10)

where is the electron temperature, is a model coefficient,is the energy flow, is the energy density loss rate, is thethermal conductivity and:

(11)

while the energy density loss is given by:

(12)

where is the energy relaxation time, is the SRH re-combination rate, is the impact ionization rate, is theAuger recombination rate, is the Silicon bandgap. Similarequations are used for holes. Usually, the mobility is mod-eled as a decreasing function of energy (because the scatteringrate increases with the energy of the particle). Finally, the con-tinuity equations given by (4) and (5) complete the system ofequations of the HD model.


Equations (8)–(12) are derived using the following simpli-fying assumptions:

(i) The temperature tensor reduces to a scalar.(ii) Closure of the hierarchy of moments in BTE is done by

relating the heat flux of the electron gas to the electrontemperature through the equation ,where the thermal conductivity is given by the Wied-mann-Franz law:

(13)

(iii) The relaxation time approximation is used for modelingthe effects of collisions on momentum and energy of theelectrons.

The advantage of the HD model over the DD model for trans-port simulation in short devices can be understood by analyzing(9), called the “energy-balance equation.” The left-hand side ofthis equation represents the variation of energy flow in space.On the right-hand side, the first term is related to the energy ab-sorbed by the electrons from the electric field. The second termis the time derivative of the energy density. Finally, the thirdterm gives the loss of energy through carrier recombination pro-cesses. Thus, the equation implies that the spatial variation ofenergy flow equals the sum-total of heat flow and transportedenergy. The applicability of the hydrodynamic model in MOS-FETs with short channels is justified since in “hot” areas wherethe electron temperature is high, it predicts a greater diffusionthan DD model, due to the finite value of the energy relaxationtime [29]. As a result, the average energy and the electron tem-perature are higher in the regions of strong electric fields com-pared to their equilibrium values. Moreover, the existing ther-moelectric field [the term in (8)] produces a drivingforce which makes possible the electron flow from hotter to-wards colder regions (carrier transport by thermal diffusion pro-cesses associated with electronic temperature gradients).

Velocity overshoot phenomenon is the immediate conse-quence of the finite time needed before the carrier energyreaches equilibrium with the electric field. This phenomenonis primarily due to the non-equivalence of electron momentumand energy relaxation times. The hydrodynamic model is ableto correctly predict velocity overshoot, which is not the caseof DD model, as previously stated. The velocity overshootphenomenon can be easily evidenced from the HD model [29].If one considers a one-dimensional case where the electric fieldincreases in the direction of motion of the particle, the result ofthe energy balance equation is that the average energy is lessthan the energy value corresponding to the local electric fieldunder homogeneous conditions. Since mobility is a decreasingfunction of energy, this means that the velocity given by HDmodel is stronger than the velocity obtained by DD model,which is based on a mobility that depends on the local electricfield.

Direct solution of the Boltzmann Transport Equation (BTE)by Monte Carlo method [16], [23], [25]: The most accurateapproach used in physics and engineering for the descriptionof carrier transport is the Monte Carlo (MC) method. Theresolution of the BTE by the Monte Carlo method provides

more accurate results than the energy transport models (hydro-dynamic), since it does not require simplifying assumptions.The principle of this method is to simulate the free particlemotion (referred to as the free flight) terminated by instan-taneous random scattering events in the semiconductor. Thesimulation algorithm is succinctly explained in the following.Carriers are represented like particles with a mass and an elec-tric charge. Firstly, free flight times are randomly generated foreach particle. In this phase of simulation all physical quantitiescharacterizing the particles (drift velocity, energy and position)are calculated. In a second phase, a scattering mechanism israndomly chosen according to the scattering probabilities ofall the possible scattering mechanisms. The scattering changesthe final energy and the momentum of the particle. At the endof this second phase one knows the new quantities related toeach particle. Then the procedure is repeated and the particlesare subjected to the same succession of physical phenomena(free flight time ended by a scattering mechanism). Samplingthe particle motion at various times throughout the simulationallows for the statistical estimation of physically interestingquantities such as the single particle distribution function, theaverage drift velocity in the presence of an applied electricfield, the average energy of the particles, etc. By simulatingan ensemble of particles, representative of the physical systemof interest, the non-stationary time-dependent evolution of theelectron and hole distributions under the influence of a time-de-pendent driving force may be simulated. MC simulation hasbeen used in the past for simulating radiation-induced chargecollection [30] and SEU in short-channel SOI MOSFETs [31],[32]. Although this method provides the most accurate sim-ulation of short-channel MOSFET, its use is limited becauseof enormous computational burden. This major drawback pre-vents Monte-Carlo method to be intensively used for simulationstudies of single-event effects.

Quantum transport approaches. As device dimensions con-tinue to shrink, the channel lengths (widths and/or thicknesses)are approaching the characteristic wavelength of particles (forexample, the de Broglie wavelength at the Fermi energy) andquantum effects are expected to be increasingly important.Quantum confinement was known to exist in inversion layersof past MOSFET technologies, but it has been consideredto have only a second-order influence on the overall devicebehavior. However, quantum effects (related to both carrierconfinement and quantum ballistic transport) may dominate thedevice operation in actual and future technologies: for example,it is expected that direct source-to-drain tunneling should bea serious limiting physical phenomena for the future devicescaling (typically below 6–8 nm channel length). The transportmodels presented above (Drift-Diffusion, Energy Transport,Monte-Carlo) do not have predictive capability for simulatingquantum transport in ultra-small structures; quantum transporttools are presently needed for accurate description of nano-de-vice operation. Different approaches have been developed, oneof the most exact being the solving of the Schrödinger equa-tion with open boundary conditions, as performed using theNon-Equilibrium Green’s Function (NEGF) formalism. At thesame time this approach is the most difficult, in terms of phys-ical complexity and computational burden. Other models have


been proposed, generally based on quantum corrections to clas-sical tools, such as Density–Gradient model [33], [34] (basedon a quantum-mechanical correction applied to the carrier den-sity within the Drift-Diffusion or the hydrodynamic model), theinclusion of quantum corrections into Monte-Carlo simulators(using the effective potential method [25]), the Wigner approach(which can be applied in the frame of Monte-Carlo simulation[35] or of a deterministic code). These approaches are less CPUtime consuming (except the Monte-Carlo approach), but lessaccurate. For example, the Wigner function approach does notallow one to simultaneously consider correlations in space andtime, both of which are expected to be important in nano-scaledevices. The NEGF formalism [36]–[39] has the capabilityto treat quantum-mechanical confinement, reflection and tun-neling at the same time. The most developed approaches inliterature currently consider effective mass band-structure ap-proximation and mode-space approach: the 1-D (respect. 2-D)Schrödinger equation is solved self-consistently with 2-D (re-spect. 3-D) Poisson equation in the perpendicular direction(s) tothe transport direction (with closed boundary conditions to takeinto account carrier confinement), and carrier transport fromsource-to-drain is treated in one-dimension using the NEGFformalism (with open boundary conditions). Fig. 2 shows thegeneral algorithm of a NEGF-based code developed in [39] forsimulating multiple-gate devices. This approach is sufficientlyaccurate for simulating the pure ballistic transport (withoutscattering) in the channel [37], which gives the highest limitof the device drain current. However, it has been shown thatactual and future ultra-short devices will certainly work in aquasi-ballistic regime, where the effects of scattering cannot beneglected. Then, the inclusion of elastic scattering effects dueto impurities and interface roughness has to be considered. TheNEGF approach offers the additional capability to take into ac-count scattering by using the so-called “Bütiker probe” method[40]: this approach provides a quantum mechanical descriptionof carrier transport and phase randomizing interactions forsimulating nanoscale MOSFETs. Recent NEGF developmentsalso consider the use of more sophisticated tight-bindingHamiltonian to take into account the “real” band-structure ofthe Silicon nanowire playing the role of the conduction channelin nanowire MOSFETs. Finally, NEGF formalism appearswell-adapted to treat the carrier transport in real-space with2-D or 3-D dimensions, as opposed to the mode-space (1-D)approach. In this sense, the Green’s function formalism iscertainly one of the most promising way for the future devel-opments of new generations of quantum transport simulationstools tackling with atomic scale issues, multi-dimensionaland time-dependent approaches. The rigorous time-dependenttreatment of the passage of an ionizing particle through a nan-odevice with the NEGF method is presently an open theoreticaland numerical problem. This simulation challenge is certainlya key-issue for predicting radiation effects in nanoelectronicscircuits.

2) Emerging Physical Effects: In this paragraph we describeseveral emerging physical phenomena that become to play anessential role in the operation of ultra-short devices, as well asthe physical models which can be used in simulation for takingthese phenomena into account.

Fig. 2. Schematic representation of a nanowire MOS transistor and typicalflowchart of a numerical code illustrating the different problems to solve in theNEGF-calculation of the output drain current (mode–space approach).

Quantum confinement: The aggressive scaling-down of metaloxide semiconductor field-effect transistors (MOSFETs) in thedeep submicrometer domain requires ultrathin oxides and highchannel doping levels for minimizing the drastic increase ofshort channel effects. The direct consequence is a strong in-crease of the electric field at Si/SiO interface, which createsa sufficiently steep potential well for inducing the quantiza-tion of carrier energy [Fig. 3(a)]. Carriers are then confined ina vertical direction in a quantum well (formed by the Siliconconduction band bending at the interface and the oxide/Siliconconduction band-offset) having feature size close to the elec-tron wavelength. This gives rise to a splitting of the energylevels into subbands (two-dimensional (2-D) density of states)[41], such that the lowest of the allowed energy levels for elec-trons (resp. for holes) in the well does not coincide with thebottom of the conduction band (resp. the top of the valenceband). In addition, the total density of states in a 2-D system isless than that in a three-dimensional (3-D) (or classical) system,especially for low energies. Carriers occupying the lowest en-ergy levels behave like quantized carriers while those lying athigher energies, which are not as tightly confined in the poten-tial well, can behave like classical (3-D) particles with threedegrees of freedom (Fig. 3). As the surface electric field in-creases, the system becomes more quantized as more and morecarriers become confined in the potential well. The quantum me-chanical confinement considerably modifies the carrier distri-bution in the channel: the maximum of the inversion charge isshifted away from the interface into the Silicon film [as shownin Fig. 3(b)]. Because of the smaller density of states in the 2-Dsystem, the total population of carriers will be smaller for thesame Fermi level than in the corresponding 3-D (or classical)case. This phenomenon affect the net sheet charge of carriersin the inversion layer, thus requiring a larger gate voltage inorder to populate a 2-D inversion layer to have the same number


Fig. 3. (a) Schematic illustration of the conduction band bending of a MOSstructure in inversion regime showing the different energy levels resulting fromthe quantization effects of the 2-D electron gas confined in the surface potentialwell. (b) Corresponding electron distributions in the direction perpendicular tothe interface for the classical and quantum-mechanical cases.

of carriers as the corresponding 3-D system. This leads to anincrease of the threshold voltage of a MOSFET, which is animportant issue, especially as the power supply voltages dropto lower levels. The gate capacitance and carrier mobility arealso modified by quantum effects. These considerations indi-cate that the wave nature of electrons and holes can no longerbe neglected in ultra-short devices and have to be considered insimulation studies. Quantum confinement becomes also impor-tant for the device response to single event. A detailed study ofquantum confinement effects on the immunity to single-event ofSOI Single-Gate and Multiple-Gate devices will be presented inSection II-B.

Various methods have been suggested to model thesequantum confinement effects. Among the approaches thatare compatible with classical device simulators based on thedrift-diffusion or hydrodynamic approaches, the physicallymost accurate method is to include the Schrödinger equationinto the self-consistent computation of the device character-istics. However, solving the Schrödinger equation in itself isvery much time-consuming. Various simpler methods havebeen suggested, such as the Van Dort model or the Hanschmodel. The van Dort model [42] expresses quantum effectsby an apparent band edge shift that is a simple function ofthe electric field. The model is based on the expression forthe lowest eigenenergies of a particle in a triangular potentialwell. Although van Dort model reproduces well the charac-teristics obtained with the Schrödinger equation, it does notgive the correct charge distribution in the device. The Hansch[43] model proposes a quantum correction of the density ofstates as a function of depth below the Si/SiO interface. Thecharge distribution is better reproduced, but the model stronglyoverestimates the impact of quantum confinement on the draincurrent characteristics.

An alternative to take into account quantum confinementis the Density–Gradient model [33], [34], coupled with theDrift-Diffusion or the hydrodynamic transport equations.Density–Gradient model considers a modified equation ofthe electronic density including an additional term dependenton the gradient of the carrier density. Then, a potential-likequantity is added in the classical electron density formula, asfollows:

(14)

where is the electron density, is the carrier temperature,is the Boltzmann constant, is the conduction band densityof states, is the conduction band energy, and is theelectron Fermi energy.

The impact of the quantum confinement on the carrier densityin the device can be taken into account by properly modeling thequantity . For Density–Gradient model, is usually given interms of a partial differential equation:

(15)

where is the reduced Planck constant, is the elec-tron density of states mass, and is a fit factor. Equations similarto (14) and (15) apply for the hole density. These new equationsfor electron and hole densities are then used in the self-consis-tent solving of Poisson’s equation and of the transport equation(Drift-Diffusion or hydrodynamic).

Ballistic and quasi-ballistic transport: Drift-Diffusion andhydrodynamic models fail at describing ballistic transport.The highest value of drain-source current which can be ob-tained for a given MOSFET geometry corresponds to the pureballistic current limit. As the channel length is increased, thecurrent decreases from this maximum value due to scatteringeffects. The transport makes a transition from the ballistic toquasi-ballistic or drift-diffusive regime with the longer channellengths. The carrier transport in the channel is considered tobe ballistic when carriers travel from the source to the drainregions without encountering a scattering event. This maybe possible if the feature size of the device becomes smallerthan the carrier mean free path [15]. If the carrier transport ispurely ballistic in the channel, modeling the device behaviorreduces to the description of the carrier transmission over andthrough the source-to-drain potential barrier. Fig. 4 illustratesthe source-to-drain potential energy profile in the channelof a nanotransistor (biased in its on-state) and the essentialmechanisms governing the quantum transport of carriers. Theamplitude and the width of the channel barrier are modulatedby the gate and drain voltages. Carriers having energy higherthan the maximum of the barrier, , are transmitted fromsource to drain by thermionic emission, while carrier withlower energy can traverse the channel only by quantum me-chanical tunneling through the source-to-drain barrier. Similarmechanisms can be also considered for electrons in the drainreservoir. Quantum reflections of carriers (i.e., wave-packets)also occur on the barrier not only at the extremities of the sourceand drain reservoirs but also in the channel, due to the potential


Fig. 4. Schematic representation of the source-to-drain potential energy profilein a nanotransistor (on-state) and illustration of the essential mechanisms gov-erning the quantum transport of carriers. Quantum reflections of carriers (i.e.,wave-packets) can occur on the barrier not only at the extremities of the source(1) and drain (3) reservoirs but also in the channel (2), due to the potential en-ergy drop induced by the source-to-drain voltage. These reflections can impactboth the tunneling and thermionic components of the pure ballistic response ofthe nanotransistor.

energy drop induced by the source-to-drain voltage (Fig. 4).These reflections can impact both the tunneling and thermioniccomponents of the pure ballistic response of the nanotransistor.

Numerous analytical and compact models of the ballisticand the quasi-ballistic transport have been proposed [44]–[46].Some models take into account only thermionic emission [44],others additionally consider quantum mechanical tunneling[45]. This later phenomenon was shown to be a fundamentalphysical limit for MOSFET scaling below 6–8 nm gate length.Other models take into account quasi-ballistic transport, suchas the general model based on the scattering theory whichcovers the full range from the ballistic to diffusive regimes [46].Full 2-D and 3-D numerical codes that treat quantum transport,optionally including scattering effects, have been also devel-oped, in the frame of NEGF formalism or Monte-Carlo/Wignerapproaches [25], [35]–[39]. Although great effort has beenmade in this topic in the last decade, ballistic transport is not yetincluded in commercial simulation codes. How quasi-ballisticand ballistic transport will influence the future device immunityto irradiation is an open question which has to be addressed infuture specific simulation studies.

3) Calibration of Device Simulator: A key step of device-level simulation is the careful calibration of the device sim-ulator before its use. The calibration is generally performedwith respect to the drain current characteristics (versus the drainvoltage and the gate voltage) and , in order toget the correct threshold voltage and the simulated characteris-tics to match those measured on real devices. This implies tocalibrate the main physical models of the device simulator, es-pecially the mobility model. This mandatory step can be delicateand time-consuming.

4) 2-D Versus 3-D Simulation: The phenomena related to anionizing particle striking a microelectronic device are naturally3-D mechanisms, due to both the tri-dimensional structure ofthe ion track and the 3-D structure of real devices. 3-D simula-tion is not only necessary for actual short/narrow devices, butalso for new device architectures for which 3-D electrostatic or

quantum confinement effects cannot be taken into account in a2-D simulation. 3-D simulation is also necessary when consid-ering non-normal incidence of the ion strike on the device.

The earliest works for device simulation consisted of one-di-mensional drift-diffusion models [47]. These 1-D devicemodels have evolved to 2-D device modeling approaches basedon either drift-diffusion equations or advanced hydrodynamicand energy balance models. Many charge collection and SEUstudies have been performed using these models. It has beenshown that in a 2-D rectangular simulation either the correctgenerated charge density or the correct total charge can besimulated, not both [11]. Different modified 2-D codes havebeen proposed in order to correct the geometry effects (scalingschemes that adjust Auger recombination rate [48], the use ofquasi-3-D codes based on cylindrical symmetry and coordinatetransformation [49]). A lot of studies have been performedusing these 2-D codes and valuable results and insights havebeen obtained; however, these codes can be only used forparticular devices.

The first fully 3-D codes were developed in the 1980s [50],but optimized 3-D codes running on desktop workstations havebeen commercially available only recently [26]–[28], typicallyin the last decade (mainly due to the enormous progress ofmicroprocessor performances as well as to the substantialimprovement of the 3-D code numerical methods and theirassociated meshing engines). A comparison of 2-D and 3-Dcharge-collection simulations has shown that while the transientresponses were qualitatively similar, quantitative differencesexisted in both the magnitude of the current response and thetime scale over which collection was observed [51]. The com-parison implies that 2-D simulations can provide basic insightwhile 3-D simulations become necessary when truly predictiveresults are to be obtained [11].

5) Ion track structure: The ion track structure to be used asinput in simulation is presently a major issue for device sim-ulation. The first representations included a simple cylindricalcharge generation with a uniform charge distribution and a con-stant LET along the ion path. However, the real ion track struc-ture is radial and varies as the particle passes through the matter.When the particle strikes a device, highly energetic primaryelectrons (called -rays) are released. They further generate avery large density of electron-hole pairs in a very short time anda very small volume around the ion trajectory, referred as theion track. These carriers are collected by both drift and diffu-sion mechanisms, and are also recombined by different mech-anisms of direct recombination (radiative, Auger) in the verydense core track, which strongly reduces the peak carrier con-centration. All these mechanisms modify the track distributionin time and space. As the particle travel through the matter, itloses energy and then the -rays become less energetic and theelectron-hole pairs are generated closer to the ion path. Then,the incident particle generates characteristic cone-shaped chargeplasma in the device [11].

The real ion track structure has been calculated using Monte-Carlo methods [52]–[54]. These simulations highlighted impor-tant differences between the track structure of low-energy andhigh-energy particles, even if the LET is the same (for detailssee [11], [55]). High-energy particles are representative for ions


existing in the real space environment, but they are not avail-able in typical laboratory SEU measurements [9]. Then the in-vestigation of the effects of high-energy particles by simulationrepresents an interesting opportunity, which may be difficult toachieve experimentally.

Analytical models for ion track structure have been also pro-posed in the literature and implemented in simulation codes.One of the most interesting models is the “non-uniform powerlaw” track model, based on the Katz theory [56] and developedby Stapor [57]. In this model, the ion track has a radial distribu-tion of excess carriers expressed by a power law distribution andallows the charge density to vary along the track (i.e., the LET isnot constant along the track) [58]. Other analytical models pro-pose constant radius non-uniform track or Gaussian distributionnon-uniform track.

In commercial simulation codes, the effect of a particle strikeis taken into account as an external generation source of car-riers. The electron-hole pair generation induced by the particlestrike is included in the continuity equations via an additionalgeneration rate. This radiation-induced generation rate can beconnected to the parameters of irradiation, such as the particleLET (defined as energy lost by unit of length ). The par-ticle LET can be converted into an equivalent number of elec-tron-hole pairs by unit of length using the mean energy neces-sary to create an electron-hole pair [59]:

(16)

where is the number of electron-hole pairs created bythe particle strike. By associating two functions describing theradial and temporal distributions of the created electron-holepairs, the number of electron-hole pairs is included in the conti-nuity equations via the following radiation-induced generationrate:

(17)

where and are the functions of radial and temporaldistributions of the radiation induced pairs, respectively. Equa-tion (17) assumes the following hypothesis: the radial distribu-tion function depends only on the distance traversed bythe particle in the material and the generation of pairs along theion path follows the same temporal distribution function in anypoint. Since function must fill the condition:

(18)

functions and are submitted to the following normal-ization conditions:

(19)

(20)

The ion track models available in commercial simulation codesusually propose a Gaussian function for the temporal distribu-tion function :

(21)

where is the characteristic time of the Gaussian functionwhich allows one to adjust the pulse duration. The radial distri-bution function is usually modeled by an exponential functionor by a Gaussian function:

(22)

where is the characteristic radius of the Gaussian functionused to adjust the ion track width.

Previous works have demonstrated that the different chargegeneration distributions used for the radial ion track does affectthe device transient response, but the variation is limited to 5%for ion strikes on bulk - diodes [11], [58]. Considering a LETwhich is not constant with depth along the path has a more sig-nificant impact on the transient response in bulk devices. Thekey parameters of the single event transient (peak current, timeto peak and collected charge) have up to 20% variation whenLET is allowed to vary with depth compared to the case of aconstant LET [58]. Nevertheless, the LET variation with depthhas no influence on the transient response of actual SOI deviceswith thin Silicon film.

B. Illustrations at Device Level for Advanced SOI Technologies

1) SEE Mechanisms in SOI Technologies: SOS (Silicon-on-Sapphire) and SOI technologies have been initially proposed asa solution to the problem of bulk devices sensitivity to ionizingirradiations [60]. In bulk Silicon devices, more than 99.9% ofthe substrate volume is not used and becomes a source of par-asitic effects, such as leakage currents, latch-up, etc. The SOImaterials eliminate this inconvenient, since the SOI structure it-self is based on the principle of separation between the activeregion (the Silicon film) and the inactive substrate by a more orless thick insulator layer (the buried oxide). Then, there is noparasitic PNPN structure leading to single-event latchup (SEL)in CMOS/SOI devices. In the 1970s and 1980s, SOS and SOItechnologies were primarily (exclusively) used for space andmilitary applications. But, besides their natural radiation hard-ness, it was observed that the parasitic capacities of SOI MOSdevices are lower than those of bulk MOS devices, due to theexistence of the buried oxide. This leads to enhanced speed per-formances for SOI circuits. Later, it was shown that the powerdissipated in SOI technologies is strongly reduced compared tobulk Silicon, and that higher integration density is obtained withSOI. All these advantages make SOI technology to graduallybecome a very attractive candidate for VLSI integrated circuitsfabrication. After more than three decades of materials researchand device studies, SOI wafers have definitively entered into themainstream of semiconductor electronics. SOI MOSFET showsenhanced short-channel effects immunity and offers new poten-tiality for extending Silicon devices into the nanometer region(sub-20 nm channel length). Concerning the sensitivity to radi-ation, the charge collection in SOI devices is limited to the Sil-icon film which is very thin compared to bulk Silicon devices.


This makes SOI device naturally hardened to single-event ef-fects. However, the unique configuration of SOI MOSFET’s isresponsible for novel mechanisms (such as floating-body) notoccurring in the bulk Silicon technology. The floating-body isat the origin of several parasitic phenomena specific to SOI de-vices like drain current overshoots and undershoots [61]–[63] orbipolar amplification. This last phenomenon is essential for thesensitivity of SOI devices and circuits to single-event [64]–[66].As it will be explained in the following, SOI devices are notinherently immune to the radiation environment due to bipolaramplification, although they have less sensitive volume thanbulk Silicon devices.

There are two major types of SOI NMOS and PMOS tran-sistor structures: fully depleted and partially depleted. Thefull or total depletion of the film depends on the Silicon filmthickness and doping level. Fully depleted (FD) SOI devices areusually designed with very thin films that are totally depletedin standard operation mode. In partially depleted (PD) SOIMOSFETs with submicron length, the lateral bipolar transistor(source-body-drain) can be easily turned on. The basic mecha-nism of the bipolar amplification is the following: the heavy-ionstrike on the device creates electron-hole pairs in the Siliconfilm. While minority carriers recombine quickly, the lifetime ofmajority carriers in the body region can be very long. Majoritycarriers that do not recombine can drift toward the sourceregion and raise the body potential. Then, the source-to-bodypotential barrier is lowered, which triggers the lateral parasiticbipolar transistor inherent to the SOI transistor. The potentialraise is maintained until majority carriers are recombined. Thebipolar current amplifies the collected charge and decreases theSEU/SET immunity, especially at low LET [67]. This effectis further enhanced by impact ionization mechanism inducedby the high electric field at the body-drain junction. The con-sequence is that the SOI immunity to radiation is degraded;although SOI devices have a smaller sensitive volume thanbulk Silicon devices, this is counterbalanced by the enhancedbipolar amplification [64]–[67].

To reduce these bipolar effects, the most common techniqueinvolves the use of body ties (which connect the floating bodyregion to a fixed potential). The excess holes created by the ionstrike no longer accumulate in the floating body region becausethey are evacuated through the body contact. This reduces con-siderably the parasitic bipolar transistor effects. However, bodyties do not completely eliminate the bipolar effect; a voltagedrop exists along the body tie due to its finite resistance, andthe reduction of bipolar effect is less effective. The ability ofbody ties to suppress the bipolar effect strongly depends on thelocation of the body tie in relation to the ion strike [68]. Thefarther the ion strike is from the body tie, the larger the effect ofthe parasitic bipolar transistor [64], [66], [69], [70].

Numerical simulation at device level has been widely used inliterature for the study of bipolar transistor and its effects on thesensitivity of SOI devices to ionizing radiation. For example, theoccurrence of bipolar amplification in spite of body ties has beensimulated in [65] for a 0.25 m gate length SOI PD n-channelMOSFET. Fig. 5 illustrates the hole current distribution in thesimulated device after the body irradiation. The parasitic bipolartransistor appears far from the body contact, near the source tobody junction, due to the accumulation of holes after irradiation.Holes are also generated by impact ionization near the high

Fig. 5. Hole current distribution during a transient irradiation of a 0.25 �mSOI NMOSFET with external body contact. After Ferlet-Cavrois et al. [65].© 2002 Institute of Electrical and Electronics Engineers Inc., reproduced withpermission.

electric field region near the drain junction. Fig. 5 highlights theholes diffusion mechanism toward the body contact. The dura-tion of this mechanism is relatively high (about several nanosec-onds), which explains the possible bipolar conduction [65], inspite of the existence of the body tie.

Bipolar amplification can also occur in fully depleted devices.Previous experimental and theoretical studies have shown that,generally, fully depleted SOI-based devices exhibit reducedfloating body effects and then lower bipolar amplification ofthe collected charge than partially-depleted SOI devices [65],[71], [72].

The bipolar transistor mechanism in fully depleted deviceshas been explained in [32] using Monte Carlo simulations of0.25 m fully depleted SOI transistors: after irradiation of an-channel MOSFET biased in its off state, excess holes are ac-cumulated in the channel (mainly near the gate oxide) and lowerthe potential barrier; then electrons diffuse from source to drainto maintain the electrical neutrality. This mechanism is compa-rable to the bipolar transistor effect in partially depleted SOItransistors [64]. Because bipolar amplification is less impor-tant for fully depleted than for partially depleted devices, cir-cuits based on fully depleted transistors are less sensitive tosingle-event upset than partially depleted circuits [72].

The effect of the parasitic bipolar transistor in SOI devicesis quantified using the bipolar gain, . The bipolar gain corre-sponds to the amplification of the deposited charge and is givenby the ratio between the total collected charge, , at the drainelectrode and the deposited charge, :

(23)

The total collected charge at drain electrode is given by:

(24)

The deposited charge in a SOI device is calculated as a functionof the particle LET using the following equation [73]:

MeVmgcm

m (25)


Fig. 6. Time evolution of currents induced by a heavy-ion strike with LET =0:4 pC=�m. JeD is the electron current at the drain electrode and JeS is theelectron current at the source. After Kobayashi et al. [74]. © 2006 Institute ofElectrical and Electronics Engineers Inc., reproduced with permission.

where is the Silicon film thickness and 10.3 is a multiplica-tion factor for Silicon (calculated using the Silicon density andthe energy needed for creating an electron-hole pair in Silicon

—[73]). In this equation a normal incident ion strike isconsidered and the LET is supposed constant along the ion pathin the active Silicon film.

When a heavy ion strikes an SOI MOSFET in the off-state,a drain current transient is observed at the drain terminal. Thistype of transient has been thoroughly investigated in literaturein both partially depleted and fully depleted SOI transistors. Itis well-known that these transients have two components: (i) aprompt component due to the discharge of excess electrons im-mediately after the ion strike and (ii) a slow-decay current dueto floating body effects (charge amplification due to parasiticbipolar effect). Recently, by separating these current compo-nents in the time domain, Kobayashi et al. have shown in [74]that the drain current transient has not two but three compo-nents: the two components reminded above and an additionalslow-decay component. The investigation of the difference be-tween the electron current flowing through the drain terminaland that through the source terminal has revealed the existenceof this new component, as shown in Fig. 6. This third com-ponent is a second discharge current of a portion of the de-posited electrons that is stored in the high-injection conditionbody to maintain quasi-neutrality. It was shown in [74] that thisdischarge current drastically expands the transient pulse width.Since the pulse width is an important feature of single eventtransient (see Section III), this third current component must becarefully taken into account in the analysis of single-event ef-fects. Finally, Kobayashi et al. analyses the effects of the devicedownscaling on this new transient component. Their investiga-tion shows that the stored- carrier discharge current has the pos-sibility to become a serious component for future miniaturizedSOI MOSFET.

Fig. 7. Bipolar gain in FD SG SOI devices for two gate lengths: 50 nm and80 nm. The experimental bipolar gain obtained at LET = 30MeV=(mg=cm )on 80 nm FD SG SOI device is also reported. After [75]. © 2006 Institute ofElectrical and Electronics Engineers Inc., reproduced with permission.

2) Simulation Study of Fully-Depleted SOI Technologies:The electrical response of Fully-Depleted SOI devices sub-mitted to heavy ions strikes have been largely simulated inliterature (e.g., in [65], [72], [75], [76]). In [75], 3-D quantumnumerical simulation has been used to highlight the influenceof quantum confinement effects on single-event transients in50 nm ultra-thin (11 nm thick Silicon film) FD Single-Gate(SG) SOI MOSFET. The simulation results have also beencompared to experimental data measured by heavy ion ex-periments on 50 nm FD SG SOI devices [75]. 3-D numericalsimulations have been performed with the 3-D Synopsis tools[26] and quantum confinement has been taken into accountusing the Density Gradient model calibrated on BALMOS3Dcode [77]. The physical parameters in simulation have beencalibrated in order to fit the simulated quantum drain current onthe static experimental data. The simulated irradiation track hasa Gaussian shape with narrow radius of 14 nm and Gaussiantime dependence, centered on 50 ps and with a characteristicwidth of 2 ps. An angle of incidence of the ion strike of 60 , asin the heavy ion experiment [75], has been also considered.

Ion strike simulation results performed in [75] have shownthat the collected charge and the bipolar gain (Fig. 7) are lower inthe quantum case, mainly due to the lower off-state current. For80 nm gate length device and for an ion strike near the drain witha MeV mg cm the bipolar gain in the quantumcase was found in excellent agreement with the experimentalresults (as shown in Fig. 7).

3) Simulation of Multiple-Gate Nanowires MOSFET andTrends for Next Technology Nodes: Simulation in the 3-Ddevice domain is the unique tool for exploring single-eventeffects in new device architectures which are not yet manu-factured or for which compact models do not exist or are notsufficiently accurate. For example, 3-D quantum simulationhas been used in [78] for investigating the drain current tran-sient produced by the ion strike in Multiple-gate nanowireMOSFETs with ultra-thin channels nm . Multiple-gatedevices are presently considered as one of the future possiblesolutions for replacing the bulk devices and continuing theMOSFET scaling in the nanometer scale [79]. A wide varietyof architectures, including planar Double-Gate (DG) [79], [80],


Fig. 8. Schematic description of the 3-D simulated DG, Triple-Gate, Omega-Gate and GAA structures and their main geometrical parameters considered in thiswork. The devices are classified as a function of the “Equivalent Gate Number” (EGN). The schematic cross-sections in the (y-z) plane are also shown. The positionof the ion strike is also indicated by the arrow; the ion strikes vertically in the middle of the channel (between the source and drain region) and in a direction parallelto the y axis. All structures have Silicon film with square section (t =W ). After [78]. © 2007 Institute of Electrical and Electronics Engineers Inc., reproducedwith permission.

Vertical Double-Gate (VRG) [81], Triple-Gate (Tri-gate) [82],FinFET [83], Omega-Gate ( -Gate) [84], Pi-Gate ( -Gate)[85], Gate-All-Around (GAA) [86], Rectangular or Cylindricalnanowires [87], has been proposed in the literature. Thesestructures exhibit a superior control of short channel effectsresulting from an exceptional electrostatic coupling betweenthe conduction channel and the surrounding gate electrode. Ithas been shown that the electrostatic control is enhanced whenincreasing the “Equivalent Gate Number” (EGN) from 2 (forDG devices) to 4 (for GAA devices where the gate electrodeis wrapped around the entire channel) [88]. The better controlof the channel potential also reduces floating body effects.Recent simulation studies show that Multiple-Gate devices areless sensitive to single event transients (SET) than Single-GateFully-Depleted SOI devices [89]–[92].

Quantum confinement effects are significant in Multiple-gatedevices, due to both ultra-thin Silicon films and the existenceof two confinement directions (for ). In [78] the im-pact of the quantum confinement on drain current transient andthe bipolar amplification in Multiple-gate nanowire MOSFETshas been investigated by 3-D quantum numerical simulation.Four different Multiple-Gate configurations have been consid-ered (Fig. 8): Double-Gate, Triple-Gate, Omega-Gate and Gate-All-Around, calibrated to fill the ITRS’2006 [1] Low Power(LP) technology requirements for the technology nodes corre-sponding to the years 2007, 2009 and 2011. These devices areexpected to be designed with 32 nm nm , 25 nm

nm and 20 nm nm physical gate lengths,respectively.

The quantum confinement has been thoroughly investigatedin [78]. In Single-Gate devices carriers are confined in a narrowtriangular potential well, formed at the Si/SiO interface [93].The quantum carrier density in y direction is then modified ascompared to the classical one: the classical electron density ismaximal at the Si/SiO interface, since the quantum densityprofile has a maximum shifted inside the Silicon film at sev-eral nanometers depth (similarly to the bulk Silicon, see Fig. 3).In the case of a Double-Gate configuration, the potential well isrectangular and its size is now equal to the silicon film thickness,

Fig. 9. Electron distribution in a vertical cut-line (parallel to y axis) in themiddle of the channel for Double-Gate devices. After [78]. © 2007 Instituteof Electrical and Electronics Engineers Inc., reproduced with permission.

which becomes a key parameter in the analysis of quantum ef-fects. The electron density profile in quantum case presents twomaxima situated within the Silicon film (Fig. 9). In the Gate-All-Around structure, carrier are confined in a double rectan-gular potential well (along and directions), which enhancesconsiderably the quantum confinement. The carrier motion isno more free in the direction (as is the case of Single-Gateand Double-Gate devices), but their energy in the direction isquantized as that in the direction. Both the gate electrode width

and the film thickness control here the quantum effects.The simulation in [78] have shown that increasing the “Equiv-

alent Gate Number” reduces the short channel effects (and im-proves the subthreshold slope and the off-state current) due tothe better electrostatic control of the gate over the channel. Atthe same time, the on-state current increases with EGN, due tothe multiple-channel conduction. The electron density distribu-tion in a vertical cross-section ( - plane) in the middle of thechannel is illustrated in Fig. 10 at different times before and afterthe ion strike. In the quantum case the maximal value of the elec-tron density is no longer located at the interface (as is the casein the classical approach) but into the Silicon film. For all de-vices the quantum electron charge is centered in the middle ofthe film and the electron density has lower values than in the


Fig. 10. Classical (CL) and quantum (Q) electron density (expressed in cm )in a vertical cross-section (y-z plane) in the middle of the channel of 32 nmDG, Tri-Gate and GAA at different times before and after the ion strike. Thebrown regions represent the gate oxide (in DG and GAA devices) and the gateand buried oxide in Tri-Gate devices. Adapted after [78]. © 2007 Institute ofElectrical and Electronics Engineers Inc., reproduced with permission.

classical case. Then the quantum current is lower than the clas-sical one, because the total inversion charge is reduced in thequantum case [Fig. 11(a)]. The bipolar amplification decreaseswhen increasing EGN [Fig. 11(b)] due to less floating body ef-fects. The quantum gain is found to be generally lower than theclassical one.

The simulations in [78] also shown that the effects of the car-rier quantum confinement become more significant when theSilicon film is thinned. This is due to the energy subband split-ting that is directly proportional with the reverse of the squareof the potential well dimension (equal to the film thickness).The collected charge and the bipolar gain are lower for thinnerchannel. Finally, the quantum bipolar gain for multiple-gate de-vices scaled down to 20 nm gate length and 5 nm 5 nm Sil-icon film cross-section was also predicted in [78]. As shownin Fig. 11(b), the difference between the four architectures isreduced for the 2011 node compared with that for years 2007and 2009, due to the very thin square wire cross-section. Whendecreasing the cross-section, the influence of the gate config-uration is attenuated and the values of the bipolar gain for thedifferent structures are almost the same. This behavior can beexplained by the fact that, around 5 nm and below, the combina-tion of gate electrostatic control and quantum mechanical con-finement leads to similar carrier density distributions in the Sil-icon film for all gate configurations [88]. At this ultimate scaleof integration, it should be expected that the sensitivity of allmultiple-gate nanowire architectures to heavy ionirradiation sensibly become equivalent.

Fig. 11. (a) Drain current transients induced by an ion strike vertically (y direc-tion) in the middle of the Silicon film. (b) Bipolar gain in multiple-gate nanowireMOSFETs as a function of the ITRS LP technology node in the quantum case.The ion LET is 1 MeV/(mg/cm ). After [78]. © 2007 Institute of Electrical andElectronics Engineers Inc., reproduced with permission.

III. CIRCUIT LEVEL MODELING

In this section, we describe the different circuit-level mod-eling approaches of soft errors in integrated circuits. Due to theevolution of microelectronics, driven by the famous Moore’slaw, and to the sensitivity of recent technologies in terms ofsingle-event effects, not only memory ICs but also high perfor-mance logic ICs must be henceforth considered to be potentiallyaffected by SEE. This section surveys the circuit-level modelingapproaches (circuit-level simulation, mixed-mode, 3-D simula-tion of full circuit) of single-event effects in integrated circuits.The SEE mechanisms in advanced SRAM and in logic circuitswill be reminded. Digital Single-Event Transient (DSETs) pro-duction and propagation in sequential and combinational logic,as well as the soft error rate trends with scaling will be par-ticularly addressed. Finally, recent bibliographical examples ofsimulation in SRAMs (bulk and Double-Gate) and logic circuits(flip-flops, inverter chains) are presented and discussed to illus-trate these topics at circuit-level.

A. Circuit Modeling Approaches

1) Circuit Level: Circuit-level SEE simulation can be per-formed using standard simulation codes widespread in theIC industry for circuit design and optimization, such as thepopular Berkeley SPICE, Silvaco SmartSPICE, Synopsys HP-SICE, Orcad PSPICE, Mentor Graphics ELDO simulators, etc.Circuit simulators such as SPICE solve systems of equationsthat describe the behavior of electrical circuits (e.g., Kirchoff’s


Fig. 12. Illustration of the simulation methods that can be used to investigate single-event effects at circuit level (here illustrated for a SRAM cell): (a) SPICE sim-ulation; (b) mixed-mode simulation; (c) numerical simulation with several discontinuous domains connected using a mixed-mode approach; d) full 3-D numericalsimulation with one continuous domain. The snapshot of the full 3-D 6T SRAM cell (d) is courtesy from P. Roche (STMicroelectronics) [59].

laws…). Basic components of these simulation codes are com-pact models that describe the static/dynamic electrical behaviorof the different elementary devices (transistors, diodes, resis-tors, etc.) constituting the circuit. Compact or circuit modelsare generally based on analytical formulae that approximatemeasured terminal characteristics. Advanced compact modelsprovide high accuracy with minimum computational com-plexity. For simulating single-event effects at circuit level, thesingle-event induced transient is usually modeled as a currentsource connected at the struck node of the circuit [Fig. 12(a)].This approach is adequate for many purposes, but presents somelimitations. The accuracy of the transient current used as theinput stimulus may considerably affect the circuit simulationprecision. A typical example is the use of the current transientresulting from the device-level simulation of an unloadeddevice. In [94] the response of a memory cell to single-eventis simulated at the circuit-level with Spice. The stimulus usedat circuit level to reproduce the effect of the ionizing particleis a current pulse obtained by simulating at device level (2-Dsimulation with PISCES) the transient response of an unloadeddevice. In this case the circuit simulation inherits the inaccuracyof the improperly loaded device simulation [11].

2) Mixed-Mode Technique: The limitations of circuit levelsimulation can be overcome by using physically-based devicesimulation to predict the response to ionizing radiation of thestruck device. This approach is referred to as “mixed-mode” or“mixed-level” simulation, since the struck device is describedby simulation in the device domain and the other devices bycompact models. The two simulation domains are tied togetherby the boundary conditions at contacts, and the solution to bothsets of equations is rolled into a single matrix solution [95], [96].Fig. 12(b) shows the construction of an SRAM cell in the frameof mixed-mode simulation. Only the struck transistor is modeledin the 3-D device domain. The current transient resulting fromthe ion strike on the struck device is directly computed by de-vice domain simulation (there is no need for using an input stim-ulus which reproduces this current transient like in circuit-levelsimulation).

Mixed-mode capability is implemented in all major commer-cial device simulators [26]–[28] and is generally used for thestudy of circuits with a reduced number of devices (like SRAMcells). Mixed-mode simulation provides several worthwhileadvantages. The approximation errors introduced by input stim-ulus can be avoided. One can also access the internal devicequantities (such as potential, electric field, carrier densities)within a physically-based device-level simulation at any pointduring the Mixed-mode simulation. In addition, mixed-modetechnique can typically be used to simulate ionizing radiationimpact in new devices (such as ultra-scaled multiple-gateand Silicon nanowire devices) and/or for taking into accountemerging physical phenomena (e.g., quantum confinement orquasi-ballistic transport) for which compact models do not existor are not yet satisfactory. In this case, all transistors containedin an SRAM cell can be simulated in the 3-D device domain.For example, the circuit shown in Fig. 12(c) is used to studythe SEU sensitivity in SRAM cells based on GAA MOSFETwith very thin Silicon film envisaged in the long term ITRSnodes [1].

The main inconvenient of the mixed-level simulationapproach is the increased CPU time compared with a fullcircuit-level (SPICE) approach. In addition, mixed-mode sim-ulation becomes not tractable for complex circuits. But, in thecase of SRAM cells for example, the 3-D mixed-mode simu-lations need significantly reduced computing times comparedwith the numerical simulation of the full cell in the 3-D devicedomain. Finally, it is important to note that 3-D mixed-levelsimulation is accurate for SRAMs only in the case where thereare no coupling effects between the devices [11]. Since thespacing between devices will decrease with pushing the inte-gration level, it is expected that coupling effects will becomemore important, and simulating the cell in the device domainmay become mandatory [97]–[99].

3) Full Numerical Simulation: The most accurate solutionfor studying the SEU in SRAM is to numerically model theentire cell in the 3-D device domain. This was possible onlyrecently (typically in the past decade), due to the improvement


of commercial device simulator numerical methods and theirmeshing engines (integration of new efficient strategies and sig-nificant improvement of already existing iterative linear solvers,integration of thread parallelism which enables the device sim-ulations to be run on multiple processors or parallel machines),and to the enhancement of computer performances (CPU clockspeed, memory resources) which reduced the computationaltime. Pioneering works of Roche et al. [97], [98] and Doddet al. [99] have demonstrated the capability of commercialcodes to build and numerically simulate single-event-effects oncomplete 3-D SRAM cell. An example is shown in Fig. 12(d),with a full 3D 6T SRAM cell [59]. Although the simulationtime needed for simulation of the entire cell in the 3-D de-vice domain was substantially reduced, it is still considerablecompared with the time needed to simulate the same circuitwith Spice and mixed-level approaches. The recent emergenceof PC-based parallel machines (clusters) with hundreds ofprocessors and important memory resource is certainly onevery promising way to develop in the future such full 3-Dsimulations on portions of circuits.

B. SEU Mechanism in Advanced Memories

A particle that strikes a sensitive region of an SRAM celldeposits a dense track of electron-hole pairs. If the collectedcharge at a particular sensitive circuit node exceeds the min-imum charge that is needed to flip the value stored in the cell, asoft error occurs in the SRAM. An error due to a hit of a singleparticle is called a single event upset. Fig. 13 schematicallyshows a typical SRAM cell; when the word line (WL) is lowthe cell is holding its stored data using the back-to-back inverterconfiguration. If the particle strike causes a transient in oneof the nodes, the disturbance can propagate forward throughthe CMOS inverter and induces a transient in the second node.The second node, in its turn, leads the first node towards awrong value and consequently the two nodes will flip. Then,the memory cell will reverse its state and will store a falsevalue [100]; there is no mechanism to restore its state otherthan explicitly rewriting the state via the bitlines. The SEUis a reversible phenomenon (the cell state could be recoveredby a normal writing operation) which does not lead to thedestruction of the cell. SEU can also occur when the particlestrikes the bitline [100], [101]. During the read operation, abitline is discharged by a small current from a memory cell.The bit of information is read as a one a “0” or “1” based on thevoltage differential developed on the bitline during the accessperiod of the memory cell. This voltage differential is disturbedif a particle strikes close to a diode of an access transistor ofany cell on this bitline. The smallest charge that results in a softerror is called the critical charge of the SRAM cell. Therate at which soft errors occur is called Soft Error Rate (SER)and is typically expressed in terms of Failures In Time (FIT)(the number of failures per hours of operation). Numerousapproaches have been proposed for estimating the SER by sim-ulation and dedicated simulation codes have been developed.The description of these SER codes is outside the scope ofthis paper (for a detailed review we invite the reader to consult

Fig. 13. Schematic circuit for an SRAM cell. Adapted after Karnik et al. [100].© 2004 Institute of Electrical and Electronics Engineers Inc., reproduced withpermission.

[102]). We simply remind here an elementary analytical modelfor empirically estimating SER in CMOS SRAM circuits. Thismodel developed by Hazucha and Svensson [103] was used toevaluate the effect of device scaling on the SER of memorycircuits. In this model the SER is estimated by:

(26)

where is a scaling factor, is the neutron or alpha flux inparticles cm , is the area of the circuit sensitive toparticles strikes in cm , is the critical charge in and

is the charge collection efficiency of the device, in . Themain advantage of (26) is that one can immediately identify thekey parameters for SER in SRAM cells. In addition, this modelcan be used for the SER estimation in logic circuits (as it willbe discussed in the paragraph III.C), which makes possible afirst-order comparison of SER in SRAM and sequential/combi-national logic.

Two key parameters for SER are the critical chargeof the SRAM cell and the charge collection efficiency ofthe circuit. and are determined by the process tech-nology [103], whereas also depends on characteristics ofthe circuit, particularly the supply voltage and the effective ca-pacitance of the drain nodes. and are essentially inde-pendent, but both decrease with decreasing feature size. Equa-tion (26) highlights that changes in the ratio willhave a very large impact on the resulting SER. The SER is alsoproportional to the area of the sensitive region of the device,and therefore it decreases proportional to the square of the de-vice size.

Circuit level simulation, mixed-mode approach or 3-D de-vice domain simulation of the full cell have been largely usedin the literature to study single-event effects in SRAM circuitsdesigned in different CMOS technologies (see reviews in [102]and [104]). In the following we will remind some of these sim-ulation studies.

As noted in the precedent paragraph, sensitive area of anSRAM cell is a key parameter for the estimation of the error rate.The sensitive area cannot be predicted using standard single-point (i.e., one ion strike location) 3-D mixed-level simulations,even if these simulations are known to predict upset thresholdsin very good agreement with measured thresholds [105]. Gen-erally, simplified cross-section curves are estimated from the-oretical and simulation results by making assumptions aboutthe sensitive area [106]. Recently, Dodd et al. computed for


Fig. 14. (a) Construction of the SRAM cell simulated in the 3-D device domain.The red box indicates the boundaries of the unit cell. For this SRAM design, theNMOS pull-down transistors and the NMOS access transistors share commondrains, and all source regions (PMOS and NMOS) are shared with the nearestneighboring cells. (b) Evolution of the soft-error sensitive area (black regions)of a 256 K SRAM cell as a function of increasing ion LET. Adapted after Doddet al. [99]. © 2001 Institute of Electrical and Electronics Engineers Inc., repro-duced with permission.

the first time upset cross section of SRAM using 3-D devicesimulator running on a large parallel computer [99]. Fig. 14(a)shows the 3-D simulated SRAM cell which contained about100 000 grid points with maximum grid spacing of 0.2 m [99].3-D simulations were performed for ion strikes incident every0.5 m throughout the SRAM unit cell. These simulations al-lowed the authors to build a map of the SEU-sensitive area ofthe SRAM cell for a given ion and energy. By repeating thesesimulations for several ion/energy combinations, the evolutionof the sensitive area as a function of ion LET was obtained, asillustrated in Fig. 14(b). This figure shows that for a LET valueof 11.5 MeV mg cm (just above the upset threshold), theSEU-sensitive area is the center portion of the NMOS drain,which is expected to be the most sensitive strike location [105].As the LET increases, the NMOS drain sensitive area increasesand becomes even larger than the drain region itself at very highLET values. For a LET value of 33 MeV mg cm the PMOSdrain becomes also sensitive to soft error.

3-D mixed-level simulations were also used by Dodd in [11]to investigate the variation of the SEU threshold LET as a func-tion of technology scaling for bulk and SOI technologies. Theresults are plotted in Fig. 15. The 3-D simulations predict anexponential drop in SEU threshold LET with gate length. For0.18 m bulk Silicon technology, the drain strike LET upsetthreshold is lower than 2 MeV mg cm , then bulk Siliconcircuit would be sensitive to alpha particle. The SOI circuit willprobably become sensitive to alpha particles for gate lengths

Fig. 15. Simulated LET threshold versus gate length trend for 6T SRAM cellsin a bulk Silicon technology and a partially depleted SOI technology with bodyties. The simulated devices are fully scaled (all parameters, gate length, supplyvoltage, doping level, etc., have been scaled). Predictions for the 0.6-�m and0.35-�m technology nodes were validated against experimental data fromSandia fabricated technologies. After Dodd [11]. © 2005 Institute of Electricaland Electronics Engineers Inc., reproduced with permission.

around 0.1 m. This is an important issue because particlesare one of the most abundant products resulting from the inter-action of both proton and neutron with Silicon [11]. Alpha par-ticles are also emitted from radioactive impurities in materialsused in the chip package or from contamination of semicon-ductor processing materials. The prime source of alpha particleis from heavy elements and even the smallest trace contamina-tion can cause serious problems [102]. High-energy alpha parti-cles that strike the device deposit a dense track of charge as theypass through the Silicon substrate. The simulations performedin [11] suggest that future devices in bulk Silicon and SOI tech-nologies will be very sensitive to SEU in both space and terres-trial environments. Finally, Fig. 15 shows that the gate strikeswill become an important source of soft errors in bulk technolo-gies (even if the drain is recognized as the most sensitive regionin bulk devices): the threshold LET for gate strikes drops belowthe alpha-particle LET for the 0.13 m node [11].

C. SEE Mechanisms in Digital Circuits

With the continuous decreasing of the CMOS feature size, itis well established that single event transients (SETs) becomesignificant error mechanism and are of great concern for dig-ital circuit designers. CMOS scaling is accompanied by higheroperating frequencies, lower supply voltages, and lower noisemargins which render the sensitivity of circuits SET increas-ingly higher [11], [107]–[113].

Digital single-event transients (DSETs) constitute a tempo-rary voltage or current transient generated by the collection ofcharge deposited by an energetic particle. Even if this transientdoes not induce an SEU in the struck circuit, it can propagatethrough the subsequent circuits and may be stored as incorrectdata when it reaches a latch or a memory element [11]. Unlike anSRAM cell (where an SEU occurs as a “persistent” error when aSET with sufficient charge impacts a critical node), in a combi-national logic node an SET with sufficient charge may becomemanifested as a “persistent” error only if it propagates throughthe circuit and is latched into a static cell [112]. DSETs must fill


a certain number of conditions in order to induce an error withina memory element [11], [114]:

(1) The ion strike must produce a transient able to propagatein the circuit.

(2) There must be an open logic path by which the DSETcan propagate to reach a latch or a memory element.

(3) The DSET must have sufficient amplitude and durationto change the latch/memory state.

(4) In synchronous logic, the DSET must reach the latchduring a clock pulse enabling the latch. Then the prob-ability of capturing an SET increases with increasingclock frequency.

Digital circuits are constituted from sequential elements (e.g.,latches, flip-flops, register cells) and combinational logic (e.g.,NAND and NOR gates). The effects of single-event-inducedtransients in these two types of circuits are succinctly describedin the following.

1) Sequential Logic Circuits: Typical sequential elements inthe core logic are a latch [Fig. 16(a)], a domino cell [Fig. 16(b)]or a register file cell [Fig. 16(c)]. State changes can occur in corelogic similarly to memory elements. In sequential logic (like inSRAM) the soft error rate has been found to be independent ofthe clock frequency of the circuit [115]. For example, the latchstate can be flipped by the charge deposited by a particle strikeon a circuit node regardless of the state of the clock signal.

Flip-flop circuits (Fig. 17) are other typical sequential logiccircuits. With technology scaling, flip-flops have becomemore susceptible to soft errors, mainly due to the decrease insupply voltage and in their node capacitances. The simplifiedschematics of Fig. 17 shows that flip-flops circuits are similarto SRAM cells, as both apply feedback loops of cross-coupledinverter-pairs. The soft error sensitivity of this class of circuitsis determined by the critical charge and the collectionefficiency . In an SRAM cell is mainly the samefor the two storage nodes because the cell is symmetrical. Inflip-flops, the inverters are sized differently and have differentfan-outs, which makes the flip-flop circuit asymmetric com-pared to the SRAM. Then, the individual storage nodes inflip-flops have a different critical charge than in SRAM andtheir SER sensitivity can vary with several orders of magnitude[117].

2) Combinational Logic: Any node in combinational circuitcan be impacted by an SEU and generate a voltage tran-sient which can propagate through the combinational stages[Fig. 16(d)] and can cause an error if latched by a sequentialelement, such as a memory cell. In combinational logic acertain number of transients will not be latched; but even if theyare latched, some of these data will not be perceived as errorsfor the software operation. A transient error in a logic circuitmight not be captured in a memory circuit because it could bemasked by one of the following three phenomena [101], [118]:

(i) logical masking[118], [119] occurs when a particle strikesa portion of the combinational logic that can not affect theoutput due to a subsequent gate whose result is completelydetermined by its other input values. For example, if thestrike happens on an input to a NAND (NOR) gate [as

Fig. 16. Illustration of typical sequential logic (latch, domino, register) andcombinational circuits (random logic block). Adapted after Karnik et al. [100].© 2004 Institute of Electrical and Electronics Engineers Inc., reproduced withpermission.

Fig. 17. Simplified schematic of the flip-flop circuit. The sensitive nodes arelabeled as MN, M, SN and S. After Roche et al. [116]. © 2005 Institute ofElectrical and Electronics Engineers Inc., reproduced with permission.

illustrated in Fig. 18(a)], but one of the other inputs is inthe controlling state [e.g., 0(1) for a NAND (NOR) gate],the strike will be completely masked and the output willbe unchanged (i.e., the particle strike will not cause a softerror).

(ii) temporal masking (or latching-window masking) occurswhen the pulse resulting from a particle strike reaches alatch but not at the clock transition where the latch cap-tures its input value [118]. This is explained in Fig. 18(b):


Fig. 18. Illustration of the masking phenomena in combinational logic.Adapted after Karnik et al. [100]. © 2004 Institute of Electrical and ElectronicsEngineers Inc., reproduced with permission.

when the transient propagates towards a sequential ele-ment [a latch in Fig. 18(b)], the disturbance on node DINmay be outside the latching window [120]. Hence, theerror will not be latched, and there will be no soft error.

(iii) electrical masking occurs for transients with bandwidthshigher than the cutoff frequency of the CMOS circuit.These transients will be then attenuated [121]. The pulseamplitude may reduce, the rise and fall times increase,and, eventually, the pulse may disappear [as shown inFig. 18(c)]. On the other hand, since most logic gates arenonlinear circuits with substantial voltage gain, low-fre-quency pulses with sufficient initial amplitude will be am-plified [101].

Due to these masking effects the soft error rate in combina-tional logic was found to be significantly lower than expected[101], [118], [120]. Additional to these masking mechanisms,two key-factors impact the soft error rate in combinational logic:the clock frequency and the SET pulse width [108]. With in-creasing clock frequency there are more latching clock edgesto capture a pulse and then the error rate increases. The pulsewidth is a key parameter which determines both the distance theSET will travel through the combinational chain and the prob-ability that the SET be latched in a memory element as wrongdata [109]. The wider the SET pulse width, the greater proba-bility it has of arriving on the latching edge of the clock. If thetransient becomes longer than the time period of the clock, thenevery induced transient will be latched [111]. The SET pulsewidth and amplitude depend on both process and circuit parame-ters (substrate and/or epitaxial layer doping, circuit capacitance,etc.) [112].

3) SER Scaling in Combinational Logic: DSETs mecha-nisms, their production and propagation, as well as their effectson logic circuits have been extensively addressed in previousexperimental and modeling works [108]–[129]. Some of these

works highlighted that DSETs have always been occurring incombinational logic, but their impact was minor in old tech-nologies (due to the three masking effects discussed above).Then combinational logic was in the past much less susceptibleto soft errors than memory elements [118]. Nevertheless, asCMOS technology scales down, soft errors in digital circuitsbecome a great concern, as it was shown in a recent work[118], where it was predicted that by 2011 the soft error rate incombinational logic will be comparable to that of unprotectedmemory elements. Several reasons explain this trend:

(i) The technology scaling allows more transients having suf-ficient pulse width and amplitude to be captured. Com-pared to older technology nodes, the advanced deep sub-micron technologies are capable of capturing a substantialfraction of SETs due to their higher operating frequen-cies. For combinational logic the SER is linearly depen-dent on frequency for transients shorter than the clock pe-riods [111].

(ii) When the circuit speed increases, the ability of transientsto propagate through the circuit increases [11].

(iii) With decreasing feature sizes the charge representing thelogic “high” state decreases, resulting in an increasednumber of SETs [113].

Finally, the recent examination of the digital SET pulse widthand cross-section as a function of technology node indicatesthat the pulse width strongly depends on the nominal oper-ating voltage; the pulse width could potentially increase withdecreasing the feature size due to the concomitant decrease inthe operation voltage [112]. This increase of the pulse widthwill further increase the soft error rate in future scaled digitalcircuits. For advanced technologies, the errors due to DSETsare expected to dominate the overall error rate of the entirecircuit [108]; the primary source of errors in these circuitswould then move from the static logic cells to combinationallogic cells.

D. Illustration at Circuit Level and Predictions WithTechnology Scaling for Digital Circuits

1) Simulation of DSET in Inverter Delay Chains: The pro-duction and propagation of DSETs in scaled Silicon CMOSdigital logic circuits has been recently studied by Dodd et al.using mixed-level simulations [11], [107]. The circuit used forthis purpose is a delay chain containing ten inverters (Fig. 19)and the ion strikes the NMOS transistor of the first inverter.This transistor is modeled in the 3-D device domain, whereasall others devices are modeled at circuit level. The 10-inverterchain is followed by a broadening inverter and a set-reset latch.The later is used to latch the ion-strike induced voltage transientand the former is designed to increase transient widths (and toincrease their probability to be captured by a latch) [107]. Bothbulk and body-tied SOI CMOS technologies are considered inthe simulation. For each technology, the ion has been consideredto strike the most sensitive region: the drain for bulk technolo-gies [125] and the middle of the gate in SOI technologies [107].The simulated irradiation track was considered with a Gaussianshape with a characteristic radius of 0.1 m and a Gaussian time


Fig. 19. Modeling technique for simulating a ten-inverter delay chain. The strikes to the n-channel transistor in the first inverter of the chain are modeled in thedevice domain (with Davinci tool [28]) while the rest of the circuit is modeled within the circuit domain. After Dodd et al. [107]. © 2004 Institute of Electricaland Electronics Engineers Inc., reproduced with permission.

Fig. 20. Single-event transient propagation in 10-inverter delay chains at the0.18 �m bulk CMOS technology node. After Dodd et al. [107]. © 2004 Instituteof Electrical and Electronics Engineers Inc., reproduced with permission.

dependence, centered on 200 fs and with a characteristic decaytime of 100 fs; the ion LET was considered constant along theion path. An example of the simulated output node voltages as afunction of time is presented in Fig. 20 for bulk technology andfor a MeV mg cm . One can observe that the SETeasily propagates without significant attenuation through the en-tire inverter chain and is captured as an SEU by the set-resetflip-flop. The critical LET required for unattenuated (or free)propagation is plotted in Fig. 21 for both bulk and SOI technolo-gies as a function of the technology node. Fig. 21 shows that, asexpected, the critical LET decreases with the transistor featuresize for both SOI and bulk circuits. For 100 nm gate length thecritical LET for bulk CMOS technology drops below the par-ticle maximum LET [2 MeV mg cm ].

Finally, the SOI CMOS has a much better immunity to DSETthan bulk counterparts, since higher LETs are needed in SOI toproduce long transients that can propagate freely [107]. Sim-ulations predict more than a three-generation improvement incritical LET in SOI compared to bulk Silicon circuits. Recently,the curve of the critical LET as a function of the feature size(Fig. 21) has been extended by Ferlet-Cavrois et al. in [129]until 70 nm gate length in partially-depleted SOI MOSFETs. Inthat work, circuit-level simulation of a 10 inverter chain has been

Fig. 21. Critical LET for unattenuated transient propagation as a functionof scaling for bulk and SOI CMOS technologies. After Dodd et al. [107].© 2004 Institute of Electrical and Electronics Engineers Inc., reproduced withpermission.

performed (with Eldo) using measured transients as input stim-ulus. Although partially-depleted SOI MOSFETs exhibit lowcritical LET (similar to the curve concerning bulk Silicon de-vices in Fig. 21) due to the floating body, the results are consis-tent with simulations obtained by Dodd et al. in [107]. Ferlet-Cavrois et al. show that the critical LET continue to decreasewith the technology scaling below 0.1 m gate length.

2) SER Estimation in a Logic Chain: The impact of tech-nology scaling on the soft error rates in CMOS memory, latchesand combinational logic circuits was thoroughly examined byShivakumar et al. in [118]. The SER is calculated using anend-to-end model, which captures the effects of two importantmasking phenomena: electrical masking and latching windowmasking. As noted previously, these phenomena are recognizedas inhibiting soft errors in combinational logic and have to betaken into account in the SER evaluation. The SER is estimatedusing analytical models for each stage the pulse passes from itscreation to the time it reaches the latch, as shown in Fig. 22.In the first stage the charge generated by the particle strike pro-duces a current pulse, which is then converted into a voltagepulse after traveling through a gate in the logic chain. The elec-trical masking model simulates the degradation of the pulse as


Fig. 22. Process for determining the soft error rate in a logic chain. After Shivakumar et al. [118]. © 2002 Institute of Electrical and Electronics Engineers Inc.,reproduced with permission.

it travels through the gates of the logic circuit. A model for thelatching window determines the probability that the pulse is suc-cessfully latched. Finally, the combinational logic SER was es-timated using an extended version of the Hazucha and Svenssonmodel.

The SER was calculated for SRAM cells, latches, and logiccircuits for feature sizes from 600 nm to 50 nm. Fig. 23(a) showsthe critical charge for SRAM cells, latches, and logic circuits,as well as the charge collection efficiency , as a functionof the technology node. The critical charge of logic circuits de-creases more rapidly with feature size than the of memoryelements. By the 130 nm node the critical charge of latches con-verges to about the same values as SRAMs. The steep reductionin for logic circuits is primarily due to quadratic decreasein node capacitance with feature size. Since logic transistors aretypically wider than transistors used in memory circuits (wheredensity is important), this effect is more pronounced in logic cir-cuits [118].

The predicted SER for each class of circuits is plotted inFig. 23(b). The SER of a single SRAM cell declines graduallywith decreasing device size, while the SER of a latch stays rel-atively constant. The ratio for latches is larger thanfor SRAMs at large feature sizes, but of latches decreasesmore rapidly than SRAMs with decreasing feature size. This ex-plains the relatively small change in the SER for a single latchshown in Fig. 23(b). A continuous significant increase in SER(over five orders of magnitude from 600 nm to 50 nm tech-nology nodes) is observed for a single logic chain. This is pri-mary due to the reduction in of logic circuits with de-creased feature size. Since the SER depends exponentially onthe ratio [(26)], when this ratio is large, the factor

dominates the SER expression, but its influ-ence decreases rapidly as the value of approaches .Similar results are found in [130], where the considerably in-crease of the logic-SER with downscaling is also stressed.

Finally, an interesting prediction of the work of Shivakumaret al. [118] is that the SER per chip of logic circuits will increasenine orders of magnitude from 1992 to 2011 and will be compa-rable to the SER per chip of unprotected memory elements [asshown in Fig. 23(b)]. In conclusion, computer system designersmust absolutely address the risks of soft errors in ultra-scaledlogic circuits predicted for the future technology nodes.

Fig. 23. Critical charge (a) and SER (b) for SRAM/latch/logic as a functionof the technology node. The labels “Logic” stand for static NAND gates with afan-out of 4 and various pipeline depths. “Q ” is a simulation parameter cor-responding to the charge collection efficiency in the device. After Shivakumaret al. [118]. © 2002 Institute of Electrical and Electronics Engineers Inc., re-produced with permission.

IV. CONCLUSION

The status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuitswas reviewed in this short-course. We particularly emphasizeon the current challenges concerning the physical modeling of


ultra-scaled devices (in the deca-nanometer range) and new de-vice architectures: Silicon-on-insulator, multiple-gate and Sil-icon nanowire MOSFETs. The growing interest in simulationrelies on its numerous capabilities: insight into device behaviordue to the possibility of “observing” physical quantities thatcannot be measured on real devices, predictive capability whichmay reduce radiation experiments, capability to perform “whatif” studies, which are not feasible experimentally. With reducingthe feature sizes and the emergence of new devices, such asmultiple-gate or Silicon nanowire transistors, device integrationbecomes more and more difficult and manufacturing processesmore and more complex and exponentially expensive. In thiscontext, simulation offers then the unique opportunity to inves-tigate, in advance of process integration, the radiation effectsin these ultimate devices, study which can be difficult, very ex-pensive and less rapid in experiment. Since computers are con-siderably cheaper resources, simulation is becoming an indis-pensable tool for the study of the device sensitivity to ionizingradiation.

In the past decade, substantial progress has been made innumerical methods and computer performances, which makespossible to perform heavy 3-D simulations of SEE in relativelyaffordable time. With the reduction of devices feature size in thedeca-nanometer range, current challenges concern the accuracyof the physical models used in simulation of SEE. Althoughadvanced models taking into account non-stationary effectsand quantum confinement are currently available, emergingquantum transport phenomena, predicted for gate lengthsbelow 30 nm, still have to be considered. The impact of thesephenomena (including ballistic and quasi-ballistic transport andquantum tunneling) on the sensitivity to single-event of digitaldevices and circuits is presently an open question which needsto be addressed in future studies.

ACKNOWLEDGMENT

The authors would like to thank V. Ferlet-Cavrois, fromCEA-DAM, for her continuing encouragements and interest inauthors modeling work. They also acknowledge P. Roche andG. Gasiot, from STMicroelectronics, for fruitful discussion andenriching collaboration during the last years.

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Modeling and Simulation of Single-Event Effects in Digital Devices and ICs