MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3

MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3

WP1: Giuliana Gangemi WP2: André JugeWP3: Wilmar Heuvelman WP4: Davide PandiniWP5: Loris VendrameCoordinator: Jan van Gerwen

Date: March 1st, 2010 (09.00 - 15.00 hrs)Review period: m13 : m22 (2010-12-31)

CONFIDENTIAL 2MODERN 2010 Review March 1st, 2011

Agenda (1)General information (Jan)

– Objectives– Consortium– Relationship between workpackages– Gantt Chart– Resources planned and used– Overview of deliverables and milestones status– Cooperation, dissemination and exploitation– Project management: progress, funding problems and amendments– Other issues, Q&A

For WP1 (Giuliana), WP2 (André), WP3 (Wilmar) and WP4 (Davide)– Relationship between workpackages– Progress, highlights and lowlights– Matrices showing ‘Domain and Technology Overview per Task and Partner’– Link with other WPs and Tasks– Technical status and achievements of deliverables (incl. changes)– Cooperation– Dissemination (publications, patents), exploitation– Other issues, Q&A


Agenda (2)

For WP5 (Loris)– Relationship between workpackages– Progress, highlights and lowlights– Technical status and achievements of deliverables (incl. changes)– Structuring of demonstrators: goals and objectives– Link with other WPs and Tasks– Cooperation– Dissemination (publications, patents), exploitation– Other issues, Q&A


ObjectivesThe objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices.

Specifically, the main goals of the project are: Advanced, yet accurate, models of process variations for

nanometre devices, circuits and complex architectures. Effective methods for evaluating the impact of process variations

on manufacturability, design reliability and circuit performance. oReliability, noise, EMC/EMI.oTiming, power and yield.

Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.

Validation of the modelling and design methods and tools on a variety of silicon demonstrators.

1

2 3 4 5

Layout and strain induced variability (Synopsys)


ConsortiumThe MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe.


Relationship between workpackages


Gantt Chart (1)


Gantt Chart (2)


Resources planned and used

Work

Package

Title

29 1 2 4 3 17 234 3 3 5 3 18 229 1 2 4 3 17 258 5 5 6 6 30 6

325 12 33 46 44 17 26 30 12 22 6 7 12 59388 13 33 48 37 15 25 29 11 29 10 20 12 106325 12 33 46 44 17 26 30 12 22 6 7 12 59639 19 54 84 60 24 42 48 18 48 23 32 12 174421 17 12 24 11 125 46 38 61 11 16 15 5 25 16451 22 12 24 11 125 40 62 66 11 16 15 7 27 12421 17 12 24 11 125 46 38 61 11 16 15 5 25 16686 36 13 24 18 204 66 102 108 18 23 15 12 27 20385 12 24 12 65 31 30 15 22 50 36 45 16 27360 22 22 12 48 31 30 16 22 44 37 35 16 26385 12 24 12 65 31 30 15 22 50 36 45 16 27579 66 36 12 78 36 30 30 36 72 60 58 23 42169 10 30 8 6 33 41 7 0 4 24 6151 9 39 8 3 33 15 6 0 6 23 10169 10 30 8 6 33 41 7 0 4 24 6274 14 63 19 6 54 24 10 18 12 38 1657 1 4 2 0 3 2 2 2 2 19 7 0 2 1 1 3 2 465 2 4 3 0 4 4 2 2 3 18 7 2 4 1 1 3 2 457 1 4 2 0 3 2 2 2 2 19 7 0 2 1 1 3 2 4

110 5 6 5 2 6 6 2 2 6 30 12 3 6 2 4 3 3 61,385 12 24 28 12 51 33 46 68 46 69 56 63 210 80 174 14 40 50 61 11 24 7 33 30 64 27 531,449 22 26 26 12 66 33 48 51 40 67 56 63 208 73 176 18 42 43 66 11 23 20 33 30 114 29 511,385 12 24 28 12 51 33 46 68 46 69 56 63 210 80 174 14 40 50 61 11 24 7 33 30 64 27 532,346 66 43 42 12 109 56 84 84 66 95 56 108 342 120 288 36 90 72 108 18 38 32 50 30 186 30 84

'(*) NOT FUNDED IN ITALY

12. C

EA-L

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13. M

ontp

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ory

15. N

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aly

Srl

WP3

2. A

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3. C

SEM

4. E

last

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PERIOD: m1 to m22

Actual total

TOTAL

Actual totalPlan total

Cum. Act. totalCum. Plan total

31. U

nive

rsita

t Pol

itecn

ica

de C

atal

unya

WP4

Architectural to system level:

modeling, analysis, and

Cum.Plan total

Planned total

WP1

Target technologies,

application domains,

WP2

Process/device to compact modeling

Cum. Act. total

Physical/circuit to RT-level: PV-aware and PV-

robust

Actual totalPlanned total

Planned total

Cum. Act. totalCum.Plan total

28. U

nive

rsity

of C

alab

ria

29. T

he U

nive

rsity

of G

lasg

ow

23. D

elft

Uni

vers

ity

24. E

indh

oven

Uni

vers

ity

25. G

raz

Uni

vers

ity

27. A

lma

Mat

er S

tudi

orum

26. V

ienn

a U

nive

rsity

16. (

Coo

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) NXP

-NL

18. P

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Tor

ino

19. S

TMic

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S.r.

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20. S

ynop

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Switz

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LC

22. T

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AS

21. T

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TABLE 3. PERSON-MONTH STATUS TABLECONTRACT N°: 120003ACRONYM: MODERN

WP5

Test structures and

demonstrators Cum. Act. total

Cum.Plan totalActual total

Planned totalCum. Act. totalCum.Plan total

Planned total10

. Int

egra

ted

Syst

em D

evel

opm

ent S

A

Cum.Plan total11

. Con

sorz

io N

azio

nale

TOTA

LS

WP6

Management, dissemination

and exploitationPlanned total

Cum. Act. total

Partner - Person-month per Workpackage

Cum.Plan total

Actual total

1. S

TMic

roel

ectro

nics

(G

reno

ble2

) SAS

9. S

TMic

roel

ectro

nics

SAS

Actual total

5. T

ekla

tech

Actual total

30. S

apie

nza

Uni

vers

ita d

e R

oma

Cum. Act. total

6. In

fineo

n Te

chno

logi

es

8. IM

EP-L

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Lab

orat

ory


Overview of deliverables and milestones status (1)DeliverablesDel. no. Deliverable name WP no. Task

leadNature Dissemin

ationlevel

Delivery date(proj.

month)

Contributors (lead)

Actual / Forecast

delivery date

Delivered

D1.3 Integration Specifications 1 ST-I R PP M18 ST-I, AMS, IFXA, NMX, NXP, THL

09/12/10 Yes

D2.1.1 First version of process simulator including treatment of PV for mainstream CMOS technologies, and Discrete Power Device,SiC,GaN/AlGaN technologies, interfaced to commercial TCAD tools

2 ST-I R CO M15 ST-I, AMS, TUW

15/06/10 yes

D2.2.3 Device simulation analysis of dominant variability sources in state-of-the-art Non-Volatile-Memory technologies

2 UNGL R CO M18 UNET, UNGL, NMX, SNPS

14/10/10 Yes

D2.3.2 Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices.Report on 1/f noise dispersion behavior in 45nm bulk CMOS

2 NXP R CO M18 ST-I, NXP 23/11/10 Yes

D2.5.1 PV-aware circuit-level models for standard CMOS technologies (down to 45nm), and Non-Volatile-Memory technologies. State-of-the-art based statistical models, based on hardware and/or TCAD.

2 UNET R CO M18 UNGL, UNET, NXP, POLI, ST-I, STF2, NMX

20/10/10 Yes

D5.1.2 Design of test structures for analog design parameter monitoring

5 AMS R CO M18 TUGI, AMS 28/09/10 Yes

D6.1.6 Semi-annual project progress report 6 NXP R CO M18 NXP, all 02/11/10 YesD6.2.3 First report on dissemination activities 6 UNET R CO M18 ST-I, all 10/01/11 YesD6.2.4 First update of public part of the project web-site 6 UNET D PU M18 ST-I 11/10/10 YesD6.3.1 Dissemination and use plan (first version) 6 NXP R CO M18 UNET, NXP,

all11/10/10 Yes


Overview of deliverables and milestones status (2)Milestones

Milestone number

Milestone name Work package(s) involved

Expected date (proj.

month)

Actual / Forecast

delivery date

Achieved Means of verification

M2.1 PV aware compact models available for bulk planar CMOS technologies down to 45nm, TCAD/hardware based

2 M18 20/10/10 Yes D2.1.1, D2.2.2, D2.3.1, D2.5.1

M2.2 Identification and description of major PV sources in non-foundry mainstream logic technologies, cross-technology- fertilization

2 M21 23/11/10 Yes D2.2.3D2.3.1/ D2.3.2D2.5.1

M6.2 Second project review by ENIAC all M14 29/06/10 Yes Reviewer’s feedback


Website

Public section

Restricted section


Cooperation, dissemination and exploitation

A Workshop at DATE 2010 with the theme ‘The Fruits of Variability Research in Europe’ was organized. This workshop was a co-operation of the UK EPSRC project, FP7 STREP project REALITY and MODERNVARI Workshop, 2010 May 26-27, Montpellier, FranceContribution to the Workshop on Simulation and Characterisation of Statistical CMOS Variability and Reliabilitywas presented, Sept. 9th 2010, Bologna, ItalyMODERN participated in the Poster & Demo Session at European Nanoelectronics Forum 2010 in Madrid, SpainLarge number of publicationsMain meetings:

– General meetings in Catania (Nov. 9&10, 2010) attended by 30+ persons present and 10+ called in

Due to the travel restrictions that many companies/institutes still face most of the interaction between partners is by phone and email


Project management: progress, funding problems and amendments

Progress: All planned deliverables readyMost uncertainties in countries causing funding and (national) administrative issues e.g. Italy, Swiss, Spain and Austria, are resolvedAmendments:1. The change of project coordinator from ST to NXP and ST-Crolles being

replaced by ST-Grenoble2. The removal of some inconsistencies between some deliverables3. The subcontracting of work by Glasgow to GSS Ltd.4. CSEM withdraws due to lack of national funding as of 29-06-20105. To account for the leaving of some NXP employees and a related change

in direction of the NXP PDM group the deliverables D5.3.2 and D5.3.3 are (slightly) changed

6. To account for some technical difficulties encountered in the research activities within ST-I Tasks 3.1, 3.4 and 5.3 are (slightly) changed


Other issues Q&A


Example (Davide)WP4 Domain Overview per Task and Partner

T4.1 T4.2 T4.3 T4.4 T4.5Digital IPs/macros UPC, LETI ST I, UNBO

Analog/AMS IPs/macros UPC, LETI ISD

Asynchronous IPs/macros/cells TMPO, LETI TMPO

Regular/configurable IPs/fabrics ST I, UPC

Architectures/Micro-architectures LETI LETI ISD, THL, ST F, NMX ST I, UNBO LIRM

Interconnect schemes and on-chip communication LETI ISD, THL, ST F

CAD algorithms POLI

CAD flows and integration ELX, TMPO, TEKL, POLI ST I

Design methodologies ELX, TMPO ST I, UNBO

Variability LETI, UPC ELX, TMPO, LETI TMPO LIRM (?)

EMC/EMI ELX, TMPO, TEKL, POLI, ST I

Reliability/Fault tolerance ISD, THL, ST F, NMX THL

Manufacturability and yield ST I,UPC, UNBO, TMPO

Reconfigurability ST F, THL, ISD UNBO LIRM, THL

Software and programming methods ST I, UNBO LIRM, THL


Examples (Andre, Davide)Technology Overview per Task and Partner

Technologies

Process simulation

Device simulation

Electrical Charact.

Reliability Compact Modeling

Task 2.1 2.2 2.3 2.4 2.5

HVMOS AMS TUW AMS TUW AMS TUW

Planar CMOS 65nm UNCA

45nm UNGL POLI SNPS (STF2)

IMEP STF2 UNGL UNGL POLI STF2 NXP

32nm UNGL POLI (STF2)

IMEP STF2 UNGL

NVM 41nm UNET NMX SNPS

UNET NMX UNET (N)MX) UNET NMX

FDSOI IMEP (STF2) LETI IMEP LETI

Finfets, MUG, GAA

STF2 NXP IMEP

SiC Power MOS

STI STI STI

AlGaN-GaN HEMT

STI STI STI

Technology T4.1 T4.2 T4.3 T4.4 T4.5

90nm w/- eNVM POLI, ST I, TEKL, ELX

65nm UPC TMPO ST F, ISD UPC, ST I, UNBO, TMPO LIRM (?)

45nm LETI (?)

40nm ELX, TMPO ISD ST I, UPC, TMPO

32nm LETI LETI THL THLNVM NMX


Example (Davide)WP4: Link with other WPs and Tasks

WP3

T3.3

WP4

T4.1

T4.2

T4.3

T4.4

T4.5

WP5

T5.2

T5.3

UPC, LETI UPC, LETI

LETI, TMPO

UPC, TMPO, ST I

THL

THL, LIRM

T3.4ST I

ST I


WP1 agenda

Progress, highlights and lowlights

Matrices showing ‘Domain and Technology Overview per Task and Partner’

Link with other WPs and Tasks

Technical status and achievements of deliverable D1.3

Cooperation

Dissemination (publications, patents), exploitation

Other issues, Q&A


Outline

Introduction


Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3


Cooperation

Other issues, Q&A


Introduction: Progress, highlights and lowlights

1. Clearly define the issues related to nano-electronic technologies that will be tackled in the MODERN project (e.g.,sensitivity of performances, power, yield, deficiencies of existing design techniques, etc).

2. Set the target technologies for which the above listed problems will be faced.

3. Define the specifications of the prototype tools, methods and flows that will come up as solutions of the previously listed problems.

4. Define the requirements of the integration work needed to embed the new tools into the existing design frameworks provided by the EDA partners within the flows in use at ST, NMX, IFX,THL, AMS and NXP.

5. Define up front all activities of all WPs of MODERN exception made of the management.

HIGHLIGHT : Activities recovered past delay D1.3 released OCT 2010

M1.1Problem definition and Tests

M1.2 Integraton specs

M1.4 user guides

PERIOD UNDER REVIEW

CONFIDENTIAL 22


WP2Analog (mixed)

WP3Digital

WP4System

NXP X X

AMS X

ST X X X

IFX X

NMX X X X

THL X X

MODERN 2010 Review March 1st, 2011

CONFIDENTIAL 23



WP2 WP3 WP4

NXP

Matching and 1/f-noise results will be integrated in process blocks and PDK’s. The data we collect, analyze, and model are used by the FT/DKD group in NXP-Nijmegen to construct the appropriate process blocks for circuit simulations. Equally important is the fact that we use the results measured on advanced technologies to assess where, when and how future models and process blocks should be modified, refined or expanded. For this we also use the data from other partners

Substrate noise: implementation through guidelines (documentation) and design reviewsModel Order Reduction: implementation through guidelines, training and supplying a toolbox (plug & play)EM simulation methodology: implementation through guidelines (documentation)

Not involved

AMS

After survey of results T1.2 in WP5 , tools and environment must be optimized for the final implementation in the AMS characterization and modelling flow.

The main outcome of the T2.2 task, aging modelling of HV transistors including PV will be implemented in the AMS simulation environment. At the end of the day the AMS HitKIT will extended with PV lifetime simulators for low voltage and high voltage transistors. As within the Modern project only a few and HV transistors are used as demonstrators for this approach. All other devices in the AMS HV CMOS technologies will be carried out with PV aging models in the next future.

Matching parameters and also additional analog parameters will be directly implemented in the AMS HiTKIT based on the developments performed in MODERN.

Not involved Not involved

CONFIDENTIAL 24



WP2 WP3 WP4

ST

PV aware spice Spice Models will be implemented in the ST-I simulation environment. The models are “plug and play” they do not need any integration work

T3.1 and T3.2 At the end of the project we shall update ST digital design flow, introducing additional degrees of freedom to maximizing

delay sensitivity to FBB keeping the overhead leakage power and area cost as lower as possible while the models created for the Analog IC flow are "plug and play" i.e. do not

require integrationwork

All the methodologies developed in T4.2 as part of this task were designed keeping as a strict constraint the easy interoperability with standard RTL-to-GDSII design tools.

The proposed methodologies were conceived, designed and verified with the specific aim of being "pluggable" in the existing design flow as an additional, stand-alone extra step that could enhance final performance results without altering the flow in itself.

In T4.4o Regarding the metal programmable flow the RTL

generated by the flow must be compliant with synthesis tools utilized in ST (e.g. Synopsys design compiler).

o Regarding the metal programmable flow the RTL generated by the flow must be compliant with synthesis tools utilized in ST (e.g. Synopsys design compiler)

o The “skeleton” layout and schematic containing the not-programmed datapath tiles will be realized utilizing a standard design flow. The customization of the skeleton layout and schematic will be automatically performed utilizing a skill (Cadence) script which generates a VIA4 OPUS layer of the specific accelerator implemented starting from the bitstream output of the Griffy front end flow. The skeleton layout and schematic will be further imported in Cadence OPUS and all libraries and views will be exported.

CONFIDENTIAL 25



WP2 WP3 WP4

IFX Not involved

Aging model parameters for analog reliability simulator Virtuoso® RelXpert have been extracted and will be made available as add-on to standard PDKs in design/verification flow.

Results from basic assessment of aging/reliability issues and aging induced PV in key AMS&RF building blocks will be compiled into a comprehensive documentation & catalogue (“impact matrix”) that gives circuit designers guidelines in terms of expected aging impact and strategies how to avoid, minimize or compensate effects accordingly. This documentation will be part of standard verification plans.

In a similar way the developed monitor & control circuit IP portfolio (to enable aging/reliability insensitive analog, mixed-signal and & RF circuits) will be included in the documentation. In addition prototype designs will be made available to the circuit designers

Not involved

NMX

software tools both internal and commercial have been and/or are going to be improved

with respect to PV in terms of models, efficiency, usability (allowing to avoid

workarounds in handling discrete dopants/traps whitin ‘concentration’ based

tools).This does not require any integration work just upgrade the version of the tool

The simplified and time saving methodology available in the company will be cross-checked against more complete and computationally heavy approaches available in academia to

verify (or, if necessary, improve) the coverage of the industrial flow.

This work is done internally without partners, therefore does not require an integration plan.

CONFIDENTIAL 26



WP2 WP3 WP4

THL Not involved

modify the toolchain, validate the architecture principles with

a SystemC simulator and develop a usecase

modify the toolchain, validate the architecture principles with a SystemC simulator and develop a usecase




Collaborations

WP leader: ST-I

Strong dependence on partners: NMX, NXP,THL,IFX,AMS,ST-I, ST-F

Collaboration with partners: NMX, NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F ,

Telephone conferences with: NMX,NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F according requirements of deliverables ALL SEPT – OCT 2010.

With WP Leaders weekly since the month of December.


WP2 agenda


Matrices showing‘Domain and Technology Overview per Task and Partner’


Technical status and achievements of deliverables (incl. changes): D2.1.1, D2.2.3, D2.3.2 and D2.5.1

Cooperation


Other issues, Q&A

CONFIDENTIAL

WP3 agenda




Cooperation


Other issues, Q&A

30MODERN 2010 Review March 1st, 2011


WP3Progress, highlights and lowlights

All deliverables for 2010 delivered as planned (M12)

Deliverables M24 are on schedule

Highlights:– Very successful meeting with WP3 partners on Nov. 2010 in Catania– VARI 2010 conference organized by LIRMM

Lowlights– Withdrawal of partner CSEM due to Swiss funding issues– Funding of Italian partners delayed

Number Contributors Deliverable D3.1.2 LIRM, NXP, ST-I, TUD, TUE, UNRM Statistical methodology for characterisation of digital and AMS&RF circuits D3.2.2 NMX, NXP, UNBO, UNCA, UNGL, UNRM Standardized PV-aware tools for simulation of digital blocks, AMS&RF blocks, and NVM arrays

D3.3.2 IFXA, LETI, NXP, POLI, UPC PV-tolerant lib cell designs and M&C implementation in digital and AMS&RF D3.4.3 NXP, ST-I Substrate RF coupling, RF co-simulator, Power Distribution Model (PDN) evaluation and analysis flow for

combined IC-package-PCB D3.4.4 ST-I Implementation and evaluation of clock tree synthesis techniques for low EMI

Number Contributors Deliverable D3.1.1 NXP, ST-I1, TUD, TUE, UNRM Set of alternative symbolic models for lib cells D3.2.1 ST-I1, UNBO, UNCA, UNRM Process development kit (PDK), circuit techniques, and speed-up algorithms for PV-

aware circuit simulation D3.3.1 CSEM, IFXA, LETI, POLI, UPC PV-tolerant schematics evaluation and Monitor & Control (M&C) strategies in digital

and AMS&RF D3.4.1 LIRM, ST-I2 Impact of supply noise, and clock distribution on EMI and circuit timing D3.4.2 NXP RF-interaction models for combined PCB-package-IC

CONFIDENTIAL

MatrixApplication overview per task and partner


Tasks Circuit Models Methods Tools&Flows

PV aware Circuits

EMI/EMC

3.1 3.2 3.3 3.4

Application

Digital NXP,STI,TUD,TUE,UNRM,LIRM

UNBO,NXP,STI, UNCA, UNGL,UNRM

POLI,LETI,UPC STI,LIRM

AMS STI,UNRM NMX,STI,UNRM IFX,UPC NXP,STI

RF NXP,STI IFX NXP

NVM NMX

CONFIDENTIAL

WP3 Domain Overview per Task and Partner (tbd)


T3.1 T3.2 T3.3 T3.4

Digital circuit models TUD, LIRM, NXP, UNRM

Statistical methods for digital LIRM, TUE

Analog circuit models STI,UNRM

Timing analysis TUD, TUE, NXP, LIRMM NXP

Algorithms UNRM,STI

Monte Carlo UNCA

Body Bias UNBO, STI

Spice like simulation UNGL, NMX

Design methodologies UNBO,NMX,NXP, STI, UNCA, UNGL,UNRM

Variability TUD,TUE,NXP, UNRM, STI,LIRM IFX

EMC/EMI NXP,STI

Monitor & control for digital POLI,UPC,LETI,ST

Monitor & control for analog IFX,UPC

Regular cells UPC

Substrate Noise NXP

Chip-Package-PCB co-design NXP, ST

Software and programming methods NXP


Physical/CircuitRT-level

WP3 symbolic synergy

PV-aware Circuit models

Methodologies tools & flows

PV-aware Design

Reliability EMI/EMC

T3.1 T3.2 T3.3 T3.4

CONFIDENTIAL

WP3: Link with other WPs and Tasks


WP2

T2.5

T2.3

WP4

T4.1

T4.2

T5.2 T5.3WP5

T5.1

ST I, UNRMNMX

WP3

T3.1

T3.2

T3.3

T3.4 ST I

NMX

IFX

NXP

UPC, LETI


36

Red: Surrogate model outputsBlue: Original outputs

Good performance of surrogate models on the test set

Output START_PH1: Comparison on the test set

• A larger experimentation of surrogate models is in order;

• New input-output data sets for different circuits are expected from ST-I;

• Results of main interest for task T3.2;• Cooperation between UNRM and ST-I essential.

T3.1: surrogate behavioral models

• The optimization procedures considered in T3.2 requires the availability of a circuit

simulator (e.g. SPICE). Each simulation run may require a large computing time;

• GOAL in T3.2: development of surrogate models for the circuit behaviour based on

learning machines (e.g. Neural Networks, Support Vector Machines);

• So as to employ the surrogate model instead of the circuit simulator.

CONFIDENTIAL

T3.2: Analysis of Analogue Sensing Memory Circuit with RandomSpice

Sense Amplifier circuit of NMX analyzed with RandomSpice (UNGL)

SPICE frontend for advanced statistical circuit simulation.

Allows use of UNGL-developed PCA and non-linear power method compact model parameter generation methods.

Statistical enhancement of circuit simulation to access very rare circuit instances.

Database and post-processing backend for power/performance/yield predictions.



T3.3: M&C Strategies for AMS & RFSwitches

– Monitor concepts: ring oscillator, current sensing– Control: “frequency locked loop”, analog control loop

Aging induced offsets– Avoid offset generation: e.g. chopping (comparator)– Correction of static & dynamic effects: e.g. error correction by redundancy – Burn-in: dedicated stress to increase robustness and compensate PV

38

Inv 1 ... Inv 2 ... Inv n

stress pattern control voltage

switch replicas

enable

PhaseFrequencyDetector

ChargePump

LoopFilter

RingoMonitor

FrequencyDivider

ref.

switch on-voltage

ADC search algorithm incl. redundancy

CONFIDENTIAL 39

T3.4: Neptune 5 test chip specs

Aggressor(IO or digital)

Victim(FM LNA)

isolation isolation

propagation

Control equipmentDigital pattern generator Spectrum analyzer

Neptune 5

PCB analog pads

Victim 1

Digital pads

Shiftregister 1

Aggressorsettings

anal

ogpa

ds

Dig

ital p

ads

Victim 2

Victim 3

Victim 4

Victim 5 Victim 6 Victim 7

Shiftregister 3

Shiftregister 2

Shiftregister 4

Victimsettings

Spectrum of the output of FM bufferwith and without digital noise present in the system

Current floor plan proposal

Links to WP5, demonstratortest-chip on substrate noise



WP3Cooperation

tbd


WP3Dissemination

tbd

CONFIDENTIAL

WP4: Outline



Link with other WPs and Tasks, Cooperations


Other issues, Q&A


CONFIDENTIAL

WP4 Task Structure

T4.1: Variability-aware design (LETI, UPC)T4.2: Variation-tolerant, robust, low-noise and low-EMI architectures/micro-architectures (ELX, TMPO, LETI, POLI, ST I, TEKL)T4.3: Design of reliable systems (ISD, THL, NMX, ST F)T4.4: Design of regular architectures and circuits for high manufacturability and yield (ST I, TMPO, UPC, UNBO)T4.5: Distributed reconfigurable PV-robust architectures (THL, LIRM)


CONFIDENTIAL

WP4 M24 Deliverables

44

D4.1.1 LETI, UPC Reports on PV-aware (self-) adaptive compensation and optimization techniques, including on-chip monitors

D4.2.2 TMPO, LETI, TEKL

Reports on PV-tolerant noise and EMI reduction techniques, and on asynchronous and de-synchronized communication scheme benchmarking

D4.2.3 ELX, POLI Advanced asynchronous/de-synchronization flow. Delivery of the first de-synchronized design

D4.3.2 NMX NVM design and robustness assessment report

D4.3.3 ISD, THLFunctional and test specs for a validated controller for ADC and PLL components. Fault-tolerant on-chip global communication scheme on a multi-core SoC virtual platform

D4.4.1 UPC, TMPO Report on yield prediction tool and regular structures for PV-tolerant asynchronous blocks

D4.4.2 ST I, UNBO Report on customizable and regular architectures [….] Delivery of a design flow for mapping on mask-programmable computational blocks […]

D4.5.1 THL, LIRM Report on programming methods and tools for PV-tolerant, reliable, and predictable MPSoC architectures


CONFIDENTIAL

WP4 Domain Overview per Task and Partner

45

T4.1 T4.2 T4.3 T4.4 T4.5Digital IPs/macros UPC, LETI ST I, UNBO

Analog/AMS IPs/macros UPC, LETI ISD

Asynchronous IPs/macros/cells TMPO, LETI TMPO

Regular/configurable IPs/fabrics ST I, UPC

Architectures/Micro-architectures LETI LETI ISD, THL, ST F, NMX ST I, UNBO LIRM

Interconnect schemes and on-chip communication LETI ISD, THL, ST F

CAD flows and integration ELX, TMPO, TEKL, POLI ST I

Variability LETI, UPC ELX, TMPO, LETI TMPO LIRM

EMC/EMI ELX, TMPO, TEKL, POLI, ST I

Reliability/Fault tolerance ISD, THL, ST F, NMX THL

Manufacturability and yield ST I,UPC, UNBO, TMPO

Reconfigurability ST F, THL, ISD UNBO LIRM, THL

Software and programming methods ST I, UNBO LIRM, THL


CONFIDENTIALMODERN 2010 Review March 1st, 2011

WP4 Technology Overview per Task and Partner

46

Technology T4.1 T4.2 T4.3 T4.4 T4.5

90nm + eNVM POLI, ST I, TEKL, ELX

65nm UPC TMPO ST F, ISD UPC, ST I, UNBO, TMPO LIRM

45nm LETI

40nm ELX, TMPO ISD ST I, UPC, TMPO32nm LETI LETI THL THLNVM NMX


CONFIDENTIAL

D4.1.1: PV-aware adaptive compensation techniques (1)

LAVS (Local Adaptive Voltage Scaling Architecture)– Monitor / Adapt V,F using

• Delay-based Diagnostic system • Adaptation controller• Local Power Manager


Clock H

Clock L

SupplySelector

ClockSelector

LPM

Sequencer

Core

AdaptationController

Probe 1

Probe 2

Probe 3

Vhigh Vlow

Vcore Fcore

Flow

Fhigh Ftarget

performancecontrol

perfindex

– Advantages:• Operate on local, realistic silicon

corner (vs wc analysis)• Monitor/adjust to variations along

circuit lifetime• Optimize timing / power

CONFIDENTIAL

Study of Delay-Based Variation Control using Body Bias (BB) and Voltage Scaling (VS)

– Variation is Monitored using on-chip sensors: Leakage / Dynamic Power / Delay– Based on sensor information, BB and VS is applied to reduce variability

– Study of correlation between observables:• Delay distribution shows larger correlation• Use of delay sensors can reduce not only delay variability, but also leakage and dynamic

power variability

Voltage Scaled Elastic clock architecture (with task 4.2) – Elastic clocks allow clock period margin reduction

• Objective of analysis is to quantify this reduction with respect to Voltage noise• Study of correlation between voltage at several chip locations.


D4.1.1: PV-aware adaptive compensation techniques (2)

CONFIDENTIAL

D4.2.2: PV-tolerant noise and EMI reduction techniques (1)

QDI asynchronous NoC based on Muller gates: fully designed in STM 32nm technology

GALS interfaces to communicate with synchronous IPs:– 2 Macros: Target / Initiator– Performance

• Noc Area: 108 µm x 60 µm• Asynchronous Peak :

~1GHz @tt32_1.00V_25C• Interfaces :

800MHz @tt32_1.00V_25C• Latency :

1 router : 0.8 nsinitiator to target : 1.6 ns


CONFIDENTIAL

“Power shaping” methodology and design flow for power robustness and low-EMI

– Uses standard indudstry formats (Verilog, SDF SDC), exports modified Verilog + flow specific clock tree synthesis directives.

– Proposed methodology applied to a 90nm IC reference design provided by ST-I.


Smooth design flow integration28% reduction of IC pad current peaks.25% reduction of Max Dynamic Voltage Drop.55% reduction of IC pad voltage fluctuations.Up to 30 dBµV reduction of digital core conducted EMI harmonicsFlow is now under formal evaluation by ST on 2 different product lines


CONFIDENTIAL

Variability-tolerant low-EMI asynchronous circuits: flow to design PVT-tolerant asynchronous cells

– Consolidated cells and macro-blocks (65 nm full Library [ + 45 nm library + RAM & ROM)

– Realized flow to estimate current consumption profile and estimate EMI– Demonstrated the efficiency of the approach on asynchronous ciphering

IPs like DES and AES, Compared with synchronous design– Further attenuation made available by delay insertion (2.6x in time domain,

10dB in frequency domain


Asynchronous circuit modelSystemVerilog

Synthesis

Simulation current estimation

Delay adaptationSystemVerilogcircuit model

Lib


Synchronous

Asynchronous

4 mA

1.2 mA

Asynchronous 60 dBµ

Synchronous 80 dBµ


D4.2.3: Advanced De-synchronization Flows (1)


Automated block-level de-synchronization of synchronous netlists

– Exploits existing Synthesis / P&R Tools – Synthesis of matched delays

• Delay lines track circuit variability of the circuit at multiple corners and voltages

• Delay synthesized using standard cells• Tracks high-frequency variability (e.g. dynamic

voltage fluctuations)

– Sign-Off flow• Flow requires specific sign-off procedure, based

on synchronous setup/hold constraints.• Implemented in existing STA tools

– Results: AES cipher module (10K gates,17000 µm2, 40nm)• 35% reduction vs nominal case.• 21% reduction vs standard voltage scaling• Robustness: de-synchronized circuit tracks hi-freq

voltage fluctuations (> 200mV) that lead to Synchronous circuit fails

CONFIDENTIAL

Asynchronous High-Level Synthesis (AHLS)– Same SystemC model as synchronous (untimed or with TLM-style

handshaking)• Standardized entry point vs Handshake Solutions• Lower power vs de-synchronization

– No clock: Resources controlled by handshaking• Based on Petri net formulation

– Status• Available: Petri net construction from DFG, State exploration, scheduling• Future Work: advanced pruning optimizations, comparison with other AHLS /

Synchronous, DFG generation from SysC, netlist generation for BE


D4.2.3: Advanced De-synchronization Flows (2)

mul2 mul3mul1

add2

add1


D4.3.2: NVM Reliable Design

54

High level architecture of the decoder

Comparison of different concatenation schemes to:

Minimize parity check bits

Achieve high reliability target (UBER < 10-15)

Have reasonable latency overhead

Current best solution: LDPC+BCH

Preliminary analysis: concatenation of two codes

Inner code: to improve the “channel” reliability Outer code: to “crunch” all the errors


Two independent ECC levels– Ci: Soft Decoded LDPC:

– Fully parallel solution• Needed RAM: 2 x 4 x 212 bits• ~ 10 iterations, 450 “check machines”

(each check involves ~40 bits)– Note: need for processing the whole WL

even if one ECC block is requested– Co: BCH: 32-bit parallel architecture

Soft Code Reliability info based on a predictive model (wp2) tuned

on experimental data

HIF

Buffer

Writ

e Pa

th

Rea

d Pa

th

FIF

Clocks

CONFIDENTIAL

Design methodology for Reliable Multi-cores: – Homogeneous multi-core systems equipped with spare elements

for transparent and deterministic workaround of local permanent faults

– Hardware level • exploit hardware redundancy and fault control

– Computation Resources: processor cores – Storage resources: memory tiles and clusters– Routing resources: physical links, router and network interfaces.

– System and application level (Link with Task 4.5.1)• fault tolerant parallel programming paradigms• possibly assisted by hardware extensions• robust real-time operating system and algorithmic fault tolerance at user-level


D4.3.3: Fault Tolerant Design (1)


Design methodology for Reliable Multi-cores:

– Fault Tolerant Multicore Platform based on dynamic redundancy control

• in-situ characterization (BIST/BISR)

• non-intrusiveness of monitoring process

• uninterruptible system operation

Results:– Pedestrian recognition developed on

the SysC multicore architecture– Characterized impact of task relocation

and simulated faults (Correct results, Low impact on latency, no impact on throughput)




RTL implementation of fault tolerant routing on interconnect schemes– Deployed on Spidergon STNoC technology– adaptive fault tolerant routing through re-programming network interface

routing registers, dramatically reducing the consequences of link and router faults

– As a side benefit, this introduces more freedom in dynamic modifications of network topology, enhancing NoC flexibility

– RTL already been implemented by STMicroelectronics, but will remain undisclosed due to industrial exploitation.

Usage planned on STMicroelectronics and ST-Ericsson platforms



Design and implementation of a dynamic controller for test, detect and repair faulty analog mixed signal (AMS) IP

– Design methodology based on dynamic redundancy control• in-situ operational characterization (BIST/BISR)• non-intrusiveness of monitoring process• uninterruptible system operation


Developed behavioral models of PLL/ADC with process variation in SystemC-AMSPerformed functional validation and sensitivity analysis

– Takes into account Aging and Process VariationProvided preliminary macroscopic monitoring metrics (eventually tp be linked to electrical parameters) to characterize the operational range of AMS componentThis will eventually lead to full operational characterization of the IPs


CONFIDENTIAL

D4.4.1: Regular and Asynchronous design for yield and variability (1)

Regular Structures– Analysis of lithography effects

• Characterization of channel length variation due to lithography• Statistics of channel length variation in benchmark circuits• Impact of channel length variations in performance variability

– Lithography simulations• Based on open-source 45nm kit• Channel length dependence on distance to neighboring poly stripes• Classification of poly distance distribution

– Benchmark circuit analysis• Using Calibre nmDRC scripts to obtain class statistics• From class statistics, channel length distribution statistics obtained

– Impact of channel length variation on variability• Study variability including channel length statistical variation (non regular layout)• Study variability without channel length variation (regular layout)• Result: Quantify the advantage of using regular layout


CONFIDENTIAL

Design of Variability-tolerant Circuits – Study variability-tolerant asynchronous circuits and evaluate their benefits on manufacturability

and yield– Guarantee that the circuits are timing variations tolerant and analyze the impact on parametric

yield


Specification

Schematic edition

Layout editor

Automatic layout

generation

Hspicesimulation

DRCLVS

Parasitic extraction

Characterization Library management

Validation

.sp

.sp

.sp

.oa

.lib

.lib .v

Specification

Implementation

Characterization

Validation

M24 achievements:• Consolidated flow to characterize:

– timing of asynchronous cells and macro-blocks (lib files)

– robustness of standard cells with respect to timing variability

– delay insensitivity of gate netlists

• Validated on 65 nm process:– Post Synthesis done,– Post P&R Ongoing

D4.4.1: Regular and Asynchronous design for yield and variability (2)

CONFIDENTIAL 61

D4.4.2: Customizable regular architectures (1)

gnd

gnd

vdd

Configuration through via connections


Via programmable datapath for fast SoC design– Pipelined array of identical pre-Layouted arithmethic

/ logic operators [200MHz @ 65nm]– Functionality & Routing Customized by VIA4

connection [1 Mask]

Design flow: from C-level DFG description [GriffyC] to programmable array configuration:

– Implementation of the design flow front-end architecture. – Implementation of flow for RTL generation from Griffy-C description– Implementation of back-end flow for via programmable datapath configuration


62

Design flow: from C-level DFG description [GriffyC] to transistor array configuration

– GriffyC to RTL– RTL to P&R– P&R to mask configuration

Mask programmable Transistor Array– Base Regular Cell with 4 Transistors (2xP, 2xN)– Active Area not Continuous, Fixed Layers up to

Contacts– Customization through M1/M2 Connections– Advantages:

• Increased Yield• Mask Cost reduction for Different Customizations


CONFIDENTIAL

Development of architecture & programming model for application mapping on regular multiprocessor architecture

– Hierarchical Multi-Many Core architecture– Thread level parallelism– Distributed, pipelined ASIC Acceleration mapped

on identical mask programmable macros

Development of a hardware/software design methodology for application mapping and accelerator design

– customizable System-C simulator– customizable RTL model – Automated generation of accelerator layout based

on mask programmed technology


63


CONFIDENTIAL

D4.5.1: Methods and tools for PV-tolerant, reliable and predictable MPSoC (1)

Fault tolerant HW/SW integrated model for Many core SoC

– From Coarse-grained DFG description, produce fault-robust C -code suitable for datastream applications having predictable fault reaction on MPSoC

– Run functional (High level) and timed systemC simulation allowing the user to predict performance loss in any given fault scenario


64

CONFIDENTIAL

Runtime task remapping in homogeneous MPSoCs

– Distributed MPSoC architecture, from high-level model to hardware prototype

– Distributed memory MPSoC

System is capable of adapting itself to perturbations

– Self-adaptive task migration• Monitors: CPU load, FIFO usage

– Dynamic Frequency scaling

Fault tolerance mechanism– Based on “watchdog” techniques– Each PE monitors neighbours– Diagnostics, isolation and recovery


65

D4.5.1: Methods and tools for PV-tolerant, reliable and predictable MPSoC (2)

FPGA-based prototype

SystemCModel

CONFIDENTIAL

WP4 Cooperations

In T4.1 collaboration between LETI and ST F on technology transfer

In T4.1 cooperation between LETI and UPC on the temperature monitoring activity, and to coordinate the activities of both institutions in MODERN

In T4.1 cooperation between ELX and UPC on voltage variation measurements across chip

In T4.2 cooperation between ELX, POLI, and ST I on the design flow for desynchronization and on EMI reduction techniques

In T4.2 cooperation between TEKL and ST I on the power shaping methodology for EMI reduction and flow definition and integration of TEKL’s tool into ST design flow

In T4.2 cooperation between LETI and TMPO on QDI asynchronous logic implementation


CONFIDENTIAL

WP4 Cooperations

In T4.3 common research activities and cooperation between ISD and THL, and between THL and ST F

In T4.3 cooperation between ST F and UNBO has started on STNoC technology

In T4.4 cooperation between ST I, UPC and TMPO on the evaluation of the impact of regular design

In T4.4 ST I and UNBO are cooperating on a design flow for mapping applications on mask-programmable computational blocks, regular transistor arrays, and via-/metal-programmable datapaths

In T4.5 cooperation between LIRM and LETI on fine-grain power optimization under variability

In T4.5 cooperation between LIRM and ST F on MPSoC fault tolerance



WP4 Link w/- Other MODERN’s WPs

68

WP3

T3.3

WP4

T4.1

T4.2

T4.3

T4.4

T4.5

WP5

T5.2

T5.3

UPC, LETI UPC, LETI

LETI, TMPO

UPC, TMPO, ST I

THL

THL, LIRM

T3.4ST I

ST I


CONFIDENTIAL

Published Papers

F. Campi, T. Bjerregaard, M. Stensgaard, and D. Pandini, “Power Shaping Methodology for Supply Noise and EMI Reduction,” Design Automation Conf., Jun. 2010.

I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc. VARI, May 2010

C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres, “A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio,” in Proc. Intl. Symp. on VLSI, Jul. 2010.

C. Jalier, D. Lattard, A. A. Jerraya, G. Sassatelli, P. Benoit, and L, Torres, “Heterogeneous vs. Homogeneous MPSoC Approaches for a Mobile LTE Modem,” in Proc. DATE, Mar. 2010.

J. Altet, D. Gómez, C. Dufis, J. L. González, D. Mateo, X. Aragonés, F. Moll, and A. Rubio, “On Evaluating Temperature as Observable for CMOS Technology Variability,” in Proc. VARI 2010, May 2010.

J. Cortadella, L. Lavagno, D. Amiri, J. Casanova, C. Macián, F. Martorell, J. A. Moya, L. Necchi, D. Sokolov, and E. Tuncer, “Narrowing the Margins with Elastic Clocks,” in Proc. Intl. Conf. on Integrated Circuits Design and Technology , Jun. 2010.

C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres, “Flexible and Distributed Real-Time Control on a 4G Telecom MPSoC,” in Proc. ISCAS, Jun. 2010.

I. Mansouri, C. Jalier, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc. Intl. Symp. on VLSI, Jul. 2010.

I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “A Run-time Distributed Cooperative Approach to Optimize Power Consumption in MPSoCs,”, in Proc. Intl. SOC Conf., Sep. 2010.

N. Hebert, P. Benoit, G. Sassatelli, and L. Torres, ‘’D-Scale: A Scalable System-level Dependable Method for MPSoCs,’’ in Proc. Asian Test Symposium, Dec. 2010.

M. Pons, F. Moll, A. Rubio, J. Abella, X. vera, and A. González, “VCTA: A Via-Configurable Transistor Array Regular Fabric”, VLSI-SOC 2010.

N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, “Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” in Proc. VARI, May 2010.

N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, "Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” JOLPE, vol. 6, n. 4, Dec. 2010.

Submitted Papers2011: IEEE DATE (LIRM), IEEE ISCAS (LIRM)



WP4 Summary

Several WP4 meetings to prepare M24 deliverables– F2f meetings ELX/UPC on July 12th and 19th and on October 5th, 2010.– F2f meeting ST Catania Nov. 9th

– Three web meetings (Sep. ‘10, Dec. ‘10, Jan. ‘11)

Demonstrators– System MPSoC platform, with task migration, failure analysis, power

optimization considering variability effects, and HW implementation of several blocks to propose online optimization – LIRM T4.5

All M24 deliverables completed according to milestones– No major criticality detected/reported by task leaders and partners



Future Extensions within WP5 and Beyond

Within WP5, Thales expects to develop on FPGA the smart camera multicore SoC, port the HAL to this implementation and test task migration after fault injection using the pedestrian detection application.

– currently developing the supervisor and a basic processing tile, and– considering improved fault tolerance through redundant on-chip networks

STMicroelectronics plans to commercialize STNoC technology, based on source-based routing.

Expected future collaborations:– ST-F, Thales and University of Bologna will develop a platform where all fault

tolerant STNoC features will be exploited. – ISD and Thales on MPSoC task mapping.– LIRMM and STMicroelectronics on fault tolerance.– LIRMM and CEA/LETI on distributed computing and optimization techniques.


CONFIDENTIAL

WP5 agenda


Technical status and achievements of deliverable D5.1.2 (incl. changes)

Structuring of demonstrators: goals and objectives


Cooperation


Other issues, Q&A



WP5 Progress, highlights and lowlights

Globally WP5 activities are on track

Second year deliverable achieved: D5.1.2 (see dedicated section)

Good progress on detailed demonstrator definition achieved as a results on the activities progress in the “mother” work packages

Different technologies and technologies nodes are involved

During Catania meeting cooperation strenghtened

M24 deliverables on traks (considering ST-I shift from M24 to M36)



Structuring of demonstrators: goals and objectives3 technological area involved

– RF– Power– Logic (Cmos)

5 research area touched:– reliability– monitor and recover (aging)– substrate noise– on chip sensors– adaptation (AVFS)

Major basic concepts tested:– monitoring (T3.3)– redundancy (T3.3)– Adaptation (T4.1)– Regularity (T4.4)– Robust architectures (T4.5)


Structuring of demonstrators: goals and objectives

possible summary matrix


Test chip plan: owner UPCTechnology 65nm:

– LNA with Temperature monitoring– VCO with monitor and control (T3.3)

Technology 40nm CMP:– Design of Voltage Controlled Delay Line (VCDL) and DLL– VCTA application for variation impact of regularity (T4.4)


Test chip plan: owner AMS Task 5.2 - TUG

Design and fabrication of benchmark structures.

Validation of proposed benchmark cases.

Outstanding deliverables:– D5.2.2 – M27– D5.2.3 – M36

VERIFICATION:BENCHMARK CASES vs. MEASUREMENTS

CASE_1 CASE_2 CASE_3 ……….…. CASE_N

SPECIFYBENCHMARKS

PRIMARYSIMULATION,DESIGN AND

LAYOUT

FABRICATION OF

BENCHMARKSTRUCTURES

DO MEASUREMENTS AGREE WITH THE RESULTS FROM

SIMULATION?

FIND OUT WHY

BENCHMARKCASE

OK

NO YES

STRESS

Benchmark Structures

Benchmark Cases

Rel. SimulatorHu derivative

Rel. SimulatorTUV

analytical model

MINIMOS-NTReliability WC models

hierarchically structured

Structure 1 ☺/XStructure 2

Structure 2

Structure 4

etc.


Test chip plan: owner LETI; Architecture Overview

A fine grain Local Dynamic Adaptive voltage and frequency scaling architecture

Diagnostic:– Process-Voltage-Temperature– Timing fault detection or prevention (T3.3)

Actuators:– Based on Vdd-hopping– Local clock generation using FLL

Power/Variability Control– Local control with minimum hardware (T4.1, T4.2)– Global control : high level algorithms

PE

CVPU

ANOC

RunTime

0.9v0.7v PE

CVPU

0.9v0.7v

Main HW objective : a minimum hardware based on standard cellsand simple analog macros for flow insertion and maximum efficiency


Test chip plan: owner LETI; LoCoMoTIV flooplan32nm technology

CDMA

PE0 PE1

PE2 PE3

ANOC

L2RAM

Hopping transition and switches :

Voltage genrationPVT probes

Fully digital FLL : Frequency generation


Test chip plan: owner IFXA

Objective: development and verification of monitor & control (M&C) strategies for AMS&RF circuits to deal with aging/reliability issues and aging induced parameter variations in nanometer CMOS.

Close link to T3.3 (M&C concept development)

Outline– Basic aging/reliability assessment identify sensitivities

• Aging simulations (proof of sim.-concept, model-hardware correlation in T5.2)• Dedicated test-structures for transient effects and aging-parameter-variations

– Development of M&C concepts T3.3– Implementation and verification of M&C concepts

• Silicon based proof of concept • Concept development for accelerated aging/stress tests T5.2• Development of characterization methods (fast transient effects) T5.2

80


Test chip plan: owner IFXA

to be completed


T5.1 Test structures and D5.1.2Partners: AMS, NMX, STF2, TUGTechnologies:

– 45nm CMOS technology developed by STMicroelectronics– Non volatile memory technology from Numonyx– HV-CMOS technology working up to 120V from Austriamicrosystems

T5.1 peculiarities, Goals and Obiectives:– Feed data to other WPs / verify estimation– Define improvement in test structures to increase accuracy– Development of advanced Mismatch test - structures – Development and Evaluation of PV Monitoring structures and Methods

Innovative aspects / returns:– Applications of same concepts to different technologies with smart adaptations– Higher accuracy in PV simulation results in silicon area savings– Applicable for Product design with possible increase in Yield

Links between WPs and tasks:– T2.3: SPICE Monte Carlo models– T2.5: PV-aware compact modeling– T2.1 and T2.2: T5.1 will deliver the benchmark for process and device simulation – The experimental results (NMX restricted) will be used for comparison with simulations

for the validation of NMX methodology will be discussed within WP3, T3.2, D3.2.3 (M36)


83

D5.1.2 achievements Task 5.1 – AMS, TUG

Focus of D5.1.2 is the design and layout of: – analog monitoring and characterization parameter

structures– of monitoring structures utilizing Kelvin-Probe

measurement technique for standard and butted devices

– matching test structures for HV-FETS:• with standard pad-sharing approach• with terminal multiplexing matching test structures


Example I: MOSFET Monitoring Structure utilizing Kelvin-Probe Measurement Technique

Realization for standard devices

Compensation of voltage drops due to wiring

Pad utilization of adjacent unobserved devices for the sense line reduce area consumption

“Sense” devices are active but currentless

DUT

Vin

+

-

Ohmic Losses

Voltage Follower

Force

Sense

SensePoint


Example I: MOSFET Monitoring Structure utilizing Kelvin-Probe Measurement Technique

Realization for devices which are aimed to work at Vbs=0V

S & B commonly connected with metal

Device area reduction due to missing FOX between source and bulk especially for short channel devices

A…gate line 1B…gate line 2C…sense line between drains3…drain pad 16…drain pad 24…source/bulk pad5…source/bulk pad


Example II: 5.2. Design of terminal multiplexing matching test structures for HV-FETs

Basis for matrix structure is given by standard pad sharing structure for HV-FET matching characterization

Consideration of “golden rules”: symmetry, current direction, symmetric connections, usage of guard rings etc.

Final structure for characterization is realized as matrix consisting of equidistant placed devices


Example II: 5.2. Design of terminal multiplexing matching test structures for HV-FETs

Development of multiplexer test-structure for distance dependent matching characterization of HV-FETs

Utilization of Kelvin-technique applied to individual transistor pairs within the matrix

Consideration of voltages up to 50V, which is a typical voltage level for HV-LDMOS FETs

Design of special transmission gates (switches) for gate and drain terminal multiplexing

Facts:– 208 HV-switches for gate bias multiplexing– 24 HV-switches for drain bias multiplexing– Maximum drain current Imax = 20mA


Cooperation and dissemination


Documents

MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3