Modern processor design

Engineering design

The dynamic-static interface (DSI)

Conceptuall illustration of possible placement of DSI in ISA design

Performance simulation metods

Trace-driven simulation

Execution-driven simulation

Scalar pipeline machine

Superpipelined machine of degree m=3

Superpipelined MIPS R4000 8-stage pipeline

Superscalar machine of degree n=3

VLIW machine of degree n=3

Pipeline example

4-stage 11-stage

Two commercial instruction pipelines

Activity of pipeline stages

6-stage instruction pipeline

I-cache and D-cache

Access to RF

RAW, WAR, and WAW data dependencies

WAW, WAR, and RAW hazards

Forwarding paths

Forwarding paths for ALU leading instructions

Forwarding paths for Load leading instructions

Impact on ALU, Load, and Branch penalties with increasing pipeline

depth

Mitigating the Branch penalty impact of deep pipelines

Direct, associative, and set-associative caches

Strategy of cache design

Memory hierarchy

Main memory and I/O

DRAM accesses

Virtual to physical address translation

Processes switching

Paging tables

Direct cache

Associative cache

Set-associative cache

Virtual to physical address translation

Disk

I/O device communication

Stall cycle induced by backward propagation of stalling

Machine parallelism

Parallel pipeline of width s=3

Parallel pipeline - examples

5-stage i4865-stage Pentium parallel pipeline s=2

Parallel pipeline with four execution pipes

The Motorola 88110 superscalar microprocessor

Interpipeline-stage buffers

single-entry buffer

multi-entry buffer

multi-entry buffer with reordering

Dynamic pipeline of width s=3

6-stage superscalar

pipeline

Instruction dispatching in superscalar pipeline

Centralized reservation station

Distributed reservation stations

Dynamic pipeline

with reservation stations

and reorder buffer

Disruption of

sequential control flow by Branch

instructions

Branch target

address generatio

n penalties

Branch condition resolution penalties

Alpha 21064 pipeline stages

HP PA 7100 pipeline stages

IBM POWER (RIOS) pipeline stages

Intel i960CA pipeline stages

Intel Pentium pipeline stages

Cyrix 6x86 pipeline stages

Intel P6 pipeline stages

MIPS R10000 pipeline stages

Motorola MC68060 pipeline stages

IBM/Motorola PowerPC 604 pipeline stages

Sun UltraSPARC-I pipeline stages