Modular design approach for Watt-level millimeter-wave power

Modular design approach for Watt-level millimeter-wavepower amplifiersEssing, J.A.J.

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Modular Design Approach for Watt-Level Millimeter-Wave Power Amplifiers

Jaap Essing


Jaap Essing

This work was supported by NXP Semiconductors. Cover design by Eva Duijf and Jaap Essing. Modular Design Approach for Watt-Level Millimeter-Wave Power Amplifiers / by Jaap Essing Eindhoven University of Technology. A catalogue record is available from the Eindhoven University of Technology Library ISBN: 978-90-386-4150-8 Copyright ©2016, Jaap Essing. All rights reserved. Reproduction in whole or in part is prohibited without the written consent of the copyright owner.


PROEFSCHRIFT

ter verkrijging van de graad van doctor aan de Technische Universiteit Eindhoven, op gezag van de rector magnificus prof.dr.ir. F.P.T. Baaijens, voor een commissie aangewezen door het College voor Promoties, in het

openbaar te verdedigen op donderdag 3 november 2016 om 16:00 uur

door

Jacobus Antonius Jozef Essing

geboren te Vierlingsbeek

Dit proefschrift is goedgekeurd door de promotoren en de samenstelling van de promotiecommissie is als volgt: voorzitter: prof.dr.ir. A.B. Smolders 1e promotor: prof.dr.ir. A.H.M. van Roermund 2e promotor: prof.dr.ir. D.M.W. Leenaerts leden: prof.dr.ing. L.C.N. de Vreede (TUD) prof.dr.ir. B. Nauta (UT) prof.dr. P. Reynaert (KU Leuven) prof.ir. A.M.J. Koonen adviseur(s): dr. J.L. Duarte

Het onderzoek dat in dit proefschrift wordt beschreven is uitgevoerd in overeenstemming met de TU/e Gedragscode Wetenschapsbeoefening.

“The important thing is not to stop questioning. Curiosity has its own reason for existing.”

Albert Einstein (1879-1955)

Contents 1 Introduction ................................................................................................................................................ 1

1.1 Background ........................................................................................................................................... 1

1.2 Problem Statement ............................................................................................................................... 2

1.3 Aim of the Thesis ................................................................................................................................... 3

1.4 Scope of the Thesis................................................................................................................................ 3

1.5 Original Contributions ........................................................................................................................... 4

1.6 Thesis Outline ....................................................................................................................................... 4

2 MMIC PA Design for Ka-band VSAT .............................................................................................................. 6

2.1 Ka-band VSAT PAs ................................................................................................................................. 6

2.2 Silicon vs III-V Compound Technology.................................................................................................... 9

2.2.1 Actives ......................................................................................................................................... 9

2.2.2 BEOL Passives ............................................................................................................................. 11

2.3 SiGe Technology .................................................................................................................................. 12

2.3.1 General Properties ..................................................................................................................... 12

2.3.2 Selection of SiGe Process Generation ......................................................................................... 13

2.4 Design Considerations ......................................................................................................................... 13

2.4.1 Device Efficiency ........................................................................................................................ 13

2.4.2 Impedance Matching.................................................................................................................. 14

2.4.3 Gain vs Efficiency Trade-off ........................................................................................................ 14

2.4.4 Stable Operation ........................................................................................................................ 15

2.4.5 Single-Ended vs Differential Operation ....................................................................................... 15

2.5 State-of-the-Art in Silicon-Based Design .............................................................................................. 15

2.5.1 Device-Level Combining ............................................................................................................. 16

2.5.2 Circuit-Level Combining .............................................................................................................. 16

2.6 Design Issues ....................................................................................................................................... 17

3 Modular Approach .................................................................................................................................... 19

3.1 Modular Concept ................................................................................................................................ 19

3.2 Example Topology and Modules .......................................................................................................... 19

3.3 Even-Mode and Odd-Mode Operation ................................................................................................ 21

3.4 Sources of Odd-Mode Operation ......................................................................................................... 22

3.4.1 Asymmetry and Dynamic Loading at Splitting and Combining Modules ...................................... 22

3.4.2 Imperfect Grounding .................................................................................................................. 24

3.4.3 Biasing Distribution .................................................................................................................... 25

3.4.4 Electromagnetic Coupling ........................................................................................................... 25

3.4.5 Thermal coupling........................................................................................................................ 25

3.5 Combining-Efficiency Degradation Due to Odd-Mode Operation ......................................................... 25

4 Structuring the Design Space ..................................................................................................................... 28

5 Module Options and Limitations ................................................................................................................ 29

5.1 Amplification ....................................................................................................................................... 29

5.2 Power Combining ................................................................................................................................ 31

5.3 Power Splitting .................................................................................................................................... 32

5.4 Biasing ................................................................................................................................................ 32

5.5 Stabilization ........................................................................................................................................ 33

6 Design Approach ....................................................................................................................................... 35

6.1 Design-driven Modeling ...................................................................................................................... 36

6.1.1 General Modeling....................................................................................................................... 36

6.1.2 Including EM and Electrical Coupling Effects in Module Modeling............................................... 36

6.2 Topology Design .................................................................................................................................. 43

6.3 Parameter Design ................................................................................................................................ 44

6.4 Layout Implementation ....................................................................................................................... 61

6.5 Overall PA Simulations ........................................................................................................................ 61

7 Hybrid Multi-Harmonic Load- and Source-Pull System ............................................................................... 63

7.1 Large-Signal Measurement Setups....................................................................................................... 63

7.2 Common Load-Pull Techniques............................................................................................................ 64

7.3 Proposed Hybrid Load- and Source-Pull System .................................................................................. 66

7.3.1 Principle of Operation ................................................................................................................ 66

7.3.2 Performance Assessment of the Proposed Systems .................................................................... 68

7.3.3 Device Measurements with Proposed Systems ........................................................................... 69

8 Systematic Large-Signal Verification Procedure for mm-Wave Transistors ................................................. 72

8.1 SiGe:C HBT Device Structures .............................................................................................................. 72

8.2 Verification Procedure......................................................................................................................... 73

8.2.1 Collecting Measurement Data .................................................................................................... 73

8.2.2 De-Embedding Test Fixture from Measured Data ....................................................................... 74

8.2.3 Modeling of Intrinsic Device ....................................................................................................... 75

8.2.4 Extraction of Simulated Data for Intrinsic Device ........................................................................ 75

8.2.5 Comparing the Measured Data with Simulated Data .................................................................. 75

9 30GHz, 1W Power Amplifier Design Example ............................................................................................. 79

9.1 Architecture ........................................................................................................................................ 79

9.2 Power Block PB2 .................................................................................................................................. 80

9.2.1 Power Module PM2 .................................................................................................................... 80

9.2.2 Combining Module PCN .............................................................................................................. 82

9.3 Power Block PB1 .................................................................................................................................. 83

9.4 Power Block PB0 .................................................................................................................................. 83

9.5 PA-Module Performance ..................................................................................................................... 84

9.6 PA-Module Stability ............................................................................................................................. 84

9.7 Measurement Results ......................................................................................................................... 85

9.7.1 Small-signal Measurements ........................................................................................................ 85

9.7.2 Large-signal Measurements........................................................................................................ 86

10 Conclusions and Recommendations ........................................................................................................ 89

10.1 Conclusions ..................................................................................................................................... 89

10.2 Recommendations for Future Work ................................................................................................. 91

Appendix A. Multi-port Impedance Definition ................................................................................................ 92

Appendix B. PAE Calculation .......................................................................................................................... 93

References ........................................................................................................................................................ 94

List of Publications and Patents ......................................................................................................................... 99

Summary......................................................................................................................................................... 100

Acknowledgements ......................................................................................................................................... 102

Biography ........................................................................................................................................................ 104

1

1 Introduction

1.1 Background Monolithic Microwave Integrated Circuits (MMIC) are key components in modern military and commercial

wireless communication systems for operation in the microwave and millimeter-wave frequency regime as they enable low-cost, high-density and multifunctional integration [1], [2].

MMIC power amplifiers (PA) used in millimeter-wave long distance applications need to be capable of amplifying signals to Watt-level output powers (>1W). In the Ka-band (26.5-40GHz) these applications include Very-Small-Aperture-Terminals (VSAT) [3], [4], Local Multipoint Distribution Services (LMDS) [5] and radar [6]-[8] .

Using a process technology having devices with a limited breakdown voltage, multiple distributed active devices are required to improve the PA output power towards the required level. The layout interconnect between the multiple devices shows distributed effects at these mm-wave frequencies and thermal coupling between the devices can result in a thermal hotspot. Next to the limited breakdown voltage of the devices, they have a low gain and the passive components have a low Q-factor. Hence, such a distributed design introduces severe problems in power combining, gain improvement, stability, and power-added efficiency (PAE). At the same time, a distributed design offers many choices for accomplishing power combination, gain improvement and insertion of bias and stabilization functions.

To find a power efficient design, all these choices need to be explored, which is a cumbersome and time-consuming task as many design iterations are needed. Therefore, only a limited design space is normally investigated, which might lead to sub-optimum results. To cope with this, a modular design approach is presented in this thesis to explore the available options in a structured way. This approach reduces the number of design iterations such that the optimum PA performance is found in limited time, hereby focusing on output power, efficiency and gain.

Although state-of-the-art PAs for these applications are commonly implemented in III-V compound technologies [9]-[12], silicon devices are becoming more attractive in recent years [13]-[17], due to their low cost and increased performance achieved by technology improvements. However, due to the fundamental differences between silicon and III-V compound technologies, the realization of Watt-level output powers in silicon technologies is more challenging, leading to a more urgent demand for the proposed modular approach for these technologies.

2

1.2 Problem Statement The problems encountered at power combining and gain improvement at mm-wave frequencies are first

summed up in a concise form and subsequently discussed in more detail. The problems are related, but not limited, to:

impact of layout interconnect; low-valued load impedance; thermal hotspot; complexity of multi-level power combining; low performance of actives and passives; stable operation; PAE degradation; impact biasing and stabilization on RF performance; overall design complexity; uncertainty in large-signal modeling.

The impact of the layout interconnect becomes apparent when parallelization is applied at device- and

circuit-level to perform power combining. Due to the spatial distribution of the devices the layout interconnect between the devices shows distributed effects at mm-wave frequencies. At the device parallelization these distributed effects prevent the linear scaling of output power with the number of devices and this leads to a reduction in efficiency and gain.

When device parallelization is applied and large output powers are needed, a low load impedance is required due to the limited breakdown voltage. This leads to a high transformation ratio matching network which has in general lower efficiency.

When the devices are spatially put close to each other for interconnect impact reduction purposes, the mutual thermal coupling between the devices increases, which can lead to a thermal hotspot. Power combining of multiple smaller PA cells is therefore often used to cope with the mentioned interconnect, matching and thermal issues. This results in a multi-level power combined PA architecture, increasing the design complexity.

Next to the watt-level output power, a gain level around 20dB is typically required. The problem is that the maximum power gain (Gmax) of the active devices at these frequencies is typically lower than the required gain level. This is imposed by the fundamental trade-off between speed (gain) and breakdown voltage within a process technology. Moreover, compensation for the passive losses is required. Due to these factors, gain improvement needs to be used, which can be accomplished by applying cascoding and/or cascading of active blocks. Next to this, the low Q-factors of the passive components result in larger passive losses, reducing gain and efficiency.

All the active devices need to operate within the stable-operating-area (SOA) to prevent electro-thermal breakdown. Moreover, oscillations within such a distributed PA, with many interconnected devices and loops, might easily occur. Therefore additional stabilization measures might be required to ensure stable operation from DC up to fmax, i.e. to prevent both electro-thermal breakdown and any unwanted oscillation. Part of the required stabilization networks will be located in the DC-path and hence the designs of the biasing and stabilization networks impact each other and can have conflicting requirements.

The power added efficiency (PAE) degradation due to the power and gain improvements need to be minimized, meanwhile having proper biasing and ensuring stable operation. Also, the impact towards PA performance degradation at insertion of the biasing and stabilization networks needs attention.

The design complexity is large due to the many choices existing and due to interaction between the problems. In order to increase the confidence in the performance of (multi) devices and to enable first-time-right mm-wave

power amplifier (PA) designs, large signal model verification is required.

3

1.3 Aim of the Thesis The aim of this thesis is to develop a modular design approach, and verify its effectiveness and correctness, for

mm-wave Watt-level PA design. It should explore the available options for accomplishing power combination, gain improvement and insertion of bias and stabilization functions in a structured way, such that the optimum PA performance is found in limited time, hereby focusing on output power, efficiency and gain. This approach incorporates the relevant layout effects as they impact performance significantly at these frequencies.

As regard integration technology, we want to investigate the feasibility of silicon technologies, and more specifically, SiGe:C BiCMOS technology, for Watt-level PA design. The realization of Watt-level output powers in these technologies is more challenging, leading to a more urgent demand for the proposed modular approach compared to III-V compound technologies.

Next to this, to gain confidence in the performance of a (multi) device, large-signal model verification needs to be applied. A new technique for source- and load-pull measurements is investigated, which can be used for the device characterization, the latter required for the verification.

1.4 Scope of the Thesis The scope of this thesis is defined as follows:

The focus is on VSAT applications at the Ka-band. The enormous growth market for consumer VSAT in regions with unserved/underserved terrestrial broadband internet access makes this an attractive application. However, the approach presented in this thesis is also applicable to similar mm-wave applications where Watt-level output powers are required.

Due to the focus on VSAT applications, the main performance parameters of interest are: output power, power added efficiency and gain. Linearity is not of interest as the used modulation schemes are typically constant envelope (GMSK, QPSK). The bandwidth is not of a major concern as the required bandwidth ranges from 29.5 to 30GHz, which corresponds with a relative bandwidth of only 1.7%.

The focus is on on-chip PA design. The (impact of) packaging of the PA and mounting the chip on a PCB are left out of consideration.

BiCMOS technology using SiGe:C HBT devices is used as a demonstrator in this work. In comparison with CMOS, this SiGe:C BiCMOS technology offers a higher breakdown voltage, which is beneficial for power generation. Although SiGe:C BiCMOS is used, the approach presented in this thesis is also applicable to other, both silicon (CMOS) and III-V compound, technologies.

The focus is on on-chip power combining techniques as the goal is to achieve Watt-level output power on-chip. Hence, combining in the spatial domain via a phased array is left out of consideration.

Only architectures are investigated that combine the signals of multiple equally operating active sources, having the same complex-valued signals. Hence, efficiency enhancement architectures like the Doherty or outphasing amplifier [18] that have out-of-phase signals are left out of consideration.

The focus is on the reduced conduction angle classes (class A-B) due to their ease of design and implementation. The switched amplifier classes, like class-F and class-E, are left out of consideration.

The loading of the PA is assumed to be The impact of self-heating of the devices is considered. However, mutual coupling between devices is left

out of consideration.

4

1.5 Original Contributions The original contributions of this thesis are:

A modular design approach for mm-wave Watt-level PA design to explore the available options for accomplishing power combination, gain improvement and insertion of bias and stabilization functions in a structured way. This includes:

o a basic concept for the modular approach and the definition of generic architectures and proper modules (Ch. 3);

o indicating the sources of undesired odd-mode operation and analyzing the combining efficiency degradation due to this odd-mode operation (Ch. 3);

o classification of splitting/combining modules regarding their asymmetry/dynamic loading performance (Ch. 3);

o structuring of the design space (Ch. 4); o analysis of modules options and their limitations (Ch. 5); o design-driven modeling including EM-coupling effects to shorten the design cycle (Ch. 6);

Proposal for a novel hybrid source- and load-pull system (Ch. 7). Large-signal device-model verification of SiGe:C HBT devices at 900MHz and 30GHz using a Non-Linear

Vector Network Analyzer (NVNA) (Ch. 8). Design and implementation of a 27GHz 31 .

1.6 Thesis Outline The outline of the thesis is shown in Fig. 1.1 and is briefly discussed below:

Chapter 2 discusses the state-of-the-art in PA design, targeting output powers relevant for Ka-band VSAT

applications. A comparison between the properties of silicon and III-V compound technologies is performed, focusing on SiGe vs GaAs technology. Several power combining techniques are discussed together with the related design issues for mm-wave Watt-levels PAs.

Chapter 3 presents the basic concept for the modular approach to cope with the discussed design issues. The approach is explained using an example PA topology. The desired mode of operation when combining multiple devices, the even-mode, is discussed together with its counterpart that results in an undesired mode of operation, the odd-mode. The sources of the undesired odd-mode operation are discussed and the combining efficiency degradation due to the odd-mode operation is investigated.

Chapter 4 addresses the structuring of the design space. A ‘function matrix’ is presented, showing a distribution of the required functions for power and gain improvement and for biasing and stabilization over the selected hierarchical levels, together with the available design parameters shown at each level.

Chapter 5 discusses the available module options and the modules’ limitations. The pros and cons of the different options will be discussed with their relation to the limitations imposed by the process technology constraints.

Chapter 6 presents the design approach. A design-driven modeling is presented here, which reduces the design cycle meanwhile including the relevant EM-coupling effects. The PA topology design is discussed in detail and subsequently the parameter design, the procedure for assigning values to the design parameters, is discussed.

Chapter 7 presents a novel hybrid multi-harmonic load- and source-pull system to overcome the limited reflection coefficients offered by passive systems. Source- and load-pulling is used at large-signal device characterization, the latter required for the large-signal model verification.

Chapter 8 provides systematic large-signal model verification for single and multi-device structures in order to gain confidence in the devices’ performance and to enable first-time-right mm-wave power amplifier (PA) designs.

Chapter 9 discusses a 30GHz, 1W power amplifier design example be implemented in a 0.25um SiGe:C BiCMOS technology making use of the proposed modular approach, and verifies the approach’s correctness and effectivity.

Chapter 10 provides the conclusions and recommendations.

5

Ch. 1 Introduction

Ch. 2 MMIC PA Design for Ka-band VSAT

Ch. 3 Modular Approach

Ch. 4 Structuring the Design Space

Ch. 5 Module Options and Limitations

Ch. 6 Design Approach

Ch. 7 Hybrid Multi-Harmonic Load- and Source-Pull System

Ch. 8 Systematic Large-Signal Verification Procedure for

mm-Wave Transistors

Ch. 9 30GHz, 1W Power Amplifier Design Example

Ch. 10 Conclusions and Recommendations

Fig. 1.1 Outline of the thesis.

6

2 MMIC PA Design for Ka-band VSAT This chapter discusses the state of the art in PA design, targeting Ka-band VSAT applications. The application and

the related requirements for the PA within a VSAT ground station are discussed in section 2.1. This section is completed with an overview of state-of-the-art Ka-band PAs suitable for VSAT operation. From this survey the dominant technologies (III-V compound technologies) are indicated. As a replacement, the use of a low-cost SiGe:C BiCMOS technology is investigated. The (fundamental) differences between silicon and III-V compound technologies are discussed in section 2.2, with a focus on the comparison of SiGe vs GaAs technology. Section 2.3 discusses the properties of SiGe HBT technology which are important for design. Also the selection of the specific SiGe process is discussed. Several general PA design considerations important for VSAT PAs are discussed in section 2.4 such as the device efficiency, impedance matching, the gain vs efficiency trade-off, stable operation and single-ended vs differential operation. A literature survey of published silicon PAs in the (near) mm-wave frequency regime with saturated powers towards Watt-level is presented in section 2.5 with their used power combining techniques discussed. The related design issues for these PAs are discussed in section 2.6.

2.1 Ka-band VSAT PAs Very-Small-Aperture-Terminals (VSAT) are ground stations used for one-way or two-way data transmission by

means of a satellite communication system. Fig. 2.1 depicts a typical VSAT network. VSAT networks are ideal for centralized networks with a central host and a number of geographically dispersed terminals. VSATs offer various advantages, like wide geographical area coverage, high reliability, low cost and independence from terrestrial communication infrastructure [19]. Services that are offered are broadband internet access, video broadcasting (DVB), enterprise communication and cellular backhaul. Especially, consumer VSAT is an attractive application due to the enormous growth market for in regions with unserved/underserved terrestrial broadband internet access.

Traditionally, VSAT networks are operating in the C-band (downlink 3.7-4.2 GHz, uplink 5.9-6.4 GHz) and Ku-band (downlink 10.95-12.75GHz, uplink 14.0-14.5 GHz). As spectrum licenses in these frequency bands became scarce, the demand for available spectrum and higher capacity has led to entering the Ka-band (downlink 17.7-20.2GHz, uplink 29.5-30GHz) [20], [21].

Fig. 2.1 A typical VSAT network, depicting a gateway connected to the internet and showing different types of remote terminals/clients, depending on the type of service (enterprise communication, consumer broadband or cellular backhaul) [22].

7

The required output power level at the Ka-band for the PA within a VSAT ground station can be typically divided in three classes, depending on the application: 1W (30dBm), 2W (33dBm) and 4W (36dBm). A literature survey of published state-of-the-art 30GHz Ka-band PAs in these three classes resulted in the overview depicted in Table 2.1. This table gives a good overview of the market, as all these references are published by the industry or are commercial-off-the-shelf (COTS) products. As can be seen, the PAs are all implemented in III-V compound technology with GaAs PHEMT technology dominating the market in all three output power classes, having a PAE on average higher than 20% with a gain of more than 20dB. However, this technology is costly for high volumes, mainly due to their smaller wafer size and lower yield compared to a silicon technology, leading to a higher cost per mm2 [32], [33]. Therefore, SiGe transistors are becoming more favorable due to their relatively low cost and high integration capability. However, the intrinsic performance of this technology is in general worse than GaAs technology. The next section investigates the differences in technology performance.

8

Table 2.1 30GHz Ka-Band 1, 2 and 4-Watt power amplifiers. For COTS products, the part name is also shown between parentheses in the ‘technology’ column.

Po (dBm)

Ref. freq

(GHz) Technology (Part name)

Vdd

(V) P

DC @

Po_1dB

(W) P

o_1B/P

sat (dBm) PAE

peak

(%) Linear gain

(dB)/ # stages

Chip area

(mm2)

Psat_dens

(mW/mm

2)

Pack- age

30

[23] 28-31 UMS 0.25um

GaAs PHEMT

5.5 - 29.5 / 30.1 - 17 / 4 2.55 400 -

[9] 28-30 WIN 0.15um

GaInAs/AlGaAs PHEMT

6 - - / 30.2 - 27 / 3 3.86 271 -

[24] 26-30 TRW 0.2um

AlGaAs/InGaAs/GaAs PHEMT

5 3.19 29 / 30 24.9 16 / 2 3.23 310 -

[30] 28-30 Triquint

GaAs PHEMT (TGA4539-SM)

6 5.4 30.5/30 18.5 20 / 3 - - QFN 5x5

33

[25] 27-32 Triquint 0.25um GaAs PHEMT 6.5 7.53 32.8 / 33.5 25 20 / 3 6.17 363 -

[9] 28-31 WIN 0.15um

GaInAs/AlGaAs PHEMT

6 5.99 33 / 33.5 33 21 / 3 7.39 303 -

[26] 27-30 TRW 0.15um InGaAs/AIGaAs/

GaAs PHEMT - 4.20 32 / 33.9 37 18 / 2 - - -

[30] 30-40 Triquint

GaAs PHEMT (TGA4516)

6 11.4 33/32.5 17.5 18 / 3 6.46 - QFN 5x5

[31] 27.5 - 31.5

MACOM GaAs PHEMT

(MAAP-011246) 6 <8.7 33/30 25 23 / 4 - -

QFN 5x5

36

[27] 27-31 Triquint 0.25um GaAs PHEMT - 13.2 35.2 / 35.8 25 24 / 3 12.88 295 yes

[9] 27-31 0.15um

GaInAs/AlGaAs PHEMT

6 10.1 35 / 36 31 21 / 3 14 284 -

[28] 28-31 Raytheon 0.2um AlGaAs/InGaAs

PHEMT 6 12.6 35.5 / 36.3 28 22 / 3 12.4 344 -

[29] 26-36 0.18um

AlGaN/GaN HEMT

24 - - / 36 23 12 / 2 - - -

[30] 28-21 Triquint

GaAs PHEMT (TGA4906-SM)

6 15.6 36 25.5 22 / 3 - - QFN 5x5

[31] 28.5 -

31

MACOM GaAs PHEMT

(MAAP-011139) 6 <16.2 36 / 34.5 23 22 / 4 - -

QFN 5x5

9

2.2 Silicon vs III-V Compound Technology This section discusses the differences between silicon vs III-V compound technologies with a focus on SiGe vs GaAs technology. In section 2.2.1 the performance comparison of the actives is discussed and in section 2.2.2 this is done for the passives components formed in the back-end-of-line (BEOL).

2.2.1 Actives To examine the fundamental differences between silicon (Si) and III-V compound (GaAs, InP, GaN) technologies,

some relevant material properties are summed up in Table 2.2 as the bandgap voltage, the electron mobility, the saturated electron velocity, the breakdown field and the thermal conductivity. The bandgap voltage and breakdown field are related to device voltage breakdown, whereas the electron mobility and the saturated electron velocity are related to the device speed.

For a comparison of the device breakdown and speed for different technologies, the Johnson figure-of-merit (JFOM) is also depicted in Table 2.2, which describes the fundamental relationship between frequency (speed) and power (breakdown voltage) [36], solely using the semiconductor’s material properties. Although this figure-of-merit (FOM) is derived using a highly idealized and simplified model, it allows a relative comparison between the materials. Under the used assumptions, the JFOM is described by: JFOM = E 2 = (2.1)

with Ebr the critical breakdown field, vsat the saturated electron velocity, Vmax the maximum allowable voltage and and ft the transistion frequency, which is the frequency at which the (small-signal) current gain becomes equal to one. For a giving technology, the JFOM is a constant value due to the given values for Ebr and vsat and hence this limit depicts the fundamental trade-off between frequency (ft) and power (Vmax) for a given technology. However, as the real world is more complex than assumed by the used idealized model, this limit should not be seen as a physical limit [37]. Comparing the normalized JFOMs for Si (e.g. SiGe) and GaAs, for the same speed (ft), an AlGaAs/InGaAs device could have a 2.8 times larger breakdown voltage. The potential of GaN technology for high power applications becomes also clear [38].

Table 2.2 Overview of material parameters for silicon and III-V compound semiconductors [34]. The values between parentheses refer to the corresponding heterostructures.

Property Si GaAs (AlGaAs/InGaAs)

InP (InAlAs/InGAs)

GaN (AlGaN/GaN)

Bandgap Eg (eV) 1.1 1.42 1.35 3.39

Electron mobility n (cm2/Vs) 1500 8500

(10000) 5400

(10000) 900

(>2000) Saturated (peak) electron velocity vsat (x 107 cm/s)

1.0 1.0 (2.1)

1.0 (2.3)

1.5 (2.7)

Breakdown field Ebr (x105 V/cm) 3 4 5 33

Thermal conductivity (W/cm-K) 1.5 0.5 0.7 1.3

Johnson FOM (normalized to Si) 1 1.33

(2.8) 1.67

(3.83) 16.5

(29.7) The trade-off between ft and breakdown voltage (BV) is plotted in Fig. 2.2 (left) for several generations of the NXP QUBiC4 BiCMOS process [40], [41] comprising Si BT or SiGe:C HBT devices, and for several generations of a GaAs PHEMT process [42], [43], one of them [44] is used at reference [9] in Table 2.1. For the QUBiC4 devices, the

10

breakdown voltage corresponds with the BVCEO and for the GaAs PHEMT devices this corresponds with the BVDS for DC1. The average ft*BV products for both technologies are also plotted (solid lines), resulting in a 466GHzV and a 205GHzV ft*BV product for the GaAs PHEMT and the QUBiC4 BiCMOS technology, respectively. This indicates the advantage of GaAs technology over SiGe for power applications considering the speed vs breakdown trade-off. Also in Fig. 2.2 (right), the maximum frequency of oscillation fmax is plotted versus the breakdown voltage. This figure-of-merit (fmax) is a better indication for the PA gain that can be expected as it depicts the frequency at which the maximum available power gain (MAG) becomes equal to one, instead of the current gain. In contrast to the ft vs BV plot, this plot depicts no monotonically decreasing relationship as function of BV. This comes from the fact that fmax depends also strongly on the device’s extrinsic (parasitic) parameters as the series resistances, whereas the ft is related to the intrinsic device parameters. This can be seen by the following approximation of fmax for a bipolar device: f 8 (2.2)

with Rb and Cbc the equivalent base series resistance and base-collector capacitance, respectively. This shows the strong dependency of fmax on the base series resistance Rb [45]. A similar expression as (2.2) exists for a FET device by replacing Rb for Rg (the gate resistance) and Cbc for Cgd (the gate-drain capacitance).

Fig. 2.2 ft vs breakdown voltage (BV) plotted (left) for several generations of the NXP QUBiC4 BiCMOS process [40], comprising Si BT or SiGe:C HBT devices, and for several generations of a GaAs process, comprising PHEMT devices [42]. For the NXP QUBiC4 devices, the breakdown voltage (BV) corresponds with the BVCEO and for the GaAs PHEMT device this corresponds with the BVDS. The average ft*BV product for the GaAs PHEMT technology is 466GHzV and for the QUBiC4 BiCMOS technology this is 205GHzV. The fmax vs breakdown voltage is plotted in the right figure. Although the breakdown voltage of GaAs technology is larger, its power handling capability is lower compared to a SiGe technology due to the GaAs substrate’s lower thermal conductivity compared to silicon (see Table 2.2), resulting in a lower power density [33], [46]. Hence, a larger area (more devices) is required to deliver the same power.

1 BVCEO is a worst-case value. The maximum voltage (DC+RF) for a HBT device is normally higher, as will be discussed in section 2.3. For the PHEMT devices the DC-breakdown values are shown. The maximum voltage (DC+RF) is about a factor 2 higher compared to these values [38].

11

2.2.2 BEOL Passives High-performance passive components needed for matching, interconnect and for power splitting and combining

are commonly implemented in the technology’s back end of line (BEOL). The BEOL comprises the metallization layers and dielectrics and within this back-end the inductors, MIM capacitors and transmission lines/interconnect are formed. An overview of the properties for the BEOL for a typical GaAs process and the QUBiC4 gen. 8 process are depicted in Table 2.3 together with other technology properties important for the passives’ performance. At the back of the GaAs substrate a layer of gold is deposited (the back-side plating), where the through-substrate-vias (TSV) connect to and which acts as a good ground plane. Although a SiGe BiCMOS process could have TSVs, as in the IBM BiCMOS process [47], such option is not available at the QUBiC4 process (it is expensive). At the QUBiC4 gen. 8 process deep-trench-isolation (DTI) can be implemented underneath the passive components to reduce the substrate parasitics and increase effectively the substrate resistivity.

Table 2.3 Overview of the technology properties important for the passives for a typical GaAs process and the QUBiC4 gen. 8

process. property GaAs QUBiC

gen. 8 No. of metal layers 2-3 5 Top ~3.5 3 Top metal conductivity (S/m) 3.7 3.1 Top metal distance to substrate ~3.5 10

>1x106 200 Deep Trench Isolation (DTI) N/A yes Through substrate vias yes no

Transmission lines in GaAs technology are commonly implemented as micro-strip lines (MSL) due to the

availability of the TSVs, making use of the top metal layer as signal path and the ground plane below the substrate as return path. In contrast, transmission lines in a silicon technology are commonly implemented as coplanar-waveguide (CPW) transmission lines, using the top metal layer(s) for the signal and return paths and having a patterned ground shield in the lowest metal layer M1, as shown in Fig. 2.3. To compare their performance, the attenuation constant and the Q-factor2 as a Fig. 2.4 for an MSL line in the GaAs technology and a CPW line in the QUBiC4 gen. 8 (SiGe) technology.

Fig. 2.3 CPW transmission line with patterned metal 1 ground shield.

2 The transmission-line Q-factor is defined as QTL [48].

12

Fig. 2.4 EM-simulated attenuation and Q-in SiGe technology.

Clearly observable, the attenuation constant is much larger (and the Q-factor lower) for the SiGe process as the

resistive losses are much larger. The Q-factors of lumped inductors are almost equal for both technologies, in the range of 20-30. Hence,

matching with transmission line elements is extensively used in GaAs technology due do their low losses. The impact of the component Q-factor on the matching losses will be discussed in more detail in section 2.4.2, Impedance Matching.

Having discussed these differences in technology, it is clear that the realization of mm-wave Watt-level PA in a

SiGe technology is more a challenge compared to GaAs technology.

2.3 SiGe Technology This section discusses additional properties of SiGe technology relevant for design and subsequently the selection

of the specific generation of the QUBiC4 BiCMOS process.

2.3.1 General Properties The collector current of a bipolar device in its forward-active region is given in its simplified form as [49]: = (2.3)

with Is the saturation current, VBE the base-emitter voltage and VT the thermal voltage kT/q, which equals ~26mV at T=300K. The current IC increases exponential with the base-emitter voltage VBE and is dependent on temperature via Is and VT.

The collector-emitter breakdown voltage for a bipolar device with its base open (RB B=0) is given by the parameter BVCEO. With a shortened base (RB the collector-emitter breakdown voltage becomes equal to the parameter BVCBO, the collector-base breakdown voltage with the emitter open. In normal operation the base resistance RB has a finite value and hence the collector-emitter breakdown voltage will be in practice in between BVCEO and BVCBO.

Next to this voltage breakdown (electrical breakdown), which is caused by avalanche multiplication, current flowing through a device can result in thermal runaway, caused by the collector current dependency on the temperature.

The stable-operating-area (SOA) of the devices is defined in the voltage-current plane by the operation points at which electro-thermal instability occurs, which is caused by the combination of the two mentioned mechanisms (avalanche multiplication and thermal runaway) [50], [51].

13

2.3.2 Selection of SiGe Process Generation Fig. 2.2 showed several generations of the QUBiC4 process as a function of speed (gain) and breakdown. Table

2.4 gives a comparison of the parameters of the two generations most suitable for mm-wave applications, gen. 7 and gen. 8.

Table 2.4 QUBiC4 NPN HBT transistor comparison for gen. 7 and gen. 8 [40]. QUBiC4 gen. 7 QUBiC4 gen. 8

SiGe:C HBT LV SiGe:C HBT HV SiGe:C HBT LV SiGe:C HBT HV Peak ft (GHz) 110 60 180 90

JC @ peak fT 2) 3.5 0.8 8 2 fmax (GHz) 140 120 200 200

hFE 320 320 1800 1500 BVCEO (V) 2.0 3.5 1.5 2.5 BVCBO (V) 5.5 13.4 4.5 11.5

Although the devices’ breakdown voltages are somewhat lower, the QUBiC4 gen. 8 is selected based on their

much higher values for fmax, both for the low-voltage (LV) and high-voltage (HV) device, and their higher optimum current densities, requiring fewer devices to operate at the same current.

For this generation the maximum stable gain (MSG) and maximum available gain (MAG) are plotted in Fig. 2.5 for the low-voltage device in a common-emitter configuration. At a frequency of 30GHz, a maximum gain of about 13dB is observed.

Fig. 2.5 Maximum stable gain (MSG) and maximum available gain (MAG) plotted as function of frequency for a QUBiC4 gen. 8 transistor in common-emitter configuration.

2.4 Design Considerations In this section several general PA design considerations are discussed as the device efficiency, impedance

matching, the gain vs efficiency trade-off, stable operation and single-ended vs differential operation.

2.4.1 Device Efficiency For class-A operation, an output efficiency of ideally 50% can be obtained [18]. Reducing the conduction angle of

the current waveform towards class-B operation by lowering the base bias voltage improves the efficiency as the DC-current is lowered. However, lowering the base bias voltage reduces the gain as a larger input voltage-swing is required to obtain the same output power. The power added efficiency (PAE) includes also the gain in its representation and represents better the actual efficiency: = = 1 1

(2.4)

14

o=Po/PDC the output efficiency, Pin and Po the input and output power, respectively, PDC the consumed DC power and G the power gain.

Next to reducing the current conduction angle and hence shaping the current waveform, the efficiency can be further improved by wave-shaping the voltage such that the voltage-current overlap and hence the dissipated power Pdiss reduces, as at class-F or class-E. However, this requires specific harmonic load terminations, complicating the design.

Another factor that impacts the device efficiency is the knee-voltage of the device Vknee, effectively reducing the output efficiency in class-A operation compared to a hypothetical zero knee-voltage case by a factor: = 1 (2.5)

2.4.2 Impedance Matching The maximum output power that can be extracted from one device at ideal class-A operation is given by: P = 0.5 ( , , ) (2.6)

with Vo,max and Io,max the maximum voltage the device can withstand and Io,max the maximum current the device can deliver, respectively, which are determined by the SOA, as discussed in section 2.3.1. To achieve this, the device need to be terminated in its optimum impedance, the load-line impedance, which equals Zopt=Vo.max/Io,max. When the required Zopt optimum impedance to achieve load-line matching. This matching network impacts efficiency and bandwidth.

As example, for a single-section LC-network the efficiency can be expressed as [52]: 11 + 1 (2.7)

with ITR=RL/Ropt the impedance transformation ratio and QL the inductor’s Q-factor. Fig. 2.6 shows this efficiency as function of the ITR for several values of QL. Clearly, the degradation of efficiency is observable as the impedance transformation ratio increases and as the inductor’s Q-factor reduces.

Fig. 2.6 Efficiency as function of the impedance transformation ratio (ITR) for a single-section LC network for several values for the inductor’s Q-factor.

2.4.3 Gain vs Efficiency Trade-off As the maximum power gain (Gmax) (see section 2.3.2) of the active devices at these frequencies is typically lower

than the required gain level, and compensation for the passive (matching) losses is required, gain improvement needs to be used. This can be accomplished by applying cascoding and/or cascading of active blocks. Cascading reduces the PAE as the total consumed DC power increases. As example, for two cascaded stages, the PAE becomes:

15

= 1 1 11 + 1 1 11

(2.8)

with PAE1,2 and G1,2 the PAE and gain of the first and second stage, respectively. This equation shows the impact of the first stage’s PAE (PAE1) on the total PAE, directly depending on the value of G2, the gain of the second stage.

2.4.4 Stable Operation All the active devices need to operate within the stable-operating-area (SOA) to prevent electro-thermal

breakdown. Moreover, oscillations within a distributed PA, with many interconnected devices and loops, might easily occur. Therefore additional stabilization measures might be required to ensure stable operation from DC up to fmax, i.e. to prevent both electro-thermal breakdown and any unwanted oscillation. Part of the required stabilization networks will be located in the DC-path and hence the designs of the biasing and stabilization networks impact each other and can have conflicting requirements.

2.4.5 Single-Ended vs Differential Operation As the source- and load impedance of VSAT PAs -ended, single-ended operation is

required at the PA system’s input and output. Applying single-ended to differential conversion such that the core of the circuit can operate differentially offers benefits as virtual grounding, doubling the device voltage-swing and being more immune to common-mode interferers. However, the required differential to single-ended conversion increases losses and/or introduces asymmetry in the operation, the latter happening when using e.g. transformer power combining [56].

2.5 State-of-the-Art in Silicon-Based Design This section discusses the state of the art in mm-wave silicon-based PA design towards Watt-level output powers.

Table 2.5 gives an overview of published (near) mm-wave silicon PAs with saturated powers over 23dBm. Spatial combining techniques [57], [58] are left out of consideration as the goal is to achieve Watt-level output power on-chip.

Table 2.5 Comparison with (near) mm- delivered on-chip.

[65] (’13)

[63] (‘13)

[60] (’13)

[63] (’13)

[62] (’07)

[61] (’05)

[59] (’14)

[66] (’15)

[66] (’15)

Technology 0.13um BiCMOS

45nm SOI CMOS

45nm SOI CMOS

45nm SOI CMOS

0.13um BiCMOS

0.20um BiCMOS

0.13um BiCMOS

0.35um BiCMOS

0.35um BiCMOS

Topology

16-way in-phase current

combiner

8-way lumped

combiner

4-stacked 2-bit DAC

modulated switched

PA

4-way transformer

combiner

4-way transformer

combiner

Double- stacked class-E

4-way lumped

combiner

Device Parall.

freq. (GHz) 42 37 45 45 60 22 41 24 24 Supply (V) 4 / 2.4 4.8 5.1 2.4 / 2.6 4 1.8 4 5.8 5

Psat,max (dBm)

28.4 27.3 24.3 23.4 23 23 23.4 30.8 24.7

PAEmax (%) 10 10.7 14.6 6.7 6.3 19.7 34.9 17.6 31 Gainmax

(dB) 18.5 19.4 18 11.9 20 20 14.5 16.1 18.5

Area (mm2) 5.55 4.16 0.77 4.16 3.42 6 1.02 5.37 0.86

16

Several power combining techniques are presented in these references to overcome the problem of the limited output power that one device can deliver, which are:

device-level combining techniques: o device-parallelization [66]; o device-stacking [59], [60];

circuit-level combining techniques: o transformer based voltage-combining [61], [62]; o lumped-element (Wilkinson) combining [63], [66]; o transmission-line based in-phase current combining [65].

The distinction between device-level and circuit-level combining is based on the scale of combining: the former at small electrical distances electrical distances. Another distinction can made considering the implementation of the impedance matching as this is commonly integrated in the circuit-level combiner as more area is here available due to the combining over larger distances.

Considering Table 2.5, the highest output powers are achieved by the lumped-element Wilkinson combining [63], [66] and the transmission-line based in-phase current combining [65]. These combiners allow symmetric operation for large-scale networks as these types scale well with the number of inputs such that the signals are summed up in-phase and with equal magnitude. The highest PAE-values are obtained by the device-parallelization [66] and device-stacking [59], however their generated powers are moderate. These different techniques of power combining or now discussed in more detail, starting with the device-level combining techniques in section 2.5.1 and subsequently discussing the circuit-level combining techniques in section 2.5.2.

2.5.1 Device-Level Combining Device Parallelization One way to increase the output power is to put multiple devices in parallel (device parallelization) to increase the output current [67], [68]. One problem here is that the required Zopt reduces when more power is required, increasing the impedance transformation ratio. Another problem that arises is that the impact of the layout interconnect becomes apparent when device parallelization is applied. Due to the spatial distribution of the devices the layout interconnect between the devices shows distributed effects at mm-wave frequencies. This causes the devices to operate differently from each other and limits the number of devices to use. Nevertheless, this approach for power improvement is relatively easy at design and implementation. Device Stacking

Another way to improve the power is to stack multiple devices such that the output voltage is increased [69], [70], hereby increasing the required Zopt and hence reducing the impedance transformation ratio. The output power generated by applying device-stacking is limited as it becomes more difficult to realize equally operating stacked devices, especially at mm-wave frequencies. The design is more complex as compared to device-parallelization as it is more difficult to obtain equally operating devices.

So for both techniques the linear scaling of output power with the number of devices is prevented as it becomes

more difficult to realize equally operating devices, which leads to a reduction in output power, efficiency and gain. Moreover, when the devices are spatially put close to each other at both techniques for interconnect impact reduction purposes, the mutual thermal coupling between the devices increases, which can lead to a thermal hotspot.

2.5.2 Circuit-Level Combining To cope with the mentioned interconnect, matching and thermal issues, power combining of multiple smaller PA

cells is therefore often used, leading to circuit-level combining.

17

Transformer-Based Combining

Transformer-based combining gained a lot of attention in recent years [56], especially at mm-wave frequencies as a transformer can offer properties as low loss, broadband transfer and small size [71], [72]. However, it is difficult to implement a symmetric behaving transformer combiner at an increasing number of inputs due to its inter-winding capacitances [73]. Consequently, the impedances shown towards the different output stages become unequal and hence the injected currents need to be scaled down, otherwise electro-thermal breakdown can occur more easily for some of the stages. This will lead to a degradation in total PA performance. Wilkinson Combining selecting the proper characteristic impedances for the lines. Resistors between the inputs provide isolation between the inputs [79]. The drawbacks are the large area consumption and increased losses due to the use of the

sformation range is also limited. To overcome these drawbacks, lumped-element Wilkinson combiners are used, where the are replaced with an equivalent LC-network [74]. However, transmission lines are still required to connect the multiple lumped-element branches together and sum up the currents. In general holds for a Wilkinson combiner that it is not flexible in impedance matching as it requires for each cascaded section an (equivalent) electrical length of 90°. Transmission-Line Based In-Phase Current-Combining Compared to the Wilkinson combiner, the in-phase current combiner [64], [75], [76] provides flexibility for impedance matching as it can employ arbitrary length transmission lines and can result in improved performance in terms of used area, insertion loss and frequency bandwidth. Also here, as a limited range of characteristic impedances is realizable, the impedance transformation range is also limited when using transmission lines solely. To increase the impedance transformation range, lumped elements can be added. Considering the discussed combining techniques, the device-parallelization would be a good choice to improve the output power at the device-level, due to ease of use. At the circuit-level, a combiner based on the transmission-line based in-phase current combiner seems attractive, as it allows large-scale combining and offers flexibility for impedance matching. Both techniques are current combining and transmission-line based techniques, one (device-parallelization) applying current combining at small electrical distances (d<< 20), and the other applying current combining at larger electrical distances.

In the next section, the design issues encountered at Watt-level mm-wave PA design, hereby using these two combining techniques, are discussed.

2.6 Design Issues As addressed in the previous section, at the device parallelization the performance scales not linear with the

number of device due to the impact of the layout interconnect. This causes the devices to operate differently from each other. This is visualized in Fig. 2.7, which shows a number of devices connected in parallel with the layout interconnect in between. A small difference between the devices’ base-emitter voltages causes a large difference in their collector currents, as stated by (2.3). As the differences between the collector voltages is usually not much, the differences in impedances observed by the devices is almost entirely determined by this collector current difference. The result is that the devices are not operating equally and hence the output power is not scaling proportional with the number of devices. Hence, the distribution and combination of these devices needs careful attention such that performance degradation is minimized.

18

B'

E'

C'

interconnect

interconnect

interconnect

Zc,i

Vbe,i

Fig. 2.7 Example of unequal operation of devices when applying device parallelization due to unequal collector currents Ic,i as a result of the impact of layout interconnect.

The design of the in-phase current combiner at the circuit-level has to deal with the number of inputs, the

desired input impedance, the required minimum transmission line length imposed by the pitch between two successive PA cells, and the limited range of available component values.

Next to these actions required for power improvement, multiple options exist for realization of the gain improvement. The goal is to minimize the PAE degradation due to the power and gain improvements, meanwhile having proper biasing and ensuring stable operation. Also, the impact towards PA performance degradation at insertion of the biasing and stabilization networks needs attention. Hence, the design complexity is large due to the many choices existing and due to the interaction between the problems.

To find a power efficient design, all these choices need to be explored, which is a cumbersome and

time-consuming task as many design iterations are needed. Therefore, only a limited design space is normally investigated, which might lead to non-optimum results. To cope with this, a modular design approach is presented in this thesis to explore the available options in a structured way. This approach reduces the number of design iterations such that the optimum PA performance is found in limited time, hereby focusing on output power, efficiency and gain.

19

3 Modular Approach As discussed, a modular approach is used to reduce the design complexity, by exploring the available options for

accomplishing power combination, gain improvement and insertion of bias and stabilization functions in a structured way. The modular concept is explained in the next section and subsequently in section 3.2, Example Topology and Modules, the modular approach is explained in more detail by using an example topology. This topology is used throughout this work. In chapter 6, Design Approach, the (qualitative) design for this topology will be discussed in detail in section 6.2, Topology Design, and the (quantitative) design procedure for assigning the design parameters for this topology will be discussed in section 6.3, Parameter Design. In section 3.3, Even-Mode and Odd-Mode Operation, the desired mode of operation when combining multiple devices, the even-mode, is discussed together with its counterpart that results in an undesired mode of operation, the odd-mode. The sources of the undesired odd-mode operation are discussed in section 3.4 and in section 3.5 the combining efficiency degradation due to odd-mode operation is discussed.

3.1 Modular Concept In a modular concept, multiple hierarchical levels can be specified. This provides the opportunity to distribute

both power and gain improvement, biasing and stabilization means over the various levels. A specific choice of hierarchical levels and of the (qualitative) distribution of the functions over these levels specifies a PA topology. The (sub)functions at each level are represented by ‘modules’ or a group of modules, and each module on its turn has various implementation options, the module options. The modular concept enables PA optimization by exploration of the available module options within a certain PA topology in a structured way.

3.2 Example Topology and Modules The modular approach is described now in more detail. For reasons of clarity, but without loss of generality, this

will be done on the basis of a specific topology. This topology, which is an instantiation of the generic topology, is used throughout this work and is discussed here. The motivation for selecting this topology is that it is the preferred topology for the specific design example that is used in this work. The choices made to result in this topology are discussed in more detail in section 6.2, Topology Design. The available options for the distribution of the biasing and stabilization functions throughout the multiple levels depend on the selected module options for the implementation of the power and gain improvement functions and are therefore described later on in chapter 5. The modular approach is a process-technology independent approach. However, examples used for clarification are described in relation to a SiGe:C BiCMOS process using HBT devices.

The PA topology for the power and gain improvements is shown in Fig. 3.1. To improve PA output power R-multiple active devices (AD) can be combined in the R-direction to create an active cell (AC) by using splitting module PSR and combining module PCR as shown in Fig. 3.1 left. As shown in Fig. 3.1 upper right, the AD can be implemented in a common-emitter or a common-base topology using elementary devices (ED). Elementary devices (ED) have multi gate fingers or multi emitter stripes depending on the use of a FET or a bipolar device, respectively. This ‘multiplication’ will from now on be referred to as multi-fingered devices for both. The active cells (AC) can be used in a common-emitter only (H=1) or a cascoded (H=2) topology, the latter using a common-emitter and a common-base configured active cell (AC). Cascoding performs power and gain improvement. Apart from that, power can be further improved by combining Q-multiple ACs in the Q-direction by using splitting modules PSQ and combining modules PCQ. This two-level splitting/combining results in an active module (AM). Instead of cascoding active cells (AC), in the S-direction active modules (AM) can be cascoded within a power module (PM), as shown in Fig. 3.1 lower right3.

At the highest level (the PA module) the output powers of N-multiple power modules PMK can be combined in the N-direction with combining module PCN, as shown in Fig. 3.2. Gain improvement occurs at this level in the K-direction using K-1 cascaded drivers PM with each driver cascaded with an inter-stage network ISN. At the input

3 At H=2 or S=2 only cascoding of two active cells (AC) or active modules (AM) is allowed within the used topology, respectively. So no cascading is allowed

at these levels, as will be explained in more detail in paragraph 6.2, Topology Design.

20

side of each inter-stage network, Mk-multiple (parallel) drivers are present with the index k referring to a specific driver. The PA’s input signal is distributed towards the M1-multiple (parallel) drivers PM1 with splitting module PSM.

The available sub-functions for the power improvement can be summed up as: amplification (ED, AD, AC, AM, PM, PA), power splitting (PSR, PSQ, ISN1-ISNK-1, PSM) and power combining (PCR, PCQ, PCN). The inter-stage networks ISN are here categorized as a power splitting function. However, they can also be implemented as a non-splitting network (1:1).

The amplification modules containing splitting and combining modules are AC, AM and PA. Cascoding occurs by cascoding active cells (AC) or active modules (AM). Cascoding improves gain, next to enhancing power. Cascading on the highest level, the power modules (PM), is another way of accomplishing gain improvement. An amplification module can comprise more than one active block, possibly combined with splitting and combining modules. Each of these active blocks can be seen in turn as an amplification module.

At the available discussed directions (H, Q, R, S, K, N, M1-MK-1), the total number of inputs/outputs or submodules is represented with the capital letter representing also the specific direction. A specific input/output or submodule is indicated with the small letter representing also the specific direction. As example, in the Q-direction the total number of inputs of the combining module PCQ is represented with ‘Q’, e.g. Q equals 10. When a specific input of that module need to be indicated then ‘q’ is used, e.g. q equals two indicates the second input.

+

R

PCR

PSR

AD AD AD

AC2

+

Q

PSQ PCQ

AM

SAM1 AM2

PM

AD

EDCE EDCBAC1

AC1

ED: multi-fingered devices

S=1: CES=2: Cascode

H=1: CEH=2: Cascode

+

R

PCR

PSR

AD AD AD

AC1

AC2

AC2

H

Fig. 3.1 Example topology showing the modular approach. The active devices (AD) can be implemented in a common-emitter or a common-base topology using multi-fingered elementary devices (ED). Each active cell (AC) comprises R-multiple active devices (AD), a power splitter PSR and a combiner PCR. The active cells (AC) can be used in a common-emitter only (H=1) or a cascoded (H=2) topology. An active module (AM) comprises Q-multiple active cells (AC), a power splitter PSQ and a combiner PCQ. The power module (PM) can be implemented in a common-emitter only (S=1) or a cascoded (S=2) topology using active modules (AM). Cascoding is then applied at power module (PM) level instead of cascoding active cells (AC).

21

.. +ISN2M2

PCNNPSM PMKISN1M1I PM2PM1

PA

K

M1 M2 M2 M3

Fig. 3.2 PA module comprising power splitter PSM, power modules PM1-PMK, inter-stage networks ISN1-ISNK-1 and power combiner PCN.

3.3 Even-Mode and Odd-Mode Operation At the amplification modules (AC, AM, PA) where the power improvement is performed by employing the

splitting and combining modules, the output signals of equally operating active blocks need to be combined coherently to maximize output power within such an amplification module. Referring to Fig. 3.1, the active devices (AD) within an active cell (AC) are an example of such (parallel) active blocks where it is desirable that they operate equally. Equally operating active blocks are realized by using:

Parallel active blocks that are intrinsically the same. Equal signals for the parallel active blocks, which means:

a. equal RF input signals; b. equal biasing levels.

Equal source- and load impedances over the whole frequency band from DC up to fmax. This includes the impact of the biasing and stabilization networks.

Parallel active blocks that operate isolated from each other or that experience equal interactions, which means having:

a. electrically isolated active blocks, that is no or equal electrical coupling between the active blocks exists;

b. thermally isolated active blocks, that is no or equal no mutual thermal coupling between the active blocks exists;

c. electro-magnetically (EM) isolated active blocks, that is no or equal EM-coupling between the active blocks exists;

d. spatial isolated active blocks, that is the active blocks experience no or equal impact due to spatial restrictions.

Next to these equally operating active blocks, symmetrically operating splitting and combining modules are required for distributing the amplification module’s input signal evenly towards the active blocks’ inputs and summing up the active blocks’ output signals evenly, respectively. Under these conditions ‘even-mode’ operation is realized: the active blocks’ output signals are equal in magnitude and phase as well their input signals, so no ‘odd-mode’ components exist between these outputs and between these inputs [79]. Odd-mode signals are defined here as the signal differences between pairs of output nodes or pairs of inputs nodes. At the described even-mode operation, no module interactions take place, i.e. no coupling between modules exists. The loading presented to a specific active block is not depending on the other parallel active blocks in this case. Moreover, the even-mode operation allows using an equivalent even-mode diagram, which greatly simplifies the analysis and design for such an amplification module.

22

Odd-mode operation will result in degradation of the amplification module’s combining efficiency, which will be discussed in section 3.4.2. Moreover, when odd-mode operation occurs odd-mode electrical stability becomes more of a concern, which will be discussed in more detail in section 5.5, Stabilization. In the next section the sources for undesired odd-mode operation will be discussed.

3.4 Sources of Odd-Mode Operation Undesired odd-mode operation within the amplification module results as asymmetry arises when one or more

of the required conditions for even-mode operation are not satisfied. Assuming having intrinsically the same active blocks, asymmetry can result from:

Splitting and combining modules: o Asymmetric nature of the splitting and combining modules themselves. o Electrical coupling between the outputs of the splitting module and/or between the inputs of the

combining module due to finite isolation between the outputs or inputs, respectively. This results in dynamic loading. At dynamic loading, the loading presented by the splitting and combining modules to an active block depends also on the behavior of the other parallel active blocks.

Imperfect grounding resulting in unequal ground return paths for the parallel active blocks: o Asymmetry between the ground return paths themselves. o Increased electrical coupling between the parallel active blocks due to this.

Bias distribution networks: o Impact of asymmetric nature of the networks themselves; o Increased electrical coupling between the parallel active blocks due to impact of the bias

distribution network; EM-coupling between or within modules. Thermal coupling between or within modules.

Due to coupling mechanisms (electrical, EM, thermal) existing between modules the situation becomes more

complicated as the modules can interact with each other, which leads to an increased odd-mode operation. The final odd-mode operation is the result of the combined impact of the listed sources. These sources of odd-mode operation are now discussed in more detail one by one.

3.4.1 Asymmetry and Dynamic Loading at Splitting and Combining Modules Depending on the type of module used, the splitting and combining modules can show asymmetric and/or

dynamic loading behavior. Different types of those modules will be discussed in chapter 5. The asymmetry results from unequal transmission paths and unequal reflections experienced by the outputs or inputs of a splitting or combining module, respectively, which give rise to odd-mode operation. The dynamic loading behavior results from the interaction between its (dynamic) outputs or inputs, respectively. This results from the fact that at a linear passive multi-port the loading presented by a specific port depends in general next to the multi-port’s intrinsic properties also on the (extrinsic) signals at the other ports. Due to these signal dependencies, all the signals of the other modules within the same amplification module potentially contribute to that specific port’s presented loading. Only when the ports of such multi-port are isolated from each other, no dynamic loading will occur at the multi-port. Dynamic loading increases the odd-mode operation as the inequality between the loadings presented to the parallel active blocks increases. As mentioned, depending on the type of module used the asymmetry and dynamic loading manifests itself. This is now discussed in more detail for a combining module as an example.

+12

F

F+1

L

a1

aouta2

aF

Fig. 3.3 Combining m L.

23

A combining module can be seen as a multi-port module with F inputs and one output, as shown in Fig. 3.3. The

input reflection coefficient of such a module is expressed using s-parameters as:

, = , + ,1 , ,( ) .. ..

(3.1)

with Sx,y the module’s s- L the load reflection coefficient and ax the incident waves, with x,y=1,2,..,F, and aj=f(ai) showing the condition that the incident waves at the other ports (aj) are a function of the incident wave at the port of interest (ai). This function is required to define correctly an impedance for such multi-port, as the relations between the incident wave at the port of interest and the incident waves at the other ports need to be defined for this. The impedance definition for such multi-port is discussed in detail in Appendix A, Multi-port Impedance Definition. From (3.1), one can see the dependency on the incident waves of the other input ports ax (the extrinsic signals), next to the module’s s- L.

For reasons of convenience, the condition that describes the relation between the incident waves is assumed to be implicitly included in the equations and hence is not mentioned at the equations anymore from now on. The type of module can be classified regarding the impact to the odd-mode behavior according to its intrinsic properties (described with Z/Y-parameters and indirectly with S-parameters).

As said, a combining module can be seen as a multi-port module with F inputs and one output, as shown in Fig. 3.3. According to the module’s intrinsic properties described with S-parameters the combining module can be classified considering its:

1. input reflection coefficients Si,i 2. forward transmission coefficients from the inputs towards the output SF+1,i 3. transmission coefficients between the inputs Si,j

inputs. For these coefficients reciprocity is assumed, so Si,j=Sj,i; 4. reverse transmission coefficients from the output towards the input Si,F+1

between the inputs and output.

Considering this, the following module classification is made: A symmetric module is classified as having equal input reflection coefficients and each type of transmission

coefficients is equally valued. Then (3.1) becomes:

, = , + , ,1 , (3.2)

An input isolated module is classified as having zero-valued transmission coefficients between the inputs. Then (3.1) becomes:

, = , + ,1 , , (3.3)

At a symmetric module, only when all incident waves ai in,i values are equal and symmetric operation results. For even-mode operation, this type of combining module is required, as mentioned earlier.

At an input isolated module, L equals zero (the matched case) the presented impedances depend only on its intrinsic properties and no dynamic loading occurs. When L unequals zero (the unmatched case), the presented impedances depend also on the incident waves, the input signals, and hence dynamic loading occurs.

A module can have multiple classifications, so e.g. a symmetric module can also be classified as input isolated.

24

Putting this in relation to the odd-mode operation: A combining module that is asymmetric results in odd-mode operation due to the unequal loading of

the parallel active blocks and/or non-coherent summing of the active blocks’ output signals. Only in case when this module is also input isolated and load matched, no dynamic loading occurs and hence no module interaction between the active blocks occurs. So further enlargement of the odd-mode operation will not occur.

A combining module that is not input isolated results only in no odd-mode operation when this module is also a symmetric module with having equal incident waves. Otherwise, such an module results in increased odd-mode operation due to the dynamic loading that is changing the presented loadings to each of the parallel active blocks.

A combining module that is both asymmetric and not input isolated results in odd-mode operation due to the two aforementioned mechanisms combined.

A similar classification and similar observation can be made for a splitting module, comprising one input and F

outputs. Having unilateral active blocks in front of a combining module, the active blocks’ input signals are not affected by

a potential dynamic loading behavior of this combining module. Hence, this decouples the combining module’s dynamic loading behavior from the splitting module’s dynamic loading behavior, which makes the realization of even-mode operation less complex. The degree of complexity depends on the modules’ classification type and the amount of modules participating in the dynamic loading behavior.

In chapter 5, Module Options and Limitations, the different options for implementation of the splitting and combining modules and amplification modules will be related to the presented module classification. In section 3.5, Combining-Efficiency Degradation Due to Odd-Mode Operation, the impact of the discussed asymmetry and dynamic loading is included.

3.4.2 Imperfect Grounding In process technologies where no good, low-impedance, on-chip ground plane is available, the ground return

path needs to be implemented in one (or more) of the available metal layers. The (intended) on-chip ground return paths for the RF-currents are part of the splitting and combining modules and hence the symmetry between the ground return paths of the parallel active blocks depends on the type of splitting or combining module used, as was discussed in the previous section. The ground return paths for the DC-currents are often implemented in an asymmetric way from the point of view of the parallel active blocks due to spatial (planar) restrictions within the technology. Using for this, if possible, also the RF ground return paths would lead to a larger DC voltage drop and hence reduced output power and efficiency. The DC ground paths connect at some points to the RF ground return paths, hereby introducing asymmetry in the effective ground return paths of the RF currents. Hence, the effective RF ground path and DC path resistances differ between the parallel active blocks and asymmetry between the operation of these blocks can result. Moreover, electrical coupling between the parallel active blocks can increase due to this. The RF ground return paths and DC ground return paths are explicitly included for these reasons in the modeling during design, which will be discussed at chapter 6, Design Approach.

Implementing the parallel active blocks in a differential topology ideally disconnects the differential (RF) ground paths (for the odd harmonics) from the common-mode (DC) ground paths due to the concept of virtual grounding. However, it is often required that the input and output of the chip still need to be a single-and hence transitions from single-ended to differential are required here, leading to increased loss and/or asymmetry. Hence, a single-ended topology is chosen.

For the application the chip will be finally mounted on a PCB, which has a low-impedance ground plane, with the on-chip ground paths connecting to the PCB ground via bond wires. Hence, it makes sense to have enough ground bond wires distributed along the chip sides to minimize the ground impedance from chip to PCB, which should be included in the modeling. However, the PCB design is beyond the scope of this thesis, which focuses on the chip design.

25

3.4.3 Biasing Distribution The networks required for distribution of the DC supply and bias signals can introduce an asymmetry in the

operation of the parallel active blocks as these networks are often implemented in an asymmetric way from the point of view of the parallel active blocks due to (spatial) limitations within the technology. Moreover, these networks can increase the electrical coupling between the parallel active blocks. The impact of the DC supply networks on asymmetric operation of the parallel active blocks is discussed in section 5.4, Biasing.

The biasing signals for the parallel active blocks could be generated locally at each active block, hereby reducing potential asymmetry of a distribution network. However, this is beyond the scope of this thesis due to time limitations.

3.4.4 Electromagnetic Coupling The other module interaction that can occur within a module or between modules is electromagnetic (EM)

coupling. The dominant coupling mechanism is magnetic coupling in the currents’ transverse spatial direction. At even-mode operation, transverse capacitive coupling can be neglected due to the approximately zero-valued voltages across the parasitic capacitances between the modules.

Due to these coupling effects, a changed behavior for the modules can be expected compared to the situation that they are isolated from each other, i.e. when no EM coupling exists. Therefore, the coupling effect’s impact towards performance should be investigated and hence included in the modeling. In chapter 6, Design Approach, the inclusion of this EM-coupling in the module modeling is discussed.

3.4.5 Thermal coupling Thermal coupling between the parallel active blocks results in a temperature gradient along the active blocks.

These temperature differences can result in different operation for the parallel active blocks [53]. The impact of temperature on a (single) active block’s operation is investigated in section 6.3, Parameter Design. The investigation of thermal coupling between the active blocks is beyond the scope of this thesis.

3.5 Combining-Efficiency Degradation Due to Odd-Mode Operation In this section the relations towards the combining efficiency for an amplification module containing splitting and combining modules (AC, AM, PA) are investigated. For the mentioned amplification modules, the combining efficiency relates the combining module’s output power to the total available active blocks’ output power. The available active block’s output power is the power that an active block delivers when it is load-line matched. This is investigated for general operation, so including odd-mode operation next to the desired even-mode operation. Having these relations enables to quantify potential degradation of the combining efficiency due to odd-mode operation. Next to the described module interactions, also the (intrinsic) asymmetry of a splitting and/or combining module contributes to the odd-mode operation. So all sub-blocks within these amplification modules can contribute to the odd-mode behavior. This analysis makes no assumption regarding the combining module’s classification-type, i.e. if it is (a)symmetric and/or (not) input isolated. This is in contrast to [55], which investigates the degradation of the combining efficiency due to the variability among the signal sources and assumes hereby the use of a symmetric input isolated combiner.

+12

F

F+1

ZL

I1

I2

IF

Iout

Fig. 3.4 Combining module with F inputs and with ZL the output port’s load impedance.

26

For a combining module having F inputs, as shown in Fig. 3.4, the overall combining efficiency is expressed as: = , ,

(3.4)

with Pin,opt,i the available active blocks’ output powers and Po the output power delivered to load ZL. Including the

tot becomes: = , ,, , , , = , ,, , (3.5)

with: = , ,

and with Pin,del,i the actual delivered input powers. The first factor on the right (3.5) expresses the power mismatch at the combining module’s inputs as it relates the total actually delivered input power to the available input power of the combining module. The second factor on the right, the intrinsic intr, relates the combining module’s output power to the total actually delivered combining module’s input power. Having these two factors enables to observe the contribution of each factor towards the overall combining efficiency.

Assuming equal active blocks and hence equal available optimum input powers Pin,opt,i , (3.5) reduces to: = , ,, = 1

(3.6)

with = , ,, .

The load mismatch factors, LMFs, are related to the mismatches between the actual combining module’s input impedances and the optimum load-line matched impedances and the differences between the actual and optimum input currents and voltages. Assuming that the elementary devices’ (ED) output voltages and currents will not exceed their maximum values, the LMF values are expressed in terms of currents and impedances as: = , ,, = | || | { , }{ }

(3.7)

or expressed in terms of voltages and admittances as: = , ,, = | || | { , }{ }

(3.8)

with Imax and Vmax the active blocks’ maximum allowed RF-current and voltage and Zopt/Yopt the active blocks’ optimum load-line impedance/admittance, and Ii and Vi the actual input currents and voltages and Zin,i/Yin,i the actual presented input impedances/admittances, respectively.

Considering (3.6), having all LMF values equal to one means that maximum input power is delivered to the combining module intr for a specific combining module is achieved when the delivered combining module’s input signals have the proper magnitude and phase such that they add up maximally to maximize output power.

In case dynamic loading is present, the required extrinsic condi intr can be conflicting with the required extrinsic conditions for maximizing the averaged summation of the LMFs, i.e. different sets of input currents can be required. In case for a symmetric combining module, both required extrinsic conditions are the same, which is the condition with equal input signals. Under these conditions all the input impedances are equal to each other and hence the input currents and voltages are all equal. For the case the real part of Zin is smaller than the real part of Zopt (current-limiting operation), (3.7) reduces to:

27

= = ,, = { }{ }

(3.9)

and for the case the real part of Zin is larger than the real part of Zopt (voltage-limiting operation), (3.8) reduces to: = = ,, = { }{ } (3.10)

similarly as used in [77], [78], where in the latter reference the use of such a symmetric combining module having equal input signals is assumed.

To quantify the potential degradation due to undesired odd-mode operation the LMF values should be determined. The amount of LMF degradation sets a limit on the usable electrical size when using asymetric splitting and combining modules. Assumed tot is mainly determined by the LMF factors. This is valid in the case the combining modules are not becoming very large in electrical size and hence the intrinsic intr remains close to one.

As the LMFs depend on the input currents, to determine them requires also knowledge of the behavior of the other modules within the amplification module that define these currents, which are the splitting module and the active blocks. The impact of the other modules towards these input currents is defined by the classification-types of these modules. The injected input currents Ii are related to the active blocks’ generated currents, in the small-signal case, by: = , ,, + , (3.11)

with Iact,i and YO,i the active block’ short-circuit current and output admittance, respectively.

Having unilateral active blocks, the short-circuits currents Iact,i are solely determined by the behavior of the splitting module together with the active blocks’ Y-parameters Y11,i and Y21,i. No feedback signals from combining towards splitting module are present here. Having non-negligible feedback, the short-circuits currents Iact,i are determined by the behavior of all the modules and their interactions. Dynamic loading occurring at the splitting module can therefore negatively affect the LMF values. Hence, in this case, the complete amplification module’s behavior needs to be known, as it determines the input currents and hence the LMF values.

When operating in class-A, the DC-currents can be assumed to be not depending on the input signals and hence can be approximated constant. Hence tot predicts next to the mentioned degradation of output power also the degradation in output efficiency.

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4 Structuring the Design Space The main function of a PA is the amplification function, with its subfunctions, power splitting and power

combining, required within the modular approach for obtaining a mm-wave watt-level PA. The biasing and stabilization functions are in turn required for proper operation of all the elementary devices (ED) within the PA. The options for distribution of the latter two functions depend strongly on the implementation of the power and gain improvement functions.

The distribution of these functions (amplification, power splitting, power combining, biasing and stabilization) over the selected hierarchical levels together with the available design parameters at each level can be presented with a ‘function matrix’. Such a distribution defines a PA topology and a function matrix comprising all the assigned design parameters is the outcome of a specific design.

The result of the function distribution for the power and gain improvement functions (amplification, power splitting and power combining) for an example PA topology was discussed in section 3.2. For this example PA topology the function matrix is given in Table 4.1 with the already discussed modules and their related design parameters at each level inserted in the matrix.

The choice of the hierarchical levels together with the module distribution for the functions (amplification, power splitting, power combining, biasing and stabilization) is discussed in section 6.2, Topology Design. The procedure to assign the design parameters is discussed in section 6.3, Parameter Design. Table 4.1 Function matrix showing the distribution of the functions over the hierarchical levels, together with the design parameters per level. The latter comprises ‘module type’ and ‘topology parameters’. For the example PA topology of section 3.2 the discussed modules (amplification, power slitting and combining) and their related design parameters at each level are inserted in the matrix. The items that still need to be addressed are indicated as yet with TBA.

Function Level

Amplification Power splitting

Power combining

Biasing base

Biasing collector Stabilization

Design parameters Module

type Topology

parameters

system PM1-PMK PSM ISN1-ISNK-1

PCN TBA TBA TBA TBA N, K, M1-MK-1

sub-level 1 AM - - TBA TBA TBA TBA S

sub-level 2 AC PSQ PCQ TBA TBA TBA TBA H, Q

sub-level 3 AD PSR PCR TBA TBA TBA TBA R

sub-level 4 ED - - TBA TBA TBA TBA -

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5 Module Options and Limitations In this chapter the module implementation options and the module limitations will be discussed for each of these

functions: amplification, power combining, power splitting, biasing and stabilization. For the power and gain improvement functions (amplification, power combining and power splitting), the relation of the module options to the dynamic loading from section 3.4.1 will be discussed, when relevant. The module options for the biasing and stabilization functions depend on the given module implementation options for the power and gain improvement functions, as mentioned earlier. At the module options, the pros and cons of the different options will be discussed with their relation to the limitations imposed by the process technology constraints.

5.1 Amplification The elementary devices (ED) within an active device (AD) are multi-fingered devices, which can be configured in a

common-emitter or common-base topology, to form the common-emitter only or the cascode topology (see Fig. 3.1). The remaining selectable parameters for the elementary devices (ED) are the device type, i.e. a low-voltage (LV) or high-voltage (HV) device, the number of fingers4 (Nf) and the device-area per finger (WfxLf). The HV-device has in general a higher breakdown voltage with a lower peak ft compared with the LV-device, due to the inevitable well-known trade-off between both parameters, as discussed in section 2.2.1. For the used process technology in this work (QUBiC 4 gen. 8), the peak ft/fmax and BVceo/BVcbo values are once again shown in Table 5.1 for a low- (LV) and high-voltage (HV) [40]. To obtain more insight in the behavior of ft and fmax as function of the current density, these values are now determined by simulations for a LV- and HV-device in a common-emitter configuration at VCB=1V, as shown in Fig. 5.1. Both devices have an emitter area of 0.4x20.4um2.

Table 5.1 Device parameters for low- and high-voltage device, see Table 2.4. Device type ft/fmax (GHz) BVceo/BVcbo (V) Jopt 2) Low-voltage (LV) 180 / 200 1.5 / 4.5 8 High-voltage (HV) 90 / 200 2.5 / 11.5 2

Fig. 5.1 Simulated ft and fmax as function of the current density (JC) for a single-fingered LV- and HV-device in a common-emitter configuration at VCB=1V, both devices having an emitter area of 0.4x20.4um2.

4 as mentioned in section 3.2, a finger refers for a bipolar device to an emitter stripe.

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The HV device’s maximum ft, fmax is when Jc equals about 1.2 2 and falls rapidly if the current density is further increased. The LV device’s ft, fmax curves increase smoothly and peak at 6 2. From about 3 2 onwards the increase is not much anymore. The values for the optimum current densities are lower compared to the values that were shown in Table 5.1, which come from the QUBiC4 manual [40], as the latter where extracted at optimum VCB conditions. This is also the reason for the relatively large difference in peak fmax for the LV-device (150GHz vs 200GHz).

Increasing the number of fingers of the elementary device (ED) for a given emitter area increases its fmax (and hence power gain) as it reduces its effective base resistance 2 emitter area. However, in building op a metal stack from the lowest metal (M1) to the top metal (M6) layer and hereby obeying the layout DRC rules, it is convenient to have maximum freedom in determining the spacing between the fingers (emitter stripes) and hence in view of this a single finger is desirable. The number of fingers (emitter stripes) can then effectively be increased at a higher level (see Fig. 3.1), within the active module (AM), by increasing the number of active devices (AD).

The emitter width of a finger is typically set to a minimum to minimize the device’s layout parasitics 2 emitter area such that the device gain degradation is kept to a minimum. Setting the finger’s emitter length to the maximum value allowed by the foundry model maximizes the output power per elementary device (ED) per finger, however, this increases the layout parasitics 2 emitter area, and hence reduces the device gain. This gain degradation is investigated by simulating the ft and fmax as function of the emitter length for a single-finger LV-device in a common-emitter configuration, with the results shown in Fig. 5.2.

Fig. 5.2 Simulated ft and fmax as function of the emitter length (Le for a single-fingered LV-device in a common-emitter configuration at VCB As can be seen, the ft and fmax curves decrease monotonically, as expected. The reduction in ft and fmax above an

power that can be extracted increases approximately proportional with the emitter length. Hence, an emitter length of e.g. 20.4 .2the same gain, but double output power.

To cope with the relatively low ft*BV product of the SiGe:C technology, a cascode configuration comprising a low-voltage common-emitter (LV-CE) device and a high-voltage (HV-CE) common-base device can be used to improve the gain and the breakdown voltage significantly [80]. Having a fixed supply voltage can result in efficiency degradation at cascoding compared to a common-emitter topology as only the total knee-voltage increases (see section 2.4.1). However, when the supply voltage is freely to choose the knee-voltage efficiency can become even larger for the cascoding.

The BVcbo values from Table 5.1 indicate the maximum allowable collector-base voltages with the emitter open, i.e. the emitter current is zero. In case there is emitter current flowing, as in normal PA operation, the elementary devices’ (ED) voltage and current limits are determined by the stable-operation-area (SOA) regarding electro-thermal stability, as discussed in section 2.3, together with the DC and RF current limitations for the device’s backend due to DC electro-migration and Joule-heating.

31

Considering the mentioned classification regarding dynamic loading behavior, an amplification module is simply classified by its two-port reverse transmission coefficient S12, the isolation. A cascoded amplification module (AD, PM) can be seen as a unilaterized module due to its high isolation (S12

module’s dynamic loading from the splitting module’s dynamic loading behavior, as mentioned. At a common-emitter amplification module the reverse transmission coefficient S12 is often non-negligible when operating at mm-wave frequencies. The comparison between the common-emitter and cascode topology is summarized Table 5.2.

Table 5.2 Comparison between common-emitter and cascode topology

Topology Gain Breakdown Isolation efficiency Common-emitter Moderate Moderate Moderate See (2.5)

Cascode Good Good (using (LV/HV pair) Good see (2.5)

5.2 Power Combining The performance of the combining module impacts the amplification module’s output power and efficiency

directly, as the combining module connects to the outputs of the active blocks. Three combining topologies are selected as potential candidates for implementation at network level: the star, the distributed and the binary tree topology, which are all shown in Fig. 5.3. The topologies are all current-summing and transmission-line based, as selected in section 2.5.

Next to the power combining, the combining module performs impedance transformation. Additional matching elements can be integrated with the combiner to extend the impedance transformation range and/or reduce the combiner’s losses for a certain impedance transformation ratio.

star distributed binary tree Fig. 5.3 Current-summing topologies using transmission-line elements for the splitting and combining modules.

Considering the three topologies and the module classification, none of them results in an input isolated module,

so in general dynamic loading occurs for these topologies. Obtaining an input isolated combining module would require e.g. a Wilkinson combiner, as discussed in section 2.5.2. The binary tree topology is the only topology resulting in a real symmetric module, independent of its electrical size. As discussed earlier, at a symmetric combining module with equal input signals, all input impedances are equal and also no dynamic loading occurs. The drawback of the binary tree topology is the required area, which is larger compared to the other two topologies.

The star and distributed topology have an asymmetric nature, the distributed topology more than the star topology. However, when their electrical size is small they can perform approximately as symmetric modules. Therefore, for these two topologies care must be taken at synthesizing the desired impedances as their symmetric operation depends on their electrical size, where the latter is a function of physical distance and the signals’ wavelength. This can result in unequal input impedances and dynamic loading. A (qualitative) comparison between the discussed topologies is shown in Table 5.3 considering symmetry, input isolation and area.

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Table 5.3 Characteristics for the combining module options. Topology Symmetry Input isolation Area

Star Moderate Poor Moderate Distributed Poor Poor Good Binary tree Good Poor Poor

The combiner topologies can be implemented at physical level with different types of interconnect/transmission

lines, such as CPS, Micro-strip and CPW [79]. Considering the undesired EM-coupling, a CPW-line performs outstanding in terms of self-shielding and hence the interaction is negligible. However, it consumes the largest area.

The currents flowing within the combiner are limited by the backend electro-migration and Joule-heating restrictions. The metal traces should therefore be well-dimensioned to prevent failure as relatively large powers and DC-currents are expected here.

5.3 Power Splitting For the splitting modules the same topologies as used at the power combining can be used. As mentioned in

section 3.5, symmetric operation of the splitting module is important to maximize the combining efficiency. The main differences to the power combining are the power and DC-current levels, which are relative low here. Hence, no problems will be expected due to the mentioned backend current limitations.

5.4 Biasing With the module options known for the splitting and combining modules, the module options of the biasing

and stabilization functions can be discussed. Each power module (PM) can be biased separately and in that case it needs its own biasing signals. In general, the biasing distribution can be located closer to or further away from the active devices (AD).

Without loss of generality, the available options for the collector biasing are discussed using a four-input binary-tree combining module as an example, as shown in Fig. 5.4. Considering this figure, moving the location of bias insertion from reference plane A towards C will have a number of consequences: 1) Reduce the number of supply nodes to connect. This leads to less asymmetry between the inputs introduced by the biasing network and hence reduced odd-mode operation. 2) Enlargement of the available area per bias element. 3) Increase of the DC-resistance. Considering Fig. 3.2, the power modules’ collector biasing networks are likely to be integrated at PA module level within the combining module PCN and the inter-stage networks ISN1-ISNK-1 due to the area consumption of the required inductors. Another option, which is only available for PMK, is to insert the collector biasing off-chip at reference plane ‘D’. This allows using off-chip high Q-factor components.

The inductors for the collector biasing can be implemented in a lumped or distributed fashion, the latter using transmission lines and hence occupying more area and having a lower Q-factor in the used SiGe:C BiCMOS technology. These shunt inductors can be included as part of the impedance matching. From this perspective, inserting the inductors at reference plane ‘A’ (see Fig. 5.4) would be a proper choice as the shunt inductance can resonate out directly the active blocks’ output capacitances.

The currents flowing in the output biasing networks need attention as relatively large powers and DC-currents are expected here. The metal traces should therefore be well-dimensioned to prevent failure.

33

S

G

G

A B C Doff-chip

Fig. 5.4 Different positions (plane A, B, C) for inserting the collector biasing means for a ‘binary tree’ combining module with four inputs. The option at plane ‘D’ is only available for combining module PCN.

The base DC current per active device (AD) is relatively small compared to the collector current and hence resistors are a good option to use for the input biasing. However, having a large resistor can change the voltage-drop significantly when the DC base current increases when driving the devices into compression [81]. The result is that the device’s base DC voltage reduces and hence the device operation will deviate from the intended operation as it will operate deeper into class B. The impact of this effect will be a function of input power and therefore affects the output power versus input power characteristic and hence the 1dB compression point. The focus in this work is on VSAT PAs that are operated into saturation, so the latter point is less of an issue here.

From a (small-signal) gain point of view, the impedance the bias network presents to the RF-signal must be at least 10 times the impedance of the RF-path to prevent non-negligible leakage of RF-current; otherwise the gain will reduce.

As the base biasing is often a combined design with the base stabilization networks and the distribution locations for the stabilization functions are more critical, the distribution of this combined base network is further discussed at the stabilization section in section 5.5.

5.5 Stabilization Insertion of stabilization functions can be required to prevent electro-thermal breakdown and oscillations.

Electro-thermal (ETh) breakdown is a destructive mechanism and the relation between the total base resistance in the DC path and the stable-operating-area (SOA) to prevent ETh breakdown for a bipolar transistor, as discussed in section 2.3.1. When operating below BVCEO, no avalanche current is generated and a larger base resistance can be applied. This can be desired for base-ballasting [54], which makes the generated current more robust for temperature variations.

To prevent current collapse [53]-[54], each active device (AD) should ideally have its own base resistance for ballasting. The current collapse results from a non-uniform temperature distribution over the active devices. Moreover, even- and odd-mode electrical stability [83] should be ensured over the entire frequency band from DC up to the elementary devices’ fmax to prevent oscillations. Odd-mode instabilities can arise more easily at single-ended power combining PA topologies in the form of unwanted differential operation between the parallel active blocks [84]. The k-factor method is commonly used to verify even-mode instabilities in a single-ended amplifier. However, this method only predicts unconditional stable operation with the proviso that the unloaded two-port network has no poles in the RHP [85]. Unconditional stable operation refers to the situation that the two-port remains stable for all passive source- S L|<1) presented to the two-port. However, the proviso is often neglected and not verified by the conventional k-factor test in a circuit simulator. Next to this, odd-mode instabilities are possibly not observable via the system’s two-port parameters [83]. Therefore, the rigorous generic method described in [86] is used to verify both even- and odd-mode stability. This method observes the open-loop gain of different internal loops at the power modules’ inputs and outputs by using circulators.

Adding additional series resistance at the active devices’ terminals damps out potential oscillations in general. However, implementing this at the device’s emitter and collector terminals is unpractical as large DC-currents will flow here. Having an amplification module designed for even-mode operation only, odd-mode stability is more

34

effectively improved by inserting stabilization resistances between the parallel active blocks’ inputs and outputs, which will leave the desired even-mode operation unimpaired.

Ideally, the stabilization networks need to be as close as possible to the active devices’ (AD) input and output terminals to have maximum impact to prevent the mentioned instabilities. However, depending on the implementation type of these networks, the related area consumption puts a limit on this.

When electrical stability around the operating frequency needs to be increased, the inserted base resistance will inevitably lead to gain reduction at these frequencies. However, normally the low-frequency (LF) stability is more of a concern due to the increased device gain at those frequencies. Inserting a high-pass network shunt RC network will attenuate the LF gain while leaving the gain at high frequencies (HF), as at the operating frequency, unimpaired. Due to the relatively large area of the shunt capacitance, this high-pass network limits the option to put a stabilization network at each active device’s (AD) base terminal, which would lead to an increased spacing between these devices, enlarging the required size of the splitting and combining modules. To further improve LF stability, large output (collector) bypass capacitances are required to present a low impedance also for low frequencies.

When operating above BVCEO, the requirements for total DC input resistance (RB1+Rsh1+Rser1) regarding ETh breakdown (low resistance required) and LF electrical stability, RF leakage and temperature robust operation (high resistance required) are contradictory and this results therefore in a trade-off. Using cascoding relaxes this trade-off. As the common-emitter devices can operate now below their BVCEO, they don’t require a low base resistance to sink the generated avalanche current. Therefore the input DC resistance can be increased to meet the requirements for LF electrical stability, RF leakage and robustness to temperature variations. The common-base devices will operate above BVCEO. RF leakage is not an issue for these devices and the resulting trade-off for these devices is only between resistance selection for ETh breakdown and LF electrical stability. Although the isolation increases when using a cascode configuration, the stability of the common-base device is a point of attention as a parasitic inductance between the base and ground can cause oscillation [82]. Fig. 5.5 visualizes the insertion of the base networks for biasing and stabilization for a cascode configuration with the signal paths for each of the three discussed frequency regions (HF, LF and DC) also depicted. As discussed, the high- and low-frequency paths are important for electrical stability. The DC-path is important for ETh breakdown and for the biasing purposes. The total DC-resistance for the common-emitter and the common-base device are given by RB1,tot and RB2,tot, respectively.

RFin

RB1

VB1

Csh1

Rsh1

CB1

Rser1

DC: ETh stab + Biasing LF: electrical stabHF: electrical stab

DC+RFout

RB1,tot=RB1+Rsh1+Rser1

RB2,tot=RB2

VB2Rser2

CB2

RB2

Fig. 5.5 Base networks for biasing and stabilization of cascode configuration.

The currents flowing through the stabilization networks are relatively low here compared to the collector

currents. Hence, no problems are expected due to the mentioned backend current limitations.

35

6 Design Approach In the previous sections the analysis was discussed related to the modular approach. In the coming sections the

design approach is discussed. At section 6.1, Design-driven Modeling, the module modeling which is used at the design is discussed. When no EM coupling occurs, the model for an amplification module is easily scaled with the number of active blocks by adding extra unit elements, i.e. adding additional transmission line paths within the splitting/combining modules and adding additional active blocks. However, when EM coupling occurs within or between modules this is not the case and hence the coupling should be included in the modeling. To accurately include these coupling effects, an EM-simulator is commonly used [87], [88] to characterize a passive structure that incorporates all these coupling effects. However, setting up and performing an EM-simulation can be time-consuming as for each of the multiple active devices (AD) three EM-ports (base, collector, emitter) need to be inserted to connect to the device ports. Moreover, for each new structure a new EM-simulation needs to be performed. By investigating the relevant coupling effects it is possible to shorten the design cycle as for the parts of the passive structure where coupling can be neglected, EM-simulated structures could be re-used. This allows a more easy scaling of the amplification module model. The design-driven modeling will be based on the used PA topology and the latter will be discussed afterwards in detail in section 6.2, Topology Design, and was already mentioned in section 3.2 for the power and gain improvement functions, as an example to become familiar with the modular approach. In section 6.3, Parameter Design, the procedure for assigning values to the design parameters is discussed. The topology and parameter design have a strong dependency on the frequency of operation due the potential impact of the splitting and combining modules’ electrical size on symmetric, and hence even-mode, operation. Subsequently in section 6.4, Layout Implementation, the layouts of the power blocks need to be implemented and their performance should be verified with a circuit simulator. In section 6.5, Overall PA Simulations, the performance and stability verification of the overall PA by using a circuit and an EM simulator is discussed. The matching networks need to be tuned when deviating from the intended impedance levels. The flowchart for the design approach is depicted in Fig. 6.1 with the references to the related sections included.

Start PA design

Topology design including design-driven modeling

Parameter design

Overall PA simulation, optimization and stability analysis

PA design ok?

PA design finished

section 6.1, 6.2

section 6.3

section 6.5

Layout implementation section 6.4

Yes

No

Fig. 6.1 Design flowchart for PA design

36

6.1 Design-driven Modeling This section discusses first the general modeling of the elementary devices (ED) and passives (splitting and

combining modules) when they are used in an isolated environment, i.e. no EM-coupling exists to other modules. Subsequently, based on the used PA topology, the design-driving modeling including the EM-coupling effects is discussed. The design of the used topology will be discussed in detail afterwards in section 6.2.

6.1.1 General Modeling The modeling of an ED is shown in Fig. 6.2 for an HBT device as an example and consists of the foundry transistor

model [95] together with the RC-extracted local parasitics.

RCX

B' C'

E'

E'

C'B'

ED =multi-port model electrical model

B'

C'

E'

foundry model

Fig. 6.2 Modeling ED shown for a HBT device as example. The electrical model incorporates the HBT foundry model together with the RC-extracted local parasitics. The elementary device is actually a four-port device with a base (B), collector (C), emitter (E) and a substrate terminal. However, the substrate terminal is not depicted as it is assumed implicitly to be connected to the local ground. This elementary device can be used in a common-emitter or common-base configuration. The elementary device (ED) is modeled up to metal 1 layer by the HBT foundry model. The model includes the poly and active-to-metal contact information. The local interconnect towards the top metal layer is modeled by RC-extraction. For the splitting and combining modules an EM-simulator is used to acquire an accurate model over frequency for the multiple transmission line section for each of the topologies shown in Fig. 5.3. This is especially required for the splitting and combining modules not implemented with CPW-lines, as this transmission line type is the only available type in the technology library.

6.1.2 Including EM and Electrical Coupling Effects in Module Modeling The relevant EM and electrical coupling effects are investigated for the used PA topology, and the topology

design for this will be discussed in the next section in detail. The result of this topology design for the power and gain improvement functions will already be discussed now, such that the coupling effects can be included in the modeling. The implementation for the used PA topology, shown in Fig. 6.3 once again, resulted in:

for the R-level, splitting and combining modules PSR and PCR of the ‘distributed’ type; for the Q-level, splitting and combining modules PSQ and PCQ of the ‘star’ type; for the M1, M2 and N-level, splitting and combining modules PSM and PCN and inter-stage networks ISN1 and

ISN2 of the ‘binary tree’ type. First the modeling of an active module (AM) will be discussed and subsequently the modeling of a power module (PM) and PA module.

The resulting active module (AM) for this topology is shown in Fig. 6.4 using at active cell (AC) level ‘distributed’ splitting/combining modules (PCR/PSR) and at active module (AM) level ‘star’ splitting/combining modules (PSQ/PCQ). The active devices (AD) within this active module (AM) are configured here in a common-base topology,

37

but this could also be a common-emitter topology. They comprise a single elementary device (ED), hence, the same model is used as shown in Fig. 6.2 for the active devices (AD).

+

R

PCR

PSR

AD AD AD

AC2

+

Q

PSQ PCQ

AM

SAM1 AM2

PM

AD

EDCE EDCB

AC1

AC1


S=1: CES=2: Cascode

H=1: CEH=2: Cascode

+

R

PCR

PSR

AD AD AD

AC1

AC2

AC2

H

.. +ISN2

M2 NPSM PMKISN1

M1PM2PM1

PA

K

M1 M2 M2 M3

PCN

0

Fig. 6.3 Topology diagrams at the various hierarchical levels.

AD AD ADADAD

PCR

PSR

ACR

PSQ

+-+

+-

+-

+-

Q

AD AD ADADAD

PCR

PSR

AD AD ADADAD

PCR

PSR

PCQ

+-+

+-

+-

+-

E'

C'B'

ADBAD

EAD

CAD

BAD

EAD

CAD

Fig. 6.4 Active module (AM) with the ‘distributed’ topology for modules PSR/PCR and ‘star’ topology for PSQ/PCQ. The splitting and combing modules are represented with the transmission line sections. The active devices (AD) are configured here in a common-base topology. The first and last transmission line sections of the splitting modules PSR and combining modules PCR, respectively, are depicted dark-shaded as they are only there for modeling purposes and will not be implemented in the real design.

38

As observed in Fig. 6.4, within an active cell (AC), the splitting module PSR consists of the transmission line sections connected the active devices’ (AD) inputs, the emitter ports in this case (common-base configuration). In a similar way combining module PCR connects to the active devices’ (AD) outputs, the collector ports. The ground references of the active devices (AD), the base ports, are connected to a distributed ground, which connects at the ends to the local grounds of the splitting and combining modules PSQ and PCQ. The distributed grounds are explicitly modeled to include the impact of the imperfect grounding in an accurate way, as discussed in section 3.4.2. When the active devices (AD) would be configured as common-emitter, the splitting module PSR would connect to the active devices’ (AD) base ports, the combining module PCR would still connect to the active devices’ (AD) collector ports, and the distributed ground would be connected to the active devices’ (AD) emitter ports.

PIN

RPIN

R

Q

AD

AD

AD

ADG

PSQ

+-+

+-

+-

+-

PCQ

+-+

+-

+-

+-

RPIN

RPIN

RPIN

PIN

AD

AD

AD

PIN

AD

AD

AD

AC

Fig. 6.5 Modeling of AM, including coupling effects. The active device group (ADG) comprises multiple active cells (AC). The coupling effects that exist for this active module (AM) are: 1. at active cell (AC) level, EM-coupling between the splitting (PSR) and combining module (PCR); 2. at active module (AM) level, EM-coupling between the different active cells (AC), caused by their splitting

(PSR) and combining modules (PCR); 3. also at active module (AM) level, electrical coupling between the multiple transmission paths within the

splitting and combining module PSQ and PCQ. Assumed is that the coupling of the active devices (AD) themselves to other modules is negligible compared with the first two mentioned coupling effects [87]. Due to these coupling effects the active module’s (AM) model cannot be easily scaled in the Q-direction. In contrast to the Q-direction, in the R-direction the models for the splitting and combining modules PSQ and PCQ at active cell (AC) level are easily scaled for an increasing number of inputs or outputs, as no EM or unintended electrical coupling between the multiple transmission line sections within these modules is assumed. This includes the electrical coupling via the substrate, which is considered to be negligible compared with the intended electrical coupling via the splitting and combining modules PSR and PCR.

As mentioned in the introduction of this chapter, a passive structure comprising the relevant splitting and combining modules can be characterized by an EM-simulator to incorporate all the relevant coupling effects [87], [88], however, this is time-consuming. A different (scalable) approach that can be used for modeling of the ‘distributed’ type of splitting and combining modules as PSR and PCR (see Fig. 6.4) is to use a sliced model [89]-[91],

39

which includes the first listed coupling effect: the EM-coupling between the splitting (PSR) and combining module (PCR) at active cell (AC) level, using coupled transmission line sections (passive slices).

The metal structures forming these splitting and combining modules are for a silicon technology normally more complex compared to a III-V compound technology, such as GaAs technology, as these metal structures consists commonly of more (stacked) metal layers [92] (see Table 2.3) and are denser. Moreover, in the used NXP QUBiC4 SiGe:C technology no ground plane is available below the substrate and hence the ground return path needs to be explicitly included in the structure, whereas in the GaAs technology such a ground plane is available, as explained in section 2.2.2, BEOL Passives. Therefore, to accurately model the passive slices in the QUBiC4 SiGe:C technology over frequency, it is desirable to make use of an EM-simulator.

However, the 2nd listed coupling effect is not included with this approach; the EM-coupling between the different active cells (AC) at active module (AM) level, caused by their splitting (PSR) and combining modules (PCR). Therefore, to incorporate all the listed coupling effects, the modeling approach of Fig. 6.5 is adopted where the passive interconnect networks (PIN) include the discussed coupling effects between the splitting (PSR) and combining modules (PCR) at active cell (AC) and at active module (AM) level (the 1st and 2nd listed module coupling effects). The resulting PIN has nine ports, three inner ports and six outer ports, for each value of Q. The three inner ports result as the active device (AD) only counts three ports (B, C, E), see Fig. 6.4. The PIN network has therefore 9*Q ports, as shown in Fig. 6.6 on the left, and is used multiple times along the R-direction.

Due to the coupling between the active cells (AC), the outer located active cells (AC) could be affected differently by the coupling with the surroundings than the inner located active cells (AC) and hence different operation can result between those cells [88], even at equal excitation of the active cells (AC). At a small number of Q, the ratio of the outer active cells (AC) versus the inner active cells (AC) is relative large and hence the outer active cells (AC) have a relative large impact on the amplification module’s (AM) overall performance. Adding an additional active cell (AC) in this case will not result in performance scaling in a proportional way due to the differences in operation. However, when the value of Q increases the impact of the outer active cells (AC) on the overall performance reduces and for some value of Q the performance will be mainly determined by the more equally operating inner active cells. The threshold value for Q when this is occurring is indicated with Qth. Adding an additional active cell (AC) in this case will result in performance scaling in an almost proportional way as almost all of the active cells (AC) operate equally. Hence, instead of characterizing a new PIN network, the addition of an extra active cell (AC) can be accounted for by adding a passive network called RPIN that is the averaged version of the PIN network at value Qth. Actually, for the cases when Q Qth, the averaging allows to model the PIN network with multiple, equal, RPIN networks as shown in Fig. 6.5, which are extracted at Qth. Adding an active cell (AC) means now simply adding an RPIN network together with an active device (AD).

Averaging of the PIN network for a given value of Q is expressed in y-parameters with:

, = 1 , (6.1)

with YPIN,Q representing the even-mode y-parameters of the PIN network at the value Q. The Q-value of averaging is called Qavg. The RPIN network has only nine ports and the mapping of the 9*Q port PIN network to the 9 port RPIN network under the even-mode excitation condition is visualized in Fig. 6.6.

To determine the value of Qth, multiple PIN networks for different values of Q are characterized and subsequently the RPIN networks for the corresponding Q-values are extracted with (6.1). The y-parameters of the different RPIN networks should now be compared for different Q-values and the value for Q from which on the differences in y-parameters become negligible results in the threshold value Qth. However, to have better understanding what these differences between the various extracted RPIN networks mean for the active module’s (AM) performance, a better approach would be to compare the differences between the combinations of RPIN networks and active devices (AD). The performance of such an active device group (ADG), as indicated in Fig. 6.5 in the red box, is then compared for the different obtained RPIN networks by means of the active device group’s (ADG) two-port even-mode s-parameters.

This is investigated now for a specific layout example. The spatial orientation of the multiple active devices (AD) in the Q-topology direction can be with their long- or short-side aligned with this direction. For the sake of conciseness only the short-side alignment case is discussed here, but the approach is also applicable to long-side

40

Q-direction aligned active devices (AD). The used layout example is shown in Fig. 6.7 with the connections to one active device (AD) depicted.

RPIN

Cin

Ein

CAD Cout

EAD

BADBin

Eout

Bout

Cin

Ein

CAD Cout

EAD

BADBin

Eout

Bout

Cin

Ein

CAD Cout

EAD

BADBin

Eout

Bout

PIN

Cin

Ein

CAD Cout

EAD

BADBin

Eout

Bout

Fig. 6.6 Mapping of 9xQ port PIN network to obtain the 9-port RPIN network.

Fig. 6.7 Layout example of the passive interconnect network (PIN). The short-side of the active device (AD) is aligned in the

Q-direction.

The coupling in the Q-direction impacts the performance also when scaling in the R-direction. Hence, an active device group (ADG) of 8x1 (QxR) and of 1x4 (QxR) are selected to observe the coupling’s impact towards both directions of scaling (Q and R). Fig. 6.8 shows the resulting simulated two-port even-mode s-parameters in the frequency range from 1 to 100GHz for the 8x1 active device group (ADG) using RPIN networks averaged at Q equals 1, 4, 10 and 20 (see (6.1)). Fig. 6.9 shows these s-parameters for the 1x4 active device group (ADG). In both cases the active devices (AD) are configured as common-base. Both figures show that the s-parameters converge when the Q-value of averaging (Qavg) is increased, as expected. The s-parameters for Qavg equals one differ the most in respect to the other Qavg values as within the corresponding PIN network no inter-module coupling is experienced from other active cells (AC) at all. The differences in s-parameters for Qavg equal to 4, 10 or 20 are small, which sets Qth to 4. Therefore, the approach shown in Fig. 6.5 employing multiple compact RPIN networks is sufficient to model the AD scaling behavior in the Q- and R-direction for this specific example 4 (Q th). Under this condition the performance of the active device group (ADG) scales approximately linear in the Q-direction.

41

Fig. 6.8 Comparison of the simulated 2-port even-mode s-parameters of a 8x1 (QxR) active device group (ADG) in common-base configuration using different RPIN networks averaged at Qavg=1,4,10,20.

Fig. 6.9 Comparison of the simulated 2-port even-mode s-parameters of a 1x4 (QxR) active device group (ADG) in common-base configuration using different RPIN networks averaged at Qavg=1,4,10,20. The remaining coupling effect to discuss now is the coupling, also at active module (AM) level, between the multiple transmission paths within the splitting and combining module PSQ and PCQ (the 3rd listed coupling effect). The ‘star’ topology splitting/combining modules PSQ/PCQ are implemented by a tapered microstrip line (MSL) structure using two metal layers on top of each other, as shown in Fig. 6.10. As the multiple transmission paths within each module are in the same fully filled metal plane, they inherently couple to each other and hence the realization of an easily scalable model as a function of the number of inputs/outputs becomes more difficult. Therefore, to characterize these splitting and combining modules’ performance as function of the number of Q, for several numbers of outputs (inputs) (4, 10, 20), ‘star’-topology structures are EM-simulated, under the assumption of (approximately) even-mode operation, to obtain their even-mode s-parameters.

42

Fig. 6.10 Active module’s splitting/combining module implemented as tapered microstrip-line structure using two metal layers

on top of each other. At power module (PM) level, the modeling approach as depicted in Fig. 6.11 is adopted when using a cascode

topology. This can be seen as two active modules that are cascaded with the splitting and combining modules in between removed, with active module AM1 configured as common-emitter and AM2 configured as common-base. Considering the topology diagrams shown in Fig. 6.3, this approach is used both for cascoding of active cells (H=2, S=1) as well as cascoding of active modules (H=1, S=2). The impact of the layout interconnect in between the common-emitter and the common-base active cells is assumed to be negligible. Due to the cascoding the bases of the common-base devices may not be directly connected to ground. Hence, the modeling of the common-base active module (AM2) within a cascoded power module (PM) differs in two aspects with the modeling of the (stand-alone) common-base active module (AM) shown in Fig. 6.5: 1) Decoupling capacitors need to be added across the bias source, so from the bases to the local grounds. 2) Local ground paths need to be added and included within the RPIN networks as the bases are not grounded anymore. These are modelled in Fig. 6.11 as the lower transmission line paths within the RPIN networks.

To allow easy scaling of this power module (PM) in the R- and Q-direction the number of R and Q are kept the same for both active modules. This means that ratio of the emitter areas of an active device (AD) of AM1 and an active device (AD) of AM2 are scaled with the ratio of their (near)-optimum current densities (see Fig. 5.1 ).

An active cell (AC) can now be seen as the combination of the active devices of active module AM1 and AM2 both having an equal value for R, as indicated in the dashed box in Fig. 6.11. The active cell (AC) for R equals one is defined as the reference cell for this cascode topology comprising one active device (AD) for each active module (AM) with their RPIN networks extracted at Qth. This reference cell will be scaled up as a function of R to form the active cell (AC). This is similarly as was done for a power module (PM) comprising only one active module (AM), as was shown in Fig. 6.5. Also in that case the reference cell is defined as the active cell (AC) for R equals one.

43

R

Q

PSQ

+-+

+-

+-

+-

PIN

RPIN

AD

AD

AD

RPIN

RPIN

RPIN

PIN

AD

AD

AD

PIN

RPIN

AD

AD

AD

RPIN

RPIN

RPIN

PIN

AD

AD

AD

AC

PCQ

+-+

+-

+-

+-

R

AM1 AM2

E'

C'B'

ADBAD

EAD

CAD

BAD

EAD

CAD

ADG Fig. 6.11 Modeling approach for cascode topology. For the modeling of the common-base active module (AM2) base capacitances and local ground paths are added compared with the (stand-alone) modeling of the common-base active module from Fig. 6.5.

At PA module level, no intra-module coupling is expected, for two reasons: 1) the physical distance between the modules increases, which reduces EM coupling; 2) CPW transmission lines are used here due to the increased available area at this level compared to lower levels. CPW lines are self-shielding and therefore coupling from these lines is negligible.

6.2 Topology Design The selection of the PA topology and the module options are discussed in this section, starting with the design for

the power and gain improvements functions. The three available hierarchical levels using splitting/combining modules (R, Q, N), shown in Fig. 3.1, with their

module topologies are selected based on the following considerations: at an increasing number of active blocks that need to be combined, the physical distances between the active blocks increase. Therefore, to obtain the desired even-mode operation, splitting/combining modules are required which operate more symmetric to cope with the increased electrical distances between the active blocks. However, using a more symmetric splitting/combining module inherently results in a larger occupied splitter/combiner area. Moreover, in the process technology only a 2D-planar distribution of active blocks can be applied.

These considerations resulted in the three levels with the first level, the R-level, mapped in the horizontal spatial direction using the ‘distributed’ splitting/combining topology to save area, as shown in Fig. 6.4. This topology has an asymmetric nature. However, as the electrical distance between the active blocks is relatively small this will manifest itself only in asymmetric active block performance for a larger number of active blocks.

The second level, the Q-level, is mapped to the vertical spatial direction using the ‘star’ splitting/combining topology, again for area saving considerations. This topology has a more symmetric nature than the ‘distributed’ topology and hence asymmetric active block performance will result also here only at larger electrical distance between the active blocks. The R- and Q-level form together a 2D-planar distribution at the lowest level, as shown in Fig. 6.4.

44

The third level, the N-level, is mapped to the vertical spatial direction using the ‘binary tree’ splitting/combining topology to obtain symmetric operating active blocks, even at large electrical distances between the active blocks. Adding here next to the N-level an additional level mapped to the horizontal spatial direction would require multiple large-sized symmetric splitting/combining modules and is therefore not selected. As a ‘binary tree’ combiner is inherently symmetric, the N-level combining remains symmetric, regardless of the electric distances between the inputs. Hence, these three levels should be sufficient to obtain watt-level output powers while ensuring proper symmetric operation of active blocks at each splitting/combining level. The M1-MK-1 levels at the inter-stage networks (ISN) are consequently also mapped to the vertical spatial direction and are using also the ‘binary tree’ topology in the case that MK-1<N and for Mk-1<Mk with k<K (so when they are splitting networks), for the same reasons as mentioned at the N-level. The splitting and combining modules within the PA module (PSM, PCN, ISN1-ISNK-1) will also perform impedance matching using additional matching components.

Applying cascoding at a lower level, by cascoding active cells (AC) in the topology direction H, results in not having the multiple common-base devices connected together at their emitters as occurs at cascoding at a higher level, within a power module (PM) in the topology direction S. Cascoding at the lower level (H-direction) is beneficial when the potential current collapse due to a non-uniform temperature distribution becomes an issue [96]. For this case, separate connections between the common-emitter and common-base active cells (AC) are required, in contrast to cascoding within a power module (PM) where only one (broad) connection between the two active modules (AM) is required.

The cascading of amplification modules to improve gain is applied at PA module level, the highest level, in the topology direction K. Cascaded blocks need in general their own input and output biasing signals. Cascading on the highest level results therefore in a minimum number of biasing networks. The option to select the values for the number of parallel drivers stages, Mk, is included such to have the freedom regarding the number of the drivers’ output biasing networks to insert, as discussed in section 5.4.

The topology design for the biasing and stabilization functions is now discussed, knowing the type of splitting and

combining modules used. The splitting and combining modules within the PA module (PSM, PCN, ISN1-ISNK-1) are of the type ‘binary tree’ and allow insertion of the collector biasing for the power modules, similar as was shown in Fig. 5.4. A main concern for insertion of the collector biasing is to keep the contribution to odd-mode operation small. Therefore, for power module PMK off-chip collector biasing (Fig. 5.4, reference plane ‘D’) is selected and for power modules PM1-PMK-1 on-chip collector biasing at reference plane ‘B’ or ‘C’ will be selected. Off-chip collector biasing allows also using components with higher Q-factors. Lumped inductors will be implemented at the on-chip collector feed networks as they consume smaller area compared to a transmission line stub. These will be included in the design of the inter-stage networks in the next section. Each on-chip collector biasing inductor is accompanied by a large bypass capacitance to improve LF-stability, as discussed in section 5.5.

The base biasing and stabilization networks are inserted per active module (AM) to reduce the total area consumed by these networks such that the spacing between the parallel active devices (AD) can be kept to a minimum.

Therefore, considering the function matrix shown in Table 4.1, the biasing collector function is inserted at system-level, whereas the biasing base function is inserted at sub-level. The stabilization functions are inserted at system-level (integrated with the collector biasing) and at sub-level (integrated with the base biasing).

6.3 Parameter Design In this section the parameter design for the power and gain improvement functions together with the biasing and

stabilization functions will be discussed. Having defined the topology for the power and gain improvement functions in the previous section, values need

to be assigned to the topology parameters at each hierarchical level, see Table 4.1. The topology parameters are: at system level: N, K, M1-MK-1 at sub-level 1: S at sub-level 2: H,Q at sub-level 3: R

45

The parameters S, Q, R, H are available within each power module (PM) and can be assigned different values for each PM.

The flowchart depicted in Fig. 6.14 summarizes the parameter design flow. The topology block diagrams of Fig. 3.1 and Fig. 3.2 are repeated in Fig. 6.12 and the even-mode equivalent diagram of Fig. 3.2 is depicted in Fig. 6.13 to support the explanation of the design flow. At PA module level, the splitting/combining modules and the inter-stage networks (PSM, PCN, ISN1-ISNK-1) are all called ‘coupling networks’ (CNW) in the design flow for ease of explanation, as shown in Fig. 6.12 and Fig. 6.13. The parameter design flow is explained step-by-step in the coming sections, without loss of generality, using a design example. The design example is discussed in more detail in the next chapter and is targeting 1W of output power at 30GHz with a minimum gain of 20dB and to be implemented in a 0.25um SiGe:C BiCMOS technology.

+

R

PCR

PSR

AD AD AD

AC2

+

Q

PSQ PCQ

AM

SAM1 AM2

PM

AD

EDCE EDCB

AC1

AC1


S=1: CES=2: Cascode

H=1: CEH=2: Cascode

+

R

PCR

PSR

AD AD AD

AC1

AC2

AC2

H

.. +ISN2

M2CNWK

NPSM PMKISN1

M1PM2PM1

PA

K

M1 M2 M2 M3

PCN

CNW2CNW1CNW0

PBKPB2PB1PB0

Fig. 6.12. Topology diagrams at the various hierarchical levels. At PA module level, the splitting/combining modules and the inter-stage networks (PSM, PCN, ISN1-ISNK-1) are all called ‘coupling networks’ (CNW) for ease of explanation of the design flow.

PMKPM2PM1

PDC,K ZL,PM,K

PO,PB,K

Zin,KPDC2 ZL,PM2

PO,PB2

Zin2PDC1 ZL,PM1

PO,PB1

Zin1Zin0

Pin

Zload

PBKPB2PB1PB0CNWKCNW2CNW1CNW0

Fig. 6.13 Even-mode equivalent diagram on system level (PA module) showing the multiple power blocks (PB), which are a combination of a power module (PM) and a coupling network (CNW). Power block PB0 comprises only coupling network CNW0.

46

Select device topology and reference cell of current PM

Set PBK as current power block (k=K):

PBcur=PBK

Determine scaling behavior in R-direction of current PM

{S, H}

{N, Mk}

Determine the value of Q of current PM{Q}

Determine performance CNW of current PB

Output power of current power block ok?

PA gain ok?

PBcur=PBk-1

§ 6.3

Another number of power modules for current PB?

Select most promising sets for current PB

Determine current PA performance

Yes

No

Yes

No

Yes

Yes

No

Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

Step 7

Step 8

Step 10

Step 9

Step 11

Step 12

Select number of power modules

Determine current PB performance

Step 14Set K

PAE-Gain decoupling?

No

Step 13

Fig. 6.14 Flowchart of parameter design

47

First, the global design flow at PA module level will be discussed. Considering Fig. 6.13 and Fig. 6.14, the design flow is in the reverse direction, starting with the design of the combination of power module PM3 and combining module PCN. Such a combination of a power module with its output module, in this case a combining module, is called a power block (PB). A power block is indicated in the red box in Fig. 6.13 and its related steps in the design flow are also indicated with a red box in the flowchart (Fig. 6.14). A specific power block (PB) is indicated with index k. The performance of a power block can be compared for different numbers of power modules, so for power block PBK this is for different values for N. This is indicated with the blue arrows in Fig. 6.13 and Fig. 6.14. After the design of a power block the preceding power block is considered, ending with power block PB0, which corresponds with the splitting module PSM. These steps are indicated with the green arrows in Fig. 6.13 and Fig. 6.14.

The impact of the various power blocks (PB) on the PAE can be considered with the following equation (see Appendix B. for the derivation):

= 1, , , 11 1

(6.2)

with GPM,k and PM,k denoting the power gain and output efficiency of power module PMk and GCNW,k denoting the power gain of coupling network CNWk. GPA denotes the power gain of the total PA module. Assuming a GPA value of larger than about 15dB, (6.2) can be approximated by: 1, ,= ,= +1=1 1

(6.3)

From (6.3), one can observe that the contribution of the output efficiency of power module PMk PM,k) is reduced with the factor GCNW,kGPM,k+1 compared to the contribution of the output efficiency of power module PMk+1 PM,k+1).. This justifies the reverse direction flow as the last power block (PBK) has therefore the most impact on PAE and also directly impacts the output power with the power gain of combining module PCN (GCNW,K). As an example, the PA module’s PAE and power gain are plotted in Fig. 6.15 as function of the gain of the power modules and the gain of the inter-stage/splitting modules for a PA module comprising only two power modules PM1 and PM2 (K=2) using (6.2). Assumed is that both power modules have the same power gain (GPM=GPM1=GPM2) and the same output PM PM1 PM2), the latter having a fixed value of 42%. The power gain of the interstage-network (GCNW1) and splitting module (GCNW0) are set equal (GCNW0,1=GCNW0=GCNW1) and the power gain of the combining module (GCNW2) is set to -2.0dB. These fixed values can be expected, as will be discussed later on in this section. The relative contribution of power block PB1 towards the PA module’s PAE is also depicted in Fig. 6.15 by determining the contribution of the term of the summation related to PB1 in (6.2) to the total PAE, so the summation term of k=1. Considering Fig. 6.15 right, for relatively low values of the power modules’ gain (GPM) and larger values for GCNW0,1, the impact of power block PB1 towards the PAE is considerable and cannot be neglected, as can also be observed from the PAE plot (Fig. 6.15 left). The target power gain of 20dB is indicated in the gain plot with the red solid line, putting a lower limit on the required combination of GPM and GCNW0,1.

48

Fig. 6.15 PAEPA, GPA and the contribution of PB1 to the PA module’s PAE as function of GPM for several values of GCNW0,1 for

PM=42% and GCNW2=-2.0dB. Two cascaded power modules are used here (K=2). Continued is now with the explanation of the flowchart step-by-step: Step 1: Initialization, select last power block (PB) Started is with the design of the last power block, PBK, as just is explained, so k equals K. Step 2: Select device topology and the reference cell to-be-scaled of current power module (PM)

The design of a power block is discussed now, with power block PBK taken as example. For the other power blocks a similar approach can be followed. First, in this step, the device topology used within the current power module (PM) needs to be selected as common-emitter or cascode, which relates to the topology parameters S and H. The reference cell for both device topologies will be extracted such that their performance can be compared and to determine subsequently, in step 3, the performance degradation as function of scaling in the R-direction. For the parameter design it makes no difference if cascoding of active cells (H=2, S=1) is applied or cascoding of active modules (H=1, S=2), for both situations the modeling approach shown in Fig. 6.11 is used, as discussed in section 6.1.2.

For the common-emitter configuration a reference cell with a low-voltage type active device (AD) having one finger (emitter stripe) with minimum emitter width and maximum emitter length is selected, for the reasons mentioned in section 5.1, which results in an emitter area of 0.4x20.4um.

The reference cell for the cascode configuration comprises both a common-emitter and a common-base active device (AD) and the ratio of their emitter areas is set by their (near)-optimal current densities. Using a low-voltage (LV) and high-voltage (HV) device for the common-emitter and common-base device, respectively, the resulting current density for the HV-device is set just below peak ft, fmax 2 and for the LV-device this is set to

2, see Fig. 5.1. This results in a device area ratio between the CB and CE device of 2.5. Although the LV-device’s current density could be increased to operate more towards peak ft, fmax, the profit in power gain (fmax) is not that much, while the device area ratio would increase, leading to an increase in the LV-device’s emitter-area, which is undesirable as it lower the device’s input impedance. Moreover, realizing the required increased emitter area by increasing the LV-device’s emitter length would lead again to a (small) reduction in ft, fmax as shown in Fig. 5.2. The common-base device has an emitter area of 0.4x20.4μm and the common-emitter device an emitter area of 0.4x8.2μm. For the same reasons as at the common-emitter configuration, the number of fingers and the emitter dimensions per finger are set.

49

The DC-currents for (near) optimal peak fmax operation and the input and output impedances for both reference cells are depicted in Table 6.1. These parameters are used in the design of the base networks for biasing and stabilization purposes, which will be discussed next.

Table 6.1 Common-emitter (LV) and cascode (LV+HV) active device reference cells’ DC-currents for (near) optimal peak fmax

operation CE (LV) Cascode (LV+HV) Ic,fmax (mA) 20.4 6.5 Zin 8-j4.6 22-j44

R

RPIN

AD AD

RPIN

AD AD

R

RFin

RB1/RVB1

Csh1*R

Rsh1/R

Rser1/R

VB2

Rser2*(2/R)

CB2*(R/2)

VB2

DC+RFout

RB2*(2/R)RB1,tot=(RB1+Rsh1+Rser1)/RRB2,tot=RB2/R

RB2*(2/R)

CB2*(R/2)

Rser2*(2/R)

Fig. 6.16 Cascode active cell (AC) with the biasing and stabilization base networks from Fig. 5.5 inserted. The situation for the reference cell is equal to the case with R=1. The used RPIN networks are averaged at Q=10 (see (6.1)).

For both reference cells, the required component values of the base networks need to be determined such that they operate in the stable-operating-area (SOA) regarding electro-thermal breakdown and show no electrical instabilities (oscillations), as discussed in section 5.5, Stabilization. The cascode active cell (AC) with their base networks for stabilization and biasing are shown in Fig. 6.16. The situation for the reference cell in this figure is equal to the case with R=1. For the common-emitter reference cell only the common-emitter device with its base network would remain. Although the base biasing and stabilization networks will be finally inserted per active module (AM), as mentioned in the topology design in section 6.2, these networks are inserted in the modeling approach shown in Fig. 6.16 per active cell (AC). This is done to include already the impact of these networks before scaling the active cells in the Q-direction towards active modules (AM), hereby introducing a (small) error in the modeling as the impact of the splitting and combining modules PSQ and PCQ is neglected for this moment. First the impact of the base resistance on the SOA is investigated for both reference cells and subsequently its impact on the electrical stability.

The common-emitter reference cell’s SOA is determined by simulating the IV-curves for different values of the device’s total base resistance RB1,tot,. For the cascode reference cell’s this is done for different values of the common-base device’s total base resistance RB2,tot, meanwhile keeping the common-emitter device’s base resistance RB1,tot in Fig. 6.17 and Fig. 6.18. The SOA is defined by the points on the curves where snap-back occurs, i.e. the point on the curves where dIC/dVC goes to infinity [50].

Fig. 6.17 shows for the common-emitter cell that the SOA reduces when RB1,tot is increased due to the impact of the generated avalanche current flowing out of the common-emitter’s base. Fig. 6.18 shows for the cascode cell a similar reduction of the SOA when RB2,tot is increased. However, the voltage-range of this SOA is much larger due to the use of the high-voltage device as common-base device.

For large-signals containing an RF-component next to the DC-component, the SOA regions obtained from Fig. 6.17 and Fig. 6.18 are pessimistic. The RF-impedance presented to the common-emitter cell’s base is likely to be conjugate matched with the cell’s input impedance. This input impedance (see Table 6.1) is quite low-ohmic at mm-wave frequencies and hence also the presented RF-impedance to the base will be. For the cascode cell, the RF-impedance presented to the common-base device’s base is determined by Rser2 and CB2 (Fig. 6.16) and is usually low-ohmic. With a low-ohmic RF impedance the generated RF avalanche current will induce a low-valued RF-voltage at the base, which is beneficial for electro-thermal stability.

50

Fig. 6.17 Common-emitter cell’s DC IV-curves to determine the SOA for different values of RB1,tot: RB1,tot=0 (blue), RB1,tot=500 (red), RB1,tot=1k (green). Base voltage VB1 ranges from 700mV to 900mV in steps of 20mV.Tamb=27°C and self-heating of the devices is turned on.

Fig. 6.18 Cascode cell’s DC IV-curves to determine the SOA for different values of RB1,tot: RB2,tot=0 (blue), RB2,tot=1k (red), RB2,tot=2k (green). RB1,tot=0 . Base voltage VB1 ranges from 700mV to 900mV in steps of 20mV.Tamb=27°C and self-heating of the devices is turned on. Moreover, the thermal time-constant of the devices is much larger than the time-constant of the RF signal and hence for thermal operation the average dissipated power of the device can be considered, instead of the instantaneous power dissipation. The average power dissipation equals: = + = 1 1 <

(6.4)

with the inequality on the right side . So for thermal operation it is sufficient to considerer only the DC-values of the voltages and currents (PDC=VDC*IDC). The SOA for large-signals will therefore be extended compared to the DC IV-curves of Fig. 6.17 and Fig. 6.18. In case the impact of the RF-avalanche current can be completely neglected (zero-valued external base impedance) it is sufficient to select the DC-values of the operating voltages and currents to be within the SOA regions predicted by the DC IV-curves.

Moreover, the impact of self-heating is much less noticeable at the cascode cell compared to the common-emitter cell by the smaller dIc/dVc slopes at relative low collector-voltage values. This is due to the fact that the cascode’s common-emitter device, which acts as the current source, is dissipating not much DC power compared to its common-base device and hence will heat up less.

The temperature behavior of both reference cells is further investigated by simulating the DC IV-curves as function of temperature for different values of the common-emitter’s base resistance RB1,tot, as this device acts as

51

the current source at both reference cells. The temperature is swept from 25°C to 100°C in steps of 25°C. Fig. 6.19 and Fig. 6.20 show the results for the common-emitter and the cascode reference cell, respectively, and a reduced variation in collector-current over temperature is observed for both reference cells when RB1,tot is increased as this acts as base-ballasting. The collector-current for the common-emitter cell drifts much more when temperature is increased compared to the cascode cell, as just was discussed. Hence, the common-emitter cell needs a relatively higher base resistor for ballasting, which is not beneficial for its SOA.

Fig. 6.19 Common-emitter cell’s DC IV-curves to determine the thermal behavior for different values of RB1,tot: RB1,tot=0 (blue), RB1,tot=500 (red), RB1,tot=1k (green). The temperature is swept from 25°C to 100°C in steps of 25°C. The base voltage VB1 is set fixed for each RB1,tot value.

Fig. 6.20 Cascode cell’s DC IV-curves to determine the thermal behavior for different values of RB1,tot: RB1,tot

RB1,tot B2,tot B2,tot The temperature is swept from 25°C to 100°C in steps of 25°C. Thermal coupling between both devices is not included. The base voltage VB1 is set fixed for each RB1,tot value.

Having considered the impact of the base resistances on electro-thermal stability to prevent breakdown, next point is to determine the components values of the base networks (Fig. 6.16) for both reference cells to obtain unconditional stable cells using the k-factor method (see section 5.5). The required components values for both reference cells are depicted in Table 6.2 and the resulting k-factors depicted in Fig. 6.21 show unconditional stable behavior.

52

Table 6.2 Component values for the base networks of both reference cells for unconditional (electrical) stable operation. Component values base networks

Common-emitter reference cell

Cascode reference cell

RB1 Rsh1, Csh1 Rser1 RB2, CB2 - Rser2 - 5 RB1,tot RB2,tot - 1000

Fig. 6.21 Stability factor Kf as function of frequency for the common-emitter and cascode reference cell after applying electrical

stabilization. Relating the total required base resistances for electrical stability to the SOAs of Fig. 6.17 and Fig. 6.18, shows that for the common-emitter cell the required RB1,tot DC-voltage of about 1.5V when operating at the (near) optimal current for fmax (20.4mA), hereby assuming that the impact of the RF-avalanche current can be neglected. Similarly, for the cascode cell the required RB2,tot value of

-voltage of about 5V when operating at the (near) optimal current for fmax (6.5mA).

The large-signal performance for both reference cells is now determined using the base networks component values of Table 6.2 and the results are shown in Table 6.3 after applying load-pull in the circuit simulator at the operating point for optimum PAE. Comparing both, their output powers are comparable as well as their output

o) values. The power gain Gp of the cascode reference cell is 8.5dB larger, which explains the larger-valued PAE for this cell. The almost equal output power values (0.4dB difference) are explained to the first order by the fact that the ratio of the resulting DC-currents Icc of both reference cells is more or less equal to the inverse ratio of the DC-voltages Vcc. The large voltage headroom of the cascode reference cell results in a larger-valued Zopt compared to the common-emitter reference cell, which results finally in a smaller impedance

As a conclusion, the cascode reference cell is the preferred cell to continue with, as all the parameters show comparable or better values.

Table 6.3 Comparison of common-emitter (LV) and cascode (LV+HV) active device reference cell characteristics after applying stabilization around the operating frequency. CE (LV) Cascode (LV+HV) Vcc (V) 1.5 5 Vb (V) 0.76 0.76 Po (dBm) 11.5 11.9 Gp (dB) 7.4 15.9 PAE(%) 36.4 44.6

53

o (%) 44.5 45.8 Icc (mA) 21.1 6.8 Zopt 36.1+j18.8 83.3+j176.5 Zin 10.9-j22.3 22-j46 S12 (dB) -22.5 -44.4

Step 3: Determine scaling behavior in R-direction of current power module (PM)

The performance degradation as a function of scaling in the R-direction is now investigated for the cascode configuration for the device layout alignment configuration of Fig. 6.7, so with the short-side aligned in the Q-direction. For the common-base active devices (AD), each pair has their bases together such that an equi-potential base voltage results for each pair. This is important as these bases are AC-coupled to the local grounds and have a large impact on asymmetric operation between the active devices and hence this reduces the overall combining efficiency degradation, as discussed in section 3.5, in the R-direction. For the common-emitter active device (AD) it is of less importance to connect the bases together as here their emitters are connected to the local grounds. The results of the scaling of the reference cell as function of the number of R are shown in Fig. 6.22 after applying load-pull in the circuit simulator around the operating point for optimum PAE.

Fig. 6.22 Performance of the cascode active cell as function of R for R={1,2,3,4}.

Considering Fig. 6.22, above R=2 the output power remains almost constant despite of having more active devices (AD) and is contributed to the dynamic loading. To obtain more insights in this, the LMF values observed by each common-base active device’s (AD) output (so for each input of the combining module PCQ) within the cascode active cell (AC) are determined with (3.7) and depicted in Table 6.4 as function of the scaling in the R-direction. The input currents are determined at the active cell’s input power level such that all the elementary devices’ (ED) large-signal voltages and currents remain within their SOA.

54

Table 6.4 LMF values, decomposed in the fundamental input current and impedance, for each input of the combining module PCR, so for each common-base active device’s output (AD) within the cascode active cell (AC).

R LMF1 LMF2 LMF3 LMF4

|Ii,1|2 (μA2) Zin,1 |Ii,2|2 (μA2) Zin,2 |Ii,3|2

(μA2) Zin,3 |Ii,4|2 (μA2) Zin,4

1 1 -

- -

315 99.6+j195 - - - -

2 1.01 0.97 - - 300 105.8+j200.5 304 100.5+j195 - - -

3 1.1 1.06 -0.09 - 275 124.6+j158 271 121.8+j154.6 142 -20.4+j263.0 - -

4 1.08 1.05 -0.06 -0.04 255 132.6+j130.9 252 130.9+j126.3 108 -16.8+j268.5 103 -10.9+j261.6

At R=2, all the LMF values are equal or almost equal to one, indicating that both common-base active devices (AD) deliver the optimum power to the combining module PCR as the input currents and impedances of this combining module are all approximately the same. This is due to the fact that both bases are connected together. At R=3 and R=4, the LMF values of the first two active devices (AD) are again almost equal to one, however, the other active devices (AD) have even a negative LMF value, indicating that these devices observe a negative real part of the load impedance due to the dynamic loading. The main reason for the dynamic loading is the inequality in the base voltages of the common-base active devices (AD) caused by the distributed inductance of the splitting and combining modules PSR and PCR, connecting the bases. The resulting unequal base-emitter voltages cause asymmetry in the generated collector currents and hence the impedances differ, due to the dynamic loading.

Although the output power remains almost constant above R=2, the output efficiency and power gain in Fig. 6.22 are not degrading accordingly as the devices are operated in class-B and hence the DC-current and power gain are a function of the device’s input signal, in contrast to class-A operation. The performance difference between R=1 and R=2 is not much, hence R=2 is used further on, which results in an active cell (AC) output power of 15dBm with an output efficiency of 44.5% and a power gain of about 15.4dB, as shown in Table 6.5, which depicts the performance parameters of this active cell (AC).

Table 6.5 Performance parameters of cascode active cell at the selected R-value, R=2.

Cascode (LV+HV) @ R=2 Po (dBm) 15 Gp (dB) 15.4 PAE(%) 43.2

o (%) 44.5 Icc (mA) 14.2 Zopt 41.6+j88.3 Zin 11.3-j21

55

Step 4-5: Select number of power modules (PM) and determine number of active cells (AC) for current PM Linear scaling of the performance of the reference cells can be applied when Q Qth, as discussed in section 6.1.2.

Under this condition linear scaling rules can be applied for the performance of an active device group (ADG); such a group comprises multiple active cells (AC), as discussed in section 6.1.2. The linear scaling rules are: , = , , (6.5)

, = , , (6.6) = , (6.7)

, = , , (6.8)

, = , , (6.9)

with for PO,AC,ref , GP,AC,ref AC,ref, Zopt,AC,ref and Zin,AC,ref the parameter values obtained for the selected active cell (AC) with their values shown in Table 6.3.

Knowing the required Zopt for the active device group (Zopt,ADG), the impact of the combining module PCQ and

splitting module PSQ can be included. This is done by cascading the splitting and combining modules with the active device group’s (ADG) input and output, respectively. The resulting required load reflection coefficient of the combining module PCQ, which is the load reflection coefficient of the power module (PM), can be determined with:

, = ,, + (6.10)

with Sii, Sij the even-mode s-parameters of the combining module PCQ opt,ADG the optimum load reflection coefficient of the active device group (ADG). Similarly, the resulting input reflection coefficient of the splitting module PSQ, which is the input reflection coefficient of the power module (PM), can be determined with:

, = + ,1 , (6.11)

with Sii, Sij the even-mode s-parameters of the splitting module PSQ in,ADC the input reflection coefficient of the active device group (ADG).

Selecting a value for N, the number of power modules for the current power block PBK, and using (6.5) the required value for Q can be estimated by: = , , ,, , ,

(6.12)

with PO,PB,k,des the desired total output power of the current power block, CNW,k the (estimated) efficiency of the current power block’s coupling network and PO,AC,ref the output power of the selected active cell (Table 6.5). The impact of combining module PCQ is neglected in this. The target output power is set to 31dBm, which includes 1dB margin to obtain finally 1W (30dBm) of output power at measurement. E CNW,K as -2dB and using the results depicted in Table 6.5, then (6.12) results in:

56

= 12590.63 31.6 = 63.2

(6.13)

The outcome of (6.13) is used to determine the required Zopt,PM with (6.8) and (6.10) and subsequently this impedance is used as target in the design of the current power block’s coupling network (CNW), which is for power block PBK the combining module PCN. The design of this combining module is described next. Step 6-10: Determine performance of current coupling network (CNW) and check performance of current power block (PB).

Knowing now the required load impedance of the current power module, the next step is the design of the current coupling network, the combining module PCN. To obtain the combiner’s optimum design parameters for maximum output power targeting the power modules’ (PM) optimum load impedance, an exhaustive search optimization routine was implemented in Matlab. The impact of the combining module PCQ is also immediately included within this routine. The routine is based on an even-mode analysis of the combiner and uses models for the various matching components that are based on data extracted from the technology library or data extracted employing an EM simulator to improve modeling accuracy. An exhaustive search checks for all possible candidates if they satisfy the optimization goals and will therefore deliver a global optimum. The outcome will be independent of the initial starting point, which is in contrast to an iterative optimizer. The routine takes into account the constraints imposed by: 1) the required minimum transmission line length, which is determined mainly by the pitch between two successive stages; 2) the limited range of available component values; 3) the minimum metal width to prevent DC electro-migration. The pitch is determined by the size of the power module in the Q-direction or by the size of the required matching components of combining module PCN. The maximum value of both sets the pitch.

The optimization flow is as follows: first a matching topology is determined on forehand by considering the required combiner’s input impedance, the number of inputs and the required bandwidth. The discrete set of available component values for each cascaded subsection is then reduced by considering the pitch between two successive stages and the expected DC-current flowing through each section. A large data-set is then generated comprising all possible combinations for the subsections’ component values. Afterwards the exhaustive search is applied on this data-set and looks for the highest overall combining efficiency tot, targeting the power modules’ (PM) optimum load impedance, hereby using (3.6) in combination with (3.9) and (3.10).

The used matching topology is shown in Fig. 6.23 for an eight-way combining module as example and its even-mode equivalent circuit is shown in Fig. 6.24. An example of the impedance path on the Smith-chart for this matching topology is shown in Fig. 6.25. The series inductor Lo2 is inserted to reduce losses and area consumption and shunt inductor Lo4 is resonating out the output capacitance of the power module (PM).

57

TLo1

TLo0S

G

G

combining module PCN

TLo4

TLo3

TLo4

TLo4

TLo3

TLo4

Lo2

Lo2

TLo4

TLo3

TLo4

TLo4

TLo3

TLo4

Lo2

Lo2

TLo2

TLo2

TLo2

TLo2

ZL,PM,K

TLo1

Lo4

Co4

Fig. 6.23 Used matching topology shown as example for an eight-way combining module PCN, which combines transmission line

elements with series (Lo2) and shunt (Lo4) lumped inductors.

S

G

G

Z1/2, 1Z2/4, 2Z3/4, 3

ZL,PM3/8

Z0, 0Lo2/4Z4/8, 4

Lo4/8

Co4/4

ZA

Fig. 6.24 Even-mode equivalent diagram for the eight-way combining module PCN of Fig. 6.23.

Fig. 6.25 Example of the even-mode impedance path of the used matching topology for eight-way combining module PCN

depicted on a Smith-chart. Zas equals ZL,PM,K.

58

For several values of N, the performance of the combination of combining module PCQ and combining module PCN is determined. The required value for shunt inductor Lo4 can become quite small; e.g. for the eight-way combining module this value is in the range of 50-60pH and the related Q-factor for such an inductor value is about 12. For the combining module PCN, the estimated required shunt inductor Lo4 values and the corresponding Q-factor values are depicted in Table 6.6 for several values of N. The shunt inductor values are estimated by assuming that the impedance before the shunt inductance action takes place (impedance ZA, Fig. 6.24) is real-valued, similar as shown in Fig. 6.25, and that the shunt inductor’s finite Q-factor is not influencing the presented impedance value. Moreover, the impact of the combining module PCQ is neglected. The impact of the Q-factor of the shunt inductor Lo4 on the combining module’s efficiency can then be approximated with: = 11 +

(6.14)

with RA the resistance of the combining module before the shunt inductor action takes place, QLsh the shunt inductor’s Q-factor and Lsh the value of the shunt inductor. The ratio of RA and Lsh is almost constant as a function of the number of N, as increasing N e.g. with a factor two will increase the required Zopt,PM opt,PM) (6.10) with a factor two, when neglecting the impact of combining module PCQ. Consequently, both the required RA and Lsh will increase with a factor two. The shunt inductor’s efficiency Lsh as a function of its Q-factor is plotted in Fig. 6.26 for a fixed value of RA/ Lsh of 2.65, which is determined by the Zopt of the cascode reference cell. Table 6.6 Estimated required shunt inductor Lo4 values as function of the number of N, together with the inductor’s Q-factor at 30GHz. The used R an Q values at the power module (PM) are also shown. The impact of the finite Q-factor towards the presented impedance and the impact of the combining module PCQ are neglected in this estimation.

N R Q Zopt,ADC Lo4 (pH) Q-factor 4 2 16 2.6+j5.5 30 12 8 2 8 5.2+j11 60 17 16 2 4 10.4+j22 120 24

Fig. 6.26 Estimated efficiency of shunt inductor Lo4 as function of its Q-factor using (6.14) for RA/ Lsh=2.65

Fig. 6.26 shows that the estimated shunt inductor efficiency for N equals 4 is about -0.72dB and in the case that N equals 16 it is about -0.36dB, which is a difference of 0.36dB. So selecting a larger value for N leads to an increasing shunt inductor’s efficiency. However, on the other hand the inductor size increases, which has effect on the required pitch between two successive power modules (PM) and hence the minimum required transmission lines lengths. Therefore, asymmetrically shaped lumped inductors with their height smaller than their width can be beneficial. Creating a larger inductance by increasing only the inductor width will not lead to an increase of the required pitch and hence reduces the required minimum transmission line length compared to an inductor with equal height and width. An example of two inductors with different heights having about the same inductance

59

value of 106pH is shown in Fig. 6.27. The inductor on the left has a slightly higher Q-factor (Q=20.2) compared to the inductor on the right (Q=19.8).

The efficiency of the combination of combining modules PCQ and PCN is now determined for N equal to 4,8 and 16 and the results are shown in Table 6.7. In this table PC,Q,N expresses the combined efficiency of PCQ and PCN and the efficiency of combining module PCN is decomposed into the efficiency of shunt inductor Lo4, indicated with Lo4, and the efficiency of the transmission lines and series inductor Lo2, indicated with TL. The LMF values (3.6) are almost equal to one and are not shown here. The minimum required pitch is determined for N equal to 4 and 8 by the size of the power modules (PM), whereas for N equal to 16 this is determined by the size of the required shunt inductor Lo4.

Fig. 6.27 Inductors having same inductance value (~106pH) and almost same Q-factor (20.2 vs 19.8), but with different geometry. The inductors are implemented in the top metal layer (in blue) and have a poly shield (in red).

Table 6.7 Efficiency of combining modules PCQ and PCN for different numbers of N

N Lo4 (pH) pitch (μm) PC,N PC,Q(dB) PC,Q,N (dB) TL (dB) Lo4(dB)

4 28.75 200 -0.87 -1.11 -0.19 -2.17 8 57.5 120 -0.84 -1.0 -0.09 -1.93 16 110 120 -0.97 -0.76 -0.03 -1.76

Considering Table 6.7, the differences in PC,Q,N result mainly from the differences in the shunt inductor efficiency

Lo4. These shunt inductor efficiency values are lower than estimated with (6.14) and depicted in Fig. 6.26 as now the impact of the finite Q-factor towards the presented impedance and the impact of the combining module PCQ are not neglected. N equal to 16 shows the highest value for PC,Q,N, however, the estimated area consumption of its combining module PCN is about a factor two larger compared to the case when N equals 8 as the required pitch is the same. Hence, N=8 is selected for the number of power modules PMK as its PC,Q,N is only 0.17dB worse compared to the case when N equals 16. The resulting total output power of the power block PMK using N=8 is now: , , = , , @ , = (31.6 8 8) 0.64 = 31.1 (6.15)

which is sufficient as the target PA output power is 31dBm.

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Having obtained the output power of the current power block, the rest of the performance parameters (gain, PAE and input impedance) of the current power block need to be determined. To determine the power blocks’ gain the only thing remaining is to determine the power gain of the splitting module PSQ as the gain values of the other modules within the power block were already obtained in the previous steps. This is easily done as the input impedance of the active device group (ADG) (see Fig. 6.11) is known, which acts as the load impedance of the splitting module PSQ. Next, the power block’s input impedance, which equals the power module’s input impedance, can be determined with (6.11). With the power gain known, the PAE of the power block can be determined. The power block’s performance parameters are summed up in Table 6.8 together with the parameters for the power module PMK and the coupling network PCN (=CNWK). The parameter values refer to the even-mode equivalent values, as shown in Fig. 6.13. So, as an example, the power module’s (PM) output power refers to the total output power of the eight power modules together in this table.

Table 6.8 Performance parameters of the current power block PBK together with the performance of power module PMK and coupling network PCN (=CNWK). The parameter values refer to the (total) even-mode equivalent values, as shown in Fig. 6.13.

Performance parameter

PMK performance PCN performance PBK performance

Po (dBm) 23.9+9 31.1 31.1 GP (dB) 15.0 -1.93 13.1 PAE(%) 41 - 25.8

o (%) 42.3 - 27.1 ZL ( ) (3.7+j9.2)/8 - - Zin ( ) (1.1-j1.8)/8 (3.8+j9.4)/8 (1.1-j1.8)/8

Having discussed the design approach for the combination of the power module PMK with its coupling network,

the combining module PCN, these steps can be repeated in a similar way for the preceding combinations of power modules and coupling networks. For each of the coupling networks a suitable matching topology should be selected. Step 11: Determine current PA performance

Having obtained the performance of the current power block for different values of power modules, the current PA performance, i.e. the combined performance of the up to now designed power blocks, need to be determined. Referring to Fig. 6.13: , = , , (6.16)

, = , (6.17)

, = 1 1 11 ,

(6.18)

, = , (6.19)

With only power block PBK designed up to now, using (6.16)-(6.19) results in the current PA performance similar as shown in Table 6.8 for power block PBK.

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Step 12-14: Check if current PA gain is sufficient. Check if PAE performance can be decoupled from gain. Set total number of cascaded power modules (PM).

With the current PA performance determined, it needs first to be checked in step 12 if the current PA gain is sufficient to meet to specification. If this is sufficient, continued is with step 14. If the PA gain is not sufficient, in step 13 it needs to be checked if the gain and PAE can be decoupled, i.e. that the gain is sufficient large that its impact on the PAE can be neglected. When the latter is the case, the final PA module’s PAE can be predicted with good accuracy by the current PA’s PAE. Otherwise, the design of potential preceding power block(s) using the design flow should be considered and hereby returning to step 2, see Fig. 6.14.

Estimating the performance of the preceding power modules as having the same power module gain (15dB) and efficiency as power module PMK (42%), as shown in Table 6.8, Fig. 6.15 shows that the total PA module’s gain is likely to be sufficient when using two power modules as the required 20dB of gain is obtained, even when the power gains of the inter-stage module (CNW1) and splitting module (CNW0) are both -4dB. Moreover, the figure shows that the power gains of the inter-stage and splitting module have a fairly negligible impact on the contribution of the preceding power block (PB2) to the PA module’s PAE. For a power module gain GPM of 15dB, having a (worst-case) value for GCNW0,1 of -4dB results in the contribution of PB2 to the PAE of about only 7.4%, so the expectation is that the final PA module’s PAE can be predicted to be close to the value depicted in Fig. 6.15. The PA module’s PAE will accordingly be in the range of 24.4-25.4% for a GCNW0,1 range of -1 to -4dB, as show on the left in this figure. The design of the preceding power blocks can therefore be assumed less non-critical and hence there is no need for designing the preceding power block (PBK-1) within this parameter design flow. Hence, in step 14, the number of cascaded power modules (PM) to be used within the PA module, can be set to two (K=2).

6.4 Layout Implementation After the parameter design, the layouts of the power blocks need to be completed and their interconnect and parasitics should be extracted. Subsequently, the power blocks’ performance should be verified by post-layout simulations and, if required, optimized.

6.5 Overall PA Simulations After the layout implementation of the power blocks, the performance of the overall design needs to be verified by post-layout simulations and, if required, to be optimized. These simulations need to include the impact of the whole layout environment such that all the (potential) asymmetry due to the imperfect grounding and biasing, as discussed in section 3.4, is taken into account. Special attention needs the overall electrical stability. As mentioned in section 5.5, Stabilization, the rigorous generic method described in [86] is used to verify both even- and odd-mode stability by observing the internal loop gains. Depending on the open-loop gain to be characterized, each of the active stages’ inputs and outputs need to be connected in one of these three states: to a circulator, to an isolator or to a thru. To speed up the simulation time a self-created component was added which can easily switch between these three states [97]. The method allows to observe the stability with the active stages embedded in the complete test bench, hence the impact of all the components and interconnect external to the active stages is included.

LDC,GNDLDC,B1 LDC,B2LDC,C2

CBPCB1

CB2

L1

RB1+Rsh RB2

Fig. 6.28 Low-frequency even-mode equivalent circuit for a power module to indicate critical components for LF bias instabilities. The DC-probing equivalent circuit external to the chip is shown in the dashed box.

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Concerning LF even-mode stability, the impact of the DC-probing need to be included. A typical equivalent simplified LF even-mode circuit to indicate the critical components for the LF bias instabilities is depicted in Fig. 6.28. The DC-probe’s ground pin inductances can cause an additional feedback mechanism and can therefore play an important role for these instabilities. Proper decoupling (CB1, CBP) is therefore required up to low frequencies. Concerning the odd-mode stability, the analysis will show if it is required to insert odd-mode stabilization resistors between the parallel power modules.

When the obtained PA performance (output power, gain) of the overall design is not meeting the specification,

one need to iterate back in the design flow, as depicted in Fig. 6.1, building in larger margins for the required output power and/or gain.

In this chapter, the design approach was explained making use of a design example and targeting its specification.

This design example will be discussed in more detail in chapter 9, titled 30GHz, 1W Power Amplifier Design Example. In the next chapter, Hybrid Multi-Harmonic Load- and Source-Pull System, first measurement techniques are discussed to perform large-signal device characterization. In chapter 8, the obtained measured data from this characterization is used for the large-signal model verification, which is performed to gain confidence in the modeled performance.

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7 Hybrid Multi-Harmonic Load- and Source-Pull System Large-signal model verification requires non-linear device characterization to acquire the measurement data used at the verification. At this non-linear characterization, the importance of proper load- and source terminations for the active device is emphasized due to their impact on the device’s output power, efficiency, gain and linearity. Mostly, passive load- and source-pull systems serve this purpose, however, they can offer only a limited reflection coefficient. Using active techniques to extend the reflection coefficient is not a cost-effective solution. Hence, in recent years, hybrid techniques gained attention, combining the passive and active techniques. This chapter focusses on a novel broadband hybrid load- and source-pull system. First, in section 7.1, large-signal measurements setups using source- and load-pulling to allow device characterization are discussed. Subsequently, in section 7.2, common load-pull techniques are discussed and in section 7.3 the novel hybrid multi-harmonic load- and source-pull system is discussed in detail. Parts of this chapter have been published in [98].

7.1 Large-Signal Measurement Setups A conventional measurement setup for load- and source pulling using passive tuners is depicted in Fig. 7.1. Such a

setup typically comprises an RF source, passive tuners, pre-amplifiers, bias tees, attenuators, directional couplers and power meters. The passive tuners perform the tuning to the desired fundamental and harmonic impedance values and the pre-amplifier is required in case the RF-source is not able to deliver the required input power. The two bias-tees supply the DC-voltages to the DUT’s input and output. The power meters (PMA, PMB) are used to measure, after calibration and de-embedding, the powers of the incident wave at the DUT’s input and the incident wave towards the DUT’s load at, typically, the fundamental frequency only. The incident wave at the input is fed to the power meter PMA using a directional coupler, which has a main path (between port 1 and 2) having low losses and a coupled path (between port 1 and 3) having an attenuation of e.g. 10dB. As the power meters have a broadband characteristic, filters in front of the meters (not depicted) are therefore normally required to measure only the fundamental powers.

s~

PMA

inf0 f0, 2f0, 3f0

PMB

pre-ampRF source bias-tee bias-teeprobe probe

power meter

power meter

attenuatorsource-pull

tunerload-pull

tunerdirectionalcoupler

1 23

Fig. 7.1 Conventional measurement setup for passive load- and source pulling.

A typical measurement setup using a Non-linear Vector Network Analyzer (NVNA) [99] for passive load- and

source pulling is depicted in Fig. 7.2. The NVNA enables the characterization of a non-linear device by reconstruction the device’s time domain waveforms after measuring the signals’ fundamental and harmonics’ complex components (magnitude and phase) at the DUT’s ports. One application of such setup is that waveform reconstruction allows to monitor the dynamic load-line and apply waveform engineering [18]. Another application is to improve the accuracy of the device large-signal verification procedure as the measured data contains the information of the signals’ complex value of fundamental and harmonics, whereas in the conventional load-pull setup only the magnitude of the fundamental is monitored. The latter application is used in the large-signal verification procedure, described in chapter 8.

64

sNVNA

phaseref

source-pulltuner

source-pulltuner

f0, 2f0, 3f0f0 Fig. 7.2 Typical measurement setup using NVNA for load- and source pulling.

7.2 Common Load-Pull Techniques A passive load-pull system (Fig. 7.4) has a limited tuning range for generating a high (towards one) reflection

coefficient at the DUT reference plane. This limitation has been imposed by losses of tuners, probes, cables and connectors. Realization of a high magnitude for the reflection coefficient is required for observation and characterization of device’s high performance operation in terms of output power and efficiency.

An active load-pull system can effectively compensate the path-loss by providing auxiliary energy flow towards the reference planes [100], [101] (Fig. 7.5, Fig. 7.6). The required injected power level is a complex function of the path-loss, reflection coefficient and the output power level of the DUT. Obviously, adjusting the output power level of the DUT without taking additional measures can change the exact value of the reflection coefficient. This dependency might complicate the proper interpretation of the results. The required injected power can achieve an extremely high level when the measurement must be carried out on a high output power device requiring an extremely high reflection coefficient. These extremely high power levels are visualized for the active load-pull system depicted in Fig. 7.5 by plotting the required injected power as a function of the desired reflection coefficient’s magnitude for an example DUT, as shown in Fig. 7.3, hereby using: P = |a | = 1 1

(7.1)

with PL L the desired delivered power and load reflection coefficient of the DUT, respectively, and Lpb the passive (probe) losses.

Fig. 7.3 Required injected power as function of the desired reflection coefficient’s magnitude for PL=1W and Lpb(dB)=-1.7dB as example.

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In order to reduce the stress on the auxiliary power units, the active load-pull systems can be complimented with a passive load-pull system [102], [103]. In such hybrid systems (Fig. 7.7, Fig. 7.8) the energy flow towards the reference planes is now composed of injected power and the reflected power from the passive tuner.

In general, both active and hybrid systems can be divided in two categories: closed loop [100], [102] (Fig. 7.6, Fig. 7.8) and open loop [101], [103] (Fig. 7.5, Fig. 7.7). As the operation of the closed loop type relies on a constant loop gain, both in amplitude and phase, a highly linear microwave amplifier with negligible AM/PM conversion behavior is required when the power wave exiting from the DUT (b2) increases in amplitude. Closed loop circuits may oscillate, when the loop gain is larger than one and the phase 360 degrees; to prevent oscillations of the closed loop type at frequencies other than the operation frequency, additional selective filters can be required in the loop. This reduces the loop gain outside the frequency band of interest and prevents spontaneous spurious oscillations.

The narrowband nature of both categories demands additional paths for performing multi harmonic measurements. Each of the paths encompasses an auxiliary amplifier, circulators and adjustable narrowband filters, phase-shifters and attenuators. In addition, the proper functionality of the open loop topology demands synchronization measures between the output power level of the DUT and the injected power level.

passive

b2a2

Lpb

Fig. 7.4 Passive load-pull system.

b2a2

~Lpb

aaux

Fig. 7.5 Active load-pull system, open-loop.

b2a2

Lpb

aaux

1 23

Fig. 7.6 Active load-pull system, closed-loop

passive

b2a2

~Lpb

aaux

Fig. 7.7 Hybrid load-pull system, open-loop..

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passive

b2a2

Lpb

aaux1 2

3

Fig. 7.8 Hybrid load-pull system, closed-loop.

The closed-loop hybrid topology that will be presented in the next section proposes a solution to these problems.

The broadband nature of the presented hybrid topology enables a multi-harmonic tuning using a minimum set of components. This topology can be used as source-pull system as well.

7.3 Proposed Hybrid Load- and Source-Pull System This section describes a novel broadband hybrid load- and source-pull system. It eliminates the need for a

variable attenuator and variable phase-shifter and it employs the conventional passive tuner calibration procedure. Device measurements at 900MHz and 30GHz demonstrate a significant improvement for the measured output efficiency and transducer gain.

7.3.1 Principle of Operation The proposed hybrid system is formed around a Gamma Boosting Unit (GBU) (see Fig. 7.9), which resembles a

positive feedback loop and it encompasses two directional couplers (DCA, DCB) and an auxiliary amplifier with an available power gain G. In essence, the positive feedback loop generates a negative resistance that compensates the loss of probe and cable and in this way it boosts the maximum tunable reflection coefficient.

1 2

I

IIb

IIa

IIIout

GBU

Fig. 7.9 Proposed hybrid load-pull system with the Gamma Boosting Unit.

Fig. 7.9 presents the proposed hybrid load-pull system composed of a passive load-pull tuner (LP-tuner) and the

Gamma Boosting Unit (GBU). The losses of probe and cable are indicated as LA. Assuming the components (except of the operation of the proposed system can be explained as follows:

I. The incident wave from the DUT’s output, b2, travels towards the tuner via losses LA and the main paths of

directional couplers DCA and DCB and will be initially reflected at the input-plane of the tuner to engender a new power wave, b3. This new power wave can be expressed as b3=a3* t , in which t is the tuner reflection coefficient.

II. Power wave b3 travels back towards the DUT output via two paths:

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a) One part via the main paths of DCB and DCA (path IIa in Fig. 7.9); b) The other part via coupled paths of DCB and DCA, getting amplified by the auxiliary amplifier (path IIb in Fig.

7.9);

III. The reflected wave a2 at the DUT output can then be expressed as: a = , , (7.2)

with: S , = DC , DC ,

(7.3) S , = DC , DC , + DC , DC , G where DCX,thr and DCX,cpl represent respectively the through and the coupled path of the directional couplers.

S12,GBU consists of two parts, the passive part DCA,thrDCB,thr (path IIa) and the active amplified part DCA,cplDCB,cplG (path IIb). Obviously, the constructive summation between passive and active paths will maximize S12,GBU and it will relief the stress on the auxiliary amplifier. This can be accomplished in a broadband fashion by equalizing the group delays of both paths, e.g. by inserting additional line length. The reflection coefficient L can be expressed as: = ab = L S , S ,

(7.4)

In this case, t is boosted by S21,GBU*S12,GBU.

sSP 12

GBU

Fig. 7.10 Proposed hybrid source-pull system The hybrid source-pull system is depicted in Fig. 7.10. The principle of the operation is similar to that of Fig. 7.9.

In this case, S can be expressed as: = ab = L S , S ,

(7.5) where S12,GBU and S21,GBU are defined as in (3.2). Similar to the previous section, S is now boosted by S21,GBUS12,GBU.

As the GBU forms an integral part of the system, the calibration can be done in the conventional way: by on forehand characterizing the passive tuner and the GBU together as one block. This makes the need for real-time sensing of the a- and b-waves superfluous and hence also the need for additional directional couplers. Before starting calibration, the gain of the amplifier must be fixed such that at t,max| the desired L,max| (or S,max|) results. The obtained calibration data-set is then used for tuning towards the desired reflection coefficient, similar as done with a passive system.

Expressions (7.4) and (7.5) are in essence linear and frequency and power level independent. The operation range of these systems will then be primarily determined by the linear operation range of the auxiliary amplifier and the frequency bandwidth of the components in use. Employing broadband directional couplers and auxiliary amplifier enables a broadband loop response. Combination of a broadband GBU with a multi-harmonic tuner facilitates not only the boost of the reflection coefficient of the main tone but it will also boost the reflection coefficients of the associated harmonics.

Besides this, it is clear from (7.4), (7.5) that L and S are a direct function of t, i.e. by adjusting t the magnitude and phase of L or S can directly be controlled. Therefore no additional variable attenuator and variable

68

phase-shifter are required in the active loop. Furthermore, the calibration procedure of the proposed system is similar as at conventional passive tuners, so no complex procedure is required.

Fig. 7.11 Calibration result for the fundamental (black), 2nd (red) and 3rd (blue) harmonic impedances at f0=900MHz of the passive load-pull system (left) and for the hybrid load-pull system (right).

7.3.2 Performance Assessment of the Proposed Systems A performance assessment of the proposed topology has been carried out for two cases:

1) multi-harmonic hybrid load-pull system ( f0 = 900MHz); 2) hybrid source-pull system ( f0 = 30GHz) Both setups use 2-50GHz 10dB directional couplers.

Multi-Harmonic Hybrid Load-Pull at f0=900MHz In order to provide a proper assessment procedure, the calibration results of a 0.4GH-7GHz multi-harmonic Focus

MPT tuner for the fundamental, 2nd and 3rd harmonic are depicted in Fig. 7.11 (left). These results include the path losses from DUT’s output to the input of the tuner5. Fig. 7.11 (right) represents the calibration results accomplished by the proposed hybrid load pull system. The gain of the used amplifier was about 25dB. The maximum achievable reflection coefficients in both cases are enlisted in Table 7.1. As observed in Fig. 7.11, the centers of the calibration

, resulting in different maxima for the reflection coefficients’ magnitude as function of their phase.

Considering Table 7.1, the maximum reflection coefficients for the proposed hybrid system regarding the 2nd and 3rd harmonic are boosted considerably compared to the passive system. The fundamental reflection coefficient is boosted to a lesser extent, which is due to the fact that only 2-50GHz directional couplers were available. This causes a larger attenuation of the coupled path at f0=900MHz; hence this reduces the injected active power.

Table 7.1 Maximum reflection coefficients for multi-harmonic passive- and hybrid load-pull systems at f0=900MHz.

| L|@ f0 | L|@ 2f0 | L|@ 3f0 Passive LP 0.68 0.56 0.50 Hybrid LP 0.76 0.82 0.89

0.08 0.26 0.4

5As the directional couplers of the GBU were in front of the tuner, the path losses consist of the couplers’ through losses, next to the losses engendered by

probe, cable and connectors.

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Hybrid Source-Pull at f0=30GHz Similar as in the previous section, Fig. 7.12 present the calibration results of the passive and the proposed hybrid

source-pull system. Both systems employ a Focus MPT 8GHz-60GHz multi-harmonic tuner and the results include the path losses. The gain of the used amplifier was about 26dB. The proposed hybrid source pull system boosts the maximum reflection coefficient from 0.51 to 0.80.

Fig. 7.12 Calibration result for the fundamental impedances at f0=30GHz of the passive source-pull system (left) and for the hybrid source-pull system (right).

7.3.3 Device Measurements with Proposed Systems This section compares the capability of the proposed hybrid system to that of the conventional passive load and

source pull system for device performance assessment. To serve this purpose we have used two on-wafer HBT (NXP QUBiC gen. 7 process, see Table 2.4) with respectively an

output power of 12dBm and 22dBm.

Multi-Harmonic Load-Pull at f0=900MHz The device under test is the 12dBm HBT transistor. To achieve a higher efficiency the device operates in class-F.

This means that the 2nd and 3rd harmonic load impedances must be set to the lowest and highest available values, respectively.

As shown in Table 7.1, the conventional passive load-pull system can generate a 2nd and 3rd harmonic reflection coefficient of 0.56 and 0.50 , respectively.

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Fig. 7.13 Fundamental output efficiency contours at a fundamental load-impedance sweep using the passive load-pull system at f0=900MHz (left). The 2nd and 3rd harmonic load reflection coefficients are set to 0.56 180° and 0.50 0°, respectively. For the proposed hybrid load-pull system (right), the 2nd and 3rd harmonic load reflection coefficients are set to 0.82 180° and 0.89 0°, respectively.

While keepings these harmonic impedances at those fixed values, a maximum output efficiency of 63.4% is

measured by sweeping the fundamental load-impedance, see Fig. 7.13 (left). The proposed hybrid system realizes values of 0.82 and 0.89 0° for

respectively the 2nd and 3rd harmonic reflection coefficients. These values represent better the ideal class-F terminations. While keepings these harmonic impedances at those fixed values, a maximum output efficiency of 68.1% is measured by sweeping the fundamental load-impedance, see Fig. 7.13 (right).

Hybrid Source-Pull at f0=30GHz

For this case, the 22dBm HBT transistor is used. The transducer gain of the device is primarily a function of the source impedance. At these specific measurements, the source reflection coefficients selected for the conventional and proposed hybrid system are respectively 0.51 -159° and 0.76 -153°.

This enlarged reflection coefficient results in a significant improvement for the measured transducer gain from -1.4dB to 2.8dB, see Fig. 7.14.

Fig. 7.14 Gain contours for a source-impedance sweep at f0=30GHz. using the passive source-pull system (left) and using the

proposed hybrid source-pull system (right).

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Having discussed the measurement techniques for large-signal device characterization, the next section discusses the large-signal verification procedure.

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8 Systematic Large-Signal Verification Procedure for mm-Wave Transistors

In order to gain confidence in their performance and to enable first-time-right mm-wave power amplifier (PA) designs, verification of the large signal models with measurements is required. Large-signal verification is needed as DC and small-signal performance verifications are not sufficient due to the non-linear behavior of the active devices [107].

Although MEXTRAM [95] provides an accurate (large) signal model of an active device at low frequencies (GSM-band) [111], [112], the large-signal behavior of the model has not been verified at mm-wave frequencies. At these frequencies the interconnect starts to play an important role, especially at multiple parallelly connected active devices, which results in large geometries.

In [107] a large signal SiGe HBT model validation at 77GHz was presented, comparing the measured vs modeled data for the fundamental output power, gain and efficiency. Due to the limited frequency range of such measurement setups, the behavior of the harmonic signals at these frequencies cannot be captured by measurements and hence the model is not verified for this. Therefore, the behavior of the harmonic signals is verified at lower frequencies [109], using a spectrum analyzer to measure the magnitude of the harmonic output signals as function of input power.

The availability of the NVNA (see the previous chapter) allows improving the accuracy of the device large-signal verification procedure as the measured data contain the information of the signals’ complex value of fundamental and harmonics, whereas in the conventional setups only the magnitudes of the signals are monitored. This is demonstrated in [110], although at low frequencies (fO=900MHz).

In this chapter a systematic large-signal verification procedure for single and multi-device structures at mm-wave frequencies is presented. Measurements have been performed on two device sizes and at two distinct frequencies (900MHz and 30GHz). Although the focus of the verification procedure is for Ka-band frequencies, the 900MHz frequency is also considered to improve the accuracy of the procedure and observe in the data any scaling trend as a function of frequency and size. For the single-device structure, NVNA measurements are performed at both frequencies (900MHz and 30GHz) to improve the accuracy of the verification by comparing the measured fundamental and 2nd harmonic complex output signals with the modeled data.

In section 8.1 the devices under test will be discussed. Section 8.2 explains the verification paradigm, whereas section 8.2.5 presents the comparison between the simulation and measured data. Parts of this chapter have been published in [104].

8.1 SiGe:C HBT Device Structures The verification procedure has been carried out on single and multi-

SiGe:C BiCMOS technology, in this case the NXP QUBiC4 gen. 7 process having high speed NPN devices with an ft of 110GHz (see Table 2.4). Although this process is of a generation earlier than the NXP QUBiC gen. 8 process, which is used for the demonstrator in the modular design approach and in the design example in chapter 9, the active device modeling using MEXTRAM is the same for both generations.

-device structure is composed of 16 single devices in parallel. The die photos of both structures are depicted in Fig. 8.1. Both structures are configured in a common-emitter topology. Parallel devices have been connected by the top metal layer. In order to carry out the measurements, these structures are embedded in the required test-fixture, which is composed of interconnects, bond-pads and unwanted parasitic components and coupling effects.

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Fig. 8.1 Die photo of single device (left) and multi-device (right) test structures, with the intrinsic devices shown within the yellow boxes.

8.2 Verification Procedure The verification procedure is composed of five complementary steps:

1. Collecting the measurement data; 2. De-embedding the test fixture from the measured data; 3. Modeling of the intrinsic device; 4. Extraction of the simulated data for the intrinsic device; 5. Comparing the measured data with the simulated data.

Modeling the intrinsic device in the single structure comprises simulation of intrinsic active device plus RC-extraction of the metallization structure on top of the device, used to make the connections to the outer world. Modeling of the intrinsic device in the multi-device structure implies modeling of the individual intrinsic single structures and the associated inter-connects.

The required test fixture will have impact on the large signal operation of the intrinsic device(s). Therefore this impact must be included during the modeling and simulation of the intrinsic device(s). The verification paradigm aims at the comparison between the simulated data of the intrinsic device(s) and the de-embedded measured data. The situation is visualized in Fig. 8.2, with ports 1&2 as the probe tips reference planes and ports 3&4 as the intrinsic device ports.

1 23 4Intrinsic

Device

test fixture Fig. 8.2 Intrinsic device structure embedded in test fixture.

8.2.1 Collecting Measurement Data The measurement setup is composed of a 67GHz four-port Agilent NVNA, power meters, 67GHz calibration

structures, a 67GHz comb generator, 0.4GH-7GHz and 8GHz-60GHz multi-harmonic Focus MPT tuners, directional couplers, and pre-amplifier. The 67GHz Agilent NVNA has the capability of reconstruction of the time domain signal’s waveform which is composed of the fundamental and harmonics’ magnitudes and phases. This information is used for verification purposes and for monitoring the active devices’ output voltage for breakdown.

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Fig. 8.3 Test fixtures EM-simulator view with indication of reference planes, referring to Fig. 8.2.

The pre-amplifier has been used to overcome the input mismatch loss of the low power gain of the devices at

30GHz. After various calibration procedures the required data for the signals has been collected at the tips of the probes (reference planes 1&2, see Fig. 8.2). Load-pull measurements have been performed on the single as well as the multi-device structures. The single and multi-devices structures have been verified for two operating frequencies, i.e. 900MHz and 30GHz.

8.2.2 De-Embedding Test Fixture from Measured Data The procedure demands an accurate modeling of the test fixture which has been achieved through extensive use

of EM simulators [93], [94]. This enables the characterization at higher frequencies with respect to on-wafer de-embedding structures, which is limited by the used VNA’s bandwidth (67GHz). Extending to higher frequencies is desirable to e.g. include the 3rd harmonic load termination at a fundamental of f0 = 30GHz. Fig. 8.3 illustrates the implemented test fixture in the ADS Momentum EM simulator. The method discussed in [88] has been used as guideline for the implemented de-embedding procedure.

RCX

EM-SIM

B' C'

single device multi-device

RCX RCXRCX

B' C'

E'

E'

Fig. 8.4 Intrinsic device structure model view.

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Fig. 8.5 Intrinsic multi-device inter-connect EM-simulator view based on the schematic overview given in Fig. 8.4.

8.2.3 Modeling of Intrinsic Device Similar as described in section 6.1, the active device is modeled up to metal 1 layer by the MEXTRAM transistor

model. The model includes the poly and active-to-metal contact information. For a single device, the local intrinsic interconnect towards the top metal layer is modeled by RC-extraction. For the multi-device, this is carried out partly by RC-extraction and partly employing an EM-simulator. The latter takes care of the inter-connect wires between the parallel devices [87] as these have non-negligible inductive behavior at an operating frequency of 30GHz and its related harmonics. The intrinsic models for both single and multi-devices are depicted in Fig. 8.4, where B’, C’, E’ represent the effective base, collector and emitter terminals, respectively. Fig. 8.5 shows the inter-connect wires of the intrinsic multi-device in the Sonnet EM simulator.

8.2.4 Extraction of Simulated Data for Intrinsic Device The comparison between the measured and the simulated data in the next section requires that at the extraction

of the intrinsic device’s simulated data, the intrinsic device observes the same external environment as in the measurements. This is required to allow the intrinsic device having the same large-signal operating point in the simulation testbench as during the measurements. Hence, in the simulation testbench, the impact of the test fixture and the external DC-feed lines, which connect to the power supplies, should be included.

8.2.5 Comparing the Measured Data with Simulated Data Single device structure

Verification at 900MHz includes the fundamental and two harmonics. The values for 2nd and 3rd harmonics termination are kept fixed at a low impedance level, while the termination value at the fundamental frequency has been swept. From this procedure, the load value for the optimum PAE condition is determined as 75 + j0.5 . The results of simulated intrinsic device performance and de-embedded measurements for the output power (Pout) and power-added-efficiency (PAE) have been depicted in Fig. 8.6 for 900MHz operation.

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Fig. 8.6 Comparison of measured and simulated PO and PAE of single device at f0=900MHz. The DC biasing voltages are set to VBE=760mV and VCE=2V.

Fig. 8.7 Comparison of measured (dots, triangles) and simulated (solid,dashed) complex values for fundamental and 2nd harmonic output voltage and output current of single device at f0=900MHz.

Fig. 8.6 shows a maximum deviation of 0.3dB and 7% for respectively Pout and PAE over the entire range of Pin. Fig. 8.7 illustrates the simulated and de-embedded measured data of the complex values of the output voltage (on the left) and output current (on the right) for the fundamental and second harmonic frequency and shows excellent agreement.

Verification at 30GHz includes the fundamental and 2nd harmonic frequency. Using the procedure, we have determined the load value for the optimum PAE condition as . The results of simulated intrinsic device and de-embedded measured data of Pout and PAE for these specific terminations have been depicted in Fig. 8.8. Maximum deviations of 0.3dB and 6% for respectively of Pout and PAE over the entire range of Pin indicate the correctness of the verification procedure.

-15 -10 -5 0 5-3

1

5

9

13

17

Pin (dBm)

Pou

t (dB

m)

-15 -10 -5 0 510

22

34

46

58

70

PA

E (%

)

-15 -10 -5 0 510

22

34

46

58

70

Po measPAE measPo simPAE sim

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Fig. 8.8 Comparison of measured and simulated Po and PAE of single device at f0=30GHz. The DC biasing voltages are set to

VBE=760mV and VCE=2V.

Fig. 8.9 Comparison of measured (dots, triangles) and simulated (solid,dashed) of complex values for fundamental and 2nd

harmonic output voltage and output current of single device at f0=30GHz. Fig. 8.9 illustrates the simulated and de-embedded measured data of complex values of output voltage (on the

left) and output current (on the right) of the fundamental and second harmonic frequency. A good fit between measurements and simulation has been obtained. Multi-device structure

Measurements on the multi-device structure at 900MHz are performed with the same procedure as described in the previous section. Pout and PAE are verified at a fundamental load value of 10 , and depicted in Fig. 8.10. Maximum deviations of 0.2dB and 5% for respectively of Pout and PAE over the entire range of Pin can be observed.

-10 -5 0 5 10 15-10

-5

0

5

10

15

Pin (dBm)

Pou

t (dB

m)

-10 -5 0 5 10 152

9

16

23

30

37

PA

E (%

)

-10 -5 0 5 10 152

9

16

23

30

37


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Fig. 8.10 Comparison of measured and simulated Po and PAE of multi-device at f0=900MHz. The DC biasing voltages are set to VBE=760mV and VCE=2.5V.

Fig. 8.11 Comparison of measured and simulated Po and Eff of multi- device at f0=30GHz. The DC biasing voltages are set to VBE=760mV and VCE=2.5V. Measurements at 30GHz revealed a negative transducer gain as result of high input mismatch loss and low power gain. Hence, the output efficiency (Eff) is used as parameter of comparison instead of PAE. Pout and the efficiency are verified at a fundamental load value are depicted in Fig. 8.11. Due to the power-rating limitation of used bias-tee at input, the swept Pin range is also limited. Maximum deviations of 0.3dB and 5% for respectively Pout and the output efficiency are observed over the entire range of Pin.

A systematic large-signal verification procedure for mm-wave transistors was described and demonstrated in this chapter. The verification procedure is composed of five complementary steps: collecting the measured data, de-embedding the test fixture from the measured data, modeling of the intrinsic device, extraction of the intrinsic device data from the simulations and comparing the measured data with the simulated data. The accuracy of this method has been validated on two device sizes and at two distinct frequencies (900MHz and 30GHz). Verification has revealed an accuracy of .3dB and 7% for respectively output power level and efficiency.

Having verified the large-signal device modeling, continued is with the in detail discussion of the 30GHz, 1W design example in the next chapter.

-15 -10 -5 0 5 105

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20

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30

Pin (dBm)

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t (dB

m)

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E (%

)

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17 18 19 20 21 22 23 24 25 26 275

9

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Pin (dBm)

Pou

t (dB

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cien

cy (%

)

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9 30GHz, 1W Power Amplifier Design Example The modular design approach discussed in the previous chapter was used to design a power amplifier for

Ka-band applications hereby targeting 1W of output power and 20dB of gain and to be implemented in a 0.25um SiGe:C BiCMOS technology. In the previous section the design parameters for the dominant power block(s) towards output power and PAE were obtained, which was for this example only for power block PB2 (K=2). The design parameters of the preceding power blocks, having mainly impact only on gain, still need to be determined. Moreover, the complete power blocks, including biasing and stabilization networks, need to be implemented in the layout and the power blocks’ performance should be checked with post-layout simulations.

The architecture of the final PA module will be discussed in section 9.1, Architecture, and the power blocks design will be discussed for each power block in sections 9.2-9.4. Subsequently, simulations performed on the complete PA module to verify overall performance and stability, will be discussed in section 9.5, PA-Module Performance, and section 9.6, PA-Module Stability, respectively. The measurement results of the implemented design will be discussed in section 9.7. Parts of this chapter have been published in [113].

9.1 Architecture The final PA module architecture is shown in Fig. 9.1. As can be seen from this is, N, the number of parallel power

modules PM2, equals 8 and K, the number of cascaded power modules, equals 2, as discussed in the previous chapter.

For reasons of symmetric operation, as discussed in section 5.4, Biasing, the number of parallel power modules PM1 (M1) equals 2 such that the power modules PM1 observe the same RF impedances. This resulted in the use of two times a four-way power splitting network within inter-stage network ISN1.

TLo1

TLo0S

G

G

TLi0S

G

G

Ci0

PSM PCN

TLo4

TLo3

TLo4

TLo4

TLo3

TLo4

Lo2

Lo2

TLo4

TLo3

TLo4

TLo4

TLo3

TLo4

Lo2

Lo2

TLm2

TLm1

TLm2Cm2

Cm1

TLm2

TLm1

TLm2Cm2

VCdrv

CBP

L1

TLm2

TLm1

TLm2Cm2

Cm1

TLm2

TLm1

TLm2Cm2

L1

Ci1

TLi1

Ci2

Li1

Ci1

TLi1

Ci2

ISN1

TLo2

TLo2

TLo2

TLo2

ZL,PM2

TLo1TLi2

TLi2

ZL,PM1

Lo4

Co4

CBP

VCdrv

PM1

PM2

PM2

PM2

PM2

PM2

PM2

PM2

PM2

PM1

PB0 PB1 PB2

Fig. 9.1 Final architecture of the implemented PA module.

With the final architecture determined, the function matrix, which was discussed in chapter 4, Structuring the Design Space, can be completed and is shown in Table 9.1. The module types and designed parameters are now shown separately in Table 9.2.

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Table 9.1 Function matrix of the design example after having determined the final architecture, showing the distribution of the functions over the hierarchical levels. The mapping of the biasing and stabilization function to the levels are indicated with solid dots ( ). The topology parameters for sub-level 1 to sub-level 3 are shown in Table 9.2. Function Level

Amplification Power splitting

Power combining

Biasing + Stabilization

Design parameters

base collector Module type Topology parameters

System PM1-PM3 PSM ISN1-ISN2

PCN PSM, ISN1,2, PCN: ‘binary tree’ N=8 K=2

M1=2 sub-level 1 AM - - - Table 9.2 sub-level 2 AC PSQ PCQ PSQ, PCQ: ‘star’ Table 9.2 sub-level 3 AD PSR PCR PSQ, PCQ: ‘distributed’ Table 9.2 sub-level 4 ED - - - -

Table 9.2 Resulting topology parameters for the design example for sub-level 1 to sub-level 3 depicted for each power module

(PM). Module Level

PM1 PM2

sub-level 1 S=2 S=2 sub-level 2 H=1, Q=10 H=1, Q=10 sub-level 3 R=2 R=2

The design details for the power blocks (PB) of the shown PA architecture are discussed next, together with the resulting topology parameters of the power modules (PM) and comparing those with the outcome of the parameter design.

9.2 Power Block PB2 The (initial) design parameters of power block PB2 were determined during the parameter design in the previous chapter, resulting in R=2 and Q=8. After implementation, the combining efficiency of the implemented combining module PCN resulted in a value of -2.4dB, which is 0.47dB lower than expected via the parameter design. The output power of the implemented power module PM2 resulted in a value of 23.4dBm, which is 0.5dB lower than expected. With these numbers the PA output power would result in only 30.1dBm, which is 0.9dB lower than the target of 31dBm. Hence, the number of active cells (AC) within the power module PM2 was increased according to: = , , = 12598 0.58 218.88 = 10

(9.1)

So the updated power module PM2 has now 20 active devices (AD) per active module (AM) as now R=2 and Q=10, as shown in Table 9.2. The design details of the power module PM2 and the combining module PCN will be discussed next, together with the reasons for these performance degradations.

9.2.1 Power Module PM2 The power module PM2 was implemented according to the topology parameters depicted in Table 9.2. This

resulted in 20 active devices (AD) for each active module (AM). Each active device (AD) within the common-emitter active module AM1 2 and for the common-base active module AM2 this is

2 2 2 respectively. The layout implementation of the power module’s splitting and combining modules is shown in Fig. 9.2. As can be seen, cascoding of active modules (AM) is applied instead of cascoding active cells (AC), resulting in H=1 and S=2 (see

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Table 9.2), which is done for ease of layout implementation. The components from the biasing and stabilization networks (Fig. 6.16) are also added in this figure in their schematic view, excluding base resistor RB2 for reasons of clarity. These are inserted per active module (AM), as discussed in the topology design in section 6.2 and shown in Table 9.1. The total component values are the scaled versions of the reference cell component values depicted in Table 6.2, as shown in the simplified schematic in Fig. 9.3. Base capacitor CB2

’ is a poly capacitance with a moderate Q-factor and is designed such the series resistance Rser2 immediately is included and is implemented below the splitting and combining modules PSQ and PCQ.

Fig. 9.2 Layout implementation of the splitting and combining modules for power module PM2. The blocks depicted as PSR+PCR

comprise multiple splitting and combining modules. The components from the biasing and stabilization networks are also added in this figure in their schematic view. Regarding the modeling for this power module, the impact of the combining module PCQ from active module AM1 and the splitting module PSQ from active module AM2 is assumed to be negligible.

RFin

VB1

VB2

DC+RFout

RB1´=RB1/(RQ)

Csh1´=Csh1*(RQ)

Rsh1´=Rsh1/(RQ) RB2´=RB2/(RQ)

CB2´=CB2*(RQ/2)CB2´

Fig. 9.3 Simplified schematic of Fig. 9.2. This layout view was implemented in an EM-simulator to obtain an overall combined characterization for these modules. Afterwards the active devices (AD) were connected in a circuit simulator to the ports of this EM-simulated view. The performance parameters for this power module are depicted in Table 9.3, which are obtained after applying load-pull in the circuit simulator.

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Table 9.3 Expected performance of power module PM2 via the modular approach and via simulations. Expected via

Modular approach Simulated

R 2 2 Q 8 10 Po (dBm) 23.9 24 Po/AD (dBm) 11.9 11 Gp (dB) 15.0 13.9 PAE(%) 41.0 33.9 Icc (mA) 114 144 Icc/AD (mA) 7.1 7.2 Zopt 3.7+j9.2 3.9+j8.8 Zin 1.1-j1.8 1.9-j0.7

As mentioned shortly in the previous section, the output power per active device (AD) was degraded compared to the expected output power via the parameter design. The reason for this is that at the time this design and its implementation was carried out, the local ground paths of the common-base active module AM2 were not implemented per active device (AD) but as common paths for the whole active module AM2. This common path’s inductance didn’t scaled inversely proportionally with the number of active cells (AC) in the Q-direction and hence the effective ground path inductance observed by an active cell (AC) was increased. This resulted in PAE and output power degradation compared with the performance obtained via the parameter design in the previous chapter. The power gain is about 1dB lower. The simulated stability k-factor of this power module is depicted in Fig. 9.4 and shows a value of larger than one over the frequency range from 0.1GHz-50GHz.

Fig. 9.4 Simulated stability k-factor of power module PM2 after layout implementation and extraction.

9.2.2 Combining Module PCN The 8-way combining module (PCN) of power block PB2 uses a combination of series transmission-lines (TL) and

lumped components to perform the required impedance transformation. This is the same topology as described in section 6.3, Parameter Design. It consists of five series TL-sections (TLo0-TLo4), a lumped series inductor (Lo2) and lumped shunt inductor (Lo4). Capacitance Co4 is inserted for DC-blocking purposes. Deep trench isolation (DTI) is implemented underneath the passives to improve their Q-factor by reducing the substrate parasitics. The combining module’s design parameters determined at the parameter design served as input for the module’s layout implementation, which was simulated with an EM-simulator to verify its performance. The simulated performance of this combining module together with the expected performance via the modular approach are depicted in Table 9.4.

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Table 9.4 Expected performance via the modular approach and simulated performance of combinig module PCN.

Matching approach

Expect via modular approach

Simulated

in 3.8+j9.4 3.9+j8.3 PC,N (dB) -1.93 -2.4

The difference between the modular approach outcome and the EM-simulated combining module is 0.47dB,

which can be contributed mainly to a lower Q-factor of the finally implemented combination of shunt inductor Lo4 and DC-blocking capacitance Co4. The layout implementation of the combination of TLo4, Lo4 and Co4 is shown in Fig. 11 with the inductive loop formed by shunt inductor Lo4 visible.

Fig. 9.5 Layout implementation of the combination of TLo4, Lo4 and Co4, with the inductive loop formed by shunt inductor Lo4 shown.

9.3 Power Block PB1 The (initial) design parameters for power block PB1 were not determined with the parameter design in the previous chapter as the impact to PA performance of this power block is expected to be not dominant, as discussed at the parameter design in the previous chapter. Power Module PM1 For power module PM1 the same module is used as for power module PM2, only this power module is operating at a supply voltage (VCdrv) of 4V instead of 5V to reduce on-chip power dissipation. This power module is terminated with a load impedance of Inter-Stage Network ISN1 The inter-stage network (ISN1) consists of two times a 4-way CPW-line in-phase current splitter (TLm1-TLm2) and is implemented together with lumped shunt capacitances (Cm2) for matching, and series capacitances (Cm1) for DC-blocking purposes, see Fig. 9.1. Chokes L1 are implemented as a cascaded lumped and microstrip-line inductor design and CBP is a distributed bypass capacitor with a total value of 64pF to offer a broadband low impedance path, favorable for low frequency stability, which will be discussed in more detail in section 9.6, PA-Module Stability.

9.4 Power Block PB0 Power block PB0 comprises only the 2-way splitting module PSM, which is based on in-phase current splitting with

CPW-lines and additional lumped components. It -pass filter is implemented with a shunt inductor (Li1) and series capacitances (Ci1) to reduce the gain at lower frequencies.

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9.5 PA-Module Performance The simulated overall large-signal performance of the PA module at 30GHz is shown in Table 9.5 with the performance parameters of the power blocks’ power modules and coupling networks also depicted. Table 9.5 Simulated large-signal performance of PA module at 30GHz with the performance parameters of the power blocks’ power modules and coupling networks also depicted. The parameter values refer to the (total) even-mode equivalent values, as shown in Fig. 6.13.

PB0 PB1 PB2 PA CNW0 PM1 CNW1 PM2 CNW2

Po (dBm) - 30.3 19.5 32.7 30.3 30.3 GP (dB) -3.3 16.2 -3.5 13.2 -2.4 20.2 PAE (%) - 16.7 - 26.7 - 13.4

o (%) - 17.1 - 28 - 13.8

The target PA module’s output power of 31dBm is not reached mainly due to the DC-voltage drop across the combining module PCN that was not accounted for during the parameter design, which also lowers the PAE of the power module PM2 and hence the PA module’s PAE compared to the parameter design. The simulated PAE is 13.4%, which is significantly lower than the expected ~24% via the parameter design, due to the explained reasons at power block PB2 level and here at PA module level. The target power gain of larger than 20dB is obtained.

9.6 PA-Module Stability The stability analysis method as discussed in section 5.5, Stabilization, was carried out and showed that the

output node of power module PM1 is sensitive to low-frequency (LF) even-mode instabilities which are caused by interaction with the bias circuit’s components. This is because no damping resistor is inserted here as large DC-currents are flowing at this terminal, in contrast to the devices’ bases. The equivalent simplified LF even-mode circuit to indicate the critical components for the LF bias instabilities was depicted in Fig. 6.28. The DC-probe’s ground pin inductance (LDC,GND) causes an additional feedback mechanism and plays therefore an important role for these instabilities. Selecting the proper value for capacitance CBP is therefore important as this capacitance can bypass the impact of this inductance and inductance LDC,C2. The open-loop gain observed at the driver’s output is shown in a Nyquist plot in Fig. 9.6 for different CBP values from 10MHz to 10GHz. Encircling the +1 point in a clock-wise direction is occurring for CBP BP=64pF was selected to include an additional stability margin. Regarding the odd-mode stability, the analysis showed that there was no need to insert odd-mode stabilization resistors between the successive stages.

Fig. 9.6 Nyquist plot of open-loop gain observed at output power module PM1 for different bypass capacitance CBP values.

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9.7 Measurement Results This section describes the results of the small-signal and large-signal measurements in the chip after being

The chip photograph of the realized PA with a die size of Fig. 9.7.

Fig. 9.7 Chip photograph of 8-way power combining PA. The chip size is 1.86mmx1.52mm (2.83mm2).

9.7.1 Small-signal Measurements On-wafer small signal measurements have been carried out using a 67GHz Agilent PNA-X and Cascade Microtech

probes. Fig. 9.8 shows the results (solid lines) in which a maximum gain of 24.5dB can be observed at 28.3GHz. The results reveal a 3dB-bandwidth of 3.8GHz (from 26.5 to 30.3 GHz) and the S11 is below -10dB from 27.7GHz to 30.5GHz. Compared with the intended simulation results (sim v1, dashed lines) a downward frequency shift is observed, mainly for the graphs of S21 and S22. This is caused by the large sensitivity of the low impedance levels at inputs and outputs of the power modules towards passive modeling inaccuracies. This modeling inaccuracy is likely to result from the splitting up of the total EM-simulation layout view to speed up the simulation time and hereby neglecting some mutual coupling effects. The EM layout view comprises the modeling of the interconnect and passives, excluding capacitors and resistors. Considering the measured S22, a less inductive impedance path as function of frequency was observed compared with the intended simulated S22. Adding a series inductance of 20pH at the inputs and outputs of the power modules PM2 resulted in a better match for S22 and S21. This shows the sensitivity towards a small modeling inaccuracy. These new simulation results are also shown in Fig. 9.8 (sim v2, dotted lines).

Fig. 9.8 (sim v1, dashed) and new (sim v2, dots) simulation results are both shown.

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9.7.2 Large-signal Measurements Fully calibrated large-signal measurements were performed using an Agilent NVNA. Due to the modeling

inaccuracies, the power modules PM2 were not terminated in their optimum load impedance ZL,PM2 and this resulted in reduced output power. The more inductive load impedance resulted in a voltage-limited load line and therefore VCC was increased to cope with this. This necessitated the reduction of its common-emitter device’s base bias voltage VB1 (see Fig. 9.3) to 0.7V and 0.66V. Reducing the bias voltage VB1 extends the maximum allowable supply voltage before breakdown as it reduces the current conduction angle and hence DC-current and dissipated DC power. This extends the large-signal operating region within the SOA. However, this measure is at the expense of reduced gain. The measured saturated output power and PAE versus the output stage’s supply voltage (VCC) are shown in Fig. 9.9 at a frequency of 27GHz for the base bias voltage VB1 of the power module PM2 equal to 0.7V and 0.66V. The supply voltage VCdrv for the power module PM1 was set fixed to 4V. At VB1= 0.66V and a supply voltage VCC of 6.55V, the PA achieves a maximum saturated output power of 29.7dBm with a PAE of 10.2%. This extends the maximum saturated output power with 0.6dB compared with VB1 set to 0.7V.

-pull was applied to compensate for the impedance mismatch. This resulted in an optimum load impedance of 21.2-power and PAE versus supply voltage VCC are shown in Fig. 9.10 at a frequency of 27GHz at VB1=0.7V. The PA achieves a maximum saturated output power of 31dBm with a PAE of 13% at a VCC of 6.9V. An additional off-chip matching network is still r

are shown in Fig. 9.11 at a VCC of 5.5V and power module PM1 its supply voltage (VCdrv) of 4V. The common-emitter device’s base bias voltage VB1 of the power module PM2 is set to 0.7V. At 27GHz, the PA achieves a maximum saturated output power of 29.1dBm with a PAE of 10.3% and a collector efficiency of 10.7%. The saturated gain is more than 14.7dB in the frequency band from 26-31GHz and the output power 1dB bandwidth is about 4GHz, from ~25GHz to 30GHz, and corresponds with a 14.2% fractional bandwidth.

To observe PA instability a 50GHz spectrum analyzer was connected to the output with a directional coupler during the small- and large-signal measurements. No unexpected spurs were observed here and also the obtained measurements results show no indication for instable PA operation.

Table 9.6 summarizes and compares the performance of (near) mm-wave silicon PAs with a saturated power of 23dBm and larger. The proposed PA delivers 1.3dB more saturated output power compared to [65] and has therefore the highest reported output power in the frequency regime above 26GHz. After applying ZL=21.2- the PA delivers another 1.3dB power. The achieved PAE and gain values are moderate. The consumed area is only 2.83mm2.

Fig. 9.9 Measured saturated output power and PAE versus supply voltage VCC at 27GHz for VB1,AS2 is 0.7V and 0.66V and at

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Fig. 9.10 Measured saturated output power and PAE versus supply voltage VCC at 27GHz for VB1,AS2 is 0.7V and at ZL=21.2-

Fig. 9.11 Measured saturated output power, gain, collector efficiency and PAE versus frequency at VCC=5.5V, VB1,AS2=0.7V

Table 9.6 Comparison with (near) mm-

[65] (‘13)

[63] (‘13)

[60] (‘13)

[63] (‘13)

[59] (‘14)

[66] (’15)

[66] (’15)

This work [113] (’14)

This work* [113] (‘14)

Technology 0.13um BiCMOS

45nm SOI CMOS

45nm SOI CMOS

45nm SOI CMOS

0.13um BiCMOS

0.35um BiCMOS

0.35um BiCMOS

0.25um BiCMOS

0.25um BiCMOS

Topology


combiner

8-way lumped

combiner

4-stacked 2-bit DAC

modulated switched

PA

Double- stacked class-E

4-way lumped

combiner

device Parall.


combiner


combiner freq. (GHz) 42 37 45 45 41 24 24 27 27 Supply (V) 4 / 2.4 4.8 5.1 2.4 / 2.6 4 5.8 5 4 / 6.6 4 / 6.9

Psat,max (dBm) 28.4 27.3 24.3 23.4 23.4 30.8 24.7 29.7 31.0

PAEmax (%) 10 10.7 14.6 6.7 34.9 17.6 31 10.5 13 Gainmax

(dB) 18.5 19.4 18 11.9 14.5 16.1 18.5 20.2 20.7

Area (mm2) 5.55 4.16 0.77 4.16 1.02 5.37 0.86 2.83 2.83 *at load impedance ZL=21.2-

88

Putting the results of this design example in perspective to the performance of state-of-the-art Ka-band VSAT PAs (see Table 2.1), we see that 1W-class output powers are obtained. The finally obtained PAE value in this example (13%) is lower than typically seen at the state-of-the-art (>20%). However, by using a power module PM2 with improved grounding at its common-base active module AM2, as used at the parameter design, and by implementing a higher-Q shunt inductor at the combining module PCN, the expectation is that PAE values above 20% can be obtained in this technology, similarly as at the state-of-the-art. The outcome of the parameter design supports this.

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10 Conclusions and Recommendations

10.1 Conclusions This thesis proposes a structured modular design approach for mm-wave Watt-level power amplifiers and shows

its correctness and effectiveness. It also shows the feasibility of silicon technologies, and more specifically, SiGe:C BiCMOS technology, for Watt-level PA design.

Ka-band VSAT networks are interesting due the enormous growth market for consumer VSAT in regions with

unserved/underserved terrestrial broadband internet access. State-of-the-art PAs for these applications are commonly implemented in III-V compound technologies, with GaAs PHEMT technology dominating the market, which is indicated by a literature survey. In recent years, SiGe transistors are becoming more favorable due to their relatively low cost and high integration capability. However, the intrinsic performance of this technology is in general worse than GaAs technology. Comparison of both technologies for different process generations reveals that their average product of ft and breakdown voltage (ft*BV) is 466GHzV and 205GHzV for the GaAs PHEMT and the SiGe:C HBT devices, respectively. The Q-factors of the passive components used for matching and for interconnect are larger than 100 for the GaAs technology when using transmission lines, whereas in the SiGe technology this is 20-30 for inductors and around 10 for transmission lines.

Moreover, silicon PAs in the (near) mm-wave frequency regime with saturated powers towards Watt-level need

extensive distribution and multi-level power combining, which introduces severe problems in power combining, gain improvement, stability, and power-added efficiency (PAE). At the same time, a distributed design offers many choices for accomplishing power combination, gain improvement and insertion of bias and stabilization functions. To find a power efficient design, all these choices need to be explored, which is a cumbersome and time-consuming task as many design iterations are needed. From this it is clear that the realization of mm-wave Watt-level PA in a SiGe technology is more challenging than realization in a GaAs technology. Due to the complexity in design, only a limited design space is normally investigated, which leads to non-optimum results.

A modular design approach is presented that enables to explore the available options in a structured way and to

reduce the number of design iterations such that the optimum PA performance is found in limited time, hereby focusing on output power, efficiency and gain. The approach starts from the desired mode of operation when combining multiple devices, the even-mode, and takes into account the sources of the undesired odd-mode operation. These sources are related to the asymmetry and dynamic loading at the splitting and combing modules, imperfect grounding, biasing distribution, electromagnetic coupling and thermal coupling. A classification is made for splitting and combining modules regarding their asymmetric and dynamic loading behavior. The combining efficiency degradation due to the odd-mode operation is expressed in terms of the combining module’s intrinsic efficiency and in terms of load mismatch factors (LMF), the latter expressing the mismatches between the actual combining module’s input impedances and the optimum load-line matched impedances and the differences between the actual and optimum input currents and voltages. To quantify the potential degradation due to undesired odd-mode operation the LMF values should be determined, which requires also knowledge of the behavior of the other modules within the amplification module that define these currents, which are the splitting module and the active blocks.

A proposed ‘function matrix’ supports the structuring of the analysis and design. It gives an easy overview of the

distribution of the required functions for power and gain improvement and for biasing and stabilization over selected hierarchical levels together with the available design parameters shown at each level. Such a distribution with design parameters defines a PA topology, and a filled-in function matrix, comprising all the assigned values for the design parameters, forms a structured overview of the outcome of a specific design.

90

An overview of module options and module limitations further supports the structured approach. This is done for each of the functions amplification, power combining, power splitting, biasing and stabilization. The module options for amplification showed the trade-offs in selection of the elementary device’s parameters: the number of fingers (emitter stripes) and the emitter area dimensions per finger. Cascode topologies for enlarging the breakdown voltage and the gain cope with the relatively low ft*BV product of the SiGe:C technology. Three transmission-line based current-summing topologies are indicated as the preferred candidates for implementation of the splitting/combing modules: the star, the distributed and the binary tree topology. The selection of one these topologies is a trade-off between symmetric operation and area consumption.

The presented design approach covers the full design trajectory: design-driven module modeling, topology design, parameter design, layout implementation and overall PA simulations. The design-driven modeling approach allows including the relevant EM and electrical coupling effects, meanwhile offering a scalable (design-driven) model, which reduces the number of time-consuming EM-simulations. The options and tradeoffs for the PA topology design are provided. The parameter design, the procedure for assigning values to the design parameters, targets PAE maximization by exploring the impact of the available options in a structured way by:

Considering multiple times during the design, i.e. after each power block design, the impact of the power blocks’ performance on the PA module’s PAE.

Comparing the performance of a common-emitter and a cascode configuration active reference cell. The cascode configuration performs better or equally in almost all aspects.

Selecting the values for the biasing and stabilization networks after considering their impact on the electro-thermal stability, thermal behavior and electrical stability.

Determining the active devices’ (AD) scaling behavior in the different topology directions. Using an exhaustive search optimization routine to obtain for a ‘binary-tree’ combining module the

optimum design parameters for maximum output power, targeting the power modules’ (PM) optimum load impedance.

A novel hybrid load- and source-pull topology facilitates large-signal device characterization. The topology

minimizes the set of required components for multi-harmonic tuning by employing a broadband Gamma Boosting Unit (GBU) and eliminating the need for a variable attenuator and variable phase-shifter inside the GBU. Furthermore, the system requires no complex calibration procedure. Device measurements at 900MHz and 30GHz validate the improved functioning of the proposed topology both as load- and as source-pull system.

A systematic large-signal verification procedure for mm-wave transistors was described and demonstrated in this

section. The verification procedure is composed of five complementary steps: collecting the measured data, de-embedding the test fixture from the measured data, modeling of the intrinsic device, extraction of the intrinsic device data from the simulations, and comparing the measured data with the simulated data. The accuracy of this method has been validated on two device sizes and at two distinct frequencies (900MHz and 30GHz). Verification has revealed an accuracy of .3dB and 7% for respectively output power level and efficiency.

The usefulness and effectiveness of the design approach was further validated with a specific design example: an

eight-way in-phase current-combining power amplifier for Ka-band VSAT applications, targeting 1W of output power, and to be implemented in a 0.25um SiGe:C BiCMOS technology. Measurement results show a saturated output power of 29.7dBm at 27GHz with a maximum PAE of 10.5%. After applying load-pull, this output power increases further to a level of 31dBm, with a maximum PAE of 13%. The small-signal gain is 24.5dB and the saturated gain is more than 14.7dB in the band of interest. The consumed area is only 2.83mm2. Hence, Watt-level output powers have been realized, thanks to an extensive use of distribution along several lines and levels in the architecture and a structured design approach to cope with the associated complexity. The finally obtained PAE value in this example (13%) is lower than typically seen at the state-of-the-art Ka-band VSAT PAs (>20%). However, the reasons for that are known and also the ways to cope with them. The expectation is therefore that PAE values above 20% indeed can be obtained in this technology, as indicated at the parameter design, achieving similar values as at the state-of-the-art.

91

10.2 Recommendations for Future Work For applications where bandwidth is of a concern, the modular design approach can be extended with

bandwidth as a performance parameter of interest, next to output power, gain and PAE. The implemented exhaustive search optimization routine for the ‘binary-tree’ combining module can be extended in this by considering the combining efficiency at multiple frequency points around the center frequency instead of only at the center frequency.

To improve the PAE of the active blocks, it is worthwhile to investigate the switching type of amplifiers, like class-E as in [59]. Also device-stacking could be investigated as it can lower the required impedance transformation ratio and hence reducing the matching losses. However, both increase the design and implementation complexity.

The mutual thermal coupling between devices is a point of attention. Thermal coupling can be investigated using electro-thermal simulations on a power module (PM), by using an electro-thermal simulator as e.g. available within ADS from Keysight.

To improve the power modules’ robustness, the base biasing can be done using a current mirror at each (parallel) power module (PM).

Ways of reduction of the inequality in the signals at the inputs of the active blocks when using a ‘distributed’ topology for the splitting modules can be investigated, such that odd-mode behavior is reduced. To change the standing wave behavior (voltage distribution along the transmission line) within this splitting module, additional passive (shunt) elements can be added within this splitting module to change the transmission line loading.

In order to enhance the proposed hybrid load- and source-pull system’s robustness towards stability, the frequency response of the Gamma Boosting Unit (GBU) can be manipulated by proper adjustment of phase-shifter and time-delay. In this way the L becomes maximum around the tuned frequencies and reduces at the other, non-tuned, frequencies. This improves the stability at these non-tuned frequencies as

L reduces, without the use of selective filters. The possibilities of scaling the active devices (AD) with their long-side instead of short-side aligned in the

Q-direction can be investigated (see Fig. 6.7).

92

Appendix A. Multi-port Impedance Definition At a linear multi-port, the input impedance of a specific port is conventionally defined as the port’s ratio of

voltage and current when that specific port is excited with a signal and with all the other independent sources set to zero. However, at an amplification module containing multiple active blocks and splitting/combining modules, it is important to know the effective loading of an active block when all the other sources are also active. To define the impedance for this case, the relations between the signals of the port of excitation and the other ports must be defined.

+12

F

F+1

L

a1

aF+1a2

aF

Fig. 10.1 L. Such a module can be an amplification (F=1) or

combining (F>1) module. Considering Fig. 10.1 and using Z-parameters, the input impedance of the ith input port can be defined in a general way as:

, = , ( ) .. .. (10.1)

with Zx,y the module’s Z-parameters and Ix the port currents, with x,y=1,2,..,F+1. So the impedances can only be defined when the currents at the other ports are related to the current at the port of interest, port i. Connecting a load impedance ZL to the module’s output port, port F+1, the relation between the current IF+1 and the other currents will be known. The input impedance of the ith input port becomes now:

, = , , ,, +( ) .. ..

(10.2)

The summations in the numerator containing the current Ij are now only over the ports 1 to F, the input ports.

From (10.3), a next step is to define the even-mode impedance. The even-mode impedance is defined for the situation that all input port currents are equal. With this, all relations between the currents Ii and Ij are known. This results in: = , + ,, + ,

(10.3)

93

Appendix B. PAE Calculation The derivation of the PA module’s PAE formula used in chapter 6, Design Approach, is presented here using two

cascaded power modules (PM) as example (see Fig. 6.13). = , , 1 = ,,= ,, 1 + ,, 1

= 1, 11 1 + 1, 11 1 = 1, , , 11 1

with PM,x=(PO,PB,x/GCNW,x)/PDC,x with x=1,2 and GPA the overall PA module’s power gain.

Generalizing this result for K cascaded power modules (PM) leads to:

= 1, , , 11 1

94

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List of Publications and Patents Conference

1. technology," Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2014 IEEE, Coronado, CA, 2014, pp. 143-146.

2. Essing, J. “Towards a Broadband High-Power Power Amplifier,” Par4CR Workshop on Cognitive Radio at the

39th European Solid-State Circuit Conference, 16-20 September 2013.

3. Essing, J.A.J., Arfaei Malekzadeh, F., Roermund, A.H.M. van & Mahmoudi, R. (2012). Hybrid multi-harmonic load- and source-pull system. Proceedings of the 80th ARFTG Microwave Measurement Conference , 27-30 November 2012

4. Essing, J.; Leenaerts, D.; Mahmoudi, R.; , "Systematic large-signal verification procedure for mm-wave SiGe

bipolar transistors," Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2012 IEEE , vol., no., pp.1-4,Sept. 30 2012-Oct. 3 2012

5. Essing, J.A.J., Pei, Y., Mahmoudi, R. & Roermund, A.H.M. van (2011). A 60GHz differential

transformer-coupled power amplifier in CMOS 45nm. Proceedings of the Interface for Dutch ICT-Research (ICT.OPEN), 14-15 November 2011

6. Essing, J.; Mahmoudi, R.; Yu Pei; van Roermund, A.; , "A fully integrated 60GHz distributed transformer

power amplifier in bulky CMOS 45nm," Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE , vol., no., pp.1-4, 5-7 June 2011

7. Mahmoudi, R., Essing, J.A.J. & Leenaerts, D.M.W. , “Design Paradigm of 30dBm Power Amplifier in SiGe,”

Radio Frequency Integrated Circuits Symposium (RFIC), Workshop on towards Watt-Level mm-Wave Efficient Silicon Power Amplifier, 17 June 2012

8. Pei, Y., Essing, J.A.J., Mahmoudi, R. & Roermund, A.H.M. van (2012). A 60GHz fully integrated power

amplifier using a distributed ring transformer in CMOS 65nm. Proceedings of the 19th IEEE Symposium on Communications and Vehicular Technology in the Benelux (IEEE SCVT 2012), 16 November 2012

9. Pei, Y., Essing, J.A.J., Mahmoudi, R. & Roermund, A.H.M. van (2011). A 60GHz fully integrated power

amplifier using distributed ring transformer in CMOS 65nm. Proceedings of ICT.OPEN 2011, 14-15 November 2011

10. Sakian, P.; Janssen, E.; Essing, J.; Mahmoudi, R.; van Roermund, A.; , "Noise figure and S-parameter

measurement setups for on-wafer differential 60GHz circuits," Microwave Measurement Symposium (ARFTG), 2010 76th ARFTG , vol., no., pp.1-4, Nov. 30 2010-Dec. 3 2010

Patent

11. Essing, J.A.J., Arfaei Malekzadeh, F. & Mahmoudi, R. “Gamma Boosting Unit (GBU) for Hybrid Load and Source Pull,” issued 2015

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Summary Wireless long distance applications in the millimeter-wave frequency regime require a Monolithic Microwave

Integrated Circuit (MMIC) power amplifier (PA) capable of amplifying signals to Watt-The enormous growth market for consumer VSAT in regions with unserved/underserved terrestrial broadband internet access makes this an attractive application. Very-Small-Aperture-Terminals (VSAT) are ground stations used for one-way or two-way data transmission by means of a satellite communication system. As spectrum licenses in the traditionally used C- and Ku-band became scarce, the demand for available spectrum and higher capacity has led to entering the Ka-band.

The state-of-the-art in PA design targeting output powers relevant for Ka-band VSAT applications is discussed in

chapter 2. The application and the related requirements for the PA within a VSAT ground station are discussed here and an overview of state-of-the-art Ka-band PAs suitable for VSAT operation is given. From this survey the dominant technologies (III-V compound technologies) are indicated and their main drawbacks are given. As alternative to these technologies, the use of a low-cost technology as SiGe BiCMOS is investigated. The (fundamental) differences between silicon and III-V compound technologies are investigated, with a focus on the comparison of SiGe vs GaAs technology. A literature survey of published silicon PAs in the (near) mm-wave frequency regime with saturated powers towards Watt-level is given and the different power combining techniques for output improvement that are presented in this literature are discussed. Two promising combining techniques are selected from this overview for combining on device-level and on circuit-level.

A major design issue for these PAs is the layout interconnect between the multiple distributed devices as this shows distributed effects at mm-wave frequencies. Such a distributed design introduces severe problems in power combining, gain improvement, stability, and power-added efficiency (PAE). At the same time, a distributed design offers many choices for accomplishing power combination, gain improvement and insertion of bias and stabilization functions. To find a power efficient design, all these choices need to be explored, which is a cumbersome and time-consuming task as many design iterations are needed. Therefore, only a limited design space is normally investigated, which might lead to non-optimum results.

To cope with this, a modular design approach is presented in chapter 3 to explore the available options in a

structured way. In a modular concept, multiple hierarchical levels can be specified. This provides the opportunity to distribute both power and gain improvement, biasing and stabilization means over the various levels. The (sub)functions at each level are represented by ‘modules’ or a group of modules, and each module on its turn has various implementation options, the module options. This approach reduces the number of design iterations such that the optimum PA performance is found in limited time, hereby focusing on output power, efficiency and gain.

The desired mode of operation when combining multiple devices, the even-mode, is discussed together with its counterpart that results in an undesired mode of operation, the odd-mode. The sources of the undesired odd-mode operation are discussed and the combining efficiency degradation due to the odd-mode operation is investigated.

In chapter 4, a ‘function matrix’ is presented, depicting a distribution of the required functions for power and

gain improvement and for biasing and stabilization over the selected hierarchical levels together with the available design parameters shown at each level. Such a distribution defines a PA topology and a function matrix comprising all the assigned design parameters is the outcome of a specific design.

The module implementation options and the module limitations will be discussed in chapter 5 for each of the

required functions for power and gain improvement and for biasing and stabilization. The pros and cons of the different options will be discussed with their relation to the limitations imposed by the process technology constraints.

The design approach is discussed in chapter 6. A design-driven module modeling is here presented, which

reduces the design cycle meanwhile including the relevant EM-coupling effects. The PA topology design is

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discussed in detail and subsequently the parameter design, the procedure for assigning values to the design parameters, is discussed. The design approach is completed with the performance and stability verification of the overall PA by using a circuit and an EM simulator, after full layout implementation of the PA.

In order to gain confidence in their performance and to enable first-time-right mm-wave power amplifier (PA)

designs, large signal model verification is required. This requires non-linear device characterization to acquire the measurement data used at the verification. At this non-linear characterization, proper load- and source terminations for the active device are important due to their impact on the device’s output power, efficiency, gain and linearity. Mostly, passive load- and source-pull systems serve this purpose, however, they can offer only a limited reflection coefficient. Chapter 7 proposes a novel broadband hybrid load- and source-pull system to boost the reflection coefficient. The system overcomes several limitations of state-of-the-art hybrid systems as it eliminates the need for a variable attenuator and variable phase-shifter and employs the conventional passive tuner calibration procedure.

Large-signal verification is needed as DC and small-signal performance verifications are not sufficient due to the

non-linear behavior of the active devices. Although MEXTRAM provides an accurate (large) signal model of a single active device, for multiple parallelly connected active devices the interconnect starts to play an important role, especially with large geometries at high frequencies. Chapter 8 provides a systematic large-signal verification procedure for single and multi-device structures. The accuracy of this method has been validated on two device sizes and at two distinct frequencies (900MHz and 30GHz). Verification has revealed an accuracy of .3dB and 7% for respectively output power level and efficiency.

Chapter 9 discussed the design of an eight-way in-phase current combining power amplifier for Ka-band

applications, targeting 1W of output power and to be implemented in a 0.25um SiGe:C BiCMOS technology, hereby making use of the proposed modular design approach. Measurement results show a saturated output power of 29.7dBm at 27GHz with a maximum PAE of 10.5%. After applying load-pull, this output power increases further to a level of 31dBm, realizing Watt-level output powers, with a maximum PAE of 13%. The small-signal gain is 24.5dB and the saturated gain is more than 14.7dB in the band of interest. The consumed area is only 2.83mm2.

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Acknowledgements When I was asked during my M.Sc. graduation project if I was interested to continue as a Ph.D. student in the

same group, I immediately knew the answer. Besides the scientific challenges that come along with such a task, the atmosphere I experienced in the group was of importance to base my decision on to continue my career in the Mixed-Signal Microelectronics (MsM) group at the Eindhoven University of Technology.

I would like to thank my promotor Arthur van Roermund for providing me this opportunity. During the last period of my Ph.D. project the frequency of our meetings increased due to the writing process that was started. Our meetings were tough when major changes had to be made. Nonetheless, they were always extremely constructive and occurred in a positive atmosphere. I really enjoyed our discussions and learned a lot from them, especially from your higher abstraction level point of views. Thank you for all the hours you put in the reviewing of this thesis. Your dedication is admirable, always putting in energy at 100%.

Additionally, I would like to thank my second promotor Domine Leenaerts for his endless support during these years and making me become more critical towards my work. Thank you for all time you spend on the informative technical discussions and on the reviewing of my work. Your encouragement boosted my motivation when it was needed, especially when measurements results were not as expected.

Special words of thanks to Reza Mahmoudi, who has been my supervisor during my M.Sc. project and also during the bigger part of my Ph.D. project. Your informal, optimistic way of behaving made me feel at ease in the academic world. Your out-of-the-box ideas stimulated me and you always had the time for a (technical) discussion. I appreciated your dedication to motivate your students to develop themselves to a next level. It is really a pity that we couldn’t make it together to the end of my Ph.D. project. I wish you all the best.

I would also like to thank the other members of my doctorate committee: Bart Smolders, Leo de Vreede, Bram Nauta, Patrick Reynaert, Ton Koonen and Jorge Duarte for their time and effort.

Many thanks to the people from the MsM group. Margot van den Heuvel, for always being there when issues related to paper work and conferences needed to be solved, and for your contribution to the group’s cohesion. Piet Klessens and Rainier van Dommele for helping at the measurements. I want to thank Chuang Lu, Qian Ma and Pooyan Sakian for our discussions and for being really pleasant roommates. Also thanks to Yu Pei. All of you were always benevolent to help. I also would like to express my thanks to Hans Hegt, Georgi Radulov, Eugenio Cantatore, Marion Matters, Pieter Harpe, Jan Haagh, Hao Gao, Yu Pei, Zhe Chen, Wei Deng, Erwin Janssen and Maarten Lont. The trip with Maarten to Washington and New York after attending the IMS’11 conference in Baltimore was great fun.

I would furthermore like to express my gratitude towards the people of the RFADT team at NXP Semiconductors Eindhoven: Mark van der Heijden, Ying Chen, Jos Bergervoet and Edwin van der Heijden. Although I was only in your group doing design and layout during short periods of time, those periods were very valuable for me. Thank you for your help, especially when the tape-out deadlines were approaching.

I would also like to thank the people of Catena in Sweden, especially Mats Carlsson, for letting me do a three month internship, providing me a really nice work experience abroad.

In addition to all these people from my professional environment, I definitely want to show my appreciation and gratitude towards my family. I am thankful that my parents have provided me with the freedom to develop into the person I want to be. And last but certainly not least, I want to thank my wife Anouk, for your everlasting patience, and for giving me all the support I needed during all those years. I know it sometimes was even more difficult for

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you than for me, especially on those Sundays when I was finishing this thesis upstairs. I’m very happy together with you, feeling lucky that you are my wife and the mother of our two beautiful daughters, Nyne and Lola.

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Biography Jaap Essing was born on 02-06-1982 in Vierlingsbeek, the Netherlands. After finishing high school ‘VBO’ in 1998 at

the Raayland College in Venray, he completed ‘MBO’ electronics at the ROC ter AA in Helmond in 2002. Afterwards, he studied Electrical Engineering at Fontys Hogescholen in Eindhoven and obtained his bachelor degree (cum laude) in 2006. His bachelor project was entitled ‘A Çuk-converter as LED-driver’ and was executed at Philips Lighting Eindhoven. After obtaining his bachelor degree he worked for half a year at Philips Lighting Oss. Subsequently, he studied Electrical Engineering at Eindhoven University of Technology and in 2010 he obtained his master degree (cum laude) within the Mixed-signal Microelectronics group. His master project was entitled ‘A 60 GHz Fully Integrated Power Amplifier Using a Distributed Transformer in CMOS 45 nm’ and was executed at NXP Semiconductors Eindhoven. From 2010 he started a Ph.D. project at Eindhoven University of Technology of which the results are presented in this dissertation. Since 2014 he is employed at TNO radar technology in the Hague, working on Monolithic Microwave Integrated Circuits.

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Modular design approach for Watt-level millimeter-wave power