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Moore’s Law and the future of testBy Pooya Tadayon, Greg Iovino, Sameer Ruiwale [Intel Corporation]

oore’s Law – which has fueled the semiconductor i ndu s t r y fo r t he l a s t fifty years – is generally

associated with the observation that the number of transistors on a chip doubles at a regular cadence. As Figure 1a from Gordon Moore’s 1965 paper shows, Moore’s Law is first and foremost an economic law and the rate at which transistor count grows is governed by the minima of the cost curve [1]. Moore’s Law is the motivator behind key industry initiatives, such as migrating to larger wafers, and is the reason why the selling price for a mainstream desktop processor today is roughly the same as a 80386 chip from thirty years ago, despite the orders of magnitude higher transistor count and more complex manufacturing process.

The semiconductor industry has done a wonderful job of innovating to maintain a steady reduction in transistor cost despite the ever-increasing complexity in manufacturing (Figure 1b). That said, the journey has not been easy and Moore’s Law has come under threat many times, sometimes from unexpected sources. For example, up until the 1990s, test cost was an after-thought given that, at a per transistor level, it was several orders of magnitude less than the cost to manufacture a transistor. As late as 1997, however, the International Technology Roadmap for Semiconductors (ITRS) highlighted that test cost per transistor was holding flat and – if

left unchecked – within two decades it would exceed the cost to build a transistor [2]. This was recognized as a threat to Moore’s Law and test technologists across the industry rallied around a set of strategies – such as better design for test (DFT) features, more structural testing, and higher parallelism – that ultimately led to bending of the cost curve, and by 2001 the ITRS roadmap was showing test cost to be scaling with silicon cost.

Cost of test back in the spotlightToday, test is in the spotlight once again.

As transistor dimensions approach atomic scales, attention has shifted towards die disaggregation and heterogeneous integration to extend Moore’s Law [3]. For this strategy to succeed, it is critical that test deliver a characterized known-good-die (cKGD), which poses significant challenges to the test platform, test tooling, test flows, and the test industry. Addressing these challenges in an economically viable manner is key to advancing Moore’s Law and will require a high degree of innovation and collaboration from players across the industry.

Die disaggregation and heterogeneous integration help advance Moore’s Law by driving down the cost curve. For example, disaggregation builds yield resiliency by enabling smaller chiplets that are higher yielding. Furthermore, not all circuitry on a die needs to be manufactured using the

most cutting edge and most expensive silicon manufacturing process. Disaggregation allows for manufacturing of certain intellectual property (IP) blocks on older, higher yielding, and cheaper process nodes, thereby helping lower the overall cost of the product. This strategy, however, has a profound impact on the test ecosystem.

Nowhere is the effect of die disaggregation more noticeable than the probe card industry. Consider the monolithic die in Figure 2, which requires a single probe card design to test at wafer level. Disaggregating that monolithic die into four unique chiplets will require probe card vendors to design and manufacture four unique probe cards, with no relief in lead time as all four probe cards have to be delivered at the same time in order to support the timely integration of the chiplets. Meanwhile, the suppliers will be under tremendous cost pressure because the product cannot afford to have the cost of test collaterals quadruple relative to the monolithic baseline.

Once integrated, the chiplets will need to seamlessly communicate with each other as if they were a monolithic die. In order to mimic the same number of wires connecting different IP blocks within a monolithic chip, designers are pushing for ever increasing die-to-die interconnect density, which is a driver for an aggressive pitch reduction roadmap. Therefore, not only do probe card vendors

M

Figure 1: a) Cost curves from Gordon Moore’s 1965 paper showing that there is economic incentive to increase the number of components on an integrated circuit at a regular cadence; and b) A plot from the 1997 ITRS roadmap showing cost per transistor trends and forecast.

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have to build more probe cards within the same time window, but they also have to manage the added complexity of building denser arrays that are more expensive and time consuming to manufacture. One can avoid the complexity and cost of probing microbumps at tight pitch by introducing better DFT features, sacrificial test pads at looser pitch, and silicon that can support variable pitch bumps [4], but these solutions are not free and simply shift the cost from one point in the manufacturing flow to another.

Die d isaggregat ion also leads to inefficiencies and added overhead at wafer test because lot setup and basic connectivity tests, such as shorts/opens, have to be repeated on each chiplet. In a monolithic die, techniques to test IP blocks in parallel can be used to optimize test time, but such techniques are no longer available when chiplets are tested independently. One way to mitigate this overhead is to increase parallelism at wafer level and test multiple chiplets at once. This has, in fact, been the industry’s tried-and-true approach to bending the cost curve for the last two decades as multiple die tested in parallel allows test cost to be amortized. Increasing parallelism, however, drives a tradeoff between higher channel count test platforms, or a reduction of channels probed per die to fit within a given tester configuration. Both approaches have economic implications: increasing tester resources increases capital costs while reducing probe count per die creates test limitations during wafer test. Disaggregated die with tight pitch microbumps also pose signal integrity

challenges for testing high speed I/Os, driving the need for loopback-based test methods in wafer test. These differences between wafer test and package test can result in higher yield loss downstream and the cost-benefit tradeoff of such approaches needs to be carefully considered when architecting the product and the manufacturing flow.

Another consequence of die disaggregation and heterogeneous integration is the need for a passive interposer or silicon bridge to connect the die in the package (Figure 3). These interposers are simple structures that provide lateral connections to other die through metal traces and vertical connections to the package by way of through-silicon vias (TSVs). These interposers are the lowest cost component in a package, yet they are also the weakest link in the stack because there is no good way to test them. Because of the large number of nets at very tight pitch, and the presence of vertical connections, a test strategy to achieve a known-good interposer would be highly complex and expensive. As a result, different companies have taken different

approaches to this problem [5]. Given that interposers are generally manufactured on older high-yielding nodes, some companies blind-build and assume defect density will be low enough to justify skipping test. Others employ a sampling strategy, while some rely on redundant features in the design to build yield resiliency. And there is a group that believes full testing is needed, and innovative but complex approaches have been proposed to achieve such a result [6-8]. The consequence of this is that companies will have to spend considerable resources to test these interposers, or accept the fact that tens or hundreds of dollars of silicon and package substrate are dependent on the yield and fidelity of the simplest and lowest cost component in the stack.

The situations discussed above are just a few examples of how die disaggregation and heterogeneous integration will stress the economics of test. One of the key challenges with heterogeneous integration will be how to architect manufacturing flows to manage yields. As the number of chiplets stitched together grows, the overall yield drops and the need for KGD grows. But delivering KGD out of wafer test requires more testing with more advanced tooling and equipment, which translates to higher test cost. This problem is exacerbated by 3D stacking strategies (Figure 4) where die are bonded to a base wafer, thereby creating stacks that are then stitched together on the package. This now requires having a known-good-stack (KGS) prior to integration on the package and an additional test socket has to be introduced into the flow, which drives up the cost of test relative to the monolithic baseline.

An argument can be made that a stack test is not necessary if assembly attach yields are high. The counter argument is that die-to-die interface testing at wafer level may not be sufficient. For example, tests executed at wafer level only stress the Tx/Rx buffers on one side of the interface and need to be supplemented by tests after the stack is assembled where the Tx/Rx path through the entire interface can be exercised. Given that most die-to-die signals are buried within the interposer and are not visible to the outside

Figure 3: llustration of a Si interposer connecting chiplets together through lateral connections and to the package through vertical connections.

Figure 4: Typical manufacturing flow for a chip-on-wafer 3D stacked product. Note: SLT=system-level test.

Figure 2: a) (left) Illustration of a monolithic die and b) (right) the same die disaggregated into four unique chiplets.

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world, innovative DFT solutions, such as built-in-self-test, need to be added to each chiplet and redundant test methods need to be employed to recover defective lanes during stack testing. Furthermore, in addition to testing the interface, a repair signature has to be determined, verified, and propagated to the individual chiplets and this can be run only after the stack has been assembled. These solutions add design complexity, increase die area, and increase test times, and the problem is exacerbated by the fact that the number of die-to-die interconnects is increasing at an exponential rate.

Beyond yield: evaluating chiplet performance

Aside from yield, die disaggregation is going to demand that we have accurate characterization of the chiplet so that die of same/similar performance can be paired together to manage the total power and operational frequency of the assembled unit and maximize the overall performance [9]. In the simple example shown in Figure 5, if one of the four die being stitched is a medium performing die – lower frequency, for example – then the entire unit will have to be shipped as a medium performance unit even though the remaining die are top of the line, high-performance chiplets. Die disaggregation also enables using the same chiplet in multiple products, thereby allowing product engineers to push capability in one chiplet while re-using lower performance chiplets in product segments that don’t demand top-line performance. Situations like these have significant economic implications and are the reason why it’s critical to not just target producing KGD with high yields, but to also have that known-good-die be characterized.

Lack of characterization and intelligent pair ing of chiplets leads to random combination of chiplets on the final product, which will need to tolerate the performance variation of each chiplet [10]. As shown in Figure 6, transistor characteristics across a die have a much smaller distribution than between die, due to within-wafer and wafer-to-wafer variability. As a result, disaggregation poses a higher yield risk if the chiplets being combined are not stitched together in a controlled fashion. Figure 6 shows that by intelligently creating sub-populations of chiplets, it is possible to get the variability of chiplets to approach the same variability as a monolithic die. Even with reduced variability, however, chiplet pairing does not have a clear one-size-fits-all answer and depends on the desired outcome, which can change based on the product being assembled as well as customer demand fluctuations throughout the life of the product. Combining the die in a

purely random fashion would create a higher concern for meeting the minimum frequency of operation while helping control the total power of a unit. On the other hand, combining chiplets with the same characteristics will result in the best result for minimum frequency of operation, but would result in higher overall power for a unit. Having a well characterized chiplet enables intelligent pairing to achieve the desired outcome.

Characterizing chiplets at wafer level, however, is not trivial and requires better and more standardized test hardware, along with more test content, which result in higher test cost. For example, subtle differences in the power delivery network of a probe card from two different suppliers can have a significant impact on the measured frequency of a device. In a world where chiplets come from different nodes and different foundries, that are tested on different test platforms, using different probe card technologies from different suppliers, it will become increasingly difficult and expensive to properly characterize chiplets for pairing decisions.

The future of testA looming problem on the horizon is the

insatiable appetite for interconnect density by the design community, which is driving the pitch roadmap into regimes where traditional solder bump interconnects are no longer feasible. This will force the industry into using hybrid bonding to connect chiplets together, which will severely challenge test. Putting aside the technical and economic viability of building probe cards at <10μm pitch, the fundamental problem is how to test these wafers prior to chiplet integration. Hybrid bonding requires pristine bond pads that are sensitive to defects as small as 10nm. Probing these pads will create divots and pile-up that are considered killer defects. Some have proposed testing the wafers prior to building the hybrid bonding layers, while another option is to send the wafers back to the fab to re-polish and repair the probe marks [11]. These solutions pose multiple problems. First, how does one adequately characterize a chiplet when not all the metal layers have been completed and the power delivery network is not identical to the final

Figure 5: Illustration of two different die pairing schemes: a) (left) a scheme that is a consequence of intelligent pairing, and b) (right) a scheme that can be a result of random pairing.

Figure 6: A comparison of transistor variation between a monolithic die and chiplets. This data shows that intelligent segregation of chiplets into more discrete sub-populations reduces the chiplet-to-chiplet variation and enables optimized pairing of chiplets.

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metal stack? And second, how does one guarantee KGD in an open loop flow where there is additional processing after wafer test, but prior to assembly?

The brute force approach of adding more complexity to test hardware and test content is destined to bend the cost curve in the wrong direction and lead to test becoming a limiter to Moore’s Law. Instead, to overcome some of these challenges, test will need to rely more on artificial intelligence (AI) and take advantage of big data analytics to drive faster yield learning, optimize test content on a per unit basis, and better predict the characteristics of a device based on the wealth of fab and test data available. This will require companies to invest in AI infrastructure and test engineers will need to be trained on developing better AI algorithms. Companies will also need to invest in hardware and automation infrastructure to deal with the complexity associated with intelligent pairing of die. For example, assembly tools will need to support complex asynchronous pick-and-place algorithms and management of multiple sub-populations to achieve the desired results.

There is also a need for st ronger collaboration between design, packaging, and test to ensure solutions are optimized for cost. Such collaborations took place two decades ago where addition of self-test modes enabled the transition to lower cost structural test platforms. Today, design teams have recognized that it will be easy to make chiplets that work in isolation but are not economically viable because of complex manufacturing f lows and the inability to fully test the chiplets until they are integrated. Efforts are underway to address some of these challenges through interface standardization that would enable better access points for test pre- and post-assembly. In addition, standards are needed for a minimum feature set on chiplets to ensure basic connectivity, power delivery, and functionality at wafer level. Other approaches include built-in redundancy of cores and IP blocks, and enabling end-of-line repair/configurability to account for noise, power, and thermal variations post-assembly. But much more innovation is needed in the DFT

space to ease testing and enable resilient, self-healing designs. An immediate area of focus should be better I/O DFT that provides better coverage at wafer test and reduces the stack test, shown in Figure 4, to a simple assembly health monitor test (AHMT).

The test industry will also need to deliver innovations in support of driving down cost. Probe card suppliers will need to invest in new manufacturing techniques, such as fab-like build-up processes, to expand their capacity while driving down cost. Automated test equipment (ATE) suppliers will need to deliver low-cost, mega-parallel, asynchronous test solutions to compensate for the added sockets in the flow. Assembly equipment suppliers need to consider integrating fast and low-cost AHMT capability within their tools for faster process feedback.

SummaryIt is often said that these are exciting times

to be a packaging engineer as advanced packaging is the next frontier along the continuum of Moore’s Law. It is equally exciting to be a test engineer as future challenges provide boundless opportunities to innovate. There is, however, little margin for error. Test cost per transistor used to be several orders of magnitude smaller than transistor manufacturing cost. Today, that gap has narrowed and if test engineers and the test industry are not able to keep pace with transistor manufacturing costs, then test will become a limiter to Moore’s Law. Our goal here was to bring awareness to these challenges just as the ITRS roadmap did more than twenty years ago. We invite test technologists across the industry to propose bold and innovative solutions to take on these challenges.

References1. G. E. Moore, “Cramming more

components onto integrated circuits,” Electronics, 1965, Vol. 38.

2. International Technology Roadmap for Semiconductors: Test and Test Equipment, p.11, 2001 Edition.

3. B. Holt, “Moore’s Law, 40 years and

counting: Future directions of silicon and packaging,” InterPACK, 2005.

4. TM Mak, “Microbumps – to probe or not?,” Test Vision 20/20, SEMICON West, San Francisco, 2014.

5. G. John, “Test f low for advanced packages (2.5D/SLIM/3D),” Sixth IEEE Inter. Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Anaheim, 2015.

6. R. Wang, Z. Li, S. Kannan, K. Chakrabarty, “Prebond testing and test-path design for the silicon interposer in 2.5-D ICs,” IEEE Trans. on Computer-Aided Design of Integ. Circuits and Sys., 2017, pp. 1406-1419, Vol. 36.

7. S. K. Goel, S. Adham, M. Wang, J. Chen, T. Huang, A. Mehta, et al., “Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: a silicon case study,” Inter. Test Conf., 2013.

8. G. Hellings, M. Scholz, D. Velenis, M. Broeck, C. Roda Neve, Y. Li, et al., “Active-lite interposer for 2.5 & 3D integration,” Symp. on VLSI Technology Digest of Technical Papers, 2015.

9. R. Goodwin, R. Miller, E. Tuv, A. Borisov, “Semiconductor yield analysis and multi-chip package (MCP) die pairing optimization using statistical-learning,” 7th Inter. Conf. on Elec. Packaging Tech., Shanghai, China, 2006, pp. 1-10.

10. K. Bowman, S. Duvall, J. Meindl, “Impact of die-to-die and within-die parameter f luctuations on the maximum clock frequency distribution for gigascale integration,” IEEE Jour. of Solid-State Circuits, 2002, pp. 183-190, Vol. 37.

11. E. Bourjot, P. Stewart, C. Dubarry, E. Lagoutte, E. Rolland, et al., “Towards a complete direct hybrid bonding D2W integration flow: known-good-dies and die planarization modules development,” Inter. 3D Systems Integ. Conf., 2019.

BiographiesPooya Tadayon is an Intel Fellow at Intel Corporation, Hillsboro, Oregon. He leads Intel’s pathfinding efforts

in assembly and test and is currently focused on assembly and test solutions for co-packaged photonics. Email pooya.tadayon@intel.com

Greg Iovino is a Principal Engineer at Intel Corporation, Hillsboro, Oregon. He is driving integrated solutions across test, manufacturing, supply chain, and business processes to drive down cost and improve quality output.

Sameer Ruiwale is a Principal Engineer at Intel Corporation, Hillsboro, Oregon. He leads manufacturing development and execution for products in Intel’s client portfolio. Sameer’s passions are overall manufacturing strategy, execution and manufacturing standardization.