More Examples Dataflow/Behavioral Modeling

Section 4.12

Schedule14 3/3 Monday More example of data flow versus behavior. 15 3/5 Wednesday Test 1L 3/6 Thursday Random number generator, mixed signal scope16 3/10 Monday Latches (1)17 3/12 Wednesday Flip-flops, L 3/13 Thursday Flip-flops, D-latch,N/A 3/17 Monday Spring breakN/A 3/19 Wednesday Spring breakN/A 3/20 Thursday Spring break18 3/24 Monday Analysis of clocked sequential circuit (1), 19 3/26 Wednesday Analysis of clocked sequential circuit (2)L 3/27 Thursday Clocked sequential circuit

Assign course project: hamming decoder.

Homework

• Hw2, hw2 & labs have been graded.• Preview the lecture materials before

the lab.

Verilog Modeling

• Verilog Modeling Styles– Gate-Level Modeling– Dataflow Modeling– Behavioral Modeling

Data Flow Modeling

Data flow modeling of a combinational logic uses a number of operatorsthat act on operands to produce desired results. The keyword assign is used frequently in the dataflow modeling.

Behavior Modeling

• Behavioral modeling represents the digital circuits at a functional and algorithmic level. It is used mostly to describe sequential circuits, but can also be used to describe combinational circuits.

• Behavioral description use the keyword always. The event control expression

• Specifies when the statements will execute.

• The target output statement must be of reg data type.

More Examples of Dataflow

Verilog HDL Operators

A and B are both 4-bit binary numbers. A_gt_B is a logic 1 if A is greater than B.A_lt_B is a logic 1 if A is less than B.A_eq_B is a logic 1 if A is equal to B.

A==B is not the same as A=B.

Partial Test Bench for mag_compare.v

Use concatenation to form a4-bit array called B.

Output

Four-Bit Adder Example

{C4,S0, S1, S2, S3)=5-bit binary number{A0, A1, A2, A3)=4-bit binary number{B0, B1, B2, B3)=4-bit binary numberC0 is a 1-bit binary number

Four-Bit Adder Output

More Examples of Behavioral Modeling

4-to-1 MUX

8-to-1 Mux

if and else example

8-to-1 MUX