MOS Field-Effect Transistors (MOSFETs) ELZ 303 - … · Microelectronic Circuits - Fifth Edition Sedra/Smith Note that the PMOS transistor is formed in a separate n-type region, known

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MOS Field-Effect Transistors

(MOSFETs)

ELZ 303 - Elektronik I

Dr. Mehmet Siraç Özerdem

Elektrik Elektronik Müh. Bölümü

Dicle Üniversitesi

Microelectronic Circuits – Fourth Edition

Adel S. Sedra, Kenneth C. Smith, 1998 Oxford University Press

Copyright 2004 by Oxford University Press, Inc.

Microelectronic Circuits - Fifth Edition Sedra/Smith

Physical structure of the enhancement-type NMOS transistor:

(a) perspective view;

(b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm,

and the thickness of the oxide layer (tox) is in the range of 2 to

50 nm.

The n-channel MOSFET

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Operation with no Gate Voltage

• Back-to-back diodes exist in series between D and S

• The path between D and S has a high resistance

Th

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The enhancement-type NMOS transistor with VGS > 0

An n channel is induced at the top of the substrate beneath

the gate.

Th

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-ch

an

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l MO

SF

ET

When VGS > Vt (threshold voltage), channel is induced

1V < Vt < 3V

Creating a Channel

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Specifically, the channel conductance is proportional to vGS – Vt’ and

thus iD is proportional to (vGS – Vt) and vDS.

Th

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Applying a small VDS



The iD–vDS characteristics of the MOSFET

The device operates as a linear resistor controlled by vGS.

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OS

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The induced channel acquires a tapered shape, and its resistance

increases as vDS is increased.

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Operation as VDS is increased


Increasing vDS causes the channel to acquire a tapered shape.

Eventually, as vDS reaches vGS – Vt’ the channel is pinched off

at the drain end. Increasing vDS above vGS – Vt has little effect

(theoretically, no effect) on the channel’s shape. Microelectronic Circuits - Fifth Edition Sedra/Smith


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iD versus vDS for an enhancement-type NMOS transistor

operated with vGS > Vt




Derivation of the iD–vDS Relationship

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Th

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Th

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iD current for Triode region

Th

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nel M

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For obtaining iD current for saturation region, take the

voltage, VDS, as follows,

iD current for saturation region

Th

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nel M

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Aspect ratio

} Process transconductance parameters

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P-channel enhancement type MOSFET (PMOS)

The p-channel MOSFET

Carrier : Holes

VDS, Vt, VGS negative values

Disadvantages of PMOS.

NMOS and PMOS in CMOS circuits

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Copyright 2004 by Oxford University Press, Inc. Microelectronic Circuits - Fifth Edition Sedra/Smith

Note that the PMOS transistor is formed in a separate n-type

region, known as an n well. Another arrangement is also

possible in which an n-type body is used and the n device is

formed in a p well.

Complementary MOS (CMOS)



(a) Circuit symbol for the NMOS.

(b) Modified circuit symbol with an arrowhead on the source

terminal to distinguish it from the drain and to indicate device

polarity (i.e., n channel).

(c) Simplified circuit symbol to be used when the source is

connected to the body or when the effect of the body on device

operation is unimportant.


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(a) An n-channel enhancement-type MOSFET with vGS and vDS

applied and with the normal directions of current flow indicated.

(b) The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2.




For Triode region

Linear correlation (linear resistance)

rDS can be controlled by VGS voltage

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The iD–vGS characteristic for an enhancement-type NMOS

transistor in saturation

For saturation region

Vt = 1 V

k’n (W/L) =1.0 mA/V2

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Large-signal equivalent-circuit model of an n-channel

MOSFET operating in the saturation region.

Microelectronic Circuits - Fifth Edition Sedra/Smith The n-channel MOSFET

Ideal model

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For the broken line characteristic


vGS - Vt = vDS

substitute it in the either triode region equation or

the saturation region equation.


The relative levels of the terminal voltages of the enhancement

NMOS transistor for operation in the triode region and in the

saturation region.


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Increasing vDS beyond vDSsat causes the channel pinch-off

point to move slightly away from the drain, thus reducing the effective channel length (by ΔL).

Microelectronic Circuits - Fifth Edition Sedra/Smith 0.03 > λ > 0.005

Th

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nel

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Effect of vDS on iD in the saturation region. The MOSFET

parameter VA depends on the process technology and, for a

given process, is proportional to the channel length L.


200V > VA > 30V


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Copyright 2004 by Oxford University Press, Inc. 28

Large-signal equivalent circuit model of the n-channel

MOSFET in saturation, incorporating the output resistance ro.


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(a) Circuit symbol of PMOS

(b) Modified symbol with an

arrowhead on the source lead

(c) Simplified circuit symbol

for the case where the source

is connected to the body

(d) The MOSFET with

voltages applied and the

directions of current flow

indicated. Note that iD flows

out of the drain terminal.


Characteristics of the p-channel MOSFET





VGS ,VDS ,Vt and λ are all negative.

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The relative levels of the terminal voltages of the

enhancement-type PMOS transistor for operation in

the triode region and in the saturation region.








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(a) Circuit symbol for the n-channel depletion-type

MOSFET. (b) Simplified circuit symbol applicable for

the case the substrate (B) is connected to the source (S).

The depletion Type MOSFET




The depletion Type n-channel MOSFET

Vt = –4 V and kn(W/L) = 2 mA/V2

(a) transistor with current and voltage polarities indicated;

(b) the iD–vDS characteristics

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The iD–vGS characteristic in saturation.



The relative levels of terminal voltages of a depletion-

type NMOS transistor for operation in the triode and the

saturation regions. The case shown is for operation in

the enhancement mode (vGS is positive).



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Sketches of the iD–vGS characteristics for MOSFETs of

enhancement and depletion types, of both polarities (operating

in saturation). Note that the characteristic curves intersect the

vGS axis at Vt. Also note that for generality somewhat different

values of |Vt| are shown for n-channel and p-channel devices.

The depletion Type MOSFET



Example

For a depletion_type NMOS transistor

Vt = - 2V

kn(W/L)=2m A/V2

a) Find the minimum VDS required to operate in the

saturation region, when VGS=1V

b) iD=?

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Example

For a depletion_type NMOS transistor

Vt = - 2V

kn(W/L)=4m A/V2

Neglect the effect of VDS on iD in the saturation region

Vs = ?



The MOSFET as an amplifier

Conceptual circuit utilized to study the operation of

the MOSFET as a small-signal amplifier.

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To find the dc bias or operating point of the MOSFET,

we set the signal vgs = 0 (assume that λ=0).




vgs ≠ 0 (assume that λ=0).

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Small-signal operation of the enhancement MOSFET amplifier



Voltage Gain


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Total instantaneous

voltages vGS and vD

for the circuit. Microelectronic Circuits - Fifth Edition Sedra/Smith



(a) neglecting the dependence of iD on vDS in saturation (the

channel-length modulation effect);

(b) including the effect of channel-length modulation,

modeled by output resistance ro = |VA| /ID.

Small-signal equivalent circuit models

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Equivalent-circuit model

Example Small signal voltage gain (vo/vi) = ?

Input resistance (Ri) = ? Amplifier

circuit


For simplicity,

ro has been

omitted

Development of the T equivalent-circuit model for the MOSFET.

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ro can be added between D and S in the T model

Development of the T equivalent-circuit model for the MOSFET.


Biasing in MOS Amplifier Circuits

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The High_Frequency MOSFET Model


The High_Frequency MOSFET Model

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The MOSFET Unity-Gain Frequency (fT)

Documents

MOS Field-Effect Transistors (MOSFETs) ELZ 303 - … · Microelectronic Circuits - Fifth Edition Sedra/Smith Note that the PMOS transistor is formed in a separate n-type region, known