MOS Gate Dielectrics

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EE311 / Gate Dielectric42 tanford Universityaraswat

Outline•Scaling issues

•Technology

•Reliability of SiO2

•Nitrided SiO2

•High k dielectrics

MOS Gate Dielectrics


Nitroxides– Nitridation of SiO2 by NH3 , N2O, NO– Growth in N2O– Improvement in reliability– Barrier to dopant penetration from poly-Si gate– Marginal increase in K– Used extensively

Fluorination– Fluorination of SiO2 by F ion implantation– Improvement in reliability– Increases B penetration from P+ poly-Si gate– Reduces K– Not used intentionally– Can occur during processing (WF6 , BF2)

Poly-Si Gate

Si substrate

Oxide N or F

Incorporating nitrogen or fluorine instead of hydrogen strengthens theSi/SiO2 interface and increases the gate dielectric lifetime because Si-F andSi-N bonds are stronger than Si-H bonds.

Incorporation of N or F at the Si/SiO2Interface

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Nitridation of SiO2 in NH3

H

• Oxidation in O2 to grow SiO2.• RTP anneal in NH3 maximize N at the interface and minimize bulk incorporation.• Reoxidation in O2 remove excess nitrogen from the outer surface• Anneal in Ar remove excess hydrogen from the bulk• Process too complex


Nitridation in N2O or NO

•The problem of H can be circumvented by replacing NH3 by N2O or NO

Profile of N in SiO2 Stress-time dependence of gm degradation of a NMOS

(Ref: Ahn, et.al., IEEE Electron Dev. Lett. Feb. 1992)

SiO2

Ref. Bhat et.al IEEE IEDM 1994

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Oxidation of Si in N2ON2O → N2 + ON2O + O → 2NO

•RTP oxidation shows N accumulation near the Si/SiO2 interface•Furnace oxidation shows almost uniform N profile ⇒lower Qbd

Ref: Okada, et.al., Appl. Phys. Lett. 63(2), 1993


B in SiO2

Si

P+ Poly-Si GateB

Thick gate oxide

Si

B

Thin gate oxide Thin nitrided gate oxide

Si

B

SiOXNY

• Incorporation of nitrogen at the interface suppresses dopant diffusionfrom gate poly-Si into the channel which can can cause VT shift.

• The problem is more serious for P+ poly-Si as boron diffuses morereadily in SiO2.

• It is desirable to use P+ gate for PMOS transistors, for scaled CMOStechnology to minimize short channel effects

Dopant Penetration From Poly-Si Gate

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Outline•Scaling issues

•Technology


•Nitrided SiO2


MOS Gate Dielectrics


High-k MOS Gate Dielectrics

Historically Cox has been increased by decreasing gate oxidethickness. It can also be increased by using a higher K dielectric

Si3N4 K ≈ 8

40 Å20 Å SiO2 K ≈ 4

!

ID"C

ox"

K

thickness

Si

Higher thickness -> reduced gate leakage

Ichannel ∝ charge x source injection velocity∝ (gate oxide cap x gate overdrive) vinj∝ CCoxox (VGS - VT) Esource µµinjinj

!

JDT"e

#tox

5


Benefits of High-Benefits of High-κκ Gate Dielectrics Gate Dielectrics

Higher-κ film ⇒ thicker gate dielectric ⇒ lower leakage and power dissipation with the same capacitance

2

2

SiO

SiO

high

high tt !""

#

$

%%

&

'=

(

()

) )

)ox

ox

t

AC

0!"

= ⇒

e-

Si substrate

source drain

Gate

VDD

15 Å SiO2e-

channelSi substrate

source drain

Gate

VDD

60 Å High-κ

e-

channel

e-

Highleakage

Lowleakage

κ = 16κ = 4

oxt

DTeJ!

"

VDD VDD

Historically Cox has been increased by decreasing gate oxidethickness. It can also be increased by using a higher K dielectric


Alternatives to SiO2: Silicon Nitride

A factor of 2 increase in K Reduction in bandgap ⇒ increased gate leakage

(Ref: Guo & Ma, IEEE Electron Dev. Lett. June. 1998)

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Nitridation of SiliconThermal Nitridation of Si in NH3

• Si reacts with NH3 to grow Si3N4– Excellent gate dielectric properties– Reaction needs very high temperatures

• Si reacts with atomic nitrogen– Reaction temperature could be reduced using nitrogen plasma– More research needed

• Several deposition methods under investigations, e.g., rapid thermal CVD,jet vapor deposition (JVD)

(Ref: Moslehi & Saraswat, EEE Trans. Electron Dev. Feb. 1985)

Id - Vg of 1.5 µm Si3N4 gate NMOS

25 Å Si3N4

Drain Voltage (V)

Dra

in C

urre

nt (m

A)

Vg = 2V

1.5V

1V

0.5V


Ref: Q. Xiang, et.al., (AMD), IEDM 2000

1.2 nm EOTGate dielectric

Id

Ig

• 1.2 nm EOT (Equivalent oxide thickness)gate dielectric can be formed by

- thermally growing ultrathin oxinitride- CVD of Si3N4

• Low gate leakage• 40 nm channel length CMOSdemonstrated

Nitride / Nitroxide Sandwich Gate MOS

Ref: M. Bohr, (Intel), IEDM 2002.

1.2 nm EOT

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Requirements for the MOS gate dielectrics• High dielectric constant ⇒ higher charge induced in the channel• Wide band gap ⇒ higher barriers ⇒ lower leakage• Ability to grow high purity films on Si with a clean interface.

• High resistivity and breakdown voltage.• Low bulk and interfacial trap densities.

• Compatibility with the substrate and top electrode.• minimal interdiffusion and reaction• minimal silicon reoxidation during growth and device processing

- even a thin SiO2 layer would deteriorate the Cgate significantly.• Thermal stresses — most oxides have larger thermal expansion

coefficients than Si.• Good Si fabrication processing compatibility.

• Stability at higher processing temperatures and environments• Ability to be cleaned, etched, etc.


Candidates for High K Gate DielectricsDielectric Permittivity Band Gap

(eV)!EC to Si

SiO2 3.9 9 3.5Si3N4 7 5.3 2.4Al2O3 9 8.8 2.8TiO2 80 3.5 0

Ta2O5 26 4.4 0.3Y2O3 15 6 2.3La2O3 30 6 2.3HfO2 25 6 1.5ZrO2 25 5.8 1.4

ZrSiO4 15 6 1.5HfSiO4 15 6 -

Ref: Robertson, J., Appl. Surf . Sci. (2002) 190 (1-4), 2

• Higher K materials have lower bandgap• There are many performance, reliability and process integration issues

yet to be solved• More research is needed to make these materials manufacturable

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Thermodynamic Stability ofHigh-K Dielectric Oxides

• Unstable oxides (e.g. TiO2, Ta2O5, BST)– React with Si to form SiO2 and silicides upon thermal annealing– Barrier (e.g. Si3N4) is required to prevent such a reaction

• Dielectric stack: poly-Si/nitride/unstable oxide/nitride/Si substrate• A monolayer of nitride on both sides of gate dielectric already contributes 5 Å to

the physical oxide thickness

• Stable oxides (e.g. HfO2, ZrO2, Al2O3) and their silicates (e.g. ZrSixOy) andaluminates (e.g. ZrAlxOy)

– Do not react with Si upon thermal annealing (up to 1000°C)– May not require a barrier layer between Si and the metal oxide

• simple structure: poly-Si/stable oxide/Si substrate

100 Å K ≈ 2075 Å K ≈ 2010 Å Si3N4


After Beyers,J. Appl. Phys. 56, 157, 1984And Wang and Meyer J. Appl. Phys. 64, 4711 , 1988

Stability of Metal Oxides with Si

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Perkins, Saraswat and McIntyre,Perkins, Saraswat and McIntyre,StanfordStanford Univ Univ. 2002. 2002

Capacitance and Leakage for High-k GateDielectric Films Grown Using ALCVD

Gat

e Le

akag

e (A

/cm

2 )

10-10

10-8

10-6

10-4

10-2

100

0 0.05 0.1 0.15 0.2

Leakage (A/cm

2) @ V

FB

± 1 V

1/C'

ox (µm

2/fF)

SiO2

4 nm

2.5 nm

ALCVD ZrO2

Gat

e C

urre

nt@

VFB

+1V

(A/c

m2 )

Equivalent SiO2 Thickness (nm)

Silicon Germanium

Chui, Kim, Saraswat and McIntyre,Chui, Kim, Saraswat and McIntyre,StanfordStanford Univ Univ. 2004. 2004


Atomic Layer CVD of Hi-Atomic Layer CVD of Hi-κκ Dielectric Dielectric

McIntyre, Saraswat, Stanford

Turbo Pump

Rotary Pump

Turbo Pump

Rotary Pump

MF

CZ

rCl 4

HfC

l 4

Pump

Throttle Valve

Loadlock

Main Chamber

Carrier Gas (N2)

MF

C

MF

C

Scrubber

H2O

MF

C

Turbo Pump

Rotary Pump

Turbo Pump

Rotary Pump

MF

CM

FC

ZrC

l 4

HfC

l 4

Pump

Throttle Valve

Loadlock

Main Chamber

Carrier Gas (N2)

MF

CM

FC

MF

CM

FC

Scrubber

H2O

MF

C

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Atomic Layer DepositionAtomic Layer Deposition

ZrCl4/HfCl4 (g)

Substrate

Reactant A(ZrCl4/HfCl4)

Reactant B(H2O)

1 cycle Time (sec)

ON

OFF

1/4 cycle :Injection of reactant A(ZrCl4/HfCl4)


Atomic Layer DepositionAtomic Layer DepositionAtomic Layer DepositionAtomic Layer DepositionAtomic Layer DepositionAtomic Layer Deposition


Reactant B(H2O)

1 cycle Time (sec)

ON

OFF

2/4 cycle :Purging (N2)

Substrate

Saturated adsorption

!+""#+" HClZrClOZrZrClOHZr34

*

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Reactant B(H2O)

1 cycle Time (sec)

ON

OFF

3/4 cycle :Injection of reactant B(H2O)

Substrate

H2O (g)HCl (g)




Reactant B(H2O)

1 cycle Time (sec)

ON

OFF

4/4 cycle :Purging (N2)

Substrate

ZrO2/HfO2 (s)

!+"#+" HClOHZrOHClZr*

2

*

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Atomic Layer DepositionAtomic Layer Deposition

ZrCl4/HfCl4 (g)

Substrate Substrate

Saturated adsorption

Substrate

H2O (g)HCl (g)

Substrate

ZrO2/HfO2 (s)

- Surface saturation controlled process- Layer-by-layer deposition process- Excellent film quality and step coverage


Microstructure of ALD HfOMicrostructure of ALD HfO2 2 and HfOand HfO22

ZrO2=29Å

Chemical oxide

Si

ZrO2

ZrO2=43Å ZrO2=82Å

HfO2=28Å HfO2=45Å HfO2=62Å

Chemical oxide

Si

HfO2

As-deposited ALD-ZrO2 is polycrystalline.

As-deposited ALD-HfO2is amorphous.

It crystallizes upon hightemperature annealing

• There is always a thin layer of chemical SiO2 present at the interface• There are charges and trap states at various interfaces and grain boundaries

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Chui, et. al., IEDM 2002

HR-XTEMHR-XTEM

0.2 0.3 0.4 0.5 0.60

100

200

300

400

Si hi-! pFET

25 µm Ge hi-! pFET 30 µm Ge hi-! pFET 100 µm Ge hi-! pFET

Si Universal Mobility

Effective Field (MV/cm)

Eff

ecti

ve M

ob

ilit

y (

cm

2/V

-s)

4 nm

HfO2

Ge

GeOxNy

High-k Gate Dielectric Can Also beApplied to Other Semiconductors

Passivation of Ge with GeOxNy, ZrO2 and HfO2 1st demo of Ge MOSFETs with hi-κ p-MOSFET with 3× mobility vs. Hi-k Si Passivation of many other materials being experimented,

e.g., carbon nanotubes, GaAs, etc.


•How good is the interface with Si? ⇒ mobility

•Contamination of Si by metal atoms

•Compatibility with gate electrode ⇒ metal gate

•Device reliability and lifetime

•Minimum EOT achievable

•Technology integration

More research is needed to make these materialsmanufacturable and reliable

Issues With High k Dielectrics

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Reduced Mobility in High- K Gate Stacks

S. Saito, et al., IEEE IEDM, 2003.

HoleElectron

Coul

ombi

c Phonon

SurfaceRoughness

µ

Eeff

srphCeff µµµµ

1111++=


Possible Sources for Reduced Mobility inHigh- K Gate Stacks

S. Saito, et al., IEEE IEDM, Washington, DC, Dec., 2003.

Extensive research is needed to understand these mechanisms andhow to minimize their impact on device performance

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Effect of Interface states on CV curves

Severe distortion, hysteresis and frequency dependence in C-V can beobserved if large number of slow states are present

This causes degradation in device properties, such as, Vt, mobility, etc.

Small density of states Large density of slow states


Effect of Slow Dit states on CV Curves

-veAcceptor

Vt shift

Effect of Cit

Decreasing frequency

Measurement is like a regular C-V setup with a DC sweep from +ve to–ve followed by a DC sweep from –ve to +ve.

Hysteresis in C-V is due to the VERY slow states that do not emptyout fast enough and cannot even respond to the slow DC sweep.

C

V

Responding toDC (Ideal)

Up-sweep

Down-sweep

Responding toDC (Actual)

Respondingto DC (Actual)

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Ref: T. P. Ma, IEEE TED, Jan 04

Effect of Interface States on Mobility inHigh- K Gate Stacks

Eeff = 0.1 MV/cm

Effect of interface traps on mobility.Coulombic scattering reduces themobility

µeff, for HfO2 and SiO2 gate MOSFETs,along with their three components,including the components limited byCoulomb scattering, µcoul, surfaceroughness scattering, µsr, and thephonon scattering, µph.


High-K/Poly-Si Gate Transistors

High-K/poly-Si gate transistors suffer from high VT, degraded channelmobility and poor drive performance

Phonon scattering limits channel mobility in high-K/poly-Si gate MOSFETs

R. Chau, Intel, ICSICT 2004

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Metal Gate Screens Surface Phonon Scattering andImproves Mobility in High-K Transistors

R. Chau, Intel, ICSICT 2004

!

1

µ=

1

µii

"


Annealing Crystallization of ALD-HfO2

As-dep 10 min 20 min

50 min 60 min 70 min

Upon annealing the amorphous films cryatsllize Grain boundaries cause statistical variation in the properties By adding other elements (e.g. N, Al, Si) to HfO2 crystallization can

be impeded

In-situ anneal at 520°C using 30Å HfO2 on 25Å thermal SiO2.

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Crystallization and Phase Separation

5 nm

55% (21-12)55% SiO2

5 nm

65% SiO2 (21-15)65% SiO2

5 nm

75 % (21-18)75% SiO2

5 nm

3.1 MX20% SiO2

B.Foran et al., ALD conference, 2004

HfO2SiO2

Si

SiO2SiO2

Non-uniformity of k-valueleads to mobility degradation

This can occure in the caseof silicates.

G.B. et al., MRS 2004


Luigi Colombo, et al.,(T.I.) IWGI Nov 2003 Tokyo, Japan

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ElectronHole

Luigi Colombo, et al.,(T.I.) IWGI Nov 2003 Tokyo, Japan

Mobility: N Incorporation in HfSiO


Summary

•Scaling issues

•Technology


•Nitrided SiO2


Documents

MOS Gate Dielectrics