University of Cyprus Holistic Electronics Research Lab

MOS Transistor Matching

Dept. of Electrical & Computer Engineering University of Cyprus

Nicosia Cyprus

http://www.ece.ucy.ac.cy/labs/holistic_elab

Julius Georgiou

University of Cyprus Holistic Electronics Research Lab

Device Size Optimized for Current Match or Voltage Match?

q Differential pair – require VGS matching q Current mirror – require ID matching

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛=

qkTVII GS

Dζ

exp0

ü  Subthreshold

( )221

THGSoxnD VVLWCI −= µ

ü  Strong inversion

ü  Current input è small ΔVGS ü  Voltage input è small ΔID

University of Cyprus Holistic Electronics Research Lab

Geometric Effects

q Large transistors match better than small transistors –  Fluctuations average out over larger area

q Long channel transistors match better than short –  Less Channel length modulation effects

q Identically oriented transistors match better –  Silicon is anisotropic and hence has different conductance in

different directions

σ Vt =CVt

Weff L eff

σ Gm =CGm

Weff L eff

University of Cyprus Holistic Electronics Research Lab

Geometric Effects q Transistors with thinner gate oxides match better

(assuming same area) –  Higher back gate doping fluctuations average out over larger

area –  Edge fringing effects are less pronounced

q Transistor orientation is important

University of Cyprus Holistic Electronics Research Lab

Etch Effects q Polysilicon does not always etch uniformly

–  Large openings etch faster than small openings in mask –  Solution is to use dummy structures

University of Cyprus Holistic Electronics Research Lab

Diffusion Effects

q Diffusion widens implanted region –  Can affect doping of neighboring devices –  Solution is to increase distance and use dummy structures that

affect all transistors the same

University of Cyprus Holistic Electronics Research Lab

Thermal Effects

q Temperature affects –  Mobility and threshold voltage –  Resistance value

University of Cyprus Holistic Electronics Research Lab

Stress Effects

q The fabrication under high temperatures may leave residual stresses in chip

q Packaging can cause stress in chip

Solutions q Keep critical matched devices in centre of chip or on

centerlines q Avoid using corners for matched devices

University of Cyprus Holistic Electronics Research Lab

Oxide Thickness Gradients

q Thermally grown oxides depend on temperature and oxidizing atmosphere

q Modern oxidation furnaces, although well controlled in temperature still have temperature gradients.

Oxide thickness on 200 mm wafer

University of Cyprus Holistic Electronics Research Lab

Dealing with Large transistors

q These can be split into many parallel fingers q Contact space is shared amongst transistors q Parasitic capacitance is reduced

University of Cyprus Holistic Electronics Research Lab

Transistor Matching?

q Example of Differential Pair ✗ Not matching with thermal gradients!!!

University of Cyprus Holistic Electronics Research Lab

Common Centroid Layouts

q Matching Won’t be good!!!

M1 M1 M2 M2

6nm 5nm 4nm 3nm

M1 Average Thickness = 5.5nm M2 Average thickness=3.5nm

University of Cyprus Holistic Electronics Research Lab

Common Centroid Layouts

q Break and distribute parts of a transistor so as to canell out the effects of oxide / doping gradient profiles.

M1 M2 M2 M1

6nm 5nm 4nm 3nm

M1 Average Thickness = 4.5nm M2 Average thickness=4.5nm

University of Cyprus Holistic Electronics Research Lab

Common Centroid Layouts

q Break and distribute parts of a transistor so as to canell out the effects of oxide / doping gradient profiles.

M1 M2 M2 M1

6nm 5nm 4nm 3nm

M1 Average Thickness = 4.5nm M2 Average thickness=4.5nm

University of Cyprus Holistic Electronics Research Lab

Common Centroid Layouts

q Averages Process Variations

University of Cyprus Holistic Electronics Research Lab

Common Centroid Layouts

q Averages Process Variations

University of Cyprus Holistic Electronics Research Lab Create Floorplan before

Implementing Layout q M1 and M2 must match q M3 and M4 must match, M6 must be wider by 4xM3 q M7 must be 2x M5

University of Cyprus Holistic Electronics Research Lab Example Common Centroid

Layout q Industrial Quality

–  Includes multiple guards –  Full common centroid –  Dummy structures

University of Cyprus Holistic Electronics Research Lab

Other good practices

q Avoid placing contacts over active gate area q Avoid routing metal over gate q Use identical finger geometries q Place transistors in close proximity q Avoid using extremely short or narrow transistors q Connect gate areas using metal straps