MRQW 2015, 27-28 January 2015, El Segundo

2015 MRQW Proceedings Corporate Staff Posted February 26, 2015

Microelectronics Reliability and Qualification Working Meeting

JANUARY 27 & 28, 2015 — THE AEROSPACE CORPORATION, EL SEGUNDO, CA

MRQW provides a forum for discussing issues in all areas of microelectronics reliability and qualification for high-reliability and commercial applications. Technical sessions and keynote speakers cover the latest results or work in progress in microelectronics devices.

Presentations not linked are not available. All documents are posted with permission.

Tuesday, January 27

• Welcoming Remarks and Overview of the Technical ProgramRonald Lacoe, MRQW General Chair and Technical Program ChairThe Aerospace Corporation

• Keynote Address: Understanding Space Radiation Effects —A Key Foundation of Mission SuccessThurman “Rich” Haas, The Aerospace Corporation

SESSION 1: DEVICE RELIABILITY Chair: Daniel Marrujo, DMEA

• Aeroflex 90nm RHBD QML-V Wafer Technology Qualification Final ReportRob Ciccariello, Aeroflex

• Mechanisms Affecting the Threshold-Voltage Stability of SiC Power MOSFETsAlvar Lelis, Army Research Labs

• 1/f Noise and Defects in GaN/AlGaN HEMTsDan Fleetwood, Vanderbilt University

• Development of Guidelines for Use of Electron (EEEE) Devices Subjected toLong-Term StorageKarl Strauss, NASA Jet Propulsion Laboratory

SESSION 2: FAILURE ANALYSIS Chair: Brendan Foran, The Aerospace Corporation

• Modern Methods for FIB Circuit EditingBrandon van Leer, FEI Corp.

• Failure Analysis of Nickel-BaTiO3 Ceramic Capacitors in theTransmission Electron MicroscopeZachary Lingley, The Aerospace Corporation

SESSION 3: PACKAGING Chair: Keith Avery, Space Vehicles Directorate, Air Force Research Laboratory

• Update on 2.5/3D Processing and Trusted Split-Fab ProcessingBob Patti, Tezzaron

1

• Soft Error Qualification of a 361-pin Flip-Chip PackageSandeep Krishnegowda, Cypress

• Reliability of Capacitors/CGA-V5 onto Substrate/PCBReza Ghaffarian, NASA Jet Propulsion Laboratory

SESSION 4: SPACE PROCESSORS Chair: Gabriel Mounce, Space Vehicles Directorate, Air Force Research Laboratory

• NASA Next Generation Flight Computing: Mission Use Case Scenario FaultTolerance ConsiderationsRaphael Some, NASA Jet Propulsion Laboratory

• AFRL’s Spacecraft Performance Analytics & Computing EnvironmentResearch (SPACER) ProjectGabriel Mounce, Space Vehicles Directorate, Air Force Research Laboratory

• ARM Solutions for, and Active Programs in the Mil-Aero, Defense, and US CommunityMel Butler, ARM

• UT840 Quad Core LEON 4FT Microprocessor First Silicon ResultsRobert Ciccariello, Aeroflex Colorado Springs

SESSION 5: EMERGING TECHNOLOGIES Chair: Joel Schulman, The Aerospace Corporation

• Compressive Sensing to Reduce the Demands for On-board Processing, Storage andCommunications LinksGeorge Valley, The Aerospace Corporation

• Single Event Effects in Carbon Nanotube-Based Field Effect Transistors under EnergeticParticle Radiation: Evidence for a New Type of Single-Event EffectAdam Bushmaker, The Aerospace Corporation

Wednesday, January 28 SESSION 6: RADIATION EFFECTS Chair: Doug Sheldon, NASA Jet Propulsion Laboratory

• Single-Event Effects in Emerging Device TechnologiesRon Schrimpf, Vanderbilt University

• Evolution of Spatial Dependence of Charge Collection Responsible for Single-EventLatchup Using a Pulsed LaserStephen Buchner, NRL

• Radiation and Reliability Analysis for Complex Systems-on-a-Chip in AdvancedSemiconductor Process NodesEthan Cannon, The Boeing Company

• Radiation Effects in Emerging Technologies for Hardened SystemsSarah Armstrong, NSWC Crane

• Numerical Simulation to Assess Risk of Single Event Burnout in Power Schottky DiodesJesse Theiss, The Aerospace Corporation

2

• Two-Photon Absorption Induced Charge Deposition in Silicon by Ultrashort Optical Pulses: Quantitative Considerations Dale McMorrow, NRL

SESSION 7: GOVERNMENT PROGRAMS Chair: Maribeth Mason, The Aerospace Corporation

• The NRO Advanced Technology Programs Group Radiation Hardened Microelectronics Program: A Status Report Lew Cohn, NRO

• AFRL Space Vehicles Space Electronics Technology Program Gabriel Mounce, Space Vehicles Directorate, Air Force Research Laboratory

• Radiation Hardening by Design, Phase 3 — Enabling Advanced High Performance Microelectronics Tony Amort, The Boeing Company

• Impacts of the Counterfeit Detection and Avoidance DFARS Requirements and Guidance for Complying with the DFARS Requirements Dave Meshel, The Aerospace Corporation

• Trusted Microelectronics Daniel Marrujo, DMEA

SESSION 8: MEMORIES Chair: Erica DeIonno, The Aerospace Corporation

• Progress and Challenges in Developing a Reliable Embedded ReRAM Memory for Hostile Environments Matt Marinella, Sandia National Laboratories

• Embedded RRAM: Data Retention and Endurance Jean Yang-Scharlotta, NASA Jet Propulsion Laboratory

• Honeywell Non-Volatile 64M MRAM Qualification Tom Romanko, Honeywell

• DDR Memory Solutions for Next Generation Space Systems Joe Marshall, BAE Systems

SESSION 9: FPGA Chair: Jon Osborn, The Aerospace Corporation

• Trusted FPGA: A Path Forward Keith Avery, Air Force Research Laboratory, Space Vehicles Directorate

• Using SEU Data to Help Determine Effective Mitigation Schemes for Complex Systems Melanie Berg, NASA Goddard Space Flight Center

• Microsemi Next-Generation Radiation Tolerant FPGAs Ken O’Neill, Microsemi

• Xilinx Space Product Qualification Update Kangsen Huey, Xilinx

3

Understanding Space Radiation Effects

-- As a Key Foundation of Mission Success --

The views and opinions expressed or implied in this presentation are those of the author and should not be construed as carrying the official sanction of the Aerospace Corporation or agencies or departments of the US government

What does Mission Success Mean to Me?

• A mission is successful when systems (or system of systems) singularly or in combination not only meet specified performance requirements, but also the expectations of the users and operators (national security, civil, and commercial) in terms of safety, operability, suitability and supportability.• Launch segment• Space segment• Ground segment• User segment

• What does mission success mean to you?

Key Contributors to U.S. Space Program Mission Success

Mission Success

Quality &Safety Program Management

• Planning, Programming& Budgeting• Acquisition• Deployment• Operations

Scientific• Investigations • Analysis

Engineering • Design • Integration • Test

Disciplined application of proven scientific,engineering, quality, and program management

Scientific and Engineering Contributions

Mission Success- Research on devices, technologies,

qualification methods- Flight project qualification requirements- System, sub-system, and component manufacturer qualification tests- Anomaly resolution

Ground Test

Test Methods & Procedures

Theory &Modeling

WorkforceExpertise

Mitigation of Effects

Flight Test& OperationsInformation

Space Radiation Effects Infrastructure Risk Assessment

Key: Likely to be OK in the 2015-2025 timeframe

Potential Risk Areas in the 2015-2025 timeframe

Mission Success- Research on devices, technologies,qualification methods- Flight project qualification requirements- System, sub-system, and component manufacturer qualification tests- Anomaly resolution

Test Methods & Procedures

Handbooks

Standards,Test

Methods

Specs

PRFs

Theory &Modeling

Radiation Transport

Space EnvironmentInteraction of Radiationwith Materials & Devices

Ground Test

Total Ionizing Dose

DisplacementDamage

Single Event Effects

University Programs

Conferences,Symposia,Workshops

On the Job Training,Staff Retention

WorkforceExpertise

Mitigation of Effects Redundancy

Serendipity

Hardness-by-Process

Hardness-by-Design

Component, Subsystem, & System Data

Flight Test& OperationsInformation

Flight Anomalies –Root Cause

Flight Experiments

Challenges to the Community• Accept that our space radiation effects testing infrastructure is at significant risk and steps need to be taken that reduce that risk

• Knowledge of radiation effects is an essential element of: “Create an environment that will deliver 100% mission success.”*

• Leave the MRQW with a commitment • Work with your colleagues to form a united front & address the identified shortfalls

• Government• Industry• Academia

• Communicate to your leadership that action is required now, and help them take it• Continue to push the boundaries of what is known toward what needs to be known• Ensure that you rigorously implement appropriate proven practices

*U.S. Space Program Mission Assurance Strategic Intent

Backup

National Security Space Acquisition Enterprise

Foreign

JUDICIAL LEGISLATIVE

DOJ

USCG

DEASAFAQS

14th AF

Commercial

NASA

FBI

NSC OMB

DHS

USAF

DOD

EA4SS

EXECUTIVEOffice of the President

WH/CoS Other

OSD

STRATCOM

ODNI

COCOMS

SSI

CA&PE R&E

OtherOtherOther IC

NGA CIA

USD(I)

SPAWAR

DOT DOS Treasury

AT&L

24th AF

SMC

C3CB

USN

DISACIO

USAUSMC JCS

AFSPC

20th AF

AFGSC

AFMC

AFRL

NOAA

DOC

AFNWC

USD(P)

NRO

OSTP

OtherOtherOtherDOE

SE

NSADARPA

MDA DIA

The most important thing we build is trust

ADVANCED ELECTRONIC SOLUTIONS AVIATION SERVICES COMMUNICATIONS AND CONNECTIVITY MISSION SYSTEMS

Cobham 90nm RHBD QML-V Wafer Technology Qualification Final Report

Cobham Semiconductor SolutionsPresented at Aerospace Corporation – MRQW Presenter:Rob Ciccariello

January 2015

Cobham plcCobham plc

Thank You to our sponsors and supporters

1

http://www.nro.gov/index.html

http://www.nro.gov/index.html


90nm RHBD QML-V Wafer Technology Qual

• Develop, characterize, productize and qualify a Radiation Hardened-by-Design (RHBD) 90nm digital library:

– Demonstrate the reliability of the IBM 9SF process for aerospace – Develop a QML Qualified ASIC design flow and toolkit for the

90nm RHBD Library – Develop a QML-V Qualified production capability for the production

of ASICs to make the technology available for aerospace users – Qualify the new technology (Silicon & Package) through the

testing of a Standard Evaluation Circuit (SEC).

90nm P&Q Program Objectives

25 February 20152

•Result: 90nm QML-V ASIC design and manufacturing infrastructure is now available to meet aerospace system needs



• QML-Q approved by DLA-September 2014• QML-V Wafer Technology Qualification submittal December 2014• Quad Core LEON 4FT characterization complete• Class Y qualification project started• UT90nHBD ASICs being designed-in

– 90nm Customer ASIC Design in place and route• UT1752FC package PDR complete• SerDes UT90nHBD library toolkit available

– Includes IBIS AMI models

Cobham Semiconductor Solutions 90nm Highlights

25 February 20153


90nm RHBD QML-V Wafer Technology Qual90nm RHBD ASIC Path to QML-V

25 February 20154

Radiation Test Complete

Beta CustomerToolkit

CustomerToolkit Released

QML-Q

Netlist

H1 H2 H1 H2CY-2011

H1 H2 H1CY-2012 CY-2013

Final Report

CY-2014

Wafer Lot 1 (WB)

Design Start

HFSEC WB Tapeout

QML Fab Audit

WLR Test CompletePkg Test Complete

FMEA & Test Plan

WafersLot2 - WB

LEON & LTC-FCSEC Tapeout

Toolkit Silicon VerificationComplete

Wafer Lot3(FC)

Electrical Test Complete

H2 H1

QML-VSubmittal

Wafer Fab TechnologyQualification 3 Fab Lots

Quad Core LEON & HFSECFC Fab/Test

Library / ToolkitHFSEC WB Fab/Test

Reliability Demonstration TCV Silicon



• Cobham developed a FMEA based three phase approach to the 9SF reliability demonstration

Reliability Demonstration Methodology

25 February 20155

•Phase 3

•Phase 2

•Phase 1Physics of Failure Study / FMEAIdentified 32 Total Risk Areas

2 Fab Quality Concerns

8 RadiationConcerns

4 PackagingConcerns

3 ProductDesignConcerns

15 Risk Areas Need Additional Data

Boeing90nm RHBDData

90nm P&QPkg Char

IBM Data Analysis90nm P&QSEC Char& Qual

90nm P&QFab Audit

5 AreasLow RiskNo Further Data Needed

9 AreasPhase 3Test Plan Data Collection

2 AreasMaterialAnalysis

7 AreasElectricalTesting

90nm P&QLTC Design& Test

1: Complete Physics of Failure Study and Develop FMEA

2: Leverage available foundry reliability data

3: Collect Additional Electrical Test Data



• FMEA results on 9SF Back End of Line (BEOL) technology items included in phase 3.

Reliability Demonstration Results

25 February 20156

• All FMEA items included in reliability demonstration had reduced RPN at conclusion.

Phase 1 Phase 2 Phase 3

Process /Design Function Potential Failure Mode

Sev.

Occ.

Det.

R. P. N.

Sev.

Occ.

Det.

R. P. N.

Sev.

Occ.

Det.

R. P. N.

comments

BEOL Issues

Liner integrity Copper in metal lines is able to diffuse through weak liners and cap through ILD causing transistor upset or line to line breakdown.

7 5 5 175 7 1 5 35 7 1 5 35

Electromigration Copper resistivity and EM robustness is superior to Aluminum, but copper has issues that Al does not have.

7 3 4 84 7 2 4 56 7 1 4 28 Wafer level data shows >> 15 year life

Stress Voiding (via voids) Copper can be mobile at high temps and stress related voids can form.

7 3 4 84 7 1 4 28 7 1 4 28

Stress Voiding (line voids)

Copper can be mobile at high temps and stress related voids can form.

7 3 4 84 7 1 4 28 7 1 4 28

Copper corrosion Copper in lines can be corroded by chemicals in CMP, can interact with Ta in presence of electrolyte.

5 1 5 25 5 1 5 25 5 1 3 15 Reduced detection because Aeroflex has plans to x-section every lot

Lithography Capability Variation in min space dimensions. 5 2 2 20 5 2 2 20 5 1 2 10 Cross-sections look clean



• 90nm design system involves documentation and validation throughout the design process

90nm RHBD ASIC Flow

25 February 20157

IP Cell LibraryLiberty models:NLDM&CCS

Verilog models

Physical ViewsFRAM views, TLU-Plus,

Floor Planning

MethodologyReference Scripts

Flows

DocumentationData Sheets

Instructions & App Notes

RHBD MethodsDesign Guidelines

IP Usage Guidelines

CustomerCheckLists

DesignFor Test

Customer

Toolkit

Timing ClosureRC Extraction,Aging Models

Physical DesignGDS-II, Tech Files,

Reliability Design Rules

Design FlowsPlace & Route / Power Del

Timing Opt./Closure

DocumentationP&R MethodsTool Settings

RHBD MethodsSEU / SET Avoidance

Analysis scripts & tools

ASIC MfgCheckLists

LVSDRC

ASIC Physical D

esign

Final Sign-OffCustomer Check Lists, DFT/Fault Grade Results, Timing Analysis, Library

Rules Checker, Tester Patterns, LVS/DRC logs, Reliability Rules, RHBD Results,...


90nm RHBD QML-V Wafer Technology Qual90nm RHBD ASIC Flow

25 February 20158

• UT90nHBD ASIC flow radiation hardening based on library characterization and chip level analysis

1:Library Characterization• Prompt Dose\SEL• TID

Requirement FF SEU FF SET SRAM Reset SET Clock SET PLL Total

Recoverable Error Rate (Error/device-day) 7.0E-04 3.2E-05 3.1E-05 1.9E-05 1.9E-07 3.4E-07 1.6E-05 9.8E-05Data Integrity Error Rate (Error/device-day) 0.25 9.6E-05 9.2E-05 1.7E-04 1.9E-07 3.4E-07 1.6E-05 3.7E-04

SRAM Bits 4,598,272 Control DataSystem

Derating*Utilization Factor**

SRAM 10% 90% 20% 100%PLL's 3 Logic 25% 75% 20% 100%Latches & FF's 155,045 DICE FF's 126,884 DICE Latches 28,161 MBIST FF's -

DICE FF's or Latches w/o Data Filter 41,100 Clock Frequency (MHz)Control

DeratingSystem

DeratingGates 1,157,450 266 25% 50%Gates/FF 7.47

* System Derating accounts for bits that are not accessed Reset SET Rate 1.93E-07 after upset or do not propagate to a detection point.Clock SET Rate 3.44E-07 ** In this case the utilization factor is 100%

Composite SRAM Bit Error Rate 2.06E-10Raw SRAM Bit Error Rate 1.84E-06FF SET Bit Error Rate (44ps) 1.48E-08 Intel estimate 10%FF SET Bit Error Rate (280ps) 5.83E-14 IBM Server Estimate 40%FF SEU Bit Error Rate 4.56E-09 SDC estimate 50%

Clock RE Derating

2: Chip Level Analysis• Adjust Drive strengths• SEE\SET filter additions• Clock\Reset Tree Hardening



• UT90nHBD designs for reliability by adding timing margin based on models developed during the reliability demonstration

90nm RHBD ASIC Flow

25 February 20159

𝑖𝑖𝑖𝑖 𝑉𝑉𝑔𝑔𝑔𝑔 > 𝑉𝑉𝑡𝑡 , ∆𝑉𝑉𝑡𝑡 = 𝐴𝐴𝑉𝑉𝑔𝑔𝑔𝑔𝛽𝛽𝑒𝑒

𝑒𝑒𝑎𝑎𝑘𝑘𝑘𝑘 𝑡𝑡𝑛𝑛 ,

𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 (∆𝑉𝑉𝑡𝑡 = −0.3 ∗ 𝐴𝐴𝑉𝑉𝑑𝑑𝑑𝑑𝛽𝛽 𝑒𝑒

𝑒𝑒𝑎𝑎𝑘𝑘𝑘𝑘 𝑡𝑡𝑛𝑛)

Logic

Setup Time checks: 7.25% deratingMax PVT corner = SS / 0.9V / 125C

set_timing_derate -late -data -cell_delay 1.0725

DQDQ1: Develop physical models

2: Implement models in SPICE (MOSRA) and validate in silicon

3: Incorporate timing margin into static timing analysis



• Cobham received DLA approval for Colorado Springs Assembly Manufacturing and IBM 9SF foundry processing.

Qualified Manufacturing Capability

25 February 201510

• Initial IBM fabrication audit performed June 2012, with latest follow up audit completed in 2014.• Colorado Springs assembly

manufacturing re-certified to QML-V in 2014.



• Cobham developed a multipurpose design (LTC\HFSEC) for all parts of the program

– Library Test Vehicle (LTC): Used for library electrical characterization and radiation effects testing• LTC\HFSEC allows direct access to all cells in the library, and contains

separate structures for single event testing

– Standard Evaluation Circuit (SEC): Meet mil-standard requirements for complexity, toggle coverage, and operating frequency• LTC\HFSEC designed with this in mind, High Frequency operation

allowed addition of “HF” to SEC.

• LTC\HFSEC designed with flip chip in mind, allowing it to be used as the flip chip package technology qualification vehicle

SEC Design \ Qualification

25 February 201511

Reduced material cost, shortened learning curve for each development activity



• The UT90HBD library was qualified to MILPRF 38535 Rev J– SEC must contain one half of maximum transistors expected for

largest microcircuit on technology– SEC must operate at maximum frequency while in life testing


25 February 201512

• HFSEC covers both complexity and high frequency operation.• HFSEC designed to allow wire

bond and flip chip packaging to enable comparison during qualification.



• The HFSEC contains 91,356,675 total transistors


25 February 201513

• The HFSEC uses a PLL to drive the blocks during life test

– Max frequency path 889MHz• Achieves >93.8% toggle

coverage while in life test• Each cell in the library is

available for direct measurement.

Transistor Type Description CountLVTNFET Low Threshold Thin Gate NMOS 10,960,000LVTPFET Low Threshold Thin Gate PMOS 10,940,000RVTNFET Std. Threshold Thin Gate NMOS 44,610,000RVTPFET Std. Threshold Thin Gate PMOS 24,830,000DGNFET 2.5 V I/O (Thick Gate) NMOS 9,656DGPFET 2.5 V I/O (Thick Gate) PMOS 5,960DGVNFET 1.8 V I/O (Thick Gate) NMOS 56DGVPFET 1.8 V I/O (Thick Gate) PMOS 68EGNFET 1.5 V I/O (Intermediate Gate) NMOS 66EGPFET 1.5 V I/O (Intermediate Gate) PMOS 222MPNFET High Speed Thin gate NMOS 418MPPFET High Speed Thin gate PMOS 88ZVTNFET Thin-oxide zero-Vt NFET 44ESDVPNP Vertical PNP for ESD 97

HFSEC qualification defines library envelope to be ~182 million transistors with a maximum operating frequency of 1.1 GHz.



• High frequency operation of a high density, ultra-deep submicron chip at 125C ambient raises concern for thermal run away.


25 February 201514

• HFSEC contains a thermal resistor to allow direct measurement of junction temperature

• Cobham designed and qualified a new life test system to dynamically monitor temperature and supply power individually to each chip

• System includes active heating and cooling for better temperature control and socket heat sinks

ATX Driver Board

HFSEC draws ~3A core current under life test conditions. No sign of runaway was seen out to 4000 hours stress



UT90nRBD Library completed QML-Q qualification in October 2014– SMD currently listed on DLA website (5962-14B01)

Qualification Results

25 February 201515

Datasheet atwww.aeroflex.com/RadHardASIC



9SF QML-V wafer technology qualification testing complete.• Data collected from 3 IBM

fabrication lots• Two SEC lots built as wire bond,

with third built as flip chip All results meet specifications

Qualification Results

25 February 201516

QML-V packet submitted December 2014



• Cobham offers a standard die frame to enable cost savings through reuse and standardization (package and silicon)

Availability to Industry

25 February 201517

8 x Quad lane SerDes3.125 Gbps per lane

IO bank structures• LVDS• LVCMOS

Other IP: • Temperature monitor• PLL’s• SP & DP SRAM and

Register Files

Core logic to 30M gates

Logic Area for Tightly Constrained I/O Pin Timing



• Standard reticle allows multiple designs on same wafer, with small die for other products or test chips

Availability to Industry

25 February 201518

Max Reticle32.3mm x 23.5mm

UT1752FCDie #1

UT1752FCDie #2

SmallDie #3

SmallDie #4

SmallDie #5

SmallDie #6

•UT1752FC Reticle

•UT1752FC – 16.075mm x 18.180mm•Small Die – 7.962mm x 5.170mm



• Cobham continues developing capability for 90nm

Next Steps

25 February 201519

• SerDes – Required IP for customer

design in process– Exceeds HFSEC frequency

envelope, qualification required

• Class Y Qualification– Non-Hermetic flip chip required

for high power devices– ECD December 2015

UT1752FC Package Scheme

SerDes 4 lane Macro


UT840 LEON Quad Core First Silicon Results

• The Cobham 90nm P&Q program has completed QML-V qualification testing and the UT90nRBD library is being used in the industry.

• Program spanned entire range of micro-circuit industry– From transistor level and fab processing to advanced packaging

and stress/test methodologies

• Cobham continues developing capability for this technology

• Thank You!

Summary

25 February 201520

1/f Noise and Defects in GaN/AlGaN HEMTs Dan Fleetwood

Department of Electrical Engineering and Computer ScienceVanderbilt University

Work performed in collaboration with:Jin Chen, Tania Roy, Enxia Zhang, Yevgeniy Puzyrev,

Sokrates Pantelides, and Ron Schrimpf, Vanderbilt UniversityErin Kyle, Brian McSkimming, Stephen Kaun, and James Speck (UCSB)

This work was supported by the Air Force Office of Scientific Research and the Air Force Research Laboratory through the HiREV program, by the Office of Naval Research through the DRIFT MURI program, and by DTRA through its basic mechanisms program.

Outline

• Background and Motivation• Temperature Dependence• Defect energy scales• Defect energy levels

• As processed• Proton irradiated• High-voltage stress

• Summary and Conclusions

GaN/AlGaN HEMTs

Ga-rich PAMBE process; GaN/AlGaN HEMTs with passivated trench gates on SiC substrateDevices from Speck group at UCSB

HC Stress and Proton IrradiationsLow Frequency NoiseDFT CalculationsDefects control

long term reliability

Gate voltage dependence of 1/f noise

When RU > RG, but SRG> SRU:

UUGtotal RG

GGRRR S

fNRSSS +=+=

2α

fNRS

VS RV α

== 22

UoffGSch

offgateUGtotal R

VVnWqVL

RRR +−

=+=)(µ

When RU < RG, but SRG> SRU:

SR ∝ (VG –Voff)-1

SR ∝ (VG –Voff)-3

Empirical relation:

T. Roy, et al., “1/f noise in GaN HEMTs grown under Ga-rich, N-rich, and NH3-rich conditions,” Microelectron. Reliab. 51, 212-216 (2011).

Temperature Dependence of I-V and Noise

1/f Noise Occurs due to Superposition of RTS

• Single active trap• Random Telegraph Signal in the time domain• Lorentzian spectrum in the frequency domain

• Multiple active traps• 1/f spectrum by superposition of Lorentzians

221)(

ωττω

+∝S

∫ +∝ ττ

ωττω dDS )(

1)( 22

Bernamont J. (1937) Fluctuations de potential aux bornes d'un conducteur metallique de faible volume parcouru par un courant. Ann. Phys. (Leipzig), 7:71-140.

Review of Dutta-Horn Model

If the time constant is thermally activated

For D(E) varying slowly compared to kBT, S(ω) ~ 1 / f α , with α ≅ 1.

Dutta and Horn:

Energy distribution:

[P. Dutta and P. M. Horn, Rev. Mod. Phys. 53:497, 1981]

)/exp(0 kTEττ =

fS

ln)(ln

∂∂

−=ωα

)1lnln(

)ln(11),(

0

−∂∂

−=TST V

ωτωα

),()( 0 TSTk

ED VB

ωω∝

Defect Related Noise Peaks in AlGaN/GaN

Noise vs. T

Defect energyLow T ~ 0.2 eVHigh T ~ 0.85 eV

50 100 150 200 250 300 350 400 450 5002E-15

3E-15

4E-15

5E-15

6E-15

7E-15

8E-159E-151E-14

Svd*

f/T (V

2 /K)

T (K)

E0 (eV)0.232 0.348 0.464 0.580 0.696 0.812 0.928 1.044

Comparison with Dutta-Horn Theory

Compare frequency exponent (γ) extracted fromExperimental dataDutta Horn model calculation

Good self-consistencyNoise typically associated

with thermally activated defect reconfiguration.

Energy set by50 100 150 200 250 300 350 400 450 500

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

Experiment Dutta Horn

gam

ma

T

What is Eo?

Eo

M. B. Weissman, Rev. Mod. Phys., vol. 60, pp. 537-571, April 1988

Low-Energy Defect in AlGaN/GaNDensity functional calculations

• (left) Defect energy of substitutional O in AlGaN vs.distance from ideal lattice site, for (right) an O DX configuration. Black squares are transition points between charge states of ON during electron emission. Energy barrier to emit one electron from negatively charged O DX center ~0.25 eV. Likely candidate for low-T peak.

OAl

Ga

N

High-Energy Defect in GaN/AlGaN?VGa-ON-H

Hybrid Functional calculation Egap = 4.7 V

Localized state for [VGa-ON-H]-2 .

CBM(GaN)

LDA

Level Ec - 0.7 eV

LDA state for [VGa-ON-H]-2 is delocalized

Proton irradiation dehydrogenates ON defects

50 100 150 200 250 300 350 400 450 5000.1

0.2

0.4

0.60.8

1

2

E0(eV)

Pre 1x1013

5x1013

1x1014

Svd*

f/T (1

0-14 V

2 /K)

T (K)

Ga-rich

Vd = 0.15 VVg-Vpinch-off = 2 V

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

N vacanciesand ON

(increase)

VGa-ON-H(decrease)

J. Chen, Y. S. Puzyrev, C. X. Zhang, E. X. Zhang, M. W. McCurdy, D. M. Fleetwood, R. D. Schrimpf,S. T. Pantelides, S. W. Kaun, E. C. Kyle, and J. S. Speck, “Proton-induced dehydrogenation of defects in AlGaN/GaN HEMTs,” IEEE Trans. Nucl. Sci., vol. 60, no. 6, pp. 4080-4086, Dec. 2013.

50 100 150 200 250 300 350 400 450 5004

68

10

20

40

60

Eo(eV)

Before Stress 15V 20V 25V 30V

Svd*

f/T (1

0-15 V

2 /K)

T (K)

0.120.230.350.470.580.700.810.931.051.16

High-field stress increases defect densityDehydration (low-E); H migration (high-E)

VD

1 h

VN-FeGaVGa-VN

ON

VGa-ON-H

J. Chen, Y. S. Puzyrev, E. X. Zhang, D. M. Fleetwood, R. D. Schrimpf, S. T. Pantelides, A. R. Arehart, S. A. Ringel, S. W. Kaun, E. C. H. Kyle, and J. S. Speck, Work in Progress.

Conclusions

• Point defects and hydrogen-defect complexes are quite significant to GaN/AlGaN reliability

• Changes in defect density can be observed due to irradiation and high-field stress via temperature-dependent 1/f noise measurements.

• Experiments and density functional calculations provide evidence of dehydrogenation of defects, and formation of new complexes via H transport

DEVELOPMENT OF GUIDELINES FOR USE OF ELECTRON (EEEE) DEVICES SUBJECTED TO LONG TERM STORAGE Karl F Strauss California Institute of Technology Jet Propulsion Laboratory

Copyright 2014 California Institute of Technology

“Today’s electronic components rely on principles of physics and science with no manufacturing precedence and little data on long term stability and reliability.” [Fozard] With Little Knowledge and perhaps a dangerous amount of Hope, we are placing our bets that electronics we will need decades from now will be ready for use; and we are just now calling in our bets that electronics we stored decades ago are now up to the task. [Fozard]

2

Long-Term Storage: How Old Can You Go?

AGENDA I.  Introduction II.  Impetus III.  Research and Method IV.  First Findings V.  Further Study VI.  Conclusion VII.  Acknowledgements

3

Development of Guidelines for Use of Electron (EEEE) Devices Subjected to Long Term Storage

With 10 Major Research Centers (such as the Jet Propulsion Laboratory & Glenn Research Center) and numerous other facilities, NASA truly is in the Parts Business – not only using them, but storing them as well. As of last June, JPL had in its own Flight Electronic Component Stores facility over 2 Million Devices. Devices designed, tested and qualified for Space application (Classes S, V, and K) This same tale is told again and again for every NASA Center – for every contractor of every center. For an Institution as advanced as NASA, there are no guidelines for the use of devices that have been subjected to Long-Term Storage CAN THE RISKS ASSOCIATED WITH LTS-devices BE DEFINED?

4

II. IMPETUS The Tale Twice Told

COMPLICATING THE ISSUE is that the Market Share of Aerospace/Hi-Rel Components has been shrinking or collapsing, causing Institutions, e.g. JPL, to rely more and more on Commercial Grade or Industrial Grade components.

5

The Tale Twice Told – Only More Complicated

[McCulskey]

0

50

100

150

200

250

300

2008

2009

2010

2011

2012

2013

2014

2015

2016

Worldwide Automotive Electronics Market ($Bn)

International

CANAMEX

[Day]

LTS: Defined •  The very definition of Long-Term Storage is as flexible as there are Dialects •  For the purposes of this study, Long Term is defined as anything kept in a non-energized state for a

continuous period of 5 Years or more •  Everything from Desk Drawers to Barns to tightly sealed Moisture Barrier Bags

•  Based on the Research into the Body of Knowledge, can a Reasonable, Affordable, and Enforceable set of Guidelines be developed for application NASA-Wide on the use of LTS devices? •  How Old is Too Old? •  What Reassurances (tests) are necessary to ensure Mission Assurance that devices in hand are just as reliable –

and usable – as devices brand new?

6

Long-Term Storage: Defined

[RetroAudioLab.com]

A 1925 mica capacitor – still offered for sale [partsdiver.com]

[propertycasualty360.com]

LTS: Defined •  The very definition of Long-Term Storage is as flexible as there are Dialects •  For the purposes of this study, Long Term is defined as anything kept in a non-energized state for a

continuous period of 5 Years or more •  Everything from Desk Drawers to Barns to tightly sealed Moisture Barrier Bags

•  Based on the Research into the Body of Knowledge, can a Reasonable, Affordable, and Enforceable set of Guidelines be developed for application NASA-Wide on the use of LTS devices? •  How Old is Too Old? •  What Reassurances (tests) are necessary to ensure Mission Assurance that devices in hand are just as reliable –

and usable – as devices brand new?

7

Long-Term Storage: Defined

[RetroAudioLab.com] [propertycasualty360.com]

$

Age

Increased Cost due to NRE Increased Cost due to higher Risk


8


•  125 Journal Articles were Read and Catalogued •  17 Telephone and In-Person Interviews were Conducted •  4 Facility Tours Conducted •  Countless E-Mails from Academia and Institutional Experts

•  Aerospace to Automotive, Computers to Radios

•  Professional Affiliations – Committees Joined and Active •  JEDEC JC-14 (Quality and Reliability of Semiconductor Products) •  SAE G-21 and TEASSTCG12 (Long Term Storage Guidelines) •  IEC

9

III. RESEARCH AND METHOD

THERE IS A LOT OF INTEREST IN THIS TOPIC WHETHER BASED UPON BUDGET RESTRICTIONS OR SCHEDULE RISK REDUCTION, EVERY INSTITUTION CONTACTED IS EITHER DEVELOPING OR ALREADY HAS IMPLEMENTED A GUIDELINE ON THE USE OF LTS DEVICES •  All over the Map

•  Don’t Use At All - to - Hey Whatever! •  Difficult to Assess Risk to Budget and Schedule •  Especially when More than One Institution is Involved

10

III. RESEARCH AND METHOD

images courtesy [jimwilliams.blogspot.com]


11


With a few exceptions (below), this investigation could find no compelling evidence to distrust components that have been subjected to Long-Term Storage

Provided that they are properly stored è SEALED MOISUTRE BARRIER BAGS with DESICCANT

MAJOR FINDINGS •  Solderability: Of 389 Components stored for a period of 17 years, only 4 did not pass initial

solderability requirements [Anderson] •  Capacitors: Anecdotal evidence shows epoxy sealed, wound film capacitors may experience

swelling due to moisture intrusion •  Resistors: One instance of Wirewound capacitor shorted to Aluminum case due to LTS in

heated area •  Semiconductors: Moisture Intrusion in Package is Largest Culprit

•  Delamination and Popcorning due to improper bake-out •  Bond-wire corrosion •  Shift in Radiation Tolerance

12

IV. FIRST FINDINGS

All photos courtesy Hi-Rel Labs

FIRST FINDINGS Additional Findings

13

KNOWN ISSUES RELATED TO LONG TERM STORAGE Technology Focus Hazard Issue Seen In / Seen By Suggested Remedy Die Bond Pads Corrosion Visual MOS and Bipolar Reduction of TID Moisture intrusion

reduces TID significantly over time

Witnessed by effective energy increase in field oxide leakage

Re-run Radiation Lot Acceptance Test (RLAT)

Capacitor, Molded Ceramic

End-Cap Delamination Visual Inspection Visually Inspect before use

Oscillators, Crystal Frequency, stability Frequency shift due to moisture on crystal surface

Electrical check Electrical check. RGA if lot permits

Microcircuits, Hybrid Electrical Performance Out of bounds. Electrical check Perform RGA. If insufficient to obtain usable statistical result: reject lot.

Microcircuits, Monolithic (non-PEM)

Electrical Performance Out of bounds. Electrical check Perform RGA. If insufficient to obtain usable statistical result: reject lot.

Microcircuits, Monolithic, PEM

Mechanical fail of frame or wire bonds

Package deformation due to moisture engorgement distorts frame and or strains/snaps wire bonds.

Electrical check Perform X-ray & C-SAM. If insufficient to obtain usable statistical result: reject lot.

Relay, electromagnetic, non-sealed

Contact resistance Oxidation of surface Visual inspection Perform numerous cycles then re-examine

Transistors, metal case Leakage, moisture Change in characteristics; intermetallic corrosion

DPA, RGA Perform DPA and RGA; if insufficient lot to promote statistical validity, reject lot.

!

CAUTION PHOSPORUS •  The Avoidance of any plastic package device with Lot Date Codes indicating packaging and

assembly from late-1999 to 2003

WHY?

•  Manufacturers introduce Bromine-based compounds for flammability reduction •  Bromine fell fast out of Favor due to Environmental Contamination •  In 1996, use of Red Phosphorus as a Fire Retardant was developed •  In 2001, Fairchild Semiconductor issued the first of many Product Alert Notices that Plastic

packages were experiencing an unprecedented rate of frame and bond failures •  Traced to Phosphoric Acid being formed by moisture and exposed Phosphorus promoting corrosion and

dendritic growth

FIRST FINDINGS

14

[theriac.org]

Testing by numerous parties show a notable shift in radiation tolerance due to moisture intrusion •  In some cases the intrusion of Hydrogen – Oxygen is disruptive to the device Oxide and

alters electrical characteristics and radiation response

Modeling from Pantelides shows disruption of oxide bonds during (a) and (b) and after (c) Oxygen intrusion

Disruption increases number of Traps at the Interface increasing leakage Decreasing Total Ionizing Dose tolerance

THIS IS ESPECIALLY TRUE OF MODERN Hi-K DIELECTRICS

15

FIRST FINDINGS: SEMICONDUCTORS – Radiation Tolerance

[Pantiliedes]

[Driemeier]

THE DAMAGE IS IRREVERSIBLE

•  Are We Crying Wolf?

•  In many cases, the number of devices tested in published reports is in the two’s and three’s •  Too few to draw a strong mathematical reference – but rather counting on a strong inference

16

FIRST FINDINGS: SEMICONDUCTORS – Radiation Tolerance

Study Number of Devices Anderson 389 Batyrev 6 Casanovas 65 analog, 21 digital Djoric-Velijkovic 30 Jones 10 McCulskey 10

AGENDA I.  Introduction II.  Impetus III.  Research and Method IV.  Findings V.  Further Study VI.  Conclusion VII.  Acknowledgements

17


ANALYSIS OF DATA SUGGESTS THESE AREAS MAY BE WORTHY OF FURTHER INVESTIGATION

18

V. AREAS CONSIDERED FOR FURTHER STUDY

TECHNOLOGY* ISSUE* CAUSE* REALM* PROPOSED*INVESTIGATION*

Field*Programmable*Gate*Array,*Antifuse**

Inability)to)complete)programming)

Ability)to)program)compromised)by)excessive)ONO)element)leakage)

Electrical) Perform)programming)on)devices)that)have)been)subjected)to)LTS)

HiFK*Dielectrics**

Shift)in)radiation)tolerance)

Water)vapor)attracted)to)surface)of)HiDK)dielectrics)degrading)TID)

Electrical/)Radiation)

Perform)TID)on)PEM)encapsulated)devices))

)


19


Over 125 papers reviewed, interviews and surveys conducted •  Evidence strongly suggests that the use of LTS devices which have been properly stored may

be done so with little risk to the board or element. •  That cursory examinations, such as visual and solderability, should be performed as a matter

of course. •  That C-SAM for Plastic and RGA for Hermetic is recommended

•  Some studies show a significant change in radiation characteristics attributed to moisture intrusion – but these studies are not without outside comment or controversy due to possibly improper storage, characterization or limited lot size.

A course of further study was recommended.

THANK YOU Pre-Print Copies of the Report for the SAE Aerospace Journal, Sp. 2015, upon which this presentation is based can be obtained by emailing the author.

[email protected] kindly include LTS in the Subject line.

20

VI. CONCLUSION


21


The Author wishes to thank California Institute of Technology Jet Propulsion Laboratory, Pasadena California and NASA Electronic Parts Program (NEPP) for funding and support

http:///nepp.nasa.gov And these individuals in particular Dr. Mark White (JPL) Dr. Douglas Sheldon (JPL) Dr. Charles Barnes (JPL) Dr. Michael Sampson (GSFC) U.S. Government Sponsorship Acknowledged

22

VII. ACKNOWLEDGEMENTS

BIBLIOGRAPHY (first author)

Batyrev, I.G., Effects of Water on the Aging and Radiation Response of MOS Devices, 2006 Day, J., Strategy Analytics predicts growth in automotive electronics, 2012 Driemeier, C., Room temperature interactions of water vapor with HfO2 films on Si, 2006 Fozard, D., Do You Know Who Is Storing Your EOL Parts?, 2011 Hillman, C., White Paper: Red Phosphorus Induced Failures in Encapsulated Circuits, 2012 McCluskey, F.P., Reliability Assessment of Electronic Components Exposed to Long-Term Non-Operating Conditions. 1998 Pantiliedes, S., Performance, Reliability, Radiation Effects, and Aging Issues in Microelectronics – From Atomic-Scale Physics to Engineering-Level Modeling. 2009

Additional thanks to Roger Devaney, Hi-Rel Labs

23

Bibliography

24

A Useful Way to Use Old, Unwanted Components

Copyright: Honeywell

© 2015 The Aerospace Corporation

Failure Analysis of Nickel-BaTiO3 Ceramic Capacitors in the Transmission Electron Microscope

Zachary Lingley, Jesse Theiss, Talin Ayvazian, Miles Brodie, Brendan Foran

The Aerospace CorporationMicroelectronics Technology DepartmentElectronics and Photonics Laboratory

MRQW 2015, January 27-28, El Segundo, CA

[email protected] Technology Department

Outline1. Why we are doing failure analysis on BME MLCCs

2. Conventional Failure Analysis of life-tested BME MLCCs

3. Real-time in-situ failure analysis of nano-scale specimens in the transmission electron microscope

A. Specimen preparation B. Simultaneous structure and electrical measurementsC. Electron beam induced current mapping and results of tests

on BME samples

4. Conclusions


3 mm 1 mm

Why we are doing failure analysis on BME MLCCs

• BMEs are ubiquitous in modern electronics due to low cost and high energy density andfeature more advanced dielectric formulations than precious metal electrode (PME)MLCCs

• Reliability Issues may be associated with

• Extrinsic problems: voids in the dielectric, Ni electrode roughness andvariations in dielectric thickness that lead to localized high electric fields

• Intrinsic problems: resistance degradation associated with oxygenvacancies, large grain size distribution, inhomogeneous distribution ofchemical additives/dopants.

Yang et al., 2004, JAP 96, 7500; Chazono 2001, JJAP, 40, 5624;Samantaray, et al., 2012, JACerS, 95, 257.

http://www.google.com/url?sa=i&rct=j&q=computer+circuit+board&source=images&cd=&docid=Ax9lBRD0ghv19M&tbnid=Fmv1gHLzFpyGhM:&ved=0CAUQjRw&url=http://pixelperfectdigital.com/photo/6/computer-circuit-board.html&ei=xefkUa-lOqLliAL_uYGIBQ&bvm=bv.48705608,d.cGE&psig=AFQjCNHow7LEaO9KurUjky7g8INutqFHhw&ust=1374042352295815

http://www.google.com/url?sa=i&rct=j&q=computer+circuit+board&source=images&cd=&docid=Ax9lBRD0ghv19M&tbnid=Fmv1gHLzFpyGhM:&ved=0CAUQjRw&url=http://pixelperfectdigital.com/photo/6/computer-circuit-board.html&ei=xefkUa-lOqLliAL_uYGIBQ&bvm=bv.48705608,d.cGE&psig=AFQjCNHow7LEaO9KurUjky7g8INutqFHhw&ust=1374042352295815


X-Ray Computed Tomography of BME after electrical test

Failure site

metal in dielectric layer

edge of void originally observed by X-ray CT

Optical micrograph of cross-section at edge of failure site

Conventional Analysis of failures in life-tested parts

Ni

BaTiO3

NiBaTiO3

Ni

Commercial 10V-0402 BME after electrical test to failure at 80V / 120C

10 µm

400 µm


Cracks and Ni metal were observed in the dielectric near the failure site

BaTiO3

Nielectrode

BaTiO3

Nickel

Edge of Failure Site observed at FIB Cross Section

Nielectrode

Cracks


TEM Sample extracted from the Failure Site

Failure site with surrounding cracks and melt zone

Cracks


Chemical Analysis of the material at the failure site: Excess silicon and oxygen

• Silicon dioxide is used as a sintering agent and is found in low concentrations (<1%) at grain boundaries in BME capacitors

• Si, O and Ni metal were all found within the void

• Interpretation of failure dynamics from post-failure observation is speculative

Element Maps


edge of the void

At the edge of the void, BaTiO3 is amorphous, and spherical metal inclusions suggesting fast cooling from a melt.

Nearby crystalline BaTiO3has large cracks suggestive of thermal mechanical stress as well.

Non-crystalline BaTiOx

Structural Characteristics of the Melted Region adjacent to the Void

The dashed red line roughly indicates the extent of the melted dielectric

Crystalline BaTiO3


Problem:Post failure analysis doesn’t show the structure of the device before failure. We need to know details of the device structure and chemistry on the sub-micron scale before and during electrical stressing.

Approach: Use the TEM to observe the evolution of a small section of the device structure and chemistry during electrical stressing in-situ.

TEM in-situ electrical testing of nano-scale specimens allows focused study of structure before, during, and after electrical stress


TEM In-Situ Electrical Testing: Method

~400 nm SiNx

Specimen on lift-out probe transferring to custom holder.

TEM image of specimen electrically connected via FIB-deposited platinum

Custom TEM specimen holders with gold pads for electrical contacting

Gold Bond Pads

M. Mecklenburg, et. al, Microscopy and Microanalysis, 19, S2, 458 (2013).

Nickel Electrodes

BaTiO3

Pt Contact

Pt Contact

Pt Contact

Pt Contact

10 µm

~10 µm


2 4 6 8 10 12 14 16 18 20 220

5

10

15

20

25

30

35

40

Cur

rent

(nA

)V (Volts)

I-V with electron beam I-V without electron beam

Nickel Electrodes

BaTiO3

Pt Contact

Pt Contact Pt Contact

Pt Contact

• Nano-sized device limits stressed region to that observable at criticallength-scales related to dielectric layer thickness and grain size

• Real-time observation during electrical stress can allow correlation ofelectrical properties with structure and chemistry

TEM In-Situ Electrical Testing of BME-MLCC

In-Situ Electrical Characterization

Specimen dimensions: 100 nm x 15 µm x 3 µm


Rasteringelectron beam

Pt contact

Pt contact

Grain Boundaries

Ni NiRrightRleft

Low-noisePre-Amp

BaTiO3

ADCAdjustable low pass

filter

Damaged Surface Layers

Electron Beam Induced Current Measurement

• The 300 kV TEM beam excites charge in the sample and this is collected as a current signal

• The high resistivity of grain boundaries limits current collection• Currently working on surface treatments to reduce the effects of the FIB

damaged layer.


Current in pA

(c)

0 0.5 1 1.5 2 2.5 3 3.5-2

-1

0

1

2

3

X (um)

EBIC

(pA)BaTiO3Grain structure Current Map

Current profiles along solid green and violet lines of EBIC map.

Electron Beam Induced Current under Zero Applied Bias

• EBIC measures current drop across high resistance grain boundaries

• Grain boundary Schottky barrier height depends on local chemistry and oxygen vacancy concentration

No GB step

GB step


STEM and EBIC map at Nickel – BaTiO3 interface

The current map along the Ni – BaTiO3 interface shows a step illustrating the Schottkybarrier at the interface that depends on the distribution of BaTiO3 grain orientations.

Current in pA

Electron Beam Induced Current under Zero Applied Bias

Ni Ni

BaTiO3 BaTiO3


Electrical resistance in BME capacitors is from (1) BaTiO3 grains and Schottky barriers at the (2) grain boundaries (φGB) and (3) at the BaTiO3 – Ni interface (φNi) [1].

The Schottky barrier height at the grain boundaries depends on the local chemistry and oxygen vacancy concentration [2].

Energy diagram illustrating the two types of Schottky barriers that dominate resistance in BME capacitors.

φNi φGB,1

BaTiO3 Grain 1

Grain Boundaries

φGB,1

Εf

BaTiO3 Grain 2

Ni

Electrical Resistance in BME capacitors

[1] H. Chazono, H. Kishi, JJAP 40, 5624 (2001).[2] GY. Yang, et al., JAP. 96, 7500 (2004).

φGB,2

Next Steps: study the effects of electrical stressing on EBIC step height


Conclusions

• We are developing real-time in-situ failure analysis of microelectronic devices in the transmission electron microscope.

• In-situ electrical stress of micron-sized samples can allow observation of dynamic changes in materials to improve understanding of BME-MLCC reliability and failure.

• EBIC maps showed high resistance BaTiO3 grain boundaries and a Schottky barrier at the Ni-BaTiO3 interface.

• We are currently investigating the influence of electrical stressing on the measured EBIC step heights at grain boundaries.

• Results of in-situ studies will contribute to our understanding of currently on-going reliability tests on bulk BME-MLCCs.


This work was supported by The Aerospace Corporation’s Independent Research and Development Program.

We acknowledge helpful discussions on FIB-preparation and electrical measurements with Matthew Mecklenburg (USC).

Acknowledgements


Supplementary Slides


EBIC Measurements are independent of scan direction


A cut in the SiNxbetween the electrodesis necessary toelectrically isolate theright side contacts fromthe left side contacts.

A circular cut helps to reducethe problems related tointernal stresses in the SiNxthat can cause the SiNxmembrane to deform andeither break the sample ordeform the SiNx so it can’taccommodate the specimen.

A window the size ofthe specimen is milledout of the SiNx.

Samples are prepared in a FEI 400 dual beam FIB/SEM with an OmniProbe manipulationsystem and in-situ Pt deposition capabilities. The preparation process involves the following steps:

1. Extraction of cross-section of interest using standard lift-out techniques and transfer of the section toa standard omnigrid.

2. Thinning of the specimen on the omnigrid to 800-1000 nm. This step is necessary to minimize theamount of thinning required once the specimen is transferred to the biasing grid.

3. Transfer of specimen to TEM grid with electrical leads as shown in Figure 1.

Pre-thinnedspecimen

Details of Specimen Preparation


Notes on Electrostatic Discharge MitigationThe extremely small size of the electrically contacted in-situ TEM sample makes the device especially sensitive to electrostatic discharge (ESD) events. All electrical connections must be grounded during handling to avoid ESD failures.

• Conducting tape was used before the half-grid was loaded in the TEM sample holder.

• Double pull double throw switches were used during TEM holder loading and during connection of external electronics.

Conducting tape used during wire bonding.

Techniques used to ground the leads during sample handling.


Chemical analysis of the edge of the melted region

EDS shows that both left and right sides contain mostly Ba,Ti, and O.

The Ba, Ti, and O maps


Cracking along grain boundaries away from melted area

ADF images of crystalline BaTiO3 that shows cracks along grain boundaries.


Control Sample: Characteristics of the failed device away from failure site

TEM images of the sample away from the site of failure. No cracks or metal droplets are observed.


[1] GY. Yang, GD. Lian, EC. Dickey, CA. Randal, DE. Barber, P. Pinceloup, MA. Henderson, RA. Hill, JJ. Beeson, DJ. Skamser, Oxygen Nonstoichiometry and Dielectric Evolution of BaTiO3 Part II- Insulation Resistance Degradation under Applied DC Bias, J. Appl. Phys. 96, 7500 (2004).

[2] G. Arlt, D. Hennings, and de With, G., Dielectric Properties of Fine-grained Barium Titanate Ceramics, J. Appl. Phys., 58, 1619 (1985).

[3] W.L. Warren, K. Vanheusden, D. Dimos, G.E. Pike, B.A. Tuttle, Oxygen Vacancy Motion in Perovskite Oxides, J. Am. Cer. Soc., 79(2): 536 (2005).

[4] H. Kishi, Y. Mizuno, H. Chazono, Base-Metal Electrode-Multilayer Ceramic Capacitors: Past, Present and Future Perspectives, Japan. J. Appl. Phys., 42, 1 (2003).

[5] M. Mecklenburg, M. Brodie, W. Hubbard, E.R. White, A. Bushmaker, E. Deionno, B. Foran and B.C. Regan, Fabrication of a Lift-Out Grid with Electrical Contacts for Focused Ion Beam Preparation of Lamella for In Situ Transmission Electron Microscopy, Microscopy and Microanalysis, 19, S2, 458 (2013).

[6] K. Hayashi, T. Yamamoto,Y. Ikuhara, T. Sakuma, Direct Characterization of Grain-Boundary Electrical Activity in Doped (Ba0.6Sr0.4)TiO3 by Combined Imaging of Electron-Beam-Induced Current and Electron-Backscattered Diffraction, J. Am. Ceram. Soc., 87(6) 1153 (2004).

[7] H. Chazono, H. Kishi, DC-Electrical Degradation of the BT-Based Material for Multilayer Ceramic Capacitor with Ni internal Electrode: Impedence Analysis and Microstructure, Japanese J. of Appl. Phys, 40, 5624 (2001).

References

Tezzaron Semiconductor 01/27/2015

Update on 2.5/3D Integration and Trusted Spilt-Fab Processing

[email protected]

1


Tezzaron/Novati Fabrication

• “Volume” 2.5D and 3D• Interposers• Cu-Cu, DBI®, Oxide, IM 3D

assembly (150C assembly)• 193nm, 248nm, I-Line BS-IR

Litho• 90nm CMOS (65nm Cap)• 200/300mm• Avalanche, SPM• Fab1 Class 10 68K sf• Fab2 Class 100 12K sf

2


Technology to Enable Solutions

Start with FEOL CMOS wafer

Build novel structures BEOL

Memories, CMOS, Photonics, III-V, Novel Materials, Microfluidics, MEMS,

etc.


Technology to Enable Vertical Integration

Novati Interconnect + Customer Unique Sensor Design+ Novati Std Bond Module = New Device to Market

Wafer/Chip Level Bonding

Multi-level

Copper BEoL

Structural &

Sacrificial Materials

III-V on Silicon


Creation through 3D Integration

Si SubstrateRDL

1. Wafer thinning2. Through-Si-Via (TSV) etch3. TSV fill and DBI Bond layer4. Bond to CMOS wafer Can be repeated to create multi-wafer stacks


The Driver of 3D Integration

• Benefits of building devices joined through 3D integration:– Form factor

• Reduced volume and weight– Performance improvements

• Improved integration density• Improved transmission speed

– Faster signal processing / increased sampling rate• Reduced signal noise• Reduced power consumption

– Reduced manufacturing costs• Single-wafer dicing• Less packaging• Simpler PCB (if needed at all)


3D Integration on Completed Foundry Wafers

Wafer 2

1. Start with Completed foundry CMOS2. Thin wafer3. Build Tungsten TSV4. Build backside RDL and DBI (bond) Cu5. Mate to secondary wafer – Logic, Memory, Analog, Sensors, etc


Near End-of-Line 3D Integration

1. Start with Foundry CMOS and M1-M42. Build Tungsten TSV, M5-M83. Thin wafer (TSV reveal)4. Build backside RDL and DBI (bond) Cu5. Mate to secondary wafer – Logic, Memory, Analog, Sensors, etc

SiliconDeep W vias for 3D IC

Wafer 2


• 3D enables 4-64Gb DiRAM with integrated I/O and Controller.

• 6-wafer memory stack leveraging the performance benefits of 3D technology

• 16X density improvement, 4X performance improvement, 40% power reduction

9

M2

M1

M2

M1

1st carrier

Bit-2 wf

M8

M7

M6

M5

M4

M3

M2

M1

CTL+I/O

Next Generation 3D Devices


3D with III-V/Si integration

• 3D achieves direct interconnect of InP/GaN wafers and Si wafers

Schematic, Cross-sectional, and top view of 3D CMOS/InP/GaN and graphene integrations

Demonstration of fine-grained wafer scale integration using 5um pitch interconnect between an InP wafer and a bulk CMOS wafer using DBI bonding


Interposer Systems Product SolutionsSpec Via First Via Last

TSV Type Cu Fill Cu liner, PI Fill

TSV Diameter 5um to 10um 50um to 100um

Aspect Ratio 10:1 5:1

TSV Pitch 30um 50um

F/S RDL Design 2um/2um/2um L/S/T 2um/2um/2um L/S/T

B/S RDL Design 5um/5um/3um L/S/T 5um/5um/3um L/S/T

Interposer Sizes 44x27.6mm/32x26mm 44x27.6mm/32x26mm

Interposer Module 200mm/300mm wafer sizes 4 Front-side metal layers Single back-side RDL layer Polyimide UBM Isolation Backside bump metal pad finish PDK Available upon request

CCFPGA (4Xnm)

Active Silicon Circuit Board

2 Layer Processor2 Layer Processor3 Layer 3D Memory

CC

Organic Substrate

level#0

level#1

level#2

level#3

Solder Bumps

μBumps

C4 Bumps

Die to Wafer Cu Thermal Diffusion Bond

level#4

3D Integration2.5D Interposer Integration


Wafer-scale Integration • Silicon circuit board• Up to 85 die assembly• 10um die space• 2um placement• 150/200/300mm• In plan to flight qualify

12


Bonding in Action

13


TSV Characteristics

Nano TSV– Tungsten

• Small, very high density ~500k/sqmm

• ~1.5 Ohms• ~1-3ff• Implemented by design• True 3D circuits

Packaging TSV– Copper

• Lower density, 10-100/sqmm

• 100 mOhm – 1 Ohm• ~1-10pf• After the fact design in• Advanced packaging

14


TSV Qualification Work

• 1.2x6um W TSV Mid-line– Full electrical and thermal

• -65 to +150– >20k hours real operation

• 1.2x6um W TSV BEOL– Just starting

• Qualify by 2016• 1.6x10um W TSV NEOL

– In progress• Flight Qualify in 2016

15


TSV Qualification Work

• 10x100um Cu TSV BEOL– Development– Qualify 2016– Flight Qualify

• 80x300um Cu Conformal TSV FBEOL– Qualify by 2016– Flight Qualify 2016

16


2.5/3D Qualification Work

• 3D 130nm– Full electrical and thermal

• -65 to +150– >40k hours on operation

• 3D 150nm– 77K –data point

• 3D 65, 55, 45, 40, 28nm on going work• Interposer (2.5D)

– Full electrical and thermal• -65 to +150

17


Trusted Split-Fab

• 130nm BEOL– Prototype support

• July 2015– Full release

• Sept 2015– MIM and Inductor

• Dec 2015– ReRAM BEOL insertion

• Dec 2015

• 28nm BEOL– Prototype support

• 2016

• Plan to support BEOL 350nm down to 10nm• 2016-17 extend to FBEOL and first level organics/ceramics• Today we work with Honeywell, Jazz, IBM, GF, Vanguard,

Freescale, On-Semi18


Covers IP, EDA tools, Foundry, Masks, Temperature/voltage and timing sensitivity>10 Billion vectors/hr

Verified TrustPEN testing for circuits and systems

19


ReRAM

Tezzaron to Incorporate Rambus ReRAM Memory Technology– Architecture enhances power and performance in

military, aerospace and commercial applications• Nonvolatile• >10e12 endurance• BiSTAR enabled• >10 year retention• 3D and embedded through post-CMOS split-fab

20


Fusion Versus Bump Bonding

5.4×6.5 mm2 VIPICwith 32×38 pixels detectorbump bonded

34 µm thick VIPICDBI bonded to 64×64 with pads on its back

Grzegorz DeptuchFermi National Accelerator Laboratory

21


ENC comparison: bump vs. fusion bonded

Bump-bonded VIPIC Fusion bonded VIPIC

Fermi National Accelerator Laboratory

22


Signal amplitude comparison: bump vs. fusion bonded

Amplitude for bump-bonded VIPIC Amplitude for fusion bonded VIPIC

32×38 =1216 pixelsbump-bonded

Gain is higher for fusion bonded device

Fermi National Accelerator Laboratory23


Summary

• Novati and Tezzaron’s 2.5/3D integration techniques are being applied to a wide range of technologies including– High-speed memories– Sensors– Heterogeneous integration– Consumer products– Tamper-proof assemblies

• TSV and 3D technologies have proven to be extremely robust and reliable

• We are a proven Trusted 2.5/3D and split-fab solution provider

Soft Error Qualification of a 361pin Flip-Chip Package

Sandeep Krishnegowda and Helmut PuchnerCypress Semiconductor

MRQW 2015, JAN. 27-28, 2015 — THE AEROSPACE CORPORATION, EL SEGUNDO, CA 2

MotivationNon-hermetic Space Qualified packages gain acceptance in QML Standards (MIL-PRF-38535) and products (AeroFlex, E2V, and others actively launching QML-Y programs)

Flip-chip packages preferred package of choice for high I/O count, low cost, good performance and speed

Radiation Assessment of Flip-chip packages:

Alpha Particle Assessment according to JESD89A or MIL-STD-883 TM 1032 needed for non-hermetic packages to guarantee soft error performance for space grade devices

Error Correcting Code (ECC) can eliminate soft errors for memories, but what about SoC’s, FPGA’s?

Radiation Test Hermetic Non-HermeticSEE – Heavy Ions TID – Co60 Alpha Particles


QDR-IV Product Overview

Switches and routersHigh-performance computingMilitary and aerospace systemsTest and measurement

Applications

Available in two options: QDR-IV HP (RTR 1,334 MT/s) andQDR-IV XP (RTR 2,132 MT/s)

Two independent, bidirectional DDR1 data portsError-correcting code (ECC) to reduce soft error rate to less than 0.01 Failure-in-Time (FIT) per megabit

Bus inversion to reduce simultaneous switching I/O noiseOn-die termination (ODT) to reduce board complexityDe-skew training to improve signal-capture timingI/O levels: 1.2-1.25 V (HSTL/SSTL), 1.1-1.2 V (POD2)Package: 361-pin FCBGA3

Bus widths: x18, x36

Features

Family Table

Sampling: NowProduction: Now

Availability

Block Diagram

2 Pseudo open drain: Signaling interface that uses strong pull-down and weak pull-up drive strength 3 Flip-chip ball grid array

Preliminary Datasheet: Contact Sales

Collateral

1 Double Data Rate: two data transfers per clock cycle

Option Density MPN Max Freq RTR

QDR-IV HP 72144

MbMb

CY7C40x1KV13CY7C41x1KV13 667 MHz 1,334 MT/s

QDR-IV XP 72144

MbMb

CY7C40x2KV13CY7C41x2KV13 1,066 MHz 2,132 MT/s

QDR-IV

Control Logic

Data Port A

SRAM Array

Test Engine

Data Port BDat

a Po

rt A

(HST

L/SS

TL o

r PO

D)

Address Interface

x18, x36

Data Clocks

Address Port

x21,x22

BusInversion

ParityError

AddressParity

Bus Inversion

JTAG InterfaceControl

Dat

a Po

rt B

(HST

L/SS

TL o

r PO

D)

x18, x36

ECC

Address/Control

Clock

Bus Inversion

Impedance Matching

Data Valid

ODT

x2x2

x4

x2Data Clocks

Data Valid

x2

x2

x2

x2 x2

http://www.cypress.com/contactus


SEE – Heavy Ion AssessmentFlip-Chip package requires exposure from backside (100um thinned sample) at TAMU

Heavy Ion SEE Summary:

MBU events detected in static mode after 5000 SBU events have been accumulated in the memory

HI - Summary QDR-IV 144Mbit SRAM

SEU – static Immune up to accumulation effect

SEU – dynamic < 3E-4 Err/Device.Day

SEFI Immune

SEL > 56 LET (133C) 1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

# Un

corr

ecta

ble

MBU

Err

ors

# Raw MEM Array Errors

Prob. Single ErrorError RateQDR-IV TAMU_Data


TID - Total Ionizing Dose Assessment144Mbit QDRII+ SRAM device tested in lieu of QDRIV SRAM.Devices Biased At nom VCC & Pre Loaded With CheckerboardIrradiation In 50Krad Step Up To 350kRad W/ 50Rad(Si)/s Dose RatePost-Irradiation Tests: Bit Upsets, IDD, IDDQ CKB/CKBN, R/W, VOH,VOL, VIH,VILIdd starts degrading at 150kradTID > 300krad

1.00E-02

1.00E-01

1.00E+00

0.E+00 1.E+05 2.E+05 3.E+05 4.E+05 5.E+05

Idd

(A)

rad(Si)

65nm 144M QDRII

Idd Spec 85C


Alpha ParticlesAll terrestrial materials contain trace amounts of radioactive atoms For example, 210Po, 238U, and 232Th, at a few parts per trillion

These atoms sporadically emit Alpha particles as they disintegrate into more stable elementsAlpha particles are Helium nuclei with a double-positive charge, and are directly

ionizing, i.e., their motion in Silicon creates an electron-hole charge track; this charge can disrupt a circuit and cause soft errors

Radioactive contaminants in packaging materials need to be controlled to lower the Alpha emission rateUsage of Ultra Low Alpha (ULA) mold compounds and materialsCertificate of Compliance (CoC) and tight supply chain controlTypical Alpha emission rates for semiconductor materials are shown in the table to

the right

Alpha particles can be partially screened from reaching sensitive circuitsAdditional passivation layers (10μm polyimide 50% reduction)A dummy metal layer can also act as an Alpha shield

Materials in Packages that are close enough to Memory CellWire bond packages: mold compoundFlip-chip packages: solder bump, underfill, UBM, presolder

Typical Alpha Emission Rates:

Material α/cm2-hr

Processed Wafers 0.0009

Cu Metal (thick) 0.0019

Al Metal (thick) 0.0014

Mold Compound 0.024 - <0.002

Underfill 0.002 – 0.0009

Pb-solders 7.200 - <0.002


A tester with an open-top DUT setup and a calibrated 232Th foil positioned at a predefined distance (<2mm) from the chip surface is used

Test flowsStatic – Write data pattern (e.g., checkerboard) => Alpha exposure time x => Read-verify => log errorsDynamic – During exposure time x, enter into in infinite Write-Read loop and log errors as they occurBitmapping – collect hundreds of individual, isolated events for bitmap studiesSEL – high-temperature and high-flux, static testing attempts to overwhelm the memory and cause latchup

SER/SEL FIT Rate CalculationFIT rates are scaled to the flux of the dominant alpha emitter in the packaging materials (e.g., the mold compound for wire-bond

packages)The Alpha emission rate for Ultra-Low Alpha (ULA) mold compound is ΦPKG=0.001 α/cm2·hrSER is expressed on a per-Megabit basis, and SEL on a per-Device basis

SER:

SEL:

Alpha Particle Testing

)(][10)(#]1[

9

PKGFOILMbdensityhrerrors

MbFIT

ΦΦ⋅⋅

=

)(10)(#]1[

9

PKGFOIL

hrLUeventsDev

FITΦΦ⋅

= Memory Tester

Device under test (DUT)

Socket DUT

232Th foil

This Method works well for Wirebond Packages


Flip-Chip Package

Typical Flip-Chip BGA Package

Subcon provided Alpha Emission Rates:Underfill: 0.001 alpha/hrSolder Bump: 0.002 alpha/hr

Additional Flip-chip Materials: UBM: ?, Pre-solder:?

Alpha Testing from front side impossible!!Alpha Testing from back side requires Alpha Emission Rates for ALL materials close to SRAM cells!!

System SER (Life Testing) in “Zero-Neutron Environment” can do the job!!

Package independent Alpha particle upset requirements:

No Multi Bit Upsets from single eventsNo Multi Bit Upsets from multiple events


Flip-Chip MBUs from Single EventCan single Alpha Particles trigger Multi Bit Upsets (MBUs)?Only gracing angle particles hitting in the same row can cause MBUsSRAM Array with 16-cell Bit Interleaving:

Alpha particles from solder bumps will not cause a MBU event from a single particle since the backend stack will screen the shallow angle Alpha particle hits


SRAM’s accumulate soft errors in data retention mode (Accumulation Effect)Birthday statistic can be used to calculate probability of MBU eventMBU probability depends on:

Architecture (# of addresses)Intrinsic failure rate of SRAM cellData bus width – x18,x36

MBU failure rate of SRAM in data retention mode depends strongly on Alpha emission of the package material:ULA (<1 α/khr): MBU = 0.08 FIT/MbStd (<100 α/khr): MBU = 800 FIT/Mb

ULA packaging materials required in Flip-Chip packages to suppress MBUs

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

# Un

corr

ecta

ble

MBU

Err

ors

# Raw MEM Array Errors

Prob. Single ErrorError RateQDR-IV TAMU_Data

Flip-Chip MBUs from Multiple Events

ULA LA


Alpha Assessment - System SER TestingHundreds of devices are mounted in a system (up to 30Gb of SRAM) and written

and read continuously every four minutesExtraction of Alpha and Neutron SER through measurements at different altitudes

and environments

Cypress-preferred locationsHigh Neutron flux environment: Mauna Kea – Hawaii, 9.2x acceleration over NYCZero Neutron flux environment: Soudan – Minnesota, 10-5 n/cm2·hr, used for true Alpha SER

measurements (e.g., for flip chip package qualification)

Failure log example from Mauna Kea (305† events over 3 months)

High Neutron Environment Zero-Neutron Environment

Soudan, Minnesota (-2,360ft)Mauna Kea (+14,700ft)

Rack Mount System w/ UPS and Network


System SER TesterCustom SSER Tester:


361 FC w/ 144M QDR SRAM SSER164pc of 144M QDR SRAMs installed in Jan 2014 @ Soudan, MN mine (24.7 Gb)37 SBU events, 4 MCU events till mid Dec 2014 detectedFIT Rate = 284 FIT/Mb equivalent to 1.07 α/khr

361pin Flip Chip meets ULA criterion of < 1 α/khr

0

100

200

300

400

500

600

700

800

900

0

5

10

15

20

25

30

35

40

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200

SER

Rat

e [F

IT/M

b]

Num

ber o

f Eve

nts

Mbit Hrs (x106)

Events (SBU)

Events (MCU)

Events (Cum)

FIT/Mbit (SEU+MCU)


ConclusionsThe 144Mbit QDRIV SRAM has been successfully evaluated for QML-Y Radiation Effects:• Heavy Ions• Total Ionizing Dose• Alpha Particle Emission from Flip-Chip package

System SER is the only reliable method to validate alpha emission of flip chip packages:• Advantages:

AccurateValidates whole package at once

• Disadvantages:Long measurement time (1yr)Expensive (Power, Support)

byReza Ghaffarian, Ph.D., NASA-JPL-CalTech

Contact(818) 354-2059

[email protected]

2015 Microelectronics Reliability & Qualification Workshop (MRQW)

January 27-28, 2015

Copyright 2015 California Institute of Technology

Government sponsorship acknowledged

Reza Ghaffarian JPL/CalTech2015 MRQW

Outline CGA/LGA/HDI Objectives

Numerous >1000 I/O CGAs Non-hermetic CGA with exposed BME capacitors

BME Characterization As-received CGA with BMEs Solder joint inspection CGA package TC shock/evaluation

CGA with BME CGA assembly and thermal cycle X-section of BME Elemental and grain size

Failure Analysis CGA & BME dye-and-pry

Effect of Re-column Reflows Failure/improvement

Summary

Reza Ghaffarian/JPL/Caltech2015 MRQW

CGA/LGA/HDI Objectives &Accomplishment

CGA/LGAHDI

• √ Reported new test vehicle with microvia , CGA assembly• √ Reported assembled LGA (ceramic/plastic) on HDI PCB • √ Reported inspection/QA with TC for HDI PCB• Reliability functional CGA on HDI is yet to be funded

LGA & CGA

• √ Reported pull testing before/after isothermal aging• √ Reported LGA to CGA (two types) assembly and TC data• √ Reported assembly of ceramic LGA s (two types)• √ Reported QA indicators by inspection for LGA Assemblies

CGA

• √ Present package/capacitors reliability evaluation• √ Reported CGA assemblies, QA indicators• √ Reported 200 TC (-55°/100°C or 125°C) of CGA assemblies• √ Present 500 TC results/failure analysis CGA/Cap


CGA AssembliesCGA1752 CGA1272

CGA1517-Microspring CGA1517-Cu Wrap

CGA1517


CGA with 31 Chip Capacitors


Ceramic Capacitors PME (Precision Metal Electrode)

Reliability (bias/temp) well established Mix of Palladium Silver Electrode

BME (Base Metal Electrode) High density, commercial/cost Ni electrode Barium Titanate- BaTiO3

Tetragonal (0/130C) on face centers, Barium at corners Titanium, 1% nanometer offset, voltage/move/storage

Thinner dielectrics/more layers than PME Increase in capacitance/volumetric efficiency

Reliability?


BME Capacitor – SEM


CGA with 31 Chip Caps


SEM of a Capacitor


Solder Joint Composition

90 Pb10 Sn


SEM of Capacitor Solder Joint


SEM of Capacitor Solder Joint


Capacitor Joint after 200TCs

-55/130C, 10/10 min


CGA Solder Joint Assembly


Cap. Solder Joints after TCs


Caps Removed for Eval


Caps on CGA after TCs CGA Thermal History

Package subjected to thermal shock (-55/130°C) Reflow for assembly ( 218°C) Additional TCs package on board

Characterize CGA Assemblies Caps Removal

Mechanical Solder cut, then caps pushed/removed Shear off by twisting, concern, mechanical damage

De-soldering High temp solder Not tried yet, concern thermal shock


Cap after TC/Removal


X-section of Caps


BME- X-section


X-section & Elemental Map

Si Ca Ti

Ni Cu Ba

SEM O Al


SN8BME Cap


BME Grain Size Evaluation


Failure Analysis of Caps


Re-column/Two More ReflowsEarly Failure

Non-coated sample submitted to (shock + vibration + thermal cycling 1500 cycles @-40°C to +100°C)

Private Communication: Y. Jellali, MDA


Re-column/Two More ReflowsImproved

Private Communication: Y. Jellali, MDA

UV-coated sample (shock + vibration + thermal cycling)1500 cycles @-40°C to +100°C)


Summary High I/O CGAs

Success on Cu wrap column attach Success on Micro-coil spring column attach Success on CGA assembly

CGA with Exposed BME SEM/EDS analysis & inspection

CGA thermal shock cycles No failures of caps

CGA Assemblies TC and BME X-section/Elemental analysis Dye-and-Pry: No BME solder joint failure

Re-column CGA (industry data) Much earlier solder joint failure Coating improved SJR


The research described in this publication is being conducted at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration.

Copyright 2015 California Institute of Technology. Government sponsorship acknowledged.

The author would like to acknowledge industry/university partners. Special thanks to the JPL fabrication and failure analysis lab personnel including Atul Mehta, Jose Uribe, and Ronald Ruiz for their support. The author also extends his appreciation to program managers of NASA Electronic Parts and Packaging Program (NEPP) including co-managers Michael Sampson and Kenneth LaBel at GSFC, and Dr. Charles Barnes and Dr. Douglas Sheldon at JPL, for their continuous support and encouragement.

NASA Next Generation Flight Computing: Mission Use Case Scenario Fault Tolerance Considerations

Raphael (Rafi) SomeDave Rennels Autonomous Systems DivisionJanuary 26, 2015

© 2015 California Institute of Technology. Government sponsorship acknowledged.

Jet Propulsion LaboratoryCalifornia Institute of Technology

1. Cloud Services2. Advanced Vehicle Health

Management3. Crew Knowledge Augmentation

Systems4. Improved Displays and Controls5. Augmented Reality for

Recognition and Cataloging6. Tele-Presence7. Autonomous & Tele-Robotic

Construction8. Automated Guidance,

Navigation, and Control (GNC)9. Human Movement Assist

1. Extreme Terrain Landing2. Proximity Operations / Formation

Flying3. Fast Traverse4. New Surface Mobility Methods5. Imaging Spectrometers6. Radar7. Low Latency Products for

Disaster Response8. Space Weather9. Science Event Detection and

Response10. Immersive Environments for

Science Ops / Outreach

HEOMD (Crewed Exploration Missions) SMD (Robotic Science Missions)

NASA High Performance Space Computing Applications

2

• Extreme Terrain Landing– Enables reliable and safe landing in

hazardous terrain: TRN and HDA algorithms benchmarked by Mars Program - required six (6) dedicated RAD750s

• Fast Traverse– Remove computation as a limiting

factor to mobility – drive 10X faster and more, safely (wheel slip, obstacle detection)

• Science Event Detection and Response

– Increase capture rate for dynamic, transient events from ~10% to >75%, with <5% false positives, for increased and more timely science return

1. Extreme Terrain Landing2. Proximity Operations /

Formation Flying3. Fast Traverse4. New Surface Mobility

Methods5. Imaging Spectrometers6. Radar7. Low Latency Products for

Disaster Response8. Space Weather9. Science Event Detection

and Response10. Immersive Environments

for Science Ops / Outreach

Science Mission ApplicationsHPSC Enables New Science and Mission Capabilities

Application Mission Benefit

3

1. Cloud Services2. Advanced Vehicle Health

Management3. Crew Knowledge Augmentation

Systems4. Improved Displays and Controls5. Augmented Reality for

Recognition and Cataloging6. Tele-Presence7. Autonomous & Tele-Robotic

Construction8. Automated Guidance,

Navigation, and Control (GNC)9. Human Movement Assist

• Vehicle Health Management– Continuous monitoring/analysis of

large vehicle data sets: problem detection and response, crew workload reduction, and improved vehicle maintenance during untended operations

• Crew / Robot Interaction– Robots respond to high-level

instructions from crew or ground personnel while maintaining safe operations and interactions with the crew

• Automated GNC– Move compute-intensive GNC

applications onboard for faster, safer docking; close proximity operations; collision avoidance; and automated precision landing within an affordable power budget

Human Space Flight MissionsHPSC Enables Autonomous Human-Assist Capabilities

In Next Generation Crewed Vehicles and Missions

Application Mission Benefit

4

5

Eigen-App Throughput DSP GP P LP MC

1 1-10 GOPS X X X X2 1-10 GOPS X X X X

310-50 GOPS X X X X X

410-50 GOPS X X X X

510-50 GOPS X X X X

610-50 GOPS X X X

750-100 GOPS X X X X X

850-100 GOPS X X X X

950-100 GOPS X X X X

1050-100 GOPS X X X

• Requirements that represent groups of key cross cutting applications

• Derived by selecting low power applications from full applications set and grouping by throughput, processing type, mission criticality

App to Eigen-App Mapping DSP GP P Mission Critical LPThroughput = 1-10 GOPSAutonomous Mission Planning X X X XDisaster Response X X XHyspiri X X X

Throughput = 10-50 GOPSFast Traverse X X X X XExtreme Terrain Landing X X X X XAdept X XOptimum Observation X X X XSpace Weather X X XRobotic Servicing X X X XCloud Service X X XAdvanced ISHM X X XAutonomous and Telerobotic Construction X X X X

Througput = 50-100s GOPSHyperspectral Imaging X X X XRADAR Science X X XRADAR EDL X X X XAutomated GN&C X X X XHuman Movement Assist X X X XCrew Knowledge Augmentation X XImproved Displays and Controls X X X XAugmented Reality X X XTelepresence X X X

KEY• DSP – Digital Signal Processing• GP – General Purpose Processing• P – Parallelizable• Mission Critical – Requires Additional Fault Tolerance• LP – Max Power Available for Processor Chip <6W

Eigen-Apps Summary~60 application variants/derivatives reduced to

10 representative sets of requirements

5

Fault Tolerance in “Space Born Many-Core Computers”

A starting point

COTS IP (e.g. ARM, Tilera, etc.) with at least 16 cores

Limited change allowed/feasible to basic building blocks.

Most fault tolerance must be implemented in software – underlying hardware must support.

COTS IP typically supplies: error detecting codes on internal communications, SEC/DED on memory, diagnostic tests, support for handling error-traps, etc.

This is insufficient for mission critical applications

A new SBMC with all of its interacting processors and I/O will be many (20+) times as complex as earlier space machines.

Even after Rad-Hardening by Design, the space error rate may be high by historic standards due to declining feature size (note that errors come from many sources, not just radiation).

Fault tolerance approach: provide a “hard core” of redundant software that will continue operating correctly in the presence of errors, and that can be used to support error recovery in the other application processes operating singly or in parallel.

6

Hardware must support Software Implemented Fault Tolerance

What is Needed?

1. At least three fault-containment regions

Regions containing a set of isolated processing hardware, where a fault in one region is extremely unlikely to affect another

Redundant communication paths between regions, with message correctness checking.

Multi-core clusters are typical candidates for fault containment regions

2. Triplicated/voted software “hard core” that provides correct operation in the presence of single errors

3. Support for detection and mitigation of hardware errors that can breach fault containment, e.g.:

Breach of virtual memory protection regions due to: undetected bit flips in registers, communications, or processing hardware, especially when the hypervisor/OS is executing

Unprotected DMA controllers writing to wrong locations.

7

HardCore

HardCore

HardCore

Software Implemented Fault Tolerance On A Multicomputer

Note: Separate computers providegood fault containment

1. A small hardcore control program is run TMR inthree computers to operate correctly through any single computer failure.

2. They periodically exchange status messages to detect errors in themselves.

8

HardCore

HardCore

HardCore





3. If one hard core fails the remaining two can Start another copy.

HardCore

9






4. Each computer contains a simplex scheduler program that, after voting, accepts a list of tasks and reports back to the triplicated cores

HardCore

HardCore

HardCore

P2 SchedulerMonitorReporting




10

HardCore

HardCore

HardCore


Note: Separate computers provide good fault containment




4. Each computer contains a simplex scheduler program that after voting accepts a list of tasks and reports back to the triplicated cores

5. The scheduler can run simplex applications (parallal and sequential)

S

SS

P P

P P





11


Note: Separate computers provide good fault containment




4. Each computer contains a simplex scheduler program that, after voting, accepts a list of tasks and reports back to the triplicated cores

5. The scheduler can run simplex applications (parallal and sequential) andTMR and Duplex (self Checking)

HardCore

HardCore

HardCore

S

SS

P P

P PP3 SchedulerMonitorReporting




12

HardCore

HardCore

HardCore

S

SS

P P

P P

Support and Middleware

Middleware is supplied in each computer to support: error detection, voting, comparisons, checkpointing, rollback.

Error detection results and heartbeats are sentback to the scheduler, and to the hard core if systemreconfiguration is necessary.

The scheduler also sends periodic health messages tothe hard core.

Error recovery is done in a hierarchical manner:

If possible, applications directly implement recovery With assistance of the scheduler (e.g. rollback,restarting a disagreeing copy in a voted pair).

If these don’t work, the core can restart and relocate applications (e.g. a repeated error indicating a permanent fault).





13

What’s Different with a Many-Core System ? CLUSTERS

If the clusters and various I/O subsystems can be madeto be Fault-Containment Regions then the software-basedfault tolerance techniques apply rather directly.

Issues: common errors/failures across clusters, and intercommunications limitations.

Examples:

Physical memories shared across clusters: How is protection provided against writing to wrong memories. Are hardware firewalls adequate? Are virtual addressing and DMA designs adequately protected?

COTS IP use many different interconnect structures between subsystems: Can these interconnects provide adequate redundancy and fault isolation of messages across system boundaries.

Automated cache coherency across clusters may damage fault containment: Can coherency be turned off for protected memory areas.

In developing an SBMC it is essential to find and fix/workaround any problems in the basic low-level logic design to support software-implemented fault-tolerance with adequate fault-containment regions and redundant intercommunications.

HardCore

HardCore

HardCore

Various I/O

C3 SchedulerMonitorReporting




14

This research was carried out in part at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration (NASA), funded by the Game Changing Development Program of the NASA Space Technology Mission Directorate.

Acknowledgements

15

1

Integrity Service Excellence

Dr. Jesse Mee, PI, AFRL/RVSECapt Jeremy Higbee, PM, AFRL/RVSE

Space Vehicles DirectorateAir Force Research Laboratory

Spacecraft Performance Analytics & Computing Environment Research

(SPACER)

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

2

Motivation

→Quantify the system level impact of incremental improvements of dissimilar devices at the component level

→Identify enabling technology for next generation missions


We are creating a suite of capabilities to guide technology investments to fully support next generation missions and yield the highest Return on Investment (ROI)

3

Limitations of Present Technology Need Specifications

Processor performance requirements are highly dependent on the application Performance benchmarks

subject to large variability and fail to identify capabilities needed for specific application (MIPS, FLOPS, MOPS, etc.)

Actual performance is strongly dependent on the rate at which data can be accessed from memory (L1/L2 Cache, RAM).

Need to distinguish between theoretical peak and realizable performance

CPUGPUHybrid

L1Cache System

MemoryL2/L3Cache

Memory Speed

VirtualMemory

SRAM DRAM Hard Drive

Memory Size

APPLICATION

Capability needed for mission?

InterconnectBandwidth


4

A Concept for GuidingFuture Technology Investments

Map mission needs to lower-level computational requirements Decompose mission applications codes

(image processing, data compression algorithms, etc.) into key computational pieces

Computational pieces benchmarked on a variety of computing architecture platforms

Optimized application/architecture pairings are identified

Application Benchmarking Evaluate Application code on

commercial and rad-hard hardware resources

Create synthetic applications to examine how current and future algorithms map to different architectures

Develop a comprehensive systems engineering model that compares mission-level gains from improvements in dissimilar devices

Data Size

FLO

PS

Application Specific Requirements

1K 2K 3K256

CPU Multi-Core CPU

Hybrid

Computational Kernel

Benchmarking

Tier-1

Tier-2

Tier-3

Satellite Bus and Payload Electronics Specifications

ApplicationBenchmarking

Satellite Systems-Engineering Model

Informed Decisions


5

Processor/Algorithm Kernel Benchmarks

Device Benchmarking Developing benchmarks and testing on

targeted computational architectures Provides insights in to realizable

performance

Developing space computing benchmark suite that encompasses key computations required by Space Dwarfs Space Dwarf is an algorithmic method that

captures a pattern of computation and communications associated with common space applications (Image Processing, Compression, Remotes Sensing, etc).

Determine metrics for candidate devices Standardize approach to analyze the entire

processing architecture Define a set of metrics to compare disparate

devices. Enables objective comparison of broad

range of disparate architectures (CPU, DSP, FPGA, GPU, Hybrid).

Returns the theoretical peak performance of device but this is NOT the realizable performance!


http://www.chrec.org/

http://www.chrec.org/

6

Application Benchmarks

New Architectures Laboratory will be operational by spring 2015

Building models of data/processing requirements for sensor platforms Taking resolution, f-bands, etc. and turning

them into estimates of required processing and storage

Evaluating the performance of actual application code (Image processing, data compression, etc.) on commercial and rad-hard HW resources Significant progress on Hyper-Temporal

Image (HTI) processing algorithm

Can extend the approach to examine how synthetic applications perform on current HW resources Characterize the behavior of new algorithms Deduce how current or legacy algorithms

map to different architectures Lets us cover a wider range of architectures


SBIRS

WES

TemporalC

urre

nt

Mid

Futu

re

7DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

System Model

Taking an energetics approach, a model has been developed to determine the satellite workload per orbit DES engine and recursive summation of

component power to calculate total orbital energy usage

Examine candidate architectures ability to balance energy supply and demand

Offers flexibility to interchange/modify individual or groups of components and subsystems Build performance trade-space

characterizing top-level impact as a function of improvements at individual component and subsystem levels

Model has been tested on two representative systems, ORS2 (MSV) and Trailblazer Successfully reproduced instantaneous

power for provided operational modes and orbital energy accumulation in batteries

Dc-Dc Pic16f88 Discrete

Interconnect efficiency

Dc-Dcefficiency

ASIC EEPROM

Satellite Constellation

Sub-System Level

Sub-System (Dosimeter)

System Level (Trailblazer)

Component Level

Sub-System Level

8DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

TrailBlazer Energy Calculation

Initial Model Verification

Trailblazer

ORS2

9

Energy Balance: Case study 1

ISR

HTIOPIR

SAR

COMM

PNT

Mission Applications

TX

Collect0Collect TX

Process

IdleIdle

Idle

0

ECL

0Collect TX

Energy Use

Generated

Stored

FAILURE

0Collect TX

ProcessIdle

IdleIdle

0

ECL

0Collect TX

Energy Use

Generated

Stored

Time

Pow

er (a

.u.)


10

Energy Balance: Case study 2

ISR

HTIOPIR

SAR

COMM

PNT

Mission Applications

TX

Collect0Collect TX

Process

IdleIdle

Idle

0

ECL

0Collect TX

Energy Use

Generated

Stored

FAILURE

0Collect TX

IdleIdle

Idle

0

ECL

0Collect TX

Energy Use

Generated

Stored

Time

Pow

er (a

.u.)


11

Extensible Approach

SOLAR

Bi-directional Battery Charge

Controller

Li-Ion Battery Bank

Pwr Management and Distribution

S/C PowerBus (28V)

…

Charge Regulator

Command and Data HandlerRW’s

Assembly

Star-Trackers

Sun Sensors

IRU-Mag

TorqRods

DC-DCPOL (5V)

CDLAntenna FiltersMixers Amplifiers

FPAROICDC-DC Therm Control

CPU, DSP, FPGA, Hybrid

Non-VolMem

Volatile Mem

DC-DC

Command & Data Handler

(5V-12V)

CPU, DSP, FPGA, Hybrid

Centralized or Distributed Throughout S/C

High Data-Rate NetworkDeterministic Network

Router

DC-DC Converter

CPU, FPGA, µ-Controller

(12V)

Guidance Navigation & Control

DC-DCADCDACFPGA

Mission PayloadComm Down Link

Efficiency in DC-DC converters Vs.

Low Power FPGA

Trade-Study Capabilities

Application-X on multi-core CPUVs.

Application-X FPGA/CPU Hybrid

High-Speed Optical NetworkVs.

Aggregate Cu Interconnects


12

Summary

Establish a uniform modeling framework to compare mission level impacts resulting from improvements in performance at component level (not limited to computation or memory) Understand mission level impacts of architecture/application

pairings

Quantitative analysis to help guide new technology investments

Examine the art of the possible Create the capability to future enabling and/or disruptive

technology and how they impact the spacecraft


13

Backup Slides

14

Use-Case Scenarios

Government (vendor independent) tool for addressing key questions such as: How do algorithms map to processor architectures? What devices, configured in what architectures, perform best for needs in

image processing? Can existing HW meet OPIR computational requirements? How much computing can be done on orbit? How much computing should be done in a cold environment ( e.g. Digital

FPA)? What algorithm vs. processing trades are required? What are the impacts of new computational requirements? What are the performance and Size Weight and Power (SWaP)

characteristics of a given HW configuration? What are the bottlenecks in the current state-of-the-art computational

HW? What technology areas should be researched first?

The most important thing we build is trust

ADVANCED ELECTRONIC SOLUTIONS AVIATION SERVICES COMMUNICATIONS AND CONNECTIVITY MISSION SYSTEMS


Cobham Semiconductor SolutionsPresented at Aerospace Corporation – MRQW Presenter:Rob Ciccariello

January 2015


Thank You to our sponsors and supporters

1



• Cobham Semiconductor Solutions (Cobham), formerly Aeroflex Microelectronics – HiRel developed the UT840 quad core processor as a “proof of concept” of multiple new technologies:

– Gaisler LEON 4FT SOC IP– IBM 9SF 90nm Process Technology– Cobham UT90nHBD Library and ASIC Design Flow– Flip Chip Package Technology for Space Applications

• Cobham has completed electrical characterization focusing on benchmark tests

– Data shows that all new technology implementations were successful, and that the UT840 meets performance goals

Introduction

25 February 20152



• UT840 is the third generation fault tolerant LEON processor from Cobham Semiconductor Solutions• UT840 represents a significant improvement in performance and

capability over previous designs

Background: Comparison

25 February 20153

LEON Family Key Feature Comparison

UT699 (LEON 3FT) UT700 (LEON 3FT) UT840 (LEON 4FT)

IEEE-1754 SPARC Compliant Cores 1 1 4Process Technology 250nm TSMC 130nm TSMC 90nm IBMOperating Voltage 2.5/3.3 1.2/3.3 1.0/2.5

L1 Cache (Data/Instruction) kB 8/8 16/16 16/16/ per coreL2 Cache (kB) NA NA 256IEEE 754 FPU 1 1 1/core

Max clock Frequency (MHz) 66 166 266

Supported Interfaces

uART, 10/100 Ethernet, CAN, PCI,

SpW

uART, SPI, 10/100 Ethernet, CAN, PCI,

SpW, 1553

uART, SPI, 10/100/1000

Ethernet, CAN, PCI, SpW, 1553

Package Technology 1mil Al Wire bond 1mil Al Wire bond Flip Chip



Seven stage pipelined monolithic, high-performance, fault-tolerant SPARCTM V8/LEON 4FT Quad Core Processor

Background: Block Diagram

25 February 20154

SSRAM Support

256KB L2 Cache

1553 Interface

1000 Mbit/s Ethernet


UT840 LEON Quad Core First Silicon ResultsBackground: RadHard Design

25 February 20155

• UT840 designed using the UT90nHB ASIC RadHard flow

1:Library Characterization• Prompt Dose\SEL• TID

Requirement FF SEU FF SET SRAM Reset SET Clock SET PLL Total

Recoverable Error Rate (Error/device-day) 7.0E-04 3.2E-05 3.1E-05 1.9E-05 1.9E-07 3.4E-07 1.6E-05 9.8E-05Data Integrity Error Rate (Error/device-day) 0.25 9.6E-05 9.2E-05 1.7E-04 1.9E-07 3.4E-07 1.6E-05 3.7E-04

SRAM Bits 4,598,272 Control DataSystem

Derating*Utilization Factor**

SRAM 10% 90% 20% 100%PLL's 3 Logic 25% 75% 20% 100%Latches & FF's 155,045 DICE FF's 126,884 DICE Latches 28,161 MBIST FF's -

DICE FF's or Latches w/o Data Filter 41,100 Clock Frequency (MHz)Control

DeratingSystem

DeratingGates 1,157,450 266 25% 50%Gates/FF 7.47

* System Derating accounts for bits that are not accessed Reset SET Rate 1.93E-07 after upset or do not propagate to a detection point.Clock SET Rate 3.44E-07 ** In this case the utilization factor is 100%

Composite SRAM Bit Error Rate 2.06E-10Raw SRAM Bit Error Rate 1.84E-06FF SET Bit Error Rate (44ps) 1.48E-08 Intel estimate 10%FF SET Bit Error Rate (280ps) 5.83E-14 IBM Server Estimate 40%FF SEU Bit Error Rate 4.56E-09 SDC estimate 50%

Clock RE Derating

2: UT840 Chip Level Analysis• Adjust Drive strengths• SEE\SET filter additions• Clock\Reset Tree Hardening



• Die Size: 135 mm2 (11.6 x 11.6)• Macros: 220 placements• Package pins : 445 Signals; 229

Pwr/Gnd; 55 spare (2083 die bumps)• Gate Count: 4.4M logic gates,

5Mbit Memory (~20M trans)• SysClk : 300MHz (Nom)

Background: Device Statistics

25 February 20156



• Dhrystone benchmark was run at maximum frequency on single core and compared to maximum frequency results from UT699 and UT700

Single Core Comparison

25 February 20157

• UT840 order of magnitude improvement in W/MHz over UT699• Indicates process

technology impact• UT840 max frequency

exceeded simulation (300 vs. 266 MHz)

Performed using BCC, with UT699 @ 100MHz, UT700 @ 220MHz, and UT840 @ 300MHz. All at 25ºC. Unused cores clock gated.



• Custom tests were run to gauge UT840 power consumption with multiple cores active.

Power Tests

25 February 20158

• ~150mA/core at 100MHz• ~400mA/core at 275MHz

Performed using Aeroflex developed “CPU gate” test. During this test all interfaces except the ETH0 are clock gated. Core at 1.0V, 25ºC.

Static Current ~250mA



• Dhrystone benchmark run with 1 to 4 cores enabled, using LINUX operating system at 250MHz, 25ºC.

Quad Core Efficiency

25 February 20159

Linux Operating System, using L2 cache only. No external SDRAM.

•Multicore efficiency ~85% with 4 CPUs active.



• A sample of Standard Performance Evaluation Corporation (SPEC) CPU2000 benchmarks were run to evaluate integer and floating point performance across multiple applications

SPEC CPU2000 Benchmarks

25 February 201510

Name Description175.vpr FPGA Circuit Placement and Routing176.gcc C Programming Language Compiler186.crafty Game Playing: Chess197.parser Word Processing (syntatic analysis)252.eon Computer Visualization255.vortex Object-oriented Database

Name Description172.mgrid Multi-grid Solver: 3D Potential Field177.mesa 3-D graphics library179.art Image Recognition183.equake Seismic Wave Propagation Simulation187.facerec Image Processing: Face Recognition188.ammp Computational Chemistry189.lucas Number Theory / Primality Testing200.sixtrack Nuclear Physics Accelerator Design

Integer Benchmarks Floating Point Benchmarks

• For multi-core operations, each core ran its own individual copy of the benchmark



• Testing performed with 100MHz system clock and 50 MHz memory clock at nominal conditions

SPEC CPU2000 Integer Benchmarks

25 February 201511

• Reduced efficiency compared to Dhrystone testing expected due to increased IO and memory intensity of CPU2000 programs



• Testing performed with 100MHz system clock and 50 MHz memory clock at nominal conditions

SPEC CPU2000 Floating Point Benchmarks

25 February 201512

• Extremely (>90% four CPUs) high efficiency on some benchmarks driven by FPU/core architecture


UT840 LEON Quad Core First Silicon ResultsVoltage Temperature Dependence

25 February 201513

• UT840 performance strongly affected by core voltage and operating temperature.

• 1.1V increased max frequency 27% over nominal at 25ºC. • 125ºC overwhelmed this improvement at 1.1V.



• A next generation LEON 4FT processor has been developed and characterized

– UT840 Quad Core LEON 4FT is functional– Device meets 300MHz clock frequency and 2.2W at nominal

conditions– Multicore efficiency is ~85% when all cores are active for

Dhrystone bench mark, and has demonstrated over 90% efficiency for some floating point bench marks

• Thank You!

Summary

25 February 201514

© 2015 The Aerospace Corporation

Compressive sensing to Reduce the Demands for On-board Processing, Storage and Communications Links

George C. Valley, George A. Sefler, T. Justin ShawPhotonics Technology DepartmentThe Aerospace [email protected]

27 January 2015


Outline

• Issues in taking data on remote platforms• The Compressive Sensing Solution• Sparsity• Mixing down in dimension• Signal or Image Recovery• CS with RF signals in the optical domain• Results for RF pulses and sine waves• Conclusions

Acknowledgement: This work was supported under The Aerospace Corporation'sIndependent Research and Development Program.


Issues in taking data on remote platforms

• Information is broadband• Sensors take too much data

– Fill on-board storage in no time– Swamp communication links– Overwhelm on-board processors

• System compromises– Limited number of frequency bands– Low resolution images– Slow video rates– Sparse arrays


The Compressive Sensing Solution:Mix down in dimension in the analog domain

=Mmeasurements

NInput signal

SparseSignal

Knon-zeroelements

K < M << N

Typical values: N = 1000 - 100000K = 10 - 500M ~ 5 x K


The 3 fundamental concepts of CS

• Sparse signals/images

• Analog Mixing

• Signal/Image Recovery


Most signals and images are sparse

Example: Sparse vector

Not very interesting for applications


Add noise

A sparse vector with low level noise

Extension to matrices, images easy


Add a pedestal or background

Subtract out background


Use transforms to find sparse signals

Signal plus noise plus pedestal

Discrete FourierTransform showsSignal is sparse


What if your data is not sparse under any known transform?

• Example—find the “bicycle transform”

Not limited to transforms of applied math. Find the transform for the application

Sapiro et al. “Learning sparse representations to restore, classify, and sense images and videos”Duke Workshop on compressive sensing 2009. Reprinted with permission of Professor Sapiro.

Semi-superviseddetection/learning


Recovery before CS: solve A.x = y

• Square A

• Solution Methods– y = A-1.x– Least squares

• Actually, there were a lot of other methods prior to CS

– MUSIC– Singular Value Decomposition– CLEAN algorithm (radio astronomy)– Matching Pursuit– Maximum Likelihood . . .

=.

= .

A

A-1

x

x y

y


CS Signal recoveryy A

. xA-1 No Inverse!!!

Need a minimization algorithm that uses sparsity

xrec (λ)= argminx [ λ Sparsify(x) + Measurement(x)]

Count number of non-zero entries in x ½ |A.x – y|2

Combinatorial problem—too slow (NP hard)

Good Solution: xrec (λ)= argminx [ λ Σi |xi| + ½ |A.x – y|2]


Mixing RF signals: Wideband Converter

• Make M copies of signal• Multiply each copy by different pseudo-random bit sequence• Integrate for the duration of the PRBS and Digitize

• Electronic PRBS waveform must be accurately known

• Amplitude and timing jitter must be low• Electronics to generate PRBS has same issuesas electronic ADCs• Motivated us to consider an optical realization for GHz band signals

Mishali and Eldar IEEE Journal of Selected Topics in Signal Processing, Vol. 4, pp. 375 (2010).

Splitter/Divider

0

1

RF input

Integrator/ADC 1

0

1

Integrator/ADC M

Copy 1

Copy M


Optical Wideband Converter with Parallel Channels

Each row of SLM mixes a different PRBS with RF signalPRBS is static—no jitter

MLL

ChirpedFBG

MZM ADCs

λ

Time

Phot

odio

de A

rray

BroadbandOptical Pulse

ModulatedChirped Optical Pulse

Spatial LightModulatorDiffraction

Grating

ADC

ADCADC

ADC

ADCADCADCADC

SphericalCollimator C

ylin

dric

al L

ens

CylindricalLens

RowC

olum

n

RF Input

A Matrix y vector

Phot

odio

de A

rray

First optical wideband converter concept proposed by Valley and Sefler Proc. SPIE 7797, 2010

Mode-locked laser Mach-Zehndermodulator


OWC implemented in our Laboratory1D SLM, Serial measurements with single channel

MLL

DCF

MZMLarge-AreaPD

ADC

BroadbandOptical Pulse

ModulatedChirped Optical Pulse

Spatial LightModulator

DiffractionGrating

SphericalCollimator

CylindricalLens

RF Signal

Valley, Sefler and Shaw Opt. Lett. 2012

Build up y vector in time by varying SLM pattern. RF must be synchronizedto mode locked laser

Syncing RF and MLL unrealistic for applications

photodiodeMode-locked laser Mach-Zehndermodulator


OWC CalibrationSignal recovery very sensitive to errors in measurement matrix A

0 20 40 60 80 100 1200

0.002

0.004

0.006

0.008

0.01

0.012

0.014

"j" : SLM Pixel No.

0 20 40 60 80 100 1200

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

"j" : SLM Pixel No.0 20 40 60 80 100 120

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

"j" : SLM Pixel No.

0 20 40 60 80 100 1200

0.2

0.4

0.6

0.8

1

"j" : SLM Pixel No.

Pi(λj)

Mij x Sij x Pi(λj) x L(λj)

L(λj)

Φij

Mij

0 20 40 60 80 100 1200

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

"j" : SLM Pixel No.

Sij

Input PRBS SLM Patterning

Laser Spectrum Insertion Loss

Calibration CheckMeasured y vs. Calculated y with RF = 0

Deviations from straight line used as additional corrections to y

Effective Measurement Matrix

A =


Results 4 pulses (1 double pulse)Recovery method: Penalized ell-1 norm, λ = 10-2.5

K (intended) = 4. K(actual) ~ 12. Mmin = K log(N/K) ~ 27

s’(λ) = argmins(λ||s||1 + 1/2|| y - Α s ||22)


Sine waves recovered with Orthogonal Matching Pursuit

RF signal: sinusoids at 71.42 and 214.16 MHzInput signal: redRecovered signal: black

2 sine waves3

45

2 sine waves input,5 sine waves recoverednonlinear distortions added by OWC

Valley, Sefler, Shaw Proc SPIE 8645, 2013


Signal recovery terminates abruptly if small dimension of mixing matrix drops below critical value

M

Theory: Mcrit = K log(N/K)

Pulses K = 9, N = 118Mcrit = 23.2

Sine wavesK = 2, N = 118Mcrit = 8.2


Issues Compressive Sensing

• Sparse transform– Current work on deriving the transforms directly from the data

• Convenient mixing technology– Mixing need not be random– Current work on adapting to measurement system as is

• SNR determined by the number of measurements– “CS SNR penalty” no real penalty but undersampled measurement will

not have same SNR as Nyquist rate sampled• Speed of recovery algorithms

– Current work on algorithms matched to measurement matrix for optimal speed: e.g. CS video camera with real-time image recovery


Conclusions

• Solution to the issue of too much data is to take date more intelligently

• Undersampling and thinned phased arrays have been around for a long time

• Ell-1 norm based recovery also an old topic• Compressive Sensing research since 2005 solidifies these ideas

and gives a strong foundation for applications• Photonic CS system allows recovery of GHz-band RF signals

© The Aerospace Corporation 2015

Single Event Effects in Carbon Nanotube Based Field Effect Transistors under Energetic Particle Radiation: Evidence for a New Type of Single Event Effect

Adam W. Bushmaker, Don Walker, Colin Mann, Vanessa Oklejas and Alan R. HopkinsPhysical Science Laboratories/The Aerospace Corporation

Stephen B. Cronin, Moh AmerThe University of Southern California/Department of Electrical Engineering

Tuesday, Jan 27, 2015

[email protected]/PSL

Summary

• Experimental overview• SEE data• SEE analysis• Discussion including possible mechanisms


CNT Structure

• Graphene rolled into a cylinder• Crystal structure determined by chiral angle• Formed by extrusion on catalyst nanoparticle

Arnero / CC-BY-SA-3.0http://commons.wikimedia.org/wiki/File:Carbon_nanotube_armchair_povray.PNG

Kebes / CC-BY-SA-3.0http://en.wikipedia.org/wiki/File:CNTnames.png

Carbon seed gas

CNT

Catalyst nanoparticle

http://creativecommons.org/licenses/by-sa/3.0/

http://commons.wikimedia.org/wiki/File:Carbon_nanotube_armchair_povray.PNG

http://en.wikipedia.org/wiki/File:CNTnames.png


http://en.wikipedia.org/wiki/File:CNTnames.png


Why Study Carbon Nanotubes?

• Geometry– 1nm in diameter, 1cm in length aspect ratio ~107

– 100% surface-to-volume ratio• One-dimensional effects

– Van-Hove singularities– Ballistic electron conduction– Strong electron-phonon coupling

• Material properties– High electronic current carrying capacity (109 A/cm2)

• 1000x higher than that of the noble metals– High electron/hole mobility (100,000 cm2/Vs at room T)

• 100x higher than that of most semiconductors– High melting point ~3800oC – High Young’s modulus 1TPa

• > diamond– High Thermal conductivity (6600 W/m*K at room T)

• 2x diamond (3320 W/m*K)

Mstroeck / Wikimedia Commons / CC-BY-SA-3.0 / GFDL http://en.wikipedia.org/wiki/File:Types_of_Carbon_Nanotubes.png


http://en.wikipedia.org/wiki/Wikipedia:Text_of_the_GNU_Free_Documentation_License

http://en.wikipedia.org/wiki/File:Types_of_Carbon_Nanotubes.png


Current or Near-Term Applications of CNTs

• Microelectronics applications– Flexible and transparent electronics (conductors and FETs)– Non-volatile rad-hard memory (NRAM)– High linearity FET amplifiers

• Macroelectronics applications– Coaxial cable– ESD shield/ESD management– Thermo-acoustic speakers– Lithium-Ion battery electrode additive (improves reliability) – Conductive plastic

• Optical applications– Ultra-black optical coatings (darkest material ever made)– Saturable optical absorber for mode-locked lasers– Microwave/THz polarizing filters

• Structural applications– Structural composites– Ballistics armor

M.F.L. De Volder et al, “Carbon Nanotubes: Present and Future Commercial Applications” Science, 339, 535 (2013)


Carbon Nanotube Field Effect Transistors

• Semiconducting CNTs can be used to build field effect transistors (FETs).

• Single-CNT FETs obtained through collaboration with USC (professor Stephen Cronin)

• Suspended CNT design with Pt electrodes

sour

ce

drai

n

gate trench

CNT

1 µm


High Energy Proton Testing (50 MeV)

• Experiments conducted at the 88” Cyclotron facility• Berkeley Accelerator Space Effects (Base) Facility:

Aerospace designed and operated facility• Testing in-situ with 50 MeV protons

S D G

Semiconductor Parametric Analyzer

50 MeV protons

Beam Flux Analyzer

Beam Aperture

CNT-FET


Effects of Proton Radiation on the CNT FET

• SEE effects dominate radiation response of IV curve

• Changes observed in threshold voltage

• SEEs observed on multiple devices

GIF movie–

view in presentation mode

(Dose is in krads, not rads)

Vth shift


SEE Analysis

Major and Minor Single Event Effects


“Major” SEE AnalysisSEE Analysis


SEE AnalysisStructure of the single event effects

• Drops in drain current show step-like recovery, rather than exponential

• Duration of transient much longer than traditional SEEs (100’s of ms)

Magnitude and Duration


SEE AnalysisStructure of the single event effects

Magnitude and Duration

0 0.5 1 1.510

0

101

102

coun

ts

SEE duration (s)

e-t/τ, τ = 0.20s

Detection Threshold

• Measured duration of large number of SEEs– Results follow exponential distribution (τ = 0.2s)


pristine IV

Major SEEs

Overlay of gate sweep plots from the same device

SEE AnalysisGate Voltage Dependence of Major SEEs

• Pristine IV observed most of the time• CNT FET seems to fall into a quasi-

stable degraded state– Depth of SEE depends on gate voltage– Quasi-stable state has lower sub-

threshold slope– There are a few outliers below the

quasi-stable state

Major SEEs look like they switch to a quasi-stable state


Experimental set-up: Electrical data collection and Co60 chamber

Co60 Testing


SEE Rate Dependence on Gas Environment

• Count rates of SEEs during gamma radiation in different gasses:– N2 pre-oxygen: 0.026 cps (~1SEE/200 rad(Si)– Argon: 0.030 cps (~1SEE/200 rad(Si)– O2: 0.0045 cps (~1SEE/1000 rad(Si)– N2 post-oxygen: 0.0066 cps (~1SEE/1000 rad(Si)

Oxygen may be acting as a quench gas, which stifles the SEE count rate

Oxygen has large effect on SEE count rate

Pure O2atmosphere

Radiationoff

Radiation Induced SEEs During Exposure to Co-60

Dose rate 3.67 rad(Si)/s


In air

In N2

Co-60 SEEs:

SEE Rate Dependence on Gas Environment

• Plot SEE depth vs duration during Co-60 exposure:– In air, there is only ONE grouping

of SEEs (cyan points)– In N2, there are TWO groups of

SEEs: • N2 increases the duration of

SEEs observed in air• This suggests there are two

different processes happening in N2

N2 group 2

N2 group 1

Air group

Oxygen in air has large effect on SEEs

SEE Depth versus Duration


Multiple Major SEEs at the Same Time• Convert measured current to resistance (R = Vds/Id)• Can see multiple step-like transitions in major SEEs indicates multiple simultaneous events

0

1

22 2 2 2

22 2

22

22

3

1 1 1 1 1 11

1 1 11

1 11

0 0 0 0 0 0 0

1

Vds = 0.1V

Resistance shown is a running average of 20 data points to smooth out the noise

14

12

10

8

6

4

2

0

Current versus Time

Resistance (GΩ) versus Time

Res

ista

nce

(GΩ

)D

rain

Cur

rent

(A)


Hypothesis for SEEs: quasi-stable defect state on the CNT is ionized/switched by the radiation

Source Drain

Defect 1

Rdefect

Source Drain

Defect 1 Defect 2

Rdefect Rdefect

Source Drain

Defect 3 Defect 1 Defect 2

Rdefect Rdefect Rdefect

Ndefects = 1

Ndefects = 2

Ndefects = 3

1

0

2

1

0

2

1

2

0

• Multiple current states with uniform step sizes of resistance consistent with multiple identical defects along CNT, each adding Rdefect = 3 GΩ in series

• Switching of charged defect state causes change in:– charge density– mobility

Small, 1-D channel of very sensitive to defects

14

12

10

8

6

4

2

0

Res

ista

nce

(GΩ

)D

rain

Cur

rent

(A)


Conductance-Controlled Point Functionalization of CNTsResearchers created defects on CNTs that strongly switch conductance

Similar behavior observed in other CNT systems

• No radiation in this work


Conclusions• Single event effects observed in isolated carbon nanotube field effect transistors

– Observed in many devices

• SEE data analyzed to find

– Quantized current levels

– Discrete steps in conductance (as opposed to gradual exponential decay)

– Sensitivity to gas environment surrounding the CNT (particularly O2)

• Hypothesis: quasi-stable defect state on the CNT is ionized or switched by

the radiation

– Compared to similar data from other CNT FET systems

– Potential defects and sources for ionization explored

Bushmaker, et al. "Single Event Effects in Carbon Nanotube-Based Field Effect Transistors Under Energetic Particle Radiation." IEEE TRANSACTIONS ON NUCLEAR SCIENCE 61.6 (2014): 2839.


Thank You!

Acknowledgements– Work at The Aerospace Corporation funded by the Independent Research and Development

Program at The Aerospace Corporation– Ron Lacoe, Jon Osborn of The Aerospace Corporation and Cory Cress at NRL– Collaborators at the University of Southern California, Department of Electrical Engineering

All trademarks, service marks, and trade names are the property of their respective owners

Physical Sciences LaboratoriesThe Aerospace Corporation



Individual Defects on the CNT

• Topological defects (5-7 pairs)• Adsorbed surface molecules

– Residual carbon adsorbed-atoms from CVD process– plasticizers and solvents outgassed from plastic storage containers

• Above involved in some sort of switching event:– Quasi-stable bond formation– Quasi-stable ionized charging

Candidates:


“Minor” SEE Analysis SEE Analysis


Minor SEE

• Before radiation starts, current level is smooth (with Gaussian noise)• When the beam is turned on

– Can see Minor SEEs at discreet drain current levels

Current Level Distribution Analysis of Minor SEES

0 2 4 6 8 0

20

40

60

80

100

time (s)

drai

n cu

rrent

(nA

)

0 0.5 1normalized counts

0 5 10 0

20

40

60

80

100

time (s)

drai

n cu

rrent

(nA

)


Beam Off Beam ON

MinorSEEs

Gaussiandistribution

Current level distribution analysis



TheoryModel for N multiple identical defects switching with probability p0• Individual peak height = comb*p0

– Comb = number of combinations of N things taken k at a time:

– p0 = probability that k of N defects have switched

(Where p is the probability of an individual defect switching)

𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 =𝑁𝑁!

𝑁𝑁 − 𝑘𝑘 !𝑘𝑘!

𝑝𝑝𝑝 = 𝑝𝑝𝑘𝑘 1 − 𝑝𝑝 𝑁𝑁−𝑘𝑘


Future Work

• Further analysis of SEE data

• Measure effect of temperature on SEE statistics

• Numerical simulations of electrical transport defected CNT FETs


SEE AnalysisDiscrete levels shift as threshold voltage shift progresses



0 5 10 70

80

90

100

110

120

time (s)

drai

n cu

rrent

(nA

)


0 5 10 70

80

90

100

110

120

time (s)dr

ain

curre

nt (n

A)


0 5 10 70

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90

100

110

120

time (s)

drai

n cu

rrent

(nA

)


0 10 20 70

80

90

100

110

120

time (s)

drai

n cu

rrent

(nA

)


0 20 40 70

80

90

100

110

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time (s)

drai

n cu

rrent

(nA

)


0 10 20 30 70

80

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100

110

120

time (s)dr

ain

curre

nt (n

A)

Serial: 1515

Serial: 815 Serial: 955 Serial: 1235

Serial: 1655 Serial: 1795


SEE Analysis

• After radiation turned off, current level is

smooth again

– Can be fit with Gaussian curves again

– Current is increased due to SiNx charging

(threshold voltage shift)



0 10 20 70

80

90

100

110

120

time (s)

drai

n cu

rrent

(nA

)

Pre-Rad

Post-Rad

Si3N4

SiO2

SiliconSubstrate

100nm

1000nm

Resist

- - - ------ - - - --CNT DrainSource

Gate

Dose ~ 365 krads

Id shift

30

• SEEs occur during exposure to gamma radiation• When plotted on in a log scale, we can see that the nitrogen has an

effect on SEE depth and SEE length

Sensitive But Unclassified (SBU)Aerospace Proprietary information

Radiation Induced SEEs During Exposure to Co-60

Single-Event Effects in Emerging Device Technologies

R. D. Schrimpf, M. L. Alles, R. A. Reed, D. M. Fleetwood, S. Weeden-Wright, K. Ni,

I. Samsel, and E. X. Zhang

Vanderbilt University

Outline

•  Soft errors •  Fully-depleted SOI •  FinFETs •  Charge deposition in small volumes •  III-V MOSFETs •  Alternate-channel materials •  Resistive memories

Single-Event Effects (Soft Errors)

•  Ionizing particles (heavy ions, protons, alpha particles, muons, secondary products from neutrons) deposit energy, create “extra charge” •  Transient currents result from collection at junctions •  Known problem for charge-based devices: can change

memory states when in storage state •  Considerations for emerging memories may differ

•  Storage element may be intrinsically resistant to SEE •  Transients in surrounding circuitry (still CMOS!) may

induce false write conditions •  Window of vulnerability may be different: may only be

vulnerable when programming bias conditions present

Advanced CMOS

IBM (PD) ST (FD)

IBM

Intel TS

MC

SOI vs. Bulk – Single-Event Effects

  SOI limits collection volumes -  Assumption: no contribution from isolation regions -  Advantage for single-event and-dose rate environments

  SOI limits multiple-device collection -  Assumptions: no shared diffusion, low incident angles -  Singe-event testing at high angles in important

  SOI has floating-body effects -  Parasitic bipolar effects can amplify deposited charge

  Body contacts can mitigate at expense of area, capacitance

Single-Event Modeling

•  What happens in a small fin (esp. SOI) •  How does a single event impact a Multi-Fin FET ? •  What happens between the Fins ? •  How do we model that in TCAD and Circuit Designs

SOI SEU Trends (Commercial SRAMs)

•  Cross sections and sensitive volumes decreasing, esp. in FDSOI planar and FinFETs

•  Cross section becoming less “ideal” •  Upset thresholds also decreasing, so sensitive

to more of the environment

Single-Event Transients in SOI

•  Single-event transients are an issue for logic and clock tree circuits

•  SETs can propagate to latches and lead to errors

Ultra-Thin-Body FDSOI - SEU

•  Ultra-thin silicon layer reduces single-event charge collection •  Maximum cross section < 10-10 cm2

•  > 10X reduction in heavy-ion SEU upset cross section for 28nm UTB FDSOI vs. bulk

•  > 10X reduction in Neutron vs. 45nm PDSOI and > 5X reduction vs. 28nm bulk

14nm SEU Trends

•  Simulations indicated that thresholds for SRAM SEU continue to follow scaling trends to 14nm SOI planar and FinFETs •  Offset by smaller collection volumes to

maintain low error rates

•  SOI helps to mitigate the proportional growth of MBUs seen in bulk technologies

SER-Bulk FinFET vs. Planar

•  22 nm Bulk FinFETs less sensitive than 32 nm bulk; estimated to be less sensitive than 22 nm bulk planar

•  Multi-cell upset trends unchanged, dominated by spacing

•  No direct comparison to FDSOI or SOI FinFETs (yet)

Key Considerations for Small Volumes

•  Understanding single event sensitivity of devices, we have to ask “how much?” and “where?”

•  Many of our current assumptions are based on LET

•  Variability in direct ionization is becoming a dominant process for small volume technologies

•  LET Fluctuations, spatial energy deposition, effects of stopping ions in nano-structures

•  Variability is observed to have a significant impact SER predictions and for SEE response of emerging devices (like FinFETs).

Spatial Energy Distribution

•  Device features are now on the order/smaller than spatial carrier distribution from ion strikes

•  Sensitivity of device may now be determined by ion track

•  Is a spatial Gaussian an appropriate representation?

•  Is the LET an appropriate metric?

Spatial Carrier Distribution & LET

•  Ions with the same LET can have very different track structures •  Example: 46 MeV Cu and 280 MeV Fe, LET ~ 25 MeV-cm2/mg •  Track profiles are not truly Gaussian •  Tails and extreme events differ for ions with the same LET

10-1

100

101

102

Energy Deposited (keV)

10-6

10-5

10-4

10-3

10-2

10-1

100

P(E

i)

50 MeV Protons1 μm Si

LET ~ 2 keV/μm

LET FluctuationsLET Fluctuations

LET Fluctuations

LET: the average energy lost per unit path length

  LET Fluctuations•  Increase with decreased collection volume [1]•  Large for lightly ionizing particles

[1] H. Bichsel, Nuclear Instruments and Methods in Physics Research A, vol. 562, pp. 157–197, March 2006.

LET can be a poor representation of the distribution

50 MeV Proton 280 MeV Oxygen

Silicon

LET & Environment Models

•  Environment Models•  Use LET to represent entire radiation environment•  Peaks are associated with a single species

1.  Large abundance of high energy particles (minimum ionizing)2.  These particles have comparable LETs

Results in a pileup in LET spectra

SiliconSiliS con

Accounting for Fluctuations in Environment Spectra

  Capture energy deposition for entire radiation environment including LET Fluctuations•  Conceptually similar to 50 MeV proton case•  For all particles in environment over all energies

10-1

100

101

102

Energy Deposited (keV)

10-6

10-5

10-4

10-3

10-2

10-1

100

P(E

i)

50 MeV Protons1 μm Si

LET ~ 2 keV/μm

LET FluctuationsLET Fluctuations

10-1

100

101

102

103

104

105

106

Specific Linear Energy Density (MeV-cm2/g)

10-15

10-13

10-11

10-9

10-7

10-5

10-3

10-1

101

103

105

Flu

x (m

2 -s-s

r-(M

eV-c

m2 /g

))-1 CREME96

MRED - 500 nm

100

10110

1

103

105

AlGaN/GaN MOS-HEMTs

•  Gate oxide species and band alignment play a key role in the charge collection mechanisms of MOS-HEMT devices •  Gate transient current observed during heavy ion irradiation despite

MOS gate structure

Ion Strike

•  Small valence band barrier introduced by band alignment of HfO2 gate oxide and AlGaN allows ion-generated holes to be collected by gate terminal

•  Conventional band alignment between oxide and silicon prevents transient gate current

InGaAs MOSFET

•  Quantum well channel

•  Both electrons and holes are collected in

the channel

0.00 0.02 0.04 0.06 0.08-4

-3

-2

-1

0

1

2

ener

gy (e

V)

position (μμm)

Conduction Band Fermi Level Valance Band

InGaAs MOSFET

•  No gate transients due to large barrier

5 10 15 20 25 30

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

curr

ent (

mA)

time (ns)

drain source gate • 

• 

•  Source and drain transient have the same magnitude (transients come from the channel current)

Bias Dependence

•  Peak drain current is maximum near the threshold voltage

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.60.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

Laser Results Heavy Ion Results 2D TCAD Simulation

norm

aliz

ed p

eak

curr

ent

VGS-VTH (V)

•  It decreases quickly in inversion and slowly in accumulation and depletion

SiGe QW pFETs

•  Ultra-thin conduction channel in quantum-well structures requires consideration of potential effects of SETs of both polarities in device characterization

4nm SiGe QW Channel

Laser “Strikes”

•  Laser irradiation allows charge collection to be mapped spatially

•  Transient polarity reverses as laser “crosses” channel

•  Simulations show polarity flipping effect not present in thicker-channel devices

SEE (Soft Errors) in Emerging Memories

•  Ionizing particles deposit energy, creates “extra charge”

•  Change from charge based to spin/atomic arrangement •  Reduce single event & TID vulnerability of the

memory element

•  Tends to increase wear-out concerns

•  Considerations for emerging memories may differ

•  Vulnerability of underlying circuitry can still lead to single event and/or TID vulnerabilities

•  Window of vulnerability may be different: may only be vulnerable when programming bias conditions present

SEU in HfO2 RRAM on CMOS

  Laser or ion strike to access transistor when program bias (VDD) present shown to change resistance (SEU) > 100 KΩ to < 10 KΩ   Effects of multiple strikes can be cumulative   Window of vulnerability is small (< 0.5% of time)

Conclusions

•  Emerging device technologies •  FDSOI •  FinFETs •  Alternate channel materials

•  Challenges •  Multi-cell upsets •  Energy deposition in small volumes •  Band alignment in complex material systems •  New memory elements •  New models required

1Presented by S. Buchner at MRQW 28TH January 2015, Los Angeles

Evolution of Spatial Dependence of Charge Collection Responsible for Single Event Latch-up

using a Pulsed LaserN. J-H. Roche1,2, A. Khachatrian1,3, S. Buchner1, C.C. Foster4,

J.H. Warner1, D. McMorrow1, T. Decker5, F. Miller6, S. Morand6, M. King7

1.US Naval Research Laboratory, Washington, DC2. George Washington University, Washington DC

3. Sotera Defense Group, Herndon VA4. FCS, LLC, University Place WA

5. Analog Devices Inc., Greensboro NC 6. Airbus Innovations Group, Serennes, Paris, France

7. Sandia National Laboratories, Albuquerque, NM


Goal• Single Events are caused by charge deposition

and collection. Both temporal and spatial information are essential for understanding mechanisms of single event effects.

• Apply a focused, pulsed laser beam to study the evolution of Qcoll responsible for single event latch-up in an ADC (AD9240) because it provides both temporal and spatial information.

• The spatial dependence of Qcol was obtained by generating charge collection spectra similar to those obtained from Pulse Height Analysis (PHA) during heavy-ion irradiation.


Pulse Height Analysis• Pulse Height Analysis Measurements with

Heavy Ions – carrier generation via Coulomb Interaction.

The entire device is irradiated with spatially random ion strikes


Pulse Height Analysis• PHA spectrum for a fully depleted Surface

Barrier Detector.

P. McNulty et al. Nucl. Tracks Rad. Meas. Vol 19. 1991

Number of points comprising the peak divided by fluencegives area (cross-section) of the SBD.

E→

PHA

- +++-

-

Charge Collection Spectrum from a Surface Barrier Detector.


Pulse Height Analysis• Single Event Effect is caused by an energetic

ion generating charge at or near a sensitive junction in a circuit. The charge is collected at the junction.

P. McNulty et al. IEEE TNS Vol 38, 1991

Charge Collection Spectrum from an n-channel Transistor at two Voltages

P-substrate

N N


Pulse Height Analysis• The charge collection spectra for ICs are

complex because of the presence of multiple junctions.

• One problem is that, under bias, noise masks signals.

P. McNulty et al. IEEE TNS, Vol. 38, 1991

A

B

Charge Collection Spectrum from a CMOS SRAM


Results – Heavy Ions• PHA spectrum obtained from AD9240 obtained

at Lawrence Berkeley Nuclear Laboratory’s 88” cyclotron.

• Entire circuit exposed to ion beam

AD9240 Analog-to-Digital Converter14-bit, 10 MSPS CMOS


Pulsed Laser Testing• Use a pulsed laser beam to

generate charge collection spectra similar to PHA.

• Qcoll proportional to area under transient.

• By triggering off laser, noise under bias can be reduced

Oscilloscope

Power supply

X direction

Focusing LensSpot size 0.9 umλ = 590 nm

Pulse length = 1 ps

Laser beam


Generating Spectrum of Qcoll

• Scanned area 70 um x 70 um• Color at each pixel represents magnitude of

Qcoll (area under transient) measured at that point.

• Bin 5-um x 5-um area around maximum Qcoll


• Bin Qcoll for 10-um x 10-um area around maximum









Qcoll vs Laser EnergyPulsed Laser Mapping of Charge Collection (70 µm x 70 µm) at 0 Volts

Low Energy High EnergyMedium Energy


Pulsed Laser Mapping of Latchup (70 µm x 70 µm) at 5 Volts

Low Energy High EnergyMedium Energy

• Latchup under 5-Volt bias does not occur where there was maximum charge collection under 0-Volt bias

Latchup vs Laser Energy


Qcoll Spectrum for Large Area

• Bin Qcoll for 70-um x 70-um area with low energy


• Bin Qcoll for 70-um x 70-um area with medium energy



• Bin Qcoll for 70-um x 70-um area with high energy



Qcoll vs Laser Energy• Linear relationship between collected charge

at peak and laser pulse energy.


Test Locations• AD9240 has three power supplies:

–AVDD, –DVDD, –DRVDD

Reg#1

Reg#2


Charge Collection vs BiasRegion #1: 526.5 pJ, AVDD


Charge Collection vs BiasRegion #1: 526.5 pJ, SEL

10 20 30 40 50

10

20

30

40

50

X (µm)

Y (µ

m)

0.000

1.000

3.0 V - 526.5 pJ

10 20 30 40 50

10

20

30

40

50

X (µm)

Y (µ

m)

0.000

1.000

3.5 V - 526.5 pJ

10 20 30 40 50

10

20

30

40

50

X (µm)

Y (µ

m)

0.000

1.000

4.0 V - 526.5 pJ

10 20 30 40 50

10

20

30

40

50

X (µm)

Y (µ

m)

0.000

1.000

4.5 V - 526.5 pJ

10 20 30 40 50

10

20

30

40

50

X (µm)

Y (µ

m)

0.000

1.000

5.0 V - 526.5 pJ


Charge Collection vs BiasRegion #1: 526.5 pJ, AVDD


Charge Collection vs Bias

Reg.#1: 526.5 pJ, AVDD


Charge Collection vs BiasReg.#1: 526.5 pJ, DRVDD


Charge Collection vs Bias

Region #1: 526.5 pJ, DRVDD


Charge Collection vs BiasReg.#1: 526.5 pJ, DVDD


Charge Collection vs BiasRegion #1: 526.5 pJ, DVDD


Latchup vs EnergyRegion #1: 3.5 Volts, AVDD

27 pJ

55 pJ

260 pJ

526 pJ


Summary – Work in Progress

1. Ion PHA random strikes across the entire chip surface, laser in a small area.

2. As the scanning area grows, the plot should more closely approximate the ion PHA curve.

3. Some differences expected due to metallization.4. Investigating the role of light penetration depth by irradiating

from back side with light having wavelength of 1060 nm and with two-photon absorption.

Distribution A: Approved for Public Release

Radiation Effects in Emerging Technologies for Hardened

Systems

2015 MRQW28 January, 2015

Sarah Armstrong, Matthew Kay, Austin Roach, Adam Duncan, Matthew Halstead, and Matthew Gadlage

NSWC Crane, Crane, IN


IR&D Radiation Effects Research

• FY14 Radiation-Related Projects– “Embedded and Standalone Floating Gate Memory Exploration” --PI: Matthew

Kay– “Ensuring Integrity of Next-Generation Commercial-Off-The-Shelf Field

Programmable Gate Arrays for Trusted Applications” PI: Matthew Gadlage– “Radiation Effects in Gallium Nitride” PI: Sarah Armstrong

• FY15 Radiation-Related Projects– “Radiation Effects in GaN Devices” PI: Sarah Armstrong– “Assessment of Emerging Nonvolatile Memory Technologies: ReRAM and CNT

NRAM” PI: Austin Roach– “FinFET Technology Assessment for Trusted and Strategic Systems” PI: Adam

Duncan– “Impact of Single Electron Effects and Defects on the Reliability and Trust of DoD

Electronics” PI: Matthew Gadlage– “Multi-Die Package Decapsulation and Delayering for Failure Analysis, Trust

Assessment, and Counterfeit Detection in Scaled COTS Microelectronics” PI: Eric Whitney

– “Semiconductor Neutron Radiation Damage Time and Spectral Dependence Studies” PI: Matthew Halstead

2


Non-Volatile Memory

• Recent non-volatile memory research has focused on NAND/NOR Flash, MRAM, and CBRAM:– Explored radiation effects in 42-nm and 60-nm NAND

Flash from Samsung [presented at the 2014 HEART conference]

– Looked at the impact of positive and negative traps in the embedded Flash of an MSP430 microcontroller [to be presented at the 2015 GOMAC conference]

– Shown that no latent failures are present following a heavy-ion irradiation on a Honeywell MRAM [to be presented at the 2015 GOMAC conference]

– Began characterizing the radiation response of AdestoCBRAM cells [to be presented at the 2015 HEART conference] 3


FPGAs

• NSWC Crane is involved in a wide-range of FPGA work for the DoD (including trust, anti-counterfeit, and radiation effects)

• Some of our recent radiation work includes:– Prompt-dose testing of the V5-QV [presented at the 2014

HEART conference]– Exploring low-voltage electron-induced SEUs in 45-nm

FPGAs [presented at the 2014 HEART and SEE/MAPLD conferences]

– Comparing the radiation and aging response in 28-nm Xilinx FPGAs [to be presented at the 2015 GOMAC conference]

– Electron-LINAC upsets in 45-nm and 28-nm FPGAs [to be presented at the 2015 HEART conference]

4


FinFET FPGAs and Processors

• In FY15, we are exploring trust, reliability, and radiation effects issues with FinFET FPGAs and processors, leveraging our NDA with Intel (in place)

• Recently completed work:– Designed a board to test the

Achronix 22-nm Speedster FPGA

– Discussed soft error testing with Tabula and their FPGAs

– Working on Intel’s 22-nm FinFET processors

Achronix DUT Board Design

5


Radiation Effects in Gallium Nitride

High-Speed Devices

Test GaN transistors and MMICs in

hardened environments

TestabilityGaN Laser Testing

At-speed LINAC test Power Devices

Compare Si, GaN, SiC, and other

technologies for suitability in hardened

application

DesignAssessment of

physics of failure, design of gate stacks

for hardened applications

6


Resistive RAM (ReRAM)

• ITRS 2013 lists Resistive RAM as a promising emerging memory technology– Low power, easy integration into BEOL, highly

scalable, potential for fast operation and high endurance

• Active development by many companies:– Adesto: Commercially available CBRAM

(Conductive-Bridging RAM) EEPROM replacement– Panasonic: Commercially available microcontroller

with embedded ReRAM– Crossbar: Integrating technology into TSMC’s back-

end-of-line for SOC applications– Hewlett-Packard/Hynix: Developing a Memristor-

based “universal memory”—dense, nonvolatile memory with DRAM-like speeds

– Sony, NEC, Samsung, Micron, Sandisk, Toshiba, others experimenting with ReRAM

1. C. Gopalan et al., “Demonstration of Conductive Bridging Random Access Memory (CBRAM) in Logic CMOS Process,” Solid-State Electron., vol. 58, no. 1, pp.54-61, 2011.

ReRAM cell in Cu BEOL1

7


ReRAM: how does it work?

• Resistance of bit cell can be electrically modified

• Resistance measured to read information

• CBRAM operation:– Metal electrodes separated

by a solid electrolyte– Applied potential

electrochemically forms a conducting filament between the electrodes

– Reversing the potential dissolves the filament

• Other variants use the movement of oxygen vacancies in transition metal oxides

Image from I. Valov et al., “Electrochemical Metallization Memories—Fundamentals, Applications, Prospects,” Nanotechnology, vol. 22, no. 28, p. 254003, 2011.

8


Previous work on CBRAM reliability

• Characteristics of cells widely tunable (materials, dimensions, electrical operation)– Allows tradeoffs between endurance, data retention, speed, etc.– Can support multiple bits per cell

• Early indications of inherent radiation tolerance– No errors in CBRAM cells after exposure to Co-60 gamma rays at

maximum applied dose of 447 krad1

– No significant changes to the resistance switching characteristics of bit cells after maximum applied dose of 10 Mrad2

– Adesto markets CBRAM for radiation sterilization applications, specifies up to 20 Mrad gamma or e-beam3

1. Y. Gonzalez-Velo et al., “Total Ionizing Dose Retention Capability of Conductive Bridging Random Access Memory,” IEEE Electron Device Lett., vol. 35, no. 2, pp. 205-207, 2014.

2. P. Dandamudi et al., “Total Ionizing Dose Tolerance of Ag-Ge40S60 based Programmable Metallization Cells,” IEEE Trans. Nucl. Sci, vol. 61, no. 4, pp. 1726-1731, 2014.

3. Adesto Technologies, RM24EP128A datasheet, DS-RM24EP128-055, 2014. Available online at http://www.adestotech.com/wp-content/uploads/DS-RM24EP128-055.pdf

9


CBRAM testing at NSWC Crane

• Testing Adesto’s CBRAM in collaboration with NASA GSFC

• Bit cells retained data after:– 3 Mrad(CaF2) exposure to 100 keV x-rays– Exposure to 1x1014 1-MeV-equivalent neutrons/cm2

– 1.3x107 cm-2 of 1858 MeV Ta ions (LET = 79 MeV cm2/mg)• Numerous SEFIs during heavy ion exposure

– Devices do not use a radiation-hardened CMOS– Transients in peripheral circuitry or bit cell access

transistors

Inherent radiation tolerance, ease of integration into BEOL make ReRAM technology a good candidate for integration into hardened systems

10


FinFET FY15 Activities

• Crane researching next generation FinFETs– Radiation effects– Long term reliability

FinFET

Intel 22nm FinFET transistor FinFET vs Planar IV characteristics

11


FinFET FY15 Activities

• Preparing test articles for upcoming tests– Intel 22nm Atom processor– Achronix 22nm FPGA (Intel FinFET process)– IBM 14nm SOI FinFET test structures (maybe?)

• Radiation effects testing – Electron single event effects (Arnold Air Force Base

STAT)– Heavy ion single event effects (Texas A&M)– Total ionizing dose (Crane)

• Modeling – TCAD simulation of charged particle interactions

12


GaN Approach/Methodology

• GaN transistors and amplifiers were tested in multiple facilities 1. neutron 2. x-ray 3. total-ionizing dose4. heavy-ion

• TriQuint High Power Amplifier (HPA) (1,2,3)• Cree HPA (4)• Cree transistors (2,4)

13


Initial Testing

• TriQuint Semiconductor High Power Amplifiers (HPAs)– BW: 30 MHz – 3 GHz

• Electrical Characterization of output power and drain current performed

• Parts sent to White Sands Missile Range for neutron irradiation to a fluence of 1x1013 to 1x1014

neutrons/cm2

14


GaN Transistors

• Cree CGH40025F• GaN Unmatched HEMT• 25W, up to 6.0 GHz

• Evaluation board provides matching to 50Ω for frequency range 3.25 – 4.00 GHz

15


GaN Results/Deliverables

• TONS of test data• 2015 GOMAC

Single-Event Effects in Commercial-off-the-Shelf Gallium Nitride Amplifiers

Highlights potential single-event issues for MMIC devices operating under RF compression

• 2015 HEARTNeutron and X-ray Irradiation of COTS Gallium Nitride

Power AmplifierHighlights potential gate leakage issue

• Multiple collaboration opportunities for FY15– GaN Technology Research Combined Working

Group: AFRL, NRL, Vanderbilt, JPL16


Summary

• NSWC Crane supports numerous customers with radiation effects and trusted electronics work– Including SSP, MDA, Air Force, DARPA, and others

• The NISE/219 program funds a large amount of radiation effects research at Crane

• SPECTRA Lab recently created -(Semiconductor Physics for Electronic Component Trust and Reliability Advancement)

17


Numerical Simulation to Assess Risk of Single Event Burnout in Power Schottky Diodes

Jesse Theiss*Robert M. Moision**Brendan Foran*Brent A. Morgan***

*Electronics and Photonics Lab / Microelectronics Technology Department**Space Materials Laboratory / Surface Science and Engineering Department***MILSATCOM Division / Cross Program Engineering Operations - Systems Effectiveness

[email protected]/MTD

• Computational simulations have been performed to better understand the fundamental physics of diode Single Event Burnout (SEB) – Coupled with direct observations of failure, this effort gives a more complete

understanding of physics and appropriate risk reduction methodologies• Single Event Burnout of Schottky diodes was verified by test in 2013

– Tests of DC-DC converters built with non-space qualified diodes resulted in unexpected failures whose root cause was traced to diode burnout

– Subsequent tests of diode piece parts verified this previously unrecognized failure mode across additional Schottky diode part types

– Prior to these results, diode SEB had not been considered a risk for space programs, despite previously observed failures in terrestrial power PN diodes

• Diode SEB has an uncertain impact on reliability– Lack of test data and poor understanding of the physics of failure– Contractors’ diode derating guidelines and practices may already be sufficient

to mitigate this failure mode, but with how much margin?– Not clear if SEB concern extends to all diodes or depends on the design and/or

implementation of the diode technology

Introduction


Terrestrial power diode single event burnout (SEB) Cosmic radiation identified as the culprit in 1994. Still a current concern.

• Catastrophic failure of terrestrial PN power diodes due to cosmic radiation first reported in 19941

• Failures are accepted to be the result of recoil/spallation charge multiplication triggered by hot neutrons from the cosmic ray shower followed by localized thermal runaway

• Observed failures are random in location

• A number of factors influence the SEB frequency:– Altitude (proxy for particle environment)– Voltage (lower is better)– Temperature (inverse relationship)

1. Kabza, H., Schulze, H. J., Gerstenmaier, Y., Voss, P., Schmid, J. W. W., Pfirsch, F., & Platzoder, K. (1994). Cosmic radiation as a cause for power device failure and possible countermeasures. In Power Semiconductor Devices and ICs, 1994. ISPSD'94., Proceedings of the 6th International Symposium on (pp. 9-12). IEEE. (replotted source data)2. Nando Kaminski & Arnost Kopta, Failure rates of HiPak modules due to cosmic rays I Application Note 5SYA 2042-04, ver 04, ABB Semiconductor.

Failure threshold at STP as a fraction of rated voltage for ABB power diodes2

Eighteen diodes in parallel1(4000 V, 65 mm)


SEB reported in Schottky diodes in 2012, 2013• Burnout observed after test in DC-

DC converters intended for space1

• SEB location often located near guard ring1,2

• A bead of silicone added to mask the guard ring region of a Schottky diode caused cross sections drop by almost two orders of magnitude2

Silicone bead applied at perimeter of diode

1. Robert Gigliuto and Megan Casey, "Observed Diode Failures in DC-DC Converters", Presented by Robert Gigliuto at the NASA Electronic Parts and Packaging Program (NEPP) Electronics Technology Workshop (ETW), NASA Goddard Space Flight Center in Greenbelt, MD, June 11-13, 2012. Published on nepp.nasa.gov

2. J.S. George, R. Koga, R. M. Moision, and A. Arroyo, “Single Event Burnout Observed in Schottky Diodes”, 2013 IEEE Nuclear and Space Radiation Effects Conference (NSREC) Radiation Effects Data Workshop


SEB signature is of a high temperature event at edge of Schottky contact. Al/Si eutectic forms at 877 K.

Schottky diodes: SEB images reveal thermal event

High temperature Si/Al melt

TEM cross section of SEB failure

J. S. George, R. Koga, R. M. Moision, and A. Arroyo, “Single Event Burnout Observed in Schottky Diodes”, 2013 IEEE Nuclear and Space Radiation Effects Conference (NSREC) Radiation Effects Data Workshop

Passivation at edge of Schottky contact

Active Schottky region P+ guard ring


• Initial models employed an ionizing radiation strike consisting of 1016-1018

electron-hole pairs/cm3 delivered in 1-3 ps in a 0.2 µm radius, equivalent to an LET of 1.94 MeV-cm2/mg.

• Ion strikes within the guard ring vicinity resulted in remote heating at the edge of the Schottky contact, but the temperature increase was quite small.

Schottky diode preliminary results

That heating is in the wrong area and far too low a temperature for damage!

Ionization track

J. S. George, R. Koga, R. M. Moision, and A. Arroyo, “Single Event Burnout Observed in Schottky Diodes”, 2013 IEEE Nuclear and Space Radiation Effects Conference

(NSREC) Radiation Effects Data Workshop


• Finer simulation meshing was necessary around the ion strike in both the x and z-dimensions to more accurately model the heat flow and temperature increase from Joule heating

• Gradient meshing used to reduce simulation size but maintain accuracy around the strike region

• Change of strike profile and intensity to simulate the LBNL SEB tests with 58 MeV-cm2/mg Ag ions (0.601 pC/µm, Gaussian radial distribution with radius of 20 nm)

• Diode model was modified based on experimental analyses– Scanning and transmission electron microscope (SEM/TEM) images of the

physical device dimensions– Spreading resistance profile data of the dopant concentrations– Electron beam induced current (EBIC) mapping of the physical extent of the

doped p+ guard ring region

Changes to simulations improved results

Revisions improved fidelity and accuracy of simulation with minimal computational cost


Stri

ke #

1

Stri

ke #

2

Stri

ke #

3Schottky diode temperature after ion strike

Time (s)

Tem

pera

ture

(K)

Cross-section with mesh and guard ring doping profile


Schottky diode temperature after ion strike

Cross-section with mesh and guard ring doping profile Cross-section showing temperature profile at ~100 ps after ion strike centered at x = 70µm

Anode

Cathode

Oxide

Strike Location

xy-cross section of

strike

yz-cross section of strike


Modifications to modeled Schottky diode

Simulation structure revised / improved based on SEM/TEM imaging


SEM-EBIC color overlay of a failed Schottky diodeThese images have been vertically stretched (x1.27) to correct the aspect ratio for the 52 ° cross-sectional surface tilt relative to the electron beam

Electron beam induced current (EBIC) signal is overlaid on a scanning electron microscope (SEM) image, mapping both the Schottky barrier of the device and the P+ doped guard ring under the field oxide.

EBIC signal contours highlight a sharper peak intensity distributed beneath the active Schottky Diode (right side of image) and more diffuse at edge of p+ guard-ring moving left beneath the field oxide (yellow overlay).

p+ guard ringSchottky contact


Temperature and current density versus timeTemperature

Current density

Strike location 6 – 500 nm from the anode edge in the guard ring

1 µm

10 µm


Mechanisms for thermal increase and runaway

Without guard ring With guard ring

Ion strike-induced charges disturb the intendedflat potential at the anode edge, creating a highelectric field intensity in the silicon. As chargediffuses away from the initial strike location andreaches this high field point, impact ionizationgenerates additional charge carriers locally aboutthis point. Additional charge multiplication(avalanche) can occur as the electrons travel tothe cathode at the bottom of the device.


Behavior with and without the guard ring

Guard ring dramatically improves ion strike resilience


Current and temperature transientsDifferent strike locations considered

Strike nearest the field oxide edge is the one most likely to damage the diode.

500 nm spacing

Al/Si eutectic temperature is 877 K


Temperature transientDifferent strike locations considered

Strikes nearest the field oxide edge are the ones most likely to damage diode.

250 nm spacing

Simulated structure closely adheres to actual diode structure


Strike simulations at derated reverse biases75%, 55%, 40% of rated voltage assessed

Voltage derating reduces sensitivity and sensitive volume

Locations


LET dependence of experimental diode failures

George, Jeffrey S., Rocky Koga, Robert M. Moision, and Arturo Arroyo. 2013. “Single Event Burnout Observed in Schottky Diodes.” In Radiation Effects Data Workshop (REDW), 2013 IEEE, 1–8. IEEE.


LET dependence of simulated ion strike

A strike of 48 MeV-cm2/mg at location 7, 250 nm left of the anode/oxide edge, induces a maximum temperature ~200 K below that of a 58 MeV-cm2/mg energy strike and below the designated threshold of material failure (1000K).

The lower LET strike produces less electron-hole pairs, a lower current density, and thus less Joule heating than the higher energy strike, effectively reducing the sensitive volume of the device that can lead to ion-strike induced failure.

Strike 5

Strike 7


• Simulation of high energy ion strikes on power Schottky diodes has been successful– Simulation has same failure location as experimental failures– Highly localized temperature increase suggests mechanism for material

breakdown or alloying– Highest temperatures occur for ions striking near the guard ring at the field

oxide edge• Guard ring mitigation of high field effects is temporarily deactivated by the

temporary high concentrations of electron-hole pairs near the anode edge• High electric field intensity and reverse bias results in impact ionization of

the ion-induced charges, further increasing the current density and Joule heating

• BUT: Guard ring is still a net benefit to reliability!– Voltage derating efficacy confirmed• Reduces the sensitive volume and maximum temperature reached

– Ion energy dependence confirmed• Lower LET strikes result in lower temperatures and a reduced sensitive

volume

Conclusion


Acknowledgements

This work was supported by The Aerospace Corporation’s Independent Research and Development program.


Thank you

Questions?


Supplementary Material


• High field gradients near Schottky contact edge can limit reverse breakdown voltage– p+ doped guard ring under the edge of the contact

minimizes edge effects– Geometry of metal contact edge can also minimize

edge effects

• Reverse bias breakdown occurs via avalanche breakdown mechanism– Electron-hole pair multiplication due to impact

ionization

Schottky diode: Structural schematic cross-section

Metal

n+ Si

p+ guard ringSchottkyjunction

n-Si


• Power diodes may undergo destructive failures when struck by high-energy particles at high reverse bias

• Simulation results showed that catastrophic failures resulted from local heating caused by avalanche multiplication of ion-generated carriers (for 17 MeV carbon ion strikes on a diode operating at >= 2700 V reverse bias)

Simulation of SEB in power PN diodes

A. M. Albadri, R.D. Schrimpf, D. G. Walker, and S. V. Mahajan, “Coupled Electro-Thermal Simulations of Single Event Burnout in Power Diodes,” IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2194–2199, Dec. 2005.


• 3-D Schottky diode models are built using the ATLAS simulation framework (Silvaco, Inc.)

• 2-D slices taken from a 3-D Schottky model are shown to the right

• Building and testing devices via simulation allows many device properties to be readily modified– Geometry – Dopant levels– Ionizing strike conditions

• Modeling allows fundamental physics underlying the failure to be understood and will give us the ability to better evaluate reliability.

Schottky diode simulation

p+ doped guard ring

Location of bullet-hole failure site

SiO2Anode

Si


Effects of stress have yet to be incorporated into model


Angle dependence simulation issues• Cannot define mesh uniformly along an angled ion strike track. Grid can

only be defined in Cartesian coordinates. • Silvaco has added new selective cylindrical meshing to Victory Process

to accommodate this problem. – Must move from Devedit/Atlas to Victory framework to use these

features (as well as simulate stress in diode).


Still possible problems with meshing


Simulation of PN power diode under ion strike

• Simulation uses Silvaco TCAD • 20 µm p-doping of 1017 cm-3

• 400 µm n-base of 3.1 × 1013 cm-3

• 20 µm n-doping of 1019 cm-3

• 2700 V reverse bias• 17 MeV carbon ion strike (simulated

equivalent LET = 4 MeV-cm2/mg)

p+

n

n+

Diode cross-section

np+ n+


Silvaco simulation models used

• Impact ionization – Selberherr model (variation of Chynoweth) –lattice temperature dependent, based on E-field, commonly used for reverse-biased avalanche simulation (IMPACT SELB)

• Mobility - Klaassen models (doping, temperature, and carrier dependence)

• Auger & SRH recombination - Klaassen models (concentration and temperature dependence)

• Velocity saturation - Field mobility combined with KLA• Heat flow at high currents - GIGA enabled (LAT.TEMP)• Band gap narrowing (BGN) - due to high carrier concentration• Single Event Upset

– Electron/hole pairs generated along a track with given radial, length, and time dependence

– Estimation of Linear Charge Deposition (LCD) value from Linear Energy Transfer (LET) value – MeV-cm2/mg -> pC/µm


Lattice temperature at 600 ps after ion strike2700 V reverse bias PN diode, 17 MeV C

Highest increase in lattice temperature localized at the

pn-junction

p-doping 1018 cm-3

n-doping 3×1019 cm-3

n-doping 3.1×1013 cm-3


Strike-induced transients in a PN diode2700 V reverse bias PN diode, 17 MeV C

Time of strike

Transient time (s)

Cur

rent

(A)

Transient time (s)Te

mpe

ratu

re (K

)


Strike-induced transients in a PN diode using 17 MeV CReverse biased PN diode (-500, -2700, and -3500 V)

Time of strike

Transient time (s)

Cur

rent

(A)

Tem

pera

ture

(K)We were never able to simulate thermal

runaway using 17 MeV C ions, even atthe highest voltages.Results from Albadri showed thermalrunaway even at 2700 V (below).

A. M. Albadri, R.D. Schrimpf, D. G. Walker, and S. V. Mahajan, “Coupled Electro-Thermal Simulations of Single Event Burnout in Power Diodes,” IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2194–2199, Dec. 2005.


Strike 5 & 7 – Ion strike energy dependence

Two-Photon Absorption Induced Charge Deposition in Silicon by

Ultrashort Optical Pulses: Quantitative Considerations

Dale McMorrow1, Ani Khachatrian1,2, Nicolas J-H. Roche1,3, Jeffrey H. Warner1, Stephen P. Buchner1,

Joseph S. Melinger1, and Joel M. Hales1,2

1Naval Research Laboratory, Washington, DC2Sotera Defense, Annapolis Junction, MD

3George Washington University, Washington, DC

This work is supported by the Defense Threat Reduction Agency and the Office of Naval Research

MRQW 2015, 27-28 January 2015, El Segundo

Defense Threat Reduction Agency


Defense Threat Reduction Agency Quantitative Characterization in TPA SEE

Why do we care?• The primary advantage of laser-based SEE approaches lies in their qualitative capabilities:

• sensitive node identification• RHBD verification• basic mechanisms/model validation/calibration• part screening (ASET, SEL)• fault injection



Defense Threat Reduction Agency Quantitative Characterization in TPA SEE

Why do we care?• The primary advantage of laser-based SEE approaches lies in their qualitative capabilities:

• sensitive node identification• RHBD verification• basic mechanisms/model validation/calibration• part screening (ASET, SEL)• fault injection

• However: • Monitor operating point during experiment• Set operating point prior to experiment• Require correlation between subsequent experiments• Next-level understanding of basic mechanisms




Surface elements opaque to optical excitation

Tightly focused two- photon

excitation source

Substrate transparent to single photon

sub-bandgap excitationCircuit Layer(s)

Region of 2 PhotonCarrier Generation

Quantitative Characterization in TPA SEE

Pulse Delivered to the Chip :: TPA Dosimetry




Surface elements opaque to optical excitation

Tightly focused two- photon

excitation source

Substrate transparent to single photon

sub-bandgap excitationCircuit Layer(s)

Region of 2 PhotonCarrier Generation

Quantitative Characterization in TPA SEE

Pulse Delivered to the Chip:TPA Dosimetry

Inside the Silicon:Charge Deposition

400 600 800 1000 1200 140010-1

100

101

102

103

104

105

1.06 mm

1.26 mm

800 nm

600 nm

Abso

rptio

n Co

effic

ient

, cm

-1

Wavelength, nm

Two-Photon Absorption − Background

Linear:600 nm, 800nm, 1.06 µmAbove band gapSingle-photon absorption

Two Photon:λ > 1.15 µmSub-bandgapTwo-photon, multiphotonabsorption

Optical Absorption Spectrum of Silicon

Band Edge

µ

µ




Ec

Ev

1260 nm

+

-

- --

2-Photon Absorption

Eg=1.1eV

• Two photons absorbed

• Simultaneously

• Creates a single e-h pair

Optical Excitation of Carriers by TPA



Two-Photon Absorption SEE Experiment

• Carriers are highly concentrated in the high irradiance region near the focus of the beam

• Because of the lack of exponential attenuation, carriers can be injected at any depth in the semiconductor material



-4 -2 0 2 4

030

1020

N α I2

w(z)

1/e Contour

Position, mm

Dept

h in

Mat

eria

l, mm

Two-Photon Absorption SEE Experiment

• Carriers are highly concentrated in the high irradiance region near the focus of the beam

• Because of the lack of exponential attenuation, carriers can be injected at any depth in the semiconductor material



NRL Laser Single-Event Effects



NRL Laser Single-Event Effects




Ti:Al2O3 OPA

DUT

xyz

120 fs1.26 µm

NIRFPA

PD2

PD1

Ti:Al2O3 OPA

DUT

xyz

120 fs1.26 µm

NIRFPA

PD2

PD1

Ti:Al2O3 OPATi:Al2O3 OPA

DUT

xyz

120 fs1.26 µm

NIRFPA

PD2

PD1

V(t) ∼ PE

Calibrated InGaAsPhotodiode:

Part 1. TPA SEE Dosimetry

Experimental Observable:




TPA SEE Dosimetry

Definition for TPA Dosimetry: Measurement of the relevant characteristics of the optical pulse delivered to the surface of the DUT

Goals for TPA Dosimetry System: Convenient, reliable, reproducible measurement of the relevant characteristics of the optical pulse delivered to the surface of the DUT

• Development of online monitors

• Develop ability for control vs. monitoring




Experimental Setup for TPA SEE Dosimetry




Truncation of Gaussian Beams

Tr = 2ωz /D

D = 2.75 mm




SFWHM = KFWHM λ F#

KFWHM = 1.036

– 0.058Tr – 0.156/Tr2

PL = exp(2/Tr)2

Truncation of Gaussian Beams

*H. Urey, Applied Optics, vol. 43, pp. 620-625, 2004.




Truncated Beams: Linear Calibration




Experimental Setup for TPA SEE Dosimetry




Online Monitor #3: Nonlinear Detector

NL PD

Laser pulse

Bulk Silicon Photodiode:• Response is described by the

expression:

• Reproducibility• Stability• Durability• Adequate active area and size of

the input aperture • Ease of use, including simplicity of

alignment

Requirements:




VNL_OL = κ/SFWHM4

SFWHM = κ1/4/VNL_OL1/4

Data exhibit the expected r4 dependence

Online Monitor #3: Nonlinear Detector




Three methods to determine Focused Spot Size

1. NL Detector

3. Power Loss

2. Knife Edge

Kni

fe e

dge




TPA Dosimetry: Redundancy




TPA Dosimetry − Summary

• Dosimetry methodology for TPA SEE developed, implemented, and verified

• Three online beam monitors• Laser pulse energy• Laser pulse width• Focused spot size

• Capabilities:• Monitor and correct fluctuations in laser

system operating point • Set system to predefined operating point• Correlation of different experiments




Part 2. What Happens Inside the Silicon?

• Need exists for understanding quantitatively the carrier density distribution in TPA SEE experiments

• Complicated problem• Community has been relying on a “Zeroth Order” representation

• Only considers carrier generation• Neglects all all other effects

• NRL has been working with a nonlinear-optics group at GT to address this problem

• The present status of this effort is presented here

-4 -2 0 2 40

3010

20

N α I2

w(z)

1/e Contour

Position, mmDe

pth

in M

ater

ial,

mm

McMorrow, et. al, TNS 49, 3002 (2002).




• Produce a software program that can accurately simulate the TPA-induced carrier deposition profile in silicon for any given set of experimental conditions

• Simulate/predict impact of various optical nonlinearities on the beam propagation through, and generation of free carriers in the medium

Goals:

• Numerical modeling using existing simulation software (NLO-BPM) adapted for carrier generation and applied to silicon

[Kovsh, et al., Applied Optics, 38, 1568 (1999)]

• Confirm that capabilities can accommodate experimental conditions

• Validate results through experimental measurement

Approach:

Goals and Approach



1.6 nJ Gaussian Beam

27

Some of the ResultsDefense Threat Reduction Agency

Some ResultsDefense Threat Reduction Agency






( ) ( ) ),(exp,, trjtrAtrE

Φ⋅=

NLk

Ak

zA χ

∂∂ Im

2

20= NLk

k

zχ

∂∂ Re

2

20−=ΦOptically thin media:

Nonlinear Beam Propagation in Silicon

∇ − = −T

E r t jkE r t kNL

E r t2 202( , ) ( , ) ( , )

χParaxial nonlinear wave equation:




LensSample

Nonlinear refraction (NLR), n2

Two-photon absorption (TPA), β

Nonlinear Beam Propagation in Si

ImχNL:

ReχNL:




1. Accuracy limit for modeling of angular components of the beam (< 25o for Pade(1,1)1 ). For F/#1 systems α ~ 27o . The relevant angle for propagation in Si is β ~ 7.5o

2. Power limit for critical Kerr-type self-focusing.Relevant when Kerr effect dominates (focus on front surface and energy > 800 pJ). Focus is in sample and TPA + free carrier

defocusing dominates Input powers > 100x critical Kerr self-focusing are

possible

3. Sample thickness limit of ~ 100 Rayleigh ranges2

(~2 mm) Sample thickness <700 µm

Potential Limitations of NLO-BPM

air Si

αβ




Under-filled Objective: Gaussian Beam

Over-filled Objective: Non-Gaussian (Truncated) Beam

Controlling the Focused Laser Spot Size

Input Aperture: 2.7 mm diameterCASE 1: 1/e2 radius of 640 µm (Gaussian)CASE 2: 1/e2 radius of 4.5 mm (Truncated)



FWHM DiffractionLimit = 0.95 µm

Underfilled

Overfilled


36

1.6 nJ Gaussian BeamPulse Irradiance Charge Density



1.6 nJ Gaussian Beam

What is the origin of this effect:

• Photon loss to TPA• Photon loss to FCA• FCR

1.6 nJ

5 nJ

16 nJ

1.6 nJ Truncated Beam




FWHM DiffractionLimit = 0.95 µm

Underfilled

Overfilled

1.6 nJ Truncated Beam

Markedly non-Gaussian

Underfilled Objective

FWHM: 1.55 µm

Overfilled Objective

FWHM: 0.98 µm

Comparison of Gaussian and Truncated Beam: 1.6 nJ



Defense Threat Reduction Agency Experimental Verification

*H. Urey, Applied Optics, vol. 43, pp. 620-625, 2004.

SFWHM = KFWHM λ f#

KFWHM = 1.036

– 0.058Tr – 0.156/Tr2



Defense Threat Reduction Agency Conclusions/Summary

• NLO BPM adapted for calculating TPA-Induced charge generation profiles in silicon

• Valid for Gaussian and non-Gaussian beams• Necessary for matching the experimental

conditions• Exhibits quantitative agreement with experimental

observables • Additional tests are in progress

• Provides basis for quantitative analysis and interpretation of TPA SEE measurements

Presented at the Aerospace Corporation Microelectronics Reliability and Qualification Workshop

January 27-28, 2015

SUPRA ET ULTRA

Advanced Technology Programs Group Radiation Hardened Microelectronics Branch

Program: Overview and Status L.M. Cohn NRO/AS&T

UNCLASSIFIED

UNCLASSIFIED

2

Agenda

Radiation Hardened Microelectronics Branch • Mission • Objectives

Radiation Hardened Microelectronics Branch • Near Term Program • Mid Term Program

Overview & Motivation RHBD 45nm ASIC Task Onboard Processing & Control Technology Task Analog & Mixed Signal Technology Task Radiation Testing & Characterization Trusted FPGA

• Far Term Program Nano-scale Microelectronics Investigation CNT Technology

Advanced Power Converter Technology Development Summary

3

RHM Branch Mission, Objectives & Applications

Mission: Develop both evolutionary and revolutionary microelectronics technologies to enhance satellite electronic systems capabilities

Objectives: • Onboard Processing (OBP) Enhancements: • Provide flexible, heterogeneous capability to efficiently support full range of OBP requirements (MIPS to TIPS) & TB storage at reduced SWaP • Provide high performance analog/mixed-signal technologies to support communications and signal processing applications

• Front End & Electronically Steerable Array (ESA) Enablement: •Very high SFDR low power CNT FET technology for LNA, mixer and ADCs • Ultra Deep Submicron Microelectronics technology for elemental digital beam-forming

Applications: •System survivability; Trusted, radiation hardened & high reliability •Pre-planned program upgrades by providing improvements in performance, reliability & SWaP • New mission capabilities

4

Objective: • Productization & Qualification of RH Electronics Technologies (250nm

to 150nm) • 10X improvement in OB processing performance

Tasks: • RH15F Process Class V Qualification • L2 Cache MCM/Synchronous SRAM Qualification • 4Mb CRAM Qualification • RH18/RAD750 200MHz/400MIPS Processor Qualification • 100 MHz Bridge ASSP Development • RAD750/250MHz 500 MIPS processor • Structured Array Development • Optimized SERDES Development • Advanced Packaging Development • HX-5000 SEE Characterization • RHBD 90nm Reliability Demonstration

Near Term Technology Program Completed

5

Near Term Program Status: Completed Balanced design to support > 400 MIPS Throughput

L2 CACHE Memory Class Q Qualification

Completed

RH15F Class V Qual Completed

RH 4Mb NVRAM Class Q & V Quall

Completed

RH 16Mb (X32) SRAM Class Q Qual 4QCY12

RAD750 200MHz/400MIPS

Class Q Qual Complete 250MHz/500 MIPS In development

100MHz Bridge Chip Class Q Qual

4QCY12

SERDES Test Chip

BAE SYSTEMS

RH SERDES Pass 2 Completed

Class Q Qual 4QCY12 X 5Gbps SERDES

Design Complete Demo 2QCY13

Structured Array Complete

FPGA Replacement

RH15 Class V Qual Complete

Satellite Front-End & Processing System

6

Objective: • Demonstration of technology to provide a heterogeneous, flexible OBP

architecture to support full range of processing needs (MIPS to TIPS) Adaptation of Commercial Processes & IP for Space Applications

>1000X in OB processing performance; > TFLOP OBP performance

• Demonstration of high performance AMS technology GSPS wide-band ADC/DAC

Technology Development Areas: • RHBD 45nm ASIC Design, Demonstration and Qualification • RHBD Processor Development & Demonstration

RHBD 90nm & 45nm GFLOP DSP Development

RHBD 45nm Next Generation multi-core GPP Family (RAD55XX)

RHBD SBC Next Generation GPP

RH DDRX Radiation Effects Mitigation Assembly

• RHBD Next Generation Analog/Mixed-Signal Technology Development RHBD 45nm ASIC Switch Technology Development

Enhanced SERDES Demonstration

RHBD High Dynamic Range ADC Technology Development

• RHBD Next Generation FPGA Investigation

Mid-Term RHM Technology Program

7

Mid-Term RHM Program Tasks

8

Integrated RHBD 45nm Development Strategy

Commercial IP adopted for space applications and fabricated at a Trusted Foundry

*

* Fabricated at the Trusted IBM EFK facility

9

RHBD 45nm ASIC Development, Demonstration & Qualification Program

Program Objectives • Development, demonstration, and Class Q/V qualification of a

RHBD 45nm ASIC technology.

Program Tasks • Radiation & Reliability Technology Assessment & Characterization

Reliability assessment and remediation RHBD library development & demonstration Radiation effects modeling and simulation

• RHBD ASIC Design and Demonstration Design, fabrication and test of two ASICs Package development and demonstration

• ASIC & Technology Qualification QML Class V qualification QML Class Q ASIC qualification Design flow qualification

10

RHBD 45nm Technology Program Roadmap

11

RHBD 45nm Technology Goals and Requirements

12

RHBD 45nm Library Radiation Hardening and

Reliability Enhancements

Reliability enhancements • Selective metal width modifications for electro-migration • Lower Vdd (0.95 volts nominal) to limit NBTI/GOI. • Enhanced design methodology (e.g., power aware placement) to reduce hot spots • Power gridding segmentation to control thermal profile and power distribution • Identification and avoidance of circuit topologies that may impact reliability • Package/image co-design

Radiation hardness enhancements • RH bit cells with RAM trench capacitors • Critical nodal spacing and interleaving • Selective dual path logic on critical control circuits • RH latches at RAM input/output • Transistor sizing and other SET mitigation approaches for critical circuits • Hardened registers and clock power level cells for control and critical signals

Low power enhancements • Additional high Vt (XVT) device/library for lower leakage • Clock gating library cells and low power registers

The RH45 library has been enhanced to support QML space qualification requirements

13

RHBD 45nm Library Overview

14

RH45 ASIC Library and PDK Summary

ASIC Product Design Kit (PDK)

Combinational Cells – full family of Boolean and data path cells Clock Cells – specially designed re-drive and gating functions for radiation hardness and glitch free operation Sequential Cells – registers and latches; scan and SET filtering options Embedded RAMs - dual port and single port compilers; eFUSE for repair; low power/high performance options

• PLLs- programmable; low power/low jitter • SERDES – 8 lane macro; up to 5Gbs; multiple

protocol support; power down and unidirectional features

• I/Os – programmable LVCMOS, LVDS, SSTL(DDR2/3)

• Support Cells – filler, antennae, ESD, delay cells, etc

Library Content

• Accessible via BAE Systems Sharepoint • Content:

• Four corner characterized models • Black box timing/synthesis models for

SRAM, IO, PLL, SERDES • Verilog simulation models • Floor plan and image/cover models • Run Scripts and setup files for design tools

and methodology flow • Documentation (electrical specification, user

guides)

15

Reliability Technology Characterization Vehicle

16

Technology Reliability Testing Summary (1/2)

17

Technology Reliability Testing Summary (2/2)

18

RHBD 45nm SRAM (ASIC) to Support QML V Testing and Qualification

19

QML Class V Qualification Test Flow

20

QML Class V Accelerated Life Test Results

21

ASIC Qualification Devices

24M eq. gates 15M eq. gates

22

ASIC-1Functionality Testing Status

• Fully Functional First Pass ASIC-1 Design

Achieved

• The status: • Electrical testing

successfully completed over temperature & voltage

• Average yield of first 21 wafers > 40%.

• Flight units delivered. • MIL-PRF-38535 Groups A-E

testing initiated with QML qualification test completed

Chip under test

Testing Report cared: All Green!

23

ASIC-1 QML Qualification Status: Testing Completed

24

ASIC-1Total Ionizing Dose Radiation Test Results*

• 22 parts tested IAW MIL-T-1019 to include rebound • Result: RHACL= 500krd

*

25

ASIC-1 Single Event Effects Test Results

26

ASIC-1 Single Event Effects Test Results

27

Library Test Vehicle (LTV)

Purpose: Comprehensive test vehicle for elemental evaluation and validation of ASIC library and custom blocks of the RAD5545

Contents: • Entire Standard Cell library - every cell in the RH45

library exists as standalone test structure for functionality • I/O (LVCMOS and LVDS) - test structure to test

functionality and characterize • Compiled and Custom RAMs - RAMs selected to cover

each bit cell type and the extreme array dimensions (tallest/shortest, widest/narrowest, largest bank/smallest bank)

• eFuse - eFuse controller with BISR (built-in-self-repair) registers and RAM blocks to test full self-repair function

• Platform PLL - functional and SEE testing • DFF chains – various chains of 400 stages to ensure

large enough cross-section for SEU/SET testing. Chain of each DFF function (set, reset, set/reset) for various power levels and Vts.

• ASIC SER test structure - synchronous logic representative of an ASIC to test SER vs. frequency

• Ring oscillators – rings of different logic gates (eg: inv, nand, nor, and aoi) for each Vt to measure hardware to model correlation

• Miscellaneous - thermal sensor

LTV Physical Design View

Status • Electrical performance &

functionality verified • SEE laser testing performed on

selected circuits • Initial SEE heavy Ion radiation

test completed on 6/20/14.

15 ring oscillators

RAMs8 single ports8 dual ports4 customs

165 DFF chains

ASIC SER experiment

EntireLibrary

PLL

eFuse

28

LTV Single Event Effects Test Results

29

Package Development - Completed Ceramic Column Grid Array (CCGA) package

35mm; 1144 pin; flip chip die attachment Leverages qualified CCGA design (GoldenGate Bridge ASIC) and >10 years CCGA and >30 years flip-chip production Modified substrate routing for Qualification ASICs - specific signal integrity considerations

Substrate Design Package vendor is NTK Development guidelines, routing rules, and other constraints levied by both ASIC subcontractors and BAE Systems

Electrical Analysis Impedance for signals, loop LCRs for signal, S-parameters for select signals i.e., signals of interest such as ADC or SERDES inputs, longest and shortest paths Power plane impedance and IR drop for respective planes

144 Ceramic Column Grid Array Package Drawing and Layer Stack

Ceramic Column Grid Array (CCGA) Samples

25 mm 32mm 35 mm

ASIC 1/ 2/LTV package has been released to manufacture.

1144 pin 624 pin 360 pin

30

RHBD 90nm/45nm Onboard Processing & Control Technology Development & Demonstration Program

• Program Objectives

• Design, development, demonstration and verification of a RH, flexible and heterogeneous architecture onboard processing capability to meet the full range of satellite payload processing and control function needs (MIPS to TIPS)

• Technical Approach • Combines advanced commercial DSP & GPP IP with RHBD

45nm technology to achieve program objectives • Develop and demonstrate:

• GFLOP DSP (90nm mid term& 45nm far term) • Host Bridge to support TFLOP SBC capability • GPP (RAD55XX) family and SBC • RH REM DIMM Module

31

RHBD 90nm RADSPEED™ Single Instruction Multiple Data (SIMD) Digital Signal Processor

The RADSPEED DSP is a radiation hardened variant of the CSX700 digital signal processor (DSP) from ClearSpeed Technology RADSPEED DSP features @ 90nm • 160 (152 + 8 spare) processing elements (PE) in

two multi-threaded array processors (MTAP) • Throughput: 70 GFLOPS @ 15 W power • Each PE incorporates double precision floating

point hardware as well as integer processing • Single instruction, multiple data (SIMD)

architecture • Dual ClearConnect™ bridges (CCBR)

Each with ~ 30 Gb/s throughput Supports direct connection between DSPs or to a backplane using a bridge

• Dual DDR2 DRAM interfaces A DDR2 interface is dedicated to each MTAP, avoiding bottlenecks Throughput: ~30 Gb/s each

Supported by mature commercial software development kit Software prototyping hardware available now

The RADSPEED DSP has successfully completed electrical & functionality characterization, and radiation testing.

Transition to RHBD 45nm TBD

32

Software Development Environment

Software Development platform is available for customers to start RADSPEED DSP algorithm development

• Open-VPN to workstation (allows external customer access) • User’s guide for configuration of ClearSpeed processors to mimic RADSPEED DSPs

Hardware platform contains: • 2 ClearSpeed e710 cards in Dell workstation

Each contains a CSX700 processor and local memory • Cn compiler – ClearSpeed multicore compiler • SDK including MATLAB libraries • Graphical profiler • Graphical debugger

Two organizations have used the development environment RADSPEED DSP SDK was developed for use on Phase B2 and beyond:

• Optimized version of Cn compiler/SDK for RADSPEED DSP configuration

33

RHBD Host Bridge & RAD55XX Family

Embedded 4-core e5500 processor

Custom I/O For GFLOP

Single Core w/o High Speed Transfer

Off-the-Shelf Space qualified solutions for processing & control applications Prototype Demonstration 2Q2015

Host Bridge sRIO Manager 20-Lanes SERDES Real Time DeBug

34

RAD5545 System-on-Chip Multi-core Processor

Status: • Design > 95% Complete • Fabrication scheduled for 2QCY15

35

RAD55XX Software Support

36

RAD55XX Prototyping & Software Development Support

37

RHBD Analog and Mixed-Signal Technology Development & Demonstration Program

• Program Objectives

• Design, development, and demonstration RH analog and mixed-signal technologies to support onboard data transfer, signal conditioning and conversing applications.

• Technical Approach • Adoption of advanced commercial network switching and

analog-to digital/digital- to- analog (ADC/DAC) for space applications.

• Development and demonstration tasks: • RHBD Packet and Cross-Point Switch demonstration • End-Point ASIC Demonstration • High Dynamic Range (interleaved) ADC Development • Enhanced SERDES Demonstration

38

RHBD 45nm Switch/Interface Development Efforts

Protocol Independent or

Cross-Point Switch

Common Processor Flexible Interface or End-

Point Switch

Packet Switch

Packet Switch Demonstrations

2Q2015

39

High Dynamic Range (HDR) ADC Technology Development

• RHBD 32nm HDR ADC inter-leaved design approach advances the state-of-the-art

• RHBD 32nm technology required to

achieve instantaneous bandwidth; “jitter” control and insertion of adaptive calibration circuits

40

RHBD 45nm Enhanced SERDES Demonstration

Initial program goals

41

RHM Branch Technology Development Support Efforts

NASA & NRL Radiation Effects Testing & Characterization

SEE Laser Testing @ NRL

Conventional radiation effects testing

Cyclotron Heavy Ion testing @ Texas A&M

NRL Laser Test Facility

42

Objective: • Demonstration of Revolutionary and State–of-the-Art Evolutionary

technologies to provide a paradigm shift in on-board processing. • Demonstration of:

CNT high Spurious Dynamic Range (SFDR) with very low power Mixers and Low Noise Amplifiers (LNA) CNT Non-volatile Memory RHBD 14nm ASIC technology

Technology Development Areas: • High SFDR Mixers & LNAs using CNT Linear field Effect Transistor Development • CNT Memory Technology Development • < RHBD 14nm CMOS Technology Development

Radiation Effects

Reliability Characterization Radiation & Reliability Effects Modeling and Simulation RHBD ASIC Library Development and Demonstration

• 3-D Packaging

Far-Term Technology Program

43

CNT Technology Program

44

RHM Branch Nano-scale ( < 32nm) Technology Development Efforts

Program Objectives: • Investigate < 32nm* technologies for potential

DoD/IC space & other system applications (e.g., SWaP-C, radiation, reliability, cost, Trust)

• Develop & demonstrate RHBD & reliability mitigation approaches

• Develop & demonstrate an ASIC library & design flow

• Identify & adopt selected commercial IP

• Productization & qualification

* Initial efforts focused on 14nm with anticipated transfer to ~ 7nm as it becomes available

Initial Program Tasks: • VU: Investigate & characterize radiation effects and develop mitigation approaches for ~14nm technology

• BAE: Investigate and characterize reliability degradation modes in ~14nm technologies

• Boeing: Investigate and characterize combined radiation & reliability degradation modes in ~14nm technologies

Program Schedule:

FY14 FY15 FY16 FY17 FY18 FY19 FY20

T&E

TCV/SEC

Library Demo

ASIC Demo

P&Q

45

Advanced Point-of-Load Converter Technology

• Advanced POL technology needed to support insertion of scaled electronics

• Poor efficiency @ < 1v • Large footprint • Does not support MIL

temperature range, susceptible to radiation effects

• Several ongoing efforts to provide POL technology for various applications with focus on digital control

46

Summary The ATPG RHM Program is supporting the development of both evolutionary and revolutionary technologies to enhance DoD and IC satellite system performance & reduce SWaP.

Near Term Program: Completed P&Q efforts for a variety of 250nm to 150nm devices and technologies to enhance OBP; e.g., > 10X increase in performance compared to current capabilities (RAD6000)

Mid-Term Program: Exploitation of < 45 nm technology to address the full range of OBP applications from MIPS to TIPS and wide band very high performance ADC/DAC applications to include:

• RHBD 45nm ASIC design, demonstration and qualification • Analog/Mixed-Signal technology:

High speed data switch family Gsps performance ADC @ the 32nm technology node

• General Purpose Processor and Digital Signal Processor design and demonstrations with from > 10X to 1000X increased performance compared to RAD750 processor.

Far-term Program: • Next Generation microelectronics; e.g., RHBD 14nm technology • Novel approaches (e.g., near threshold operation) to achieve significant SwaP savings • 3D/2.5 D packaging • Developing CNT technology for mixed signal and linear circuit applications

Additionally, advanced Digital Point-of-Load converter technology is in development

Applications for these technologies have been identified by a number of flight and technology development programs

47

Contact Information

Lew Cohn 703-808-4250 (O) 850-4250 © Lewis.cohn@nro. Mil [email protected] [email protected]

mailto:Lewis.cohn@nr

mailto:[email protected]

Integrity Service Excellence

AFRL Space Electronics

Technology (SET) Program

27 Jan 2015

Space Vehicles DirectorateAir Force Research Laboratory


2/25/2015

Atomic Scale Modeling

Embedded Cluster Modeling

Device Physics

Circuit Research & Development

Integrated Solutions

Spacecraft Components

Fundamental

TechnologyDevelopment

Applied Research

Our Portfolio Spans Science to Systems

Spacecraft Systems

3/12

Mixed Signal

Mixed SignalMixed Signal

Digital

Mixed SignalMixed Signal

Scope of the SET Program

Amplify/Convert

Process/Store

Convert/Amplify

Power Management

Translate raw data into

information

Modify input signalto prepare for

processing

Modify output signalto prepare for “transmission”

Sense

Detectsignals (RF,

optical, etc) from

environment

Send output to other subsystem,

actuator, or platform

Convert to specific voltages; carefully control

Power Generation and StorageAssured OperationAssure components, etc., operate reliably in harsh environs for

many years

Transmit

Network

Provide signal and power interconnects,

and effective interfaces

XX


Need Solutions for the Diverse Challenges of Space Systems

Commercial Technology is Driver• Cost demands we leverage industry advancements• Production has moved offshore• IC¹ lifetime is decreasing (Reliability)• 3D use increasing (transistor and chip level)

Dynamic Space EnvironmentReliable in Harsh, TID², SEE³, Temperature Environments

Trapped ParticlesProtons, Electrons, Heavy Ions

After Nikkei Science, Inc. of Japan, by K. Endo

Galactic Cosmic Rays (GCRs)

Solar Protons& Heavier Ions

Earth

Resiliency

Affordability

10k6k

3k

1.5k1k

800500

250180

90130

65

2k

350

3245

10,000

1,000

100

101970 1980 1990 2000 2010

IC*

Feat

ure

Size

(nm

)

Feature Size (nm)

Intel Products

Range of Needs• Diversified needs drive technology choices• Not all needs can be met by a single technology

Capability

1. Integrated Circuit2. TID: Total Ionizing Dose 3. SEE: Single-Event Effect

5Distribution A: Approved for Public Release

Space ElectronicsVision, Mission, & Strategy

• Vision– ID and develop advanced rad-hard electronics (RHE) that enable future

AF space system capabilities

• Mission– Team with AFSPC and SMC to codify future RHE needs in CFSP– Create and transition advanced RHE that enables new operational

capabilities for AF and DoD space systems

• Strategy– Develop techniques to harden advanced commercial electronics and

leverage commercial electronics development– Understand rad effects and vulnerabilities in emerging technologies

and develop techniques to mitigate them– Apply strategic hardening techniques using expertise in radiation

effects on electronics– Analyze and evaluate and develop promising innovative solutions to

overcome future technology shortfalls6


Space Electronics Technology

1.1Space Electronics

Technology

1.1.1Digital

1.1.1.1Processing

1.1.1.2Memory

1.1.1.3Logic

1.1.1.4Advanced

Technology

1.1.2Analog/Mixed Signal

1.1.2.1ADC/DAC

1.1.2.2PMAD

1.1.2.3Linear

1.1.2.4 COMSEC

1.1.3Assured Operations

1.1.3.1Reliability

1.1.3.2Survivability

1.1.3.3Mod/Sim

1.1.3.4Rad Effects


Digital

• Processing– Structured ASIC: Nearing qualification– Next Generation Space Processing Investigation

• Multi / many core, hybrid, reconfigurability, power scalabilty

• Memory– Non-volatile (64Mb)– Volatile memory (Gb goal)– Density improvements to reach Tera bit levels

• Logic– On-shore fabrication capability– 45/32 nm investigation– Advanced Litho techniques

• Advanced Technology– Memristor development– Junctionless transistors– 3D circuit/device development

Structured ASIC

Grated 1D Design Concept

MemristorsJunctionless Transistor TSVs

Courtesy of Tela Innovations, Inc and Multibeam Corp.

Courtesy of M-RDC


Analog/Mixed Signal

• ADC/DAC– Require High resolution– Reuqire Low power– Configurable Analog Array

• PMAD– RH high efficiency POL converters– Power management

• COMSEC– Highly Assured Internet Protocol

Encryption (HAIPE)– Low power & compact form factor

• Cyber– Coordinating closely with AFRL/RV

Spacecraft Cyber Initiative

A/D

PMAD

DACS

DC-DC

VPN Gateway

LAN: 10.0.0.0/29

NIPRNet

RTS

VPN Gateway

HAIPE

LAN: 10.0.0.8/29

Multi Level MOC

HAIPE

Spacecraft LAN: 10.1.0.0/16

Top Secret Payload

Unclassified Payload

Secret Payload

MOC LAN: 10.254.0.0/16

Top Secret Terminal

Secret Terminal

Unclassified Terminal

HAIPE


Assured Operation

• Reliability– Lifetime of modern electronics is less than the

satellite mission life– Discovering new reliability mechanisms– National High Reliability Electronics Virtual Center

(HiREV)

• Survivability– ASAT protection

• Modeling & Simulation– Spacecraft Power/Performance Analytics Research– Developing compact memristor models for circuit

operation

• Radiation Effects– Radiation test facilities– Ongoing testing of materials/devices for in-house

research– Support for external use of facilities through

Cooperative Research And Development Agreements

60Cobalt

137Cs Gamma Aracor X-ray

Flash X-rayLow Energy X-ray

Understanding built-up from atomic scale

Materials degradation rates quantified

Assured mission operation

Mean

Ser

vice L

ife (y

rs)

From: State of the Art Semiconductor Devices in Future AerospaceSystemsL. Condra, Boeing, J. Qin and J.B. Bernstein, U of Maryland 2007


Next Gen Space Computing Study

11

Tech node advances increase: • Ability to add more & varied functions to SoC• Ability to arrange functions to address wider

variety of computation• Evolution of architecture schemes

enable improved fault tolerance, power scalability, and reconfiguration

Computing is segmenting to address wider

variety of computational

classes


Spacecraft Power/PerformanceAnalytics Research

12

Applications Models: Mission Requirements → Computational Requirements

Determine Energy Supply

per orbit(s)

Determine Workload per

orbit

Determine ability of candidate

architecture to balance supply and

demand

Theoretical Peak Performance Fundamental Algorithm Performance

Application Performance Application Power Model Realizable Peak Performance

Sys Eng Requirements Mission Models Day In The Life

Systems Models

Research StudiesA) AnalysesB) Device metricsC) Targeted benchmarking

Processor/Architecture and Kernel Models

Space Dwarfs (Kernels)A) Sensor processingB) Autonomous processingC) Other processing

Space DevicesA) ExistingB) In DevelopmentC) Emerging

CPUDSP

FPGAGPU

Hybrid

Circuit Approaches

Emerging Computing Types

Dwarf 1 Dwarf 2 Dwarf 5

Processing Chain

Dr. Lyke & Edwards (DARPA: PERFECT & UPSIDE)Dr. Cunio & Weber (RVB Adv OPIR research)

2Lt Guthrie

Dr. Pineda

NASA

PM: Capt Higbee, PI: Dr. Jesse Mee


Space Electronics TechnologyEnabling Trust Through Technology

13

The Problem• The low-volume need for space ICs

makes it difficult to access large fabs• Boutique fabs cannot afford advanced

lithography equipment• Few (1) trusted mask shops remain

Solution: Maskless Lithography• Capability allows “maskless” fabrication

of advanced technology ICso Maskless means lower cost and no need

for trusted mask producer • Co-funded with SMC and DTRA

Impacts / Benefits• Enable trusted method for creating ICs

for Government systems• Eliminates need for costly masks• Enables split-line fab to increase sources

of trusted ICDistribution A: Approved for Public Release

Courtesy of Multibeam Corp.

• Advance GPS Tech activity to systematically evaluate high-power L-band GaN HEMTs for performance and rad-effects– First: evaluate in ionizing radiation using RV-owned sources– Next: evaluate in heavy ion radiation at Lawrence/Berkley

• Funding fundamental research into the causes of electrical anomalies and radiation effects in GaN HEMTs– Teamed with AFRL/RX and RY to investigate unexplained

electrical behavior

GaN HEMT Eval & Research

14

•Gallium-Nitride (GaN) High-Electron-Mobility Transistors (HEMTs) provide more efficient radio-frequency (RF) amplification than existing transistors (reduce SWaP)– GaN is a relatively new technology with no systematic

evaluation of the suitability of GaN amplifiers for space systems


AFRL Technology flying Today MilSatCom, SBIRs, & GPS Spacecraft

Four AEHF spacecraft in Geostationary orbits will replace the AF Milstar System

Provide the Joint Service with survivable, global, secure, and protected communication for ground,

sea & air. AEHF-1: Aug 2010; AEHF-2: May 2012

Lockheed A2100M Bus

8x RAD750 Rad-Hard Processors 80x SRAM Rad-

Hard memory

2x RAD6000 Rad Hard Processors

400x Rad-Hard ASICs C-RAM Chacogenide

memory (AEHF-4)

Rad-Hard RH1020 FPGAs

Lockheed A2100M Bus Boeing GPS IIF

SBIRS spacecraft in Geostationary orbits will replace the DSP Missile Warning System

Provide the nation with critical missile defense, missile warning, battlespace awareness, and

technical intelligence capabilityGEO-1: May 2011; GEO-2: July 2012 (TBR)

GPS Spacecraft ConstellationProvides precise, continuous, all-weather,

highly accurate 3-D position, velocity and timing information for military and civilian users

worldwide.

RH32 Single-Board Computer on HEO & GEO 3/4

(Honeywell)

SRAM Rad-Hard memory

Rad-Hard ASICsRH32 Single-Board Computer on GPS IIF (Honeywell)

RAD6000 (BAE)Processors on GPS IIF

Rad-Hard Power Converters on GPS-

IIF (VPT)RAD750 Rad-Hard Processors onGPS-III (BAE)

Rad-Hard Power PC (RHPPC) on GPS-III (Honeywell)

Air Force Research Laboratory Space Vehicles Directorate

www.kirtland.af.mil/afrl_vs

http://www.kirtland.af.mil/afrl_vs


Impacts of the Counterfeit Detection and Avoidance DFARS Requirements and Guidance for Complying with the DFARS RequirementsDavid MeshelSr. Project LeaderThe Aerospace Corporation(571) 307-3741

Rebecca McKennaSenior Member of Technical StaffThe Aerospace Corporation(703) 808-5011

Agenda

• Background• NDAA Overview and Content• Aerospace TOR Content Review• Questions / Discussion

2

Motivation

• 250% increase in suspected counterfeit cases between 2005 – 2008 with another 4X increase between 2009 – 2012– For NSS systems only 2 known occurrences

• New Public Law Instituted – 2012 NDAA, §818– As amended 2013 NDAA § 833

– Requires “counterfeit electronic parts avoidance and detection systems”

– Increased contractor liability / financial risk with limited safe harbor

• Maintain Currency…Continuous Improvement

• Significant Portion of Counterfeit Threat Can Be Eliminated– Simply procuring only from

“authorized suppliers”

– Applying risk mitigation techniqueswhen using “unauthorized suppliers”

Threat

Is This a Possible Source…..?

….a Higher Probability from Distributor/Broker *Photos courtesy of Tom Sharpe and SMT Corporation**Photo courtesy of Basal Action Network

Impact of Counterfeit Parts

• Counterfeit Parts Can Cause:– Personal injury

– Mission failure

– Reduced reliability

– Risk to the War Fighter

– Potential loss of contracts

– Shutdown of manufacturing lines

– Negative cost and schedule impacts

– Penalties for companies and individuals

Phobos Grunt

No 2nd Chances for

Space

Examples of USG Products with Counterfeit Parts

• 2007 Aerospace reported to SQIC 1st NSS CF part• Traced to broker

•Display units with parts of unknown reliability• Parts traced to China

•Mission Computers•Distributor provided parts•Obsolescence

Navy SH-60B Army THAADAir Force C-130J

Themes• Unauthorized source procurement• Inadequate requirement flow down• Unspecified testing and inspection requirements• Reporting and quarantining failures

Relevance to Counterfeit Guide• Preventive measures to avoid procuring from

unauthorized sources• Mitigation actions when only option is

unauthorized source procurement• Evaluation of all parts received from suspect

suppliers

Differentiators

• Preventative measures being implemented by NSS programs

• Techniques to ensure part availability from authorized suppliers

• Lessons learned, best practices, observations and case studies

• Basis for building an effective training program with links to fully developed programs

• New reporting and quarantining requirements

• Structured to match DFARS rule, 48 CFR 246.870 (released 16 May 2014)

Themes from Lower-Tier Survey

• Assistance welcomed to better comply with requirements

• Procure from OCM and Authorized Distributors

• Standardized flow downs helpful‒ Commonality lowers costs

• Increased costs to implement law

• Unlimited liability potential

Better education, training, process assessment and sharing of lessons learned

15. What can prime contractors do to help sub-tiers with counterfeit parts prevention?

Counterfeit PM&P Components - DefinitionFAR/DFAR 48 CFR 202.101

• Counterfeit part means—– (1) An unauthorized copy or substitute part that has been identified, marked,

and/or altered by a source other than the part’s legally authorized source and has been misrepresented to be from a legally authorized source;

– (2) An item misrepresented to be an authorized item of the legally authorized source; or

– (3) A new, used, outdated, or expired item from a legally authorized source that is misrepresented by any source to the end-user as meeting the performance requirements for the intended use.

• Legally authorized source means –– The current design activity or the original manufacturer or a supplier

authorized by the current design activity or the original manufacturer to produce an item.

• Suspect counterfeit part means –– A part for which visual inspection, testing, or other information provide reason

to believe that a part may be a counterfeit part.

246.870 Contractors’ counterfeit electronic part detection and avoidance systems.246.870-2 Policy.

(a) General. Contractors that are subject to the Cost Accounting Standards (CAS) and that supply electronic parts or products that include electronic parts and their subcontractors that supply electronic parts or products that include electronic parts, are required to establish and maintain an acceptable counterfeit electronic part detection and avoidance system.Failure to do so may result in disapproval of the purchasing system by the contracting officer and/or withholding of payments (see 252.244-7001, Contractor Purchasing System Administration).

246.870-2 Policy.(b) System criteria. A counterfeit electronic part detection and avoidance system shall include risk-based policies and procedures that address, at a minimum, the following areas (see 252.246-7007, Contractor Counterfeit Electronic Part Detection and Avoidance System):(1) The training of personnel.(2) The inspection and testing of electronic parts, including criteria for acceptance and rejection.

including criteria for acceptance and rejection. Tests and inspections shall be performed in accordance with accepted Government- and industry-recognized techniques. Selection of tests and inspections shall be based on minimizing risk to the Government. Determination of risk shall be based on the assessed probability of receiving a counterfeit electronic part; the probability that the inspection or test selected will detect a counterfeit electronic part; and the potential negative consequences of a counterfeit electronic part being installed (e.g., human safety, mission success) where such consequences are made known to the Contractor.

246.870-2 Policy.(b) System criteria. A counterfeit electronic part detection and avoidance system shall include risk-based policies and procedures that address, at a minimum, the following areas (see 252.246-7007, Contractor Counterfeit Electronic Part Detection and Avoidance System):(3) Processes to abolish counterfeit parts proliferation.(4) Processes for maintaining electronic part traceability.

(e.g., item unique identification) that enable tracking of the supply chain back to the original manufacturer, whether the electronic parts are supplied as discrete electronic parts or are contained in assemblies. This traceability process shall include certification and traceability documentation developed by manufacturers in accordance with Government and industry standards; clear identification of the name and location of supply chain intermediaries from the manufacturer to the direct source of the product for the seller; and where available, the manufacturer's batch identification for the electronic part(s), such as date codes, lot codes, or serial numbers. If IUID marking is selected as a traceability mechanism, its usage shall comply with the item marking requirements of 252.211-7003, Item Unique Identification and Valuation.

246.870-2 Policy.(b) System criteria. A counterfeit electronic part detection and avoidance system shall include risk-based policies and procedures that address, at a minimum, the following areas (see 252.246-7007, Contractor Counterfeit Electronic Part Detection and Avoidance System):(5) Use of suppliers that are the original manufacturer, sources with the express written authority of the original manufacturer or current design activity, including an authorized aftermarket manufacturer or suppliers that obtain parts exclusively from one or more of these sources.

When parts are not available from any of these sources, use of suppliers that meet applicable counterfeit detection and avoidance system criteria.

(6) The reporting and quarantining of counterfeit electronic parts and suspect counterfeit electronic parts.

Reporting is required to the Contracting Officer and to the Government- Industry Data Exchange Program (GIDEP) when the Contractor becomes aware of, or has reason to suspect that, any electronic part or end item, component, part, or assembly containing electronic parts purchased by the DoD, or purchased by a Contractor for delivery to, or on behalf of, the DoD, contains counterfeit electronic parts or suspect counterfeit electronic parts. Counterfeit electronic parts and suspect counterfeit electronic parts shall not be returned to the seller or otherwise returned to the supply chain until such time that the parts are determined to be authentic.

246.870-2 Policy.(b) System criteria. A counterfeit electronic part detection and avoidance system shall include risk-based policies and procedures that address, at a minimum, the following areas (see 252.246-7007, Contractor Counterfeit Electronic Part Detection and Avoidance System):(7) Methodologies to identify suspect counterfeit electronic parts and to rapidly determine if a suspect counterfeit electronic part is, in fact, counterfeit.(8) Design, operation, and maintenance of systems to detect and avoid counterfeit electronic parts and suspect counterfeit electronic parts.

The Contractor may elect to use current Government- or industry-recognized standards to meet this requirement.

(9) Flow down of counterfeit detection and avoidance requirements.including applicable system criteria provided herein, to subcontractors at all levels in the supply chain that are responsible for buying or selling electronic parts or assemblies containing electronic parts, or for performing authentication testing.

246.870-2 Policy.(b) System criteria. A counterfeit electronic part detection and avoidance system shall include risk-based policies and procedures that address, at a minimum, the following areas (see 252.246-7007, Contractor Counterfeit Electronic Part Detection and Avoidance System):(10) Process for keeping continually informed of current counterfeiting information and trends.

including detection and avoidance techniques contained in appropriate industry standards, and using such information and techniques for continuously upgrading internal processes.

(11) Process for screening the Government-Industry Data Exchange Program (GIDEP) reports and other credible sources of counterfeiting information.

to avoid the purchase or use of counterfeit electronic parts(12) Control of obsolete electronic parts.

in order to maximize the availability and use of authentic, originally designed, and qualified electronic parts throughout the product’s life cycle.

246.870 Contractors’ counterfeit electronic part detection and avoidance systems.246.870-2 Policy.

(d) Government review and evaluation of the Contractor’s policies and procedures will be accomplished as part of the evaluation of the Contractor’s purchasing system in accordance with 252.244-7001, Contractor Purchasing System Administration— Basic, or Contractor Purchasing System Administration—Alternate I.

(e) The Contractor shall include the substance of this clause, including paragraphs (a) through (e), in subcontracts, including subcontracts for commercial items, for electronic parts or assemblies containing electronic parts.

The MAIW formed a task group to develop a Counterfeit Parts Prevention Strategy Guide that meets the requirements of the released DFARS on the Contractor’s Counterfeit Electronics Parts Avoidance and Detection System

Aerospace TOR: Guidelines on Implementing Counterfeit DFARS Requirements

DFARS Counterfeit Avoidance and Detection Criteria

Criteria(1) Training of personnel

(2) Inspection and testing

(3) Processes to abolish counterfeit parts proliferation

(4) Process for electronic part traceability

(5) Use of original manufacturer or authorized sources

(6) Reporting and quarantining

(7) Methodologies to identify suspect counterfeit

(8) Design, operation, and maintenance

(9) Flow down

(10) Process for improvement

(11) Screening of GIDEP

(12) Obsolescence management

Notables:• Electronics parts includes

assemblies and embedded software / firmware

• Traceability• Flow down to all sub-tier

contractors• GIDEP Access

Counterfeit Parts Prevention Strategy Guide Charter• Outline recommendations for Contractor

Systems for Detection and Avoidance of Counterfeit Electronic Parts

• Provide methodologies for counterfeit avoidance

• Develop a risk assessment methodology when using unauthorized or non-franchised suppliers

• Identify methods to ensure and verify sub-tier compliance

• Address the evolving nature of the threat and what is needed to maintain currency

Counterfeit Parts Prevention Content (1 of 2)Main Body

Executive Summary

1. Introduction

2. Design, Operation and Maintenance of Systems to Detect and Avoid Counterfeit Electronic Parts

3. Use and Approval of Suppliers

4. Traceability of Parts to Suppliers

5. Inspection and Testing of Electronic Parts, Including Criteria for Acceptance and Rejection

6. Reporting and Quarantining of Counterfeit Electronic Parts and Suspect Counterfeit Parts

7. Flow Down of Counterfeit Avoidance and Detection Requirements

8. Training of Personnel

9. Summary

10. Suggested Updates to Industry Standards

AppendicesA – Training Resources

B – Best Practices and Lessons Learned

C – Observations and Driving Philosophies

D – Case Studies

E – How This Guide Fits In The Total Picture

F – CF Prevention Standards Applicability Analysis

H – Counterfeit Parts Process Audit Checklist

I – Acronyms

J – References

Aligns to the Released DFARS

Counterfeit Parts Prevention Content (2 of 2)

Program Management and Procurement Flow

Section2

Section3

Section7

Section5 Section

6

Section4

Section3

Section8

Intended Product Use• Provide Guiding Principles and Practices for Contractors and

Suppliers to align to and be compliant to 2012 NDAA, §818, 2013 NDAA §833 and DFARS rule, 48 CFR 246.870 (especially lower tiers)– Establish and strengthen counterfeit prevention systems

– Provide consistent implementation methodology throughout supply chain

– Assist the supply chain in preparing for certifications

– Potential utilization outside of space systems

• Professional associations or educational organizations– SAE International, JEDEC, AIA, NDIA, SIA, etc.

• Guide for Certifying Agencies– DCMA

• Assist for criminal investigation (support to)– DOJ Computer Crimes and Proprietary Information Section– National Intellectual Property Rights Coordination Center

Team Members

Core Team

Company ParticipantThe Aerospace Corporation David Meshel

BAE Systems Henry Livingston

Ball Aerospace & Technologies Corp Mike Kahler

The Boeing Company Lilian Hanna

Lockheed Martin Corporation Scot Lichty Ken Baier

Northrop Grumman Electronic Systems Bob Ricco

Orbital Sciences Corporation Greg Hafner

Raytheon George Young Michael Woo

Space Systems/Loral John Walker

MDA Fred Schipp Barry Birdsong

NASA Carlo Abesamis

SME Review TeamSME Reviewers

Company ParticipantThe Aerospace Corporation Larry Harzstark, Edward Ortiz, Terita Norton

Aerojet Rocketdyne Dale Gordon

Ball Aerospace & Technologies Corp. Bob Bodemuller

The Boeing Company Gerald Aschoff

DCMA Christopher Brust

DoD AT&L/RESE GIDEP Program Jim Stein

DOJ / CCPIS Matthew Lamberti

Harris Corporation C. J. Land

Integra Technologies Sultan Ali Lilani

Lockheed Martin Corporation Shawn Cheadle

Micropac Mark King

Moog, Inc. Yehwan Kim

NASA Brian Hughitt Michael Sampson

Northrop Grumman Jim Creiman

Orbital Robert Lasky


P-1

QML V Qualification of Honeywell’s Radiation Hardened HXNV06400 64Mb MRAM Non-Volatile Memory

Tom Romanko [email protected]

P-2

Product Qualification Results

• MRAM History of Qualification - Some 64Mb MRAM Qual will draw from this history

• 64Mb MRAM Product Overview • Group A – E Qualification Tests • ESD • MRAM Specific Testing

- Endurance - Stray Magnetic Fields (SMF) Testing - Data Retention

• Summary

P-3

MRAM Non-Volatile Memory

• Radiation Hardened By Process (1Mrad TID) • No Wear Out – Unlimited Reads / Writes

- Non-destructive Readout (NDRO)

• Magnetically-shielded CFP or QCFP • Single Bit Error Detection & Correction (ECC) • 1Mb: -40OC to +105OC, 16Mb/64Mb: -40OC to +125OC

64Mb: The 3rd

Generation MRAM Product,

Thousands Of 1Mb MRAMs Shipped!

3000+ Shipped QML V Qualified QML V Qualified

P-4

MRAM Product Flow

MRAM Products

• Honeywell MRAM Product Fabrication − Combine the proven Everspin Technologies commercial MRAM

capability with Rad Hard S150 SOI CMOS

Rad Hard SOI wafers 0.15 micron SOI 200 mm wafers

Packaged at Honeywell

Everspin

MTJ MRAM Layers 0.18 micron

200 mm wafers

The Winning Combination!

P-5

Overview - 64Mb MRAM MCM Product

• HXNV06400BZH - Honeywell Rad Hard 64Mb MCM Non-Volatile Memory (4x 16Mb MRAM Die) - No data loss on power down or interruption

• Functionality

- Can be configured as 4Mx16 or 8Mx8 (4 Chip Enables like 64Mb SRAM) - Synchronous Clock Interface - Configuration Compatible with Xilinx Virtex 5QV (INIT, DONE, CLK, DQ) - Single-Bit Error Detection and Correction

• Operating Conditions

- I/O Power Supply : Supports both 2.5V ± 0.25V and 3.3V ± 0.3V - Core Power supply voltage: 3.3V ± 0.3V (On-board regulator supplies 1.8V core voltage) - Temperature Range: -40°C to 125°C

• Performance

- 100 ns read access time - 130 ns read cycle time - 150 ns write cycle time

• Radiation hardened for strategic space and missile applications

- Latch-Up Immune (SOI) - Total Dose 1E6 rad(Si) - Transient Dose Rate Upset/Operate Through 1E9 rad(Si)/s - Transient Dose Rate Survivability 1E12 rad(Si)/s - Neutron Displacement 1E14 N/cm2 - Single-Event-Upset 1E-10 upsets/bit-day

• Ceramic Package: Magnetically-Shielded Ceramic 112-lead Dual Flatpack • Data Retention ≥ 15 Years @ 105C • Endurance ≥ 1E15 Write and Read Cycles

QML V Qualified! SMD 5962-14230

P-6

MIL-PRF-38535 Testing: Group A

• Performed electrical test at 25C, -40C, 125C • 43(0) parts tested and no fails

• Electrical test consists of Preburn, Interim, and Final with the following

groups: - Static (subgroups 1, 2, and 3) - Functional (subgroups 7, 8A, and 8B) - Switching (subgroups 9, 10, and 11)

P-7

Group B

• Resistance to solvents was qualified by similarity

Subgroup Test Test Method

Condition Qual Results Sample Size (Fails)

B,1 Resistance to solvents

2015 Similarity to 1,16Mb MRAM

Qual by Similarity B,2 (c) Bond strength 2011 D, 22 wires per die 4(0) B,2 (d) Die/Cap shear 2019 3(0)

• Wirebond Clearance Assessment

− A wire-bond clearance assessment was performed and determined to have sufficient clearance for either a forward or reverse wirebond.

− All assembly builds performed for qualification followed these inspection procedures and there were no failures.

P-8

Group C

• 64Mb MRAM Life Test Results Subgroup Test Test

Method Condition Qual Results

Sample Size (Fails) C,1 (a) Steady state life test 1005 1000 hours 5(0) C,1 (b) End-point electricals 1005 5(0)

Lot # Primary Qualification Purpose

Accumulated LT Hours

Qualification Result Life Test Qualification [PU=Required for Production Upgrade]

Lot A Life Test for 16Mb Qualification

1000 2000 3000 4000

45(0) 45(0) 44(0) 44(0)

PU – 1000HR QML-V – 4000HR

Lot C 16Mb Qualification 1000 45(0) PU – 1000HR QML-V – 1000HR

Lot D 16Mb Qualification 1000 45(0)

PU – 1000HR QML-V-1000HR

• Significant Life Tests performed on the 16Mb MRAM

P-9

Additional Package Characterization Tests

• Significant characterization testing performed to demonstrate package and product robustness.

• Package characterization testing was conducted to make an initial assessment of package reliability prior to conducting formal product qualification tests.

• The characterization testing included four groups of parts: - Group 1 – Temperature cycles followed by shield stud pull and leak check - Group 2 – QCI Group D4-like testing (mechanicals) - Group 3 – QCI Group D3-like testing (thermals, moisture) - Group 4 – QCI Group D5 testing (Salt Atmosphere)

P-10

64Mb MRAM MCM Package Char/Qualification Flow

D4 Testing

w/ shields, w/

caps, w/ wire

bonds

Continuity test

(25C)

Shield and Cap Removal

(Chemical)

Fine and

Gross Leak TM1014

cond. A2, C1

External Visual

Salt Atmosphere D5a TM1009

w/ shields, w/

caps, no die

External Visual D5b

TM2009


(Chemical)

Fine and Gross Leak

D5c TM1014

cond. A2, C1

D3 Testing w/ shields, w/

caps, w/ wire

bonds

External Visual

Continuity test

(25C)


(Chemical)

Fine and

Gross Leak TM1014

cond. A2, C1

Shield Stud Pull > 28.48 lbs.

RGA D6 w/ all internal

components, no shields

no caps

Fine and

Gross Leak TM1014

Cond. A1, C1

TM1018 Internal Water Vapor Content

Fine and Gross Leak

TM1014 cond. A2, C1

200 Temp. Cycles

-65C to 150C w/ shields, no

die, no caps

200 Temp. Cycles

100 Temp. Cycles

External Visual

Shield Stud Pull

> 28.48 lbs.

Shield Stud Pull

> 28.48 lbs.

Shield Stud Pull

> 28.48 lbs.

Shield & Cap Removal

(Chemical)

64Mb MCM Assemble Empty and

Dummy Die Packages

Perform Seal Ring Crack Inspection on D3/D4P Parts

P-11

Package Characterization Tests

• Group 1 – Temperature cycles followed by shield stud pull and leak check

Test Test Method Condition Qual Results Sample Size (Fails)

Temperature cycling 1010 C, 200 cycles, -65°C to 150°C 90(0)

Shield stud pull 2027 5(0)





Seal, fine 1014 A2, He 75(0)

Seal, gross 1014 C1 75(0)


Shock 2002 B (1,500 g’s) 40(0)

Vibration, variable frequency

2007 A (20G peak) 40(0)

Acceleration 2001 D (20,000 G) without shields 40(0)

End-point electrical Continuity only 25°C 40(0)

Seal, fine 1014 A2, He 40(0)


• Group 2 – QCI Group D4-like testing (mechanicals)

P-12

Package Characterization Tests

• Group 3 - QCI Group D3-like testing (thermals, moisture)

Test Test Method Condition Qual Results

Sample Size (Fails) Thermal shock 1011 B, 15 cycles 39(0)


Moisture resistance 1004 39(0)

Visual 1004 1010

39(0)

End-point electrical Continuity only 25°C 39(0)


Seal, fine 1014 A2 30(0)



Salt atmosphere 1009 15(0) Visual 2009 15(0) Seal, fine 1014 A2, He 15(0) Seal, gross 1014 C1 15(0)

• Group 4 - QCI Group D5 testing (Salt Atmosphere)

P-13

Group D

Subgroup Test Test Method

Condition Qual Results Sample Size

(Fails) D,1 Physical dimensions 2016 Accept from supplier’s CoC

5(0) D,2 Lead integrity 2004 B2, Accept from supplier’s CoC 8(0)

D,3 (a) Thermal shock 1011 B, 15 cycles 15(0) D,3 (b) Temperature cycling 1010 C, 100 cycles, -65°C to 150°C 15(0)

D,3 (c) Moisture resistance 1004 15(0) D,3 (e) Visual 1004 15(0)

1010 D,3 (f) End-point electrical DC parameters only Specified in 64Mb MRAM SMD 15(0)

Shield & cap removal Chemical 15(0) D,3 (e) (1) Seal, fine 1014 A2 15(0) D,3 (e) (2) Seal, gross 1014 C1 15(0)

D,4 (a) Shock 2002 B (1,500 g’s) 15(0) D,4 (b) Vibration, variable frequency 2007 A (20G peak) 15(0) D,4 (c) Acceleration - Shields On 2001 B (10,000 g) 15(0) D,4 (e) Visual 1010 15(0) D,4 (f) End-point electrical Specified in 64Mb MRAM SMD 15(0)

DC parameters only [3] 15(0) Shield & cap removal Chemical 15(0)

D,4 (d) (1) Seal, fine 1014 A2, He (shields / caps removed) 15(0) D,4 (d) (2) Seal, gross 1014 C1 15(0)

• Qualification Testing Results Table

P-14

Group D (continued)

Subgroup Test Test Method Condition Qual Results Sample Size (Fails)

D,5 (a) Salt atmosphere [4] 1009 15(0) D,5 (b) Visual 2009 15(0)

Shield & cap removal Chemical 15(0) D,5 (c) (1) Seal, fine 1014 A2, He (shields / caps

removed) 15(0)

D,5 (c) (2) Seal, gross 1014 C1 15(0) Shield & cap removal Chemical 3(0) Seal, fine 1014 A2, He (shields / caps

removed) 3(0)

Seal, gross 1014 C1 3(0) D,6 Internal water vapor 1018 3(0)

D,7 Adhesion lead finish 2025 8(0)

D,9 (a) Resistance to Solder Heat 2036 3(0) D,9 (c) Visual 2009 3(0) D,9 (d) End-point electrical DC

parameters only [ Specified in 64Mb MRAM SMD 3(0)

Shield & cap removal Chemical 3(0) D,9 (b) (1) Seal, fine 1014 A2, He (shields / caps

removed) 3(0)

D,9 (b) (2) Seal, gross 1014 C1 3(0)

DPA Destructive Physical Analysis 5009 2(0)

P-15

Group E Radiation Qualification Results

Specification Type Method Value Total Ionizing Dose 1019 1 Mrad(Si)

Single Event Upset ASTM F-1192 or EIA/JESD 57

< 1E-10 upsets/bit-day [1]

Dose Rate Upset 1021 1E9 Rad(Si)/s

Dose Rate Survivability 1021 1E12 Rad(Si)/s

[1] Geosynchronous Orbit, Solar Minimum, 100mils aluminum shielding

Specification Type Method Value

Neutron Displacement Damage

1017 1E14 (1 MeV eq.) N/cm2

Latch-Up 1020 Immune

Proton Induced Upset < 1E-10 upsets/bit-day [1]

[1] Geosynchronous Orbit, Solar Minimum, 100mils aluminum shielding [2] No latch-up observed during Heavy Ion or DRU Testing

• Radiation Qualify by Similarity to the 16Mb MRAM.

P-16

Electro-Static Discharge (ESD Testing)

• ESD testing completed on 3 parts - MIL-STD 883, Method 3015.7, Human

Body Model - 48 hours of burn-in prior to test - Two parts were subjected to 500V and

then in 500V increments beyond 5000V - Three parts were subjected to 2500V

directly All three passed

- Parametric testing showed no difference between pre-test and post-test measurements

P-17

SMF Qualification Results: Pass 5(0)

• Five qual parts were subjected to SMF testing - Testing was performed at room temperature with a magnet as the SMF source and

calibrated spacers

• Results from all five parts pass 5(0)

Mode Spec Test Result Margin

Write 65 Oe 98 Oe 51%

Non-Write 100 Oe 169 Oe 69%

P-18

Technology Qualification Results

• These parameters are qualified by similarity to the 16Mb MRAM. - Data retention ≥ 15 year life

Accelerated testing was performed with Neel-Arrhenius analysis with no failures.

- Endurance ≥ 1015 cycles for write and read Endurance was demonstrated at Honeywell to 1E13 write and read cycles at 150 °C

with no failures for the 16Mb MRAM qualification. These results are consistent with expected unlimited endurance.

- Electro-migration ≥ 15 year life

Passes MIL-PRF-38535 Appendix A Section A.3.5.5 and design rules

P-19

Summary

• Three MRAM products in Production and two QML V Qualified. • Extensive qualification testing on both the 16Mb and 64Mb products.

- Additional characterization testing on 64Mb MRAM - Validated MIL-PRF-38535 Group A, B, C, D, and E performance

Demonstrated successful electrical, thermal, and mechanical performance Demonstrated successful radiation and life test performance Demonstrated successful data retention and endurance performance

• Qualified MRAM specific parameters including: - Stray Magnetic Fields - Read and Write Endurance - Data Retention

• QML V Qualified SMD 5962-13212 (16Mb) and SMD 5962-14230 (64Mb)

Continuously Driving Products To QML V

Thank You!

12015 Microelectronics Reliability and Qualification Working Meeting Approved for public release:ES MVA 012915 - BAE379

DDR Memory Solutions for Next Generation Spacecraft Systems

Joseph Marshall

Space Products and ProcessingBAE Systems

Courtesy of NASA Courtesy of NASA Courtesy of NASA

Courtesy of NASA

Courtesy of NASA Courtesy of NASA

PAGE 22015 Microelectronics Reliability and Qualification Working Meeting

Agenda

• Spacecraft Payload and Bus Evolving Architectures• DDR3 Memory Requirements and Insertion• Radiation Mitigation Solutions• RAD® DDR Radiation Effects Mitigation ASSP• COTS DDR Memory Solutions• High Density RAD® DDR3 REM DIMM• Summary

Approved for public release:ES MVA 012915 - BAE379


RH45™ enables advanced space solutions

The RADNET and other RH45 ASICs expand our Processor, RapidIO and SpaceWire capabilities beyond our two 150nm RADNET SpaceWire ASICs (endpoint and 4 port

router-bridge)

RADSPEED™ HB SoC (4 cores)

RAD5510™ Processor (1 core)

RAD5545™ Processor (4 cores)

RADNET™ 1848-PS RADNET™ 1616-XP RADNET™ SRIO-EP



Example SpaceVPX Standard Switch Topology: 16-slot backplane

SpaceWire Control Plane

Serial RapidIO (SRIO) Data Plane

sRIO, PCI, SpaceWire or Custom Expansion Plane

I2C, Clocks and ResetUtility Plane

SpaceVPX (VITA 78) extends OpenVPX (VITA 65) by adding support for dual redundant architectures and supportingHeritage (cPCI) modules

*UM – Utility Management; SW – Power, Utility and Management Switches for each

slotChMC – Chassis Controller IPMC –

Individual Slot Control

Power and SelectionUtility Plane

SRIO fat pipe (FP) = 4 lanes @ up to 5 Gbaud each

After coding overhead = 16 Gbps

SpaceVPX supports fault tolerantdual redundant architecture

VPX1

VPX2

VPX4

VPX 5

VPX10

VPX11

VPX6

VPX9

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

IPMC IPMC IPMC IPMC IPMC

DataSwitch

DataSwitch

ContrlSwitch

ContrlSwitch

TP

TP

Power A

Switched ManagementPlane (IPMB)

Control Plane(TP)

Data Plane(FP)

ExpansionPlane(32 Pairs)

Slot numbers are logical, physical slot numbers may be different

IPMC ChMC ChMC

VPX13

ContrlPlane

ExpanPlane

DataPlane

IPMCSwitched Utility Planeincludes power

UM1-2

Controller SelectionA and B (HLD)

VPX14

ExpanPlane

VPX12

ExpanPlane

ExpanPlane

Perip

hera

lSl

ot-S

epa r

ate

Perip

hera

lSl

ot- A

ttach

ed

Perip

hera

lSl

ot–

Sepa

rate

Herit

age

Com

pact

P CIS

lot

SW

Payl

oad

Brid

geSl

ot

Payl

oad

Brid

geSl

ot

ExpanPlane

PCI Bus BPCI Bus A

Cont

rolle

r&Da

taS w

itch

w/ B

ridge

Slot

ExpanPlane

Herit

age

Com

pact

P CIS

lot

VPX3

ExpanPlane

Perip

hera

lSl

ot- A

ttach

ed

ExpanPlane

Payl

oad

Slot

Payl

oad

Slot

Cont

rolle

r&Da

taS w

itch

w/ B

ridge

Slot

Payl

oad

Slot

Payl

oad

Slot

ContrlPlane

IPMC

Power B

ContrlPlane

ContrlPlane



Sensor

RADSPEED HB SoC Quad Core

Dual DSP

RAMNVRAM

RADSPEEDDSP

RADSPEED™DSP

RAMRAMNetwork Switch

SpaceWireRouter

RADNET™1616-XPCrosspoint

Switch

RADNET1848-PSSerial

RapidIOPacketSwitch

RAD5545™ Quad CoreProcessor

Single Board Computer

RAMNVRAM

RAM RAMRAM RAM

Serial RapidIO Data Plane

SpaceWire Control Plane

I2C Utility Plane

RH45™ASICSensor NVRAM

RAM

Sensor Interface

RAD750®CPU +

L2 cache

RH45ASIC

RADNETSRIO-EP

NVRAMRAM

Communications

Interface

Sensor

RADNETSRIO-EPNVRAM

Single Board ComputerH

erita

gePC

I Car

ds

Recorder

RAM RAM RAMRAM RAM RAMRAM RAM RAM

RADNET SRIO-EP

SpaceVPXOn-boardProcessor

Box

1553SpaceWire

PCISerial RapidIOClearConnect bridge

I2C

The resulting modules will create the next generation spacecraft, including high performance on-board processing

RAD750CPU +

L2 cache

Single Board ComputerRAM

NVRAM

BusElectronics

GNC Interface

ADC

DAC … Digital Sensor IMUStar

TrackerHer

itage

PCI C

ards

RADNET SRIO-EP

RADNETSPW-RB4

RADNETSPW-RB4

RADNETSPW-RB4

RADNETSPW-EP

RADNETSPW-RB4

RADNETSPW-EP

Example future spacecraft architecture(redundancy not shown)

RADNETSRIO-EP

RCC

RAMNVRAM

FPGAFPGA

RAMRAM

Sensor

RH45ASIC

RADNETSRIO-EP

RAD5510™Single Core

CPU

Sensor DetailRAM



DDRx Radiation Effects Mitigation Requirements

The RAD® DDR REM ASSP packaged with additional ECC devices in the RAD® DDR REM DIMM will meet this space processing need

Approved for public release:ES MVA - 040913


COTS vs. RAD® DDRx REM DIMM

DDRxController

withinASIC, FPGA,CPU, DSP, …

SECDED:64 data + 8 ECCDDRx

POL DDRx

DDRxController

withinASIC, FPGA,CPU, DSP, …

DDRx

DDRx

DDRx

S/D8EC: 64 data + 8 SECDEC ECC + 16/32 ECC

DDRxPOL

M

M

M

M

1VPOL

DDRx

DDRx

DDRx

DDRx

Interrupt(s) to S/W

I2C, JTAG from S/W

REM

ASSP

COTS DDR DIMM RAD DDRx REM DIMM

The DDRx-REM Assembly will be a separate multi-chip module with high performance connections containing the DDR-REM ASIC, DDRx devices and

power switching MOSFETs(M) for each DDRx device

Circuit Card Assembly (CCA)

Circuit Card Assembly (CCA)

CCA with COTS DDRx DIMMCCA with RAD DDRx REM DIMM

Approved for public release:ES MVA - 040913


RAD® DDR REM ASSP• Support for DDR2 or DDR3 memories (programmable 1.8V and 1.5V DDR I/O)• JEDEC Compatible 800 MHz Host DDR Interface• JEDEC Compliant 800 MHz Target DDR Interface• Enhanced Error Correction (S8EC or D8EC)• Programmable scrub mode

• RH45™ Technology• Total dose: > 1 MRad (Si)• SEU: <1E-10 errors/bit-day• Latch-up: immune• Performance:• DDR2/3-800 (calibrated)• I2C @ 400 KH• Power dissipation: • 4.5W worst-case • Power supplies:• 0.95V +50mV Core• 1.8V/1.5V DDR2/3 I/O (programmable)• 1.8V/2.5V/3.3V LVCMOS I/O (programmable) RAD DDR REM ASSP in Physical Design

Approved for public release:ES MVA 012915-BAE379

I2CController

Registers/Mode Control(Config/Status)

Initialization/Calibration

JTAG Slave Module

SkyBlue Controller

Snoop/Flow ControlLogic

Config SettingsInterrupts

Stall Req/Gnt

Mitigation Monitor/Controller

DecodeECC

JTAG I/F

TestI/F

I2C I/F

Clk/Strb

Data

ECC

Addr/CtrlAddr/Ctrl

Target DDR I/F

Clk/Strb

ECC

Addr/Ctrl

64

8

Addr/Ctrl

EncodeECC

ScrubQueue

64,8

32

Pwr Ctl

Input Clock Domain (CLK_IN MHz) Host Source Domain (DDR DATA RATE/2) Data Rate Domain (DDR DATA RATE)

HostDDRPHY

HSTPLL

TGTDDRPHY

Trgt Source Domain (DDR DATA RATE/2)

64(72)

64(72)MUXing

Addr/Ctrl/Data

Discretes

TEST

CLK_IN

TGTPLL

H_CK H_CK

Clock/ResetI/FReset


DDR Board Usage• COTS equipment uses DIMMs

• Isolate critical routing• Most of these are mounted perpendicular to board• Thermal paths very limited• Structural support lacking for space vibration• Highest density• JEDEC standards for each • Include SECDED ECC

• COTS XR-DIMM created for embedded market• Mounted parallel to board like a daughter card• Connector usable in space• Thermal and structural paths possible• DDR3 boards available for prototyping or interface checkout

COTS XR-DIMM

XR-DIMM adopted as base assembly for DDR2 and DDR3



RAD® DDR3 REM DIMM FeaturesTechnology• RAD DDR REM ASSP: Radiation-

hardened by design RH45™ circuit library

• Trusted foundry 45nm SOI process• Upscreened industrial DDR3 memory• GaN MOSFET DDR3 power switchingOperating temperature range• -40oC to +105oCRadiation hardness• Total ionizing dose: 100 Krad (Si)• SEU DIMM: ECC corrected• SEU: REM ASIC Flip-flops: 8E-14

upsets/bit-day• SEFI: REM mitigated• Latch-up immuneConfigurations• 2, 4, 8 or 16 GB• x8 or x16 devices

Memory interfaces• 72 bit DDR3 with SEC/DED EDAC • supports up to 4 ranks and 16 GB• 800M transfers per second peakInput/Output interfaces• I2C host interface• Interrupt and status discretesTest and debug interface• JTAG test points for REM ASIC Power supplies• 12V+/-20% power switch• 0.95 V +/- 5% REM ASIC core• 1.5V +/- 5% DDR3 and DDR3 I/O• 0.75V +/- 5% DDR3 reference• 1.8V, 2.5V and/or 3.3V CMOS I/O• 3.3V fixed I/OPower dissipation• 2-10 Watts @ 95oC depends on

configuration and modeApproved for public release:ES MVA 062614-0294


RAD® DDR3 REM DIMM Detail

RAD DDR3 REM DIMM design fully placed, analyzed and ready to route

RA

DD

DR

REM

ASSP

RAD DDR3 REM DIMM

Approved for public release:ES MVA 062614-0294


RAD® DDR3 REM DIMM Usage Summary• Single RAD DDR3 REM DIMM design supports multiple COTS DDR3 devices

• COTS DDR3 XR-DIMM may be used for bring-up of DDR3 interface• RAD DDR3 REM DIMMs may be used with variety of controllers

• 72 bit SECDED protected DDR3 interfaces• CPUs, ASICs and higher performance FPGAs

• Single bit and single device errors corrected by extended error code• Notification of errors via I2C to DDR3 controller or controlling software unit• Will continue to operate through until right time to correct

RAD DDR3 REM DIMM and its RAD DDR REM ASSP enable COTS DDR3 memories to be used in most spaceborne environments



RAD® DDR3 REM DIMM Usage Summary• Single RAD DDR3 REM DIMM design supports multiple COTS DDR3 devices

• Updated radiation testing will select best DDR3 devices to be upscreened• One or two rows may be populated – 4 to 16 GB per DIMM• COTS DDR3 XR-DIMM may be used for bring-up of DDR3 interface

• RAD DDR3 REM DIMMs may be used with variety of controllers• 72 bit SECDED protected DDR3 interfaces• CPUs, ASICs and higher performance FPGAs• One or two DIMMs per DDR3 port mounted opposite each other on board• RAD DDR3 REM DIMM equivalent to COTS DDR3 with small first access delay

• Single bit and single device errors corrected by extended error code• Log of errors in RAD DDR REM ASSP accessible through I2C• Notification of errors via I2C to DDR3 controller or controlling software unit• Scrubbing of non-SEFI errors may be done in background • Will continue to operate through until right time to correct• To correct SEFI, controller isolates memory bank and commands DDR REM ASSP to

perform power cycles, resets or initializations

RAD DDR3 REM DIMM and its RAD®DDR REM ASSP enable COTS DDR3 memories to be used in most spaceborne environments


PAGE 142015 Microelectronics Reliability and Qualification Working Meeting Approved for public release:ES MVA 012915 - BAE379

Power Matters

Radiation Tolerant FPGA UpdateKen O’NeillDirector of Marketing, Space and AviationMicrosemi SOC Group

MRQW January 28, 2015© 2015 Microsemi Corporation. . 1

Power Matters

Current Status – In-Service Radiation Tolerant FPGAs

Next-Generation FPGA for Space Applications

Qualification Plans

Conclusion and Next Steps

Agenda

© 2014 Microsemi Corporation. 2

Power Matters

In-Service RT FPGAs – Update

RTSX-SU• Over 2,000 SEU-hardened flip flops• EAR controlled, no longer ITAR• Flight heritage since 2005

RTAX-S/SL/DSP• Over 20,000 SEU-hardened flip flops• Over 500kbits on-board SRAM• Up to 120 multiply-accumulate blocks• EAR controlled, no longer ITAR• Flight heritage since 2007

RT ProASIC3• First Flash-based FPGA in space• Reprogrammable and non-volatile• EAR controlled, no longer ITAR• Now QML class Q qualified

Mars Reconnaissance OrbiterRTSX-SU on board (2005)

Cosmo Skymed 1 – 4 RTAX on board (2007)

NASA IRISRT ProASIC3 on board (2013)

Power Matters

Next Generation Radiation-Tolerant FPGAs

TM

© 2014 Microsemi Corporation. .

Power Matters

RT FPGAs Migrating to High Speed Processing


Frequency ofOperation

Logic Density

150 KLE

20 KLE

9 KLE

2 KLE RTSX-SU

RT ProASIC3

RTAX-S / DSPCommand and Control

Medium Speed Processing

High Speed Processing• 150 KLE• 5 Mbit SRAM• 126 GMults / second• 75 Gbit / second

SERDES bandwidth

Power Matters

Designed for high-bandwidth data processing in payload applications• Abundant high-performance programmable logic fabric• Embedded high speed multiply-accumulate blocks• Ample on-board memory with fast access time, two block sizes• High performance I/Os – SERDES, LVDS, DDR2, …

Based on 65nm Flash low power process• Naturally resistant to configuration upsets• Non-volatile configuration – live at power-up, no external boot memory needed• Low static power

RTG4 – radiation enhanced for GEO and deep space• Total ionizing dose, Single event effects, Latch-up immunity

Next Generation Space FPGAs

6© 2015 Microsemi Corporation. .

Power Matters

RT4G075 RT4G150 RT4G200LUT4 + TMR/SET FF 77,712 151,824 202,896

User IO (non-SERDES) 528 720 816RAM24K Blocks 111 209 269

uRAM1.5K Blocks 112 210 270RAM Mbits 2.8 5.2 6.7

UPROM Kbits 254 381 41718x18 Multiply-Accumulate Blocks 224 462 594

SERDES lanes 16 24 32DDR2/3 SDRAM Controller (with ECC) 2x32 2x32 2x32

Globals 24 24 24PLLs (Rad Tolerant) 8 8 8

Spacewire Clock & Data Recovery Circuits 12 12 12PCI Express Endpoints 2 2 2

PackagesCG1432

CG1657

CG2092

RTG4 Family Resources

7© 2015 Microsemi Corporation.

Power Matters

Total Dose• > 100 KRad TID

Single Event Effects• No configuration failures (to be tested to > 110 MeV-cm2/mg)• No single event latch-up (to be tested to > 110 MeV-cm2/mg)• Mitigation for single event upsets

– Flip-flops with TMR and asynchronous self-correction (LETTH > 37 MeV-cm2/mg)– Flip-flops in the logic fabric– Flip-flops in embedded features – Mathblocks etc

– On-chip SRAM (RAM24K and uRAM1.5K)– Built-in EDAC– 1E-10 errors/bit-day, GEO solar min

• Mitigation of single event transients– Logic cells hardened with SET filter

– SET filter can be individually enabled / disabled for higher performance– Target 1E-8 errors/bit-day, GEO solar min

Radiation Specifications

8© 2015 Microsemi Corporation. .

Power Matters

Traditional Sense-Switch interconnect• VT changes as device accumulates TID• Results in TPD increase• Example – RT ProASIC3 has 10%

TPD degradation at around 30Krad

RTG4 TID - Tolerant interconnect• Accumulation of TID causes VT changes

in PFG and NFG floating-gate devices• However, interconnect pass transistor

stays strongly turned on as long as PFG is stronger than NFG

• Minimal change in TPD with accumulated TID to > 100Krad

TID Mitigation in RTG4 Flash FPGAs

© 2015 Microsemi Corporation.. 9

Power Matters

RT4G150 Device Floorplan


Bank J1 JTAG and SPI pins

Clock HS

Serial Sub-system

HVG

EN

WL ACCESS

uPROMsIO-Clusters

IIP-Clusters

IIP-Clusters

2 CCC2 PLL

EIP-Clusters

RTG

4 Co

ntro

l

2 CCC2 PLL

2 CCC2 PLL

BL A

CCES

S

Fact

ory

Segm

ent

and

Use

r Seg

men

t

uPROM-EIPS

IIP(LSRAM, uSRAM, Math)






MSIOsBank B1

MSIOsBank B2

MSIOsBank B3

Cloc

k VS

Cloc

k VS

Cloc

k VS

Cloc

k VS

FDDR

Con

trol

ler

DDRI

Os

Bank

R1

MSI

ODs

Bank

R2

MSI

ODs

Bank

R3

FDDR

Con

trol

ler

DDRI

Os

Bank

L1M

SIO

DsBa

nk L2

MSI

ODs

Bank

L3DDR CALIB DDR CALIBCCC -EIPS

CCC -EIPSCCC -EIPS

2 CCC2 PLL

Logic Cells

μRAM(1.5Kb)

Block RAM(24Kb)

Mathblocks

SDRAM DDRxController

SERDES,PCS,

PCI-Express

PLL and CCC

CCC -EIPS

Power Matters

Dedicated STMR Flip-flop to enable efficient TMR hardening• With enable, global asynchronous set/reset, and local synchronous set/reset

Fast carry chain to complement Mathblock performance• Arithmetic functions (add/subtract)• Target 300 MHz for 32-bit functions (no SET filter)• Target 250 MHz for 32-bit function (SET filter deployed)

Industry standard LUT4 for efficient synthesis High utilization

• LUT4 and flip-flop in same module can be used independently• Hierarchical routing architecture enables >95% module utilization

RTG4 Logic Module

SimplifiedDiagram

TMRProtected


Power Matters

18 x 18 multiplier with advanced accumulate• New 3-input adder function: (C + D) +/- (A * B)

High performance for signal processing throughput• 250 MHz with SET mitigation• 300 MHz without SET mitigation

Optional SEU-protected registers on inputs and outputs (including C input)

RTG4 Mathblock

12

X

D

EN

>> 17C[43:0] SHIFT17

SEL_CASC

SN[43:0]

OVFL / CO

ADD_SUBA[17:0]

B[17:0] +

SN-1[43:0]

D[43:0]

D

EN

D

EN

D

EN

D

EN

© 2015 Microsemi Corporation.

Power Matters

Radiation Tolerant• Resistant to multi-bit upset • Built-in optional EDAC (SECDED) LSRAM – up to 24 KBit• Dual-port and two-port options• High performance synchronous operation• Example usage

– Large FFT memory

uRAM – up to 1.5 KBit• Three Port Memory

– Synchronous Write Port– Two Asynchronous or Synchronous Read Ports

• Example usage– Folded FIR filters and FFT twiddle factors

Mixed port sizes• Write and read port sizes can be different

300 MHz performance

RTG4 Memory Blocks

RAM24K

CLKA

ADDRA[ ]

WDATAA[17:0]

WENA

CLKB

ADDRB[ ]

WDATAB[17:0]

WENB

RDATAA[17:0]

RDATAB[17:0]

ECC_STATA

ECC_STATB

uRAM1.5K

WCLK

WADDR[ ]

WDATA[17:0]

WEN

RCLKA

RADDRA[ ]

RENA

RDATAA[17:0]

RDATAB[17:0]

ECC_STATA

ECC_STATB

RCLKB

RADDRB[ ]

RENB


Power Matters

Single ended standards• LVCMOS from 1.2V to 3.3V• LVTTL• PCI Voltage reference standards (600+ Mbps)• Includes on-chip termination• SSTL2, SSTL18 and SSTL15

– For DDR2/DDR3 SDRAM memories• HSTL18 and HSTL15

– For SRAM memories

Differential I/O standards• Includes on-chip termination• True LVDS (600+ Mbps)• Mini-LVDS, M-LVDS, RSDS, LVPECL

General Purpose IO


Power Matters

SpaceWire Hardened Clock Recovery

DMUX

SMUX

sel_rx_#<1:0>

dmux#_out

smux#_out

rxclk<#>

Delay Cell

Rx Recovery

del_sel<4:0>sel_rx_#<3:2>

Sele

cted

from

pad_

ccc_

clk<

3:0>

Data

Strobe To G

loba

lC

lock

Net

wor

k

• Data and Strobe can connect to LVDS or LVTTL input pins• Optional Single Event Transient filtering


Power Matters

3.125Gbps SERDES

16

PCI ExpressProtocol

x1, x2, x4

TXDn

RXDn

ProgrammableLogic

PMA

PCS

Serializer / DeserializerClock Recovery

8B/10B Encoding / Decoding

4 X16 PIPE

<= 3.125GHz <= 156MHz

1

SRIOOr

CustomProtocol

64-bit AXI /AHB

4 x 20-bit EPCS

XAUIBridge

XGMII

PCI ExpressInterface

802.3Or

CustomProtocol

PMA Based on PCIe Gen 1 PHYRT Performance = 1 – 3.125 GbpsUp to eight x4 units


Power Matters

General purpose logic• 250 MHz system performance with SET mitigation deployed• 300 MHz system performance without SET mitigation• 300 MHz DSP support performance (adders, delays, etc.) Mathblock• 250 MHz pipelined performance with SET mitigation deployed• 300 MHz pipelined performance without SET mitigation RAM18K and uRAM1K• > 300 MHz IO• > 600 Mbps LVDS and 667 Mbps DDRx SDRAM data• SERDES to 3.125 Gbps Overall• 250 MHz general system performance with SET mitigation deployed• 300 MHz signal processing performance without SET mitigation

Performance Summary


Power Matters

Flip chip assembly Hermetically-sealed cavity Internally-mounted BME decoupling capacitors

RTG4 Packaging Summary

18

RTG4 Die

BME decoupling capacitors placed inside

Under fill (passed RGA <5,000ppm, passed outgas to NASA spec)

Thermal adhesive between die and seal lid (passed RGA <5,000ppm, passed outgas to NASA spec)

Kovar Lid


Power Matters

RT devices for space flight applications• Initial device: RT4G150• Early access to software and documents via Lead Customer Program: NOW• Sample RT4G150 silicon: March 2015• RT4G150 development kit: April 2015• Mil Std 883 class B flight units: 1Q CY2016• QML class Q qualification: 4Q CY2016• QML class V qualification: 2017

RTG4 Lead Customer Program• Start product evaluation and provide feedback• Early access software: NOW• RTG4 user guides: NOW• Power calculator: NOW• Open to new participants – send email to

[email protected]

RTG4 Product Availability


Power Matters

Mil Std 883 Class B qualification• Starts 4th quarter, CY2015• Completes 1st quarter, CY2016• Qualification will use RT4G150 in CG1657 packages

– 3 wafer lots– 3 assembly lots– 1,000 hour HTOL

QML class Q qualification• Technology insertion package currently in preparation phase• Intent is to achieve QML-Q by end of CY2016 QML class V qualification• It is our intention to achieve QML class V• Working with DLA, SMC / Aerospace, NASA, JPL to ensure

requirements are clear and understood

Qualification Plans

© 2015 Microsemi Corporation.. 20

Power Matters

Non-volatile RT FPGA for payload data processing• High density, high performance, low power RTG4 FPGA• Lead customer program with software access NOW• Sample RT4G150 silicon: March 2015• RT4G150 development kit: April 2015• Mil Std 883 class B flight units: 1Q CY2016• QML class Q qualification: 4Q CY2016

Next steps• Mil Std 883 class B qualification: 1Q CY2016• QML class Q qualification: 4Q CY2016• QML class V qualification: 2017

RTG4 Conclusions and Next Steps


Power Matters

Detailed discussions on• Microsemi space products – discrete, power, RF, ASIC, FPGA, timing• Space product roadmap• Design tips and tricks• Qualification and reliability updates• Radiation testing results and mitigation strategies• Package development and roadmap• Development and verification tools Downloads at http://www.microsemi.com/spaceforum Next events• June 2015 – USA (Los Angeles, Washington DC area)• June 2015 – Europe (Noordwijk, Netherlands)• August 2015 – India (Bangalore, Ahmedabad)

Microsemi Space Forum


http://www.microsemi.com/spaceforum

© Copyright 2015 Xilinx.

Kangsen HueySpace Product Marketing ManagerJanuary, 2014

Xilinx CN Package Qualification Updates for MRQW 2015


CF (IBM) vs CN (Kyocera) Packages

Page 2


Comparison between IBM (CF)and Kyocera (CN) Packages

Original IBM CF Package New Kyocera CN PackageSilicon and Substrate Remain the Same

All design tools and timing files remain the same

Package pin assignment and Design place & route are preserved

BME capacitors used remain the same parts (Tin-Lead Terminals)

Assembly Related ChangesAssembled at IBM at Bromont Canada Assembled at Kyocera at San Diego

CGA with IBM 90/10 solder columns CGA with 6-Sigma 80/20 solder columnsHigh Lead Flip Chip Solder BumpHigh Lead Solder for Capacitor Attach

Eutectic Flip Chip Solder BumpEutectic Solder for Capacitor Attach

SiC Lid (Electrically Non-Conductive) Al-SiC Lid (Electrically Conductive)

TIM and Underfill Material (IBM Specific) TIM and Underfill Material (Kyocera)

PCB Land Pad diameter = 0.7 mm PCB Land Pad diameter = 0.8 mm

Page 3


Virtex-5QV is the CN qualification vehicle– V5QV has the largest die, the largest package, the most solder bumps,

and the highest pin counts among all Virtex-4QV and Virtex-5QV packages– 3 assembly lots built from 3 wafer lots are required for qualification– Virtex-4QV families of devices are automatically qualified by Virtex-5QV

qualification results

Qualification tests include:– QML Group A, B, C, D, E– Destructive Physical Analysis (DPA)– Temperature Cycles (TC)– Biased-HAST– High Temperature Storage (HTS)

Qualification has completed in January, 2015– Qualification Report to publish around the end of January– Qualification data will be submitted for MIL-PRF-38535 class Y certification

• Target for QML-Y for Virtex-5QV in 2016

CN Package Qualification Summary

Page 4


Lots Quantity Status NoteAssembly 3 all parts Completed at KyoceraGroup A 3 all parts CompletedGroup B 3 3 / lot CompletedGroup C 3 47 / lot Completed 1,000hrs@125oCGroup D 3 45 / lot CompletedGroup E 3 22 / lot CompletedDPA 3 5 / lot CompletedTemp. Cycle 3 15 / lot CompletedBiased-HAST 3 15 / lot CompletedHTS 3 15 / lot Completed

Virtex-5QV CN Package Qualification Status

501 parts consumed to conduct CN package qualification tests

Page 5


Pre-Qualification at Kyocera conducted– Multiple engineering built for process optimizations – XQDaisy-CN1752 build completed as process validation– Material Characterization

• Moisture Sensitivity Level (MSL) = 1• Out-Gassing per ASTM E-595 meets TML < 1.0% and CVCM < 0.1%

requirement

Standard Assembly process utilized for Qualification Builds– 3 assembly lots built from 3 wafer lots with a total of 600+ parts assembled

• All required assembly monitoring tests (internal/external visuals, die pull, CSAM, Lid shear) conducted

– Time separation required between assembled lots to account for material and process variations• Lot #1 assembly lot built in April 2014, lot size > 200• Lot #2 assembly lot built in June 2014, lot size > 200• Lot #3 assembly lot built in July 2014, lot size > 200

Assembly Builds

Page 6


Group A Electrical Tests Completed– 100% electrical test with full functional vector sets

at 3-Temperatures on 100% production units for all lots– Lot #1, Lot #2, and Lot #3 have all completed Group A tests

• All qualification units are ready for reliability tests• Parts designated for customer shipments, have completed electrical screening

tests All shippable parts stay as LGA in inventory Columns will be added when backlogs are booked

Group B Completed– Physical Dimensions, Internal Visual, Die Pull tests

• Other assembly inline tests also serves as Group Brequirements

– Lot #1, Lot #2, and Lot #3 have all completed Group B tests

CN Qualification Test Status Update

Page 7


Group C Life Tests Completed– 47 units per lot, 1,000 hours at Ta = 125o C– Lot #1, Lot #2, and Lot #3 have all passed Group C tests

Group D Tests Completed– Includes Group D1, D3, D4, and D5 tests (15 units per each subgroup)– Lot #1, Lot #2, and Lot #3 have all passed Group D tests

Group E Tests Completed– 22 units per wafer lot tested for 1 Mrad(Si) total dose– Lot #1, Lot #2, and Lot #3 have all passed Group E tests


Page 8


Destructive Physical Analysis (DPA) Completed– 5 units per lot– MIL-STD-1580 DPA requirement– Lot #1, Lot #2, and Lot #3 have all passed DPAs

Biased-HAST (Highly Accelerated Stress Test) Completed– 15 units per lot– 130o C, 85% Humidity, 2 atm, 3.5 V, for 96 hours

• Level 1 precondition (soak + 3x reflow) performed prior to HAST

– Lot #1, Lot #2, and Lot #3 have all passed the 96 hours test– Continue to run HAST to 192, and 500 hours for data collection

• All 3 lots have passed 192 hours point, will reach 500 hours in March


Page 9


HTS (High Temperature Storage) Completed– 15 units per lot– 150o C, for 1,000 hours after 3x reflow– Lot #1, Lot #2, and Lot #3 have all passed the 1,000 hours test– Continue to run HTS to 2000 hours for data collection

• Lot #1 completed 2,000 hours• Lot #2 & #3 will reach 2,000 hours in April

Temperature Cycle Test (T/C) Completed– 15 units per lot– TM1010, Condition C (-65o C to +150o C), 500 cycles required

• Level 1 precondition (soak + 3x reflow) performed prior to T/C

– Lot #1, Lot #2, and Lot #3 have all passed 500 cycles– Continue to run T/C to 2,000 cycles for data collection

• Lot #1 done 2,000 cycles• Lot#2 & #3 will reach 2,000 cycles in March


Page 10


CSAM & Cross-Sectionconducted after 500 & 1000 Temp. Cycle testsCSAM top scan – Showed no delamination– No voids in underfill

Cross-Section examinations– Detailed examinations

done on multiple bumps at corners and center of the packages– No cracks on solder bumps, underfill, die, and substrate observed– No flux residue observed

Post-T/C Inspections

Page 11


6-Sigma Solder Column Attach– Utilize 6-Sigma QML-V production process for V-grade devices– BLR parts now in column attachment process (40+ to be used for BLR)

• Two type of Parts (no-CGA-rework and with-multiple-rework) to address effects for column reworks

BLR test shall complete in mid-2015– This is a reliability demonstration test, and does not gate CN qualification

• Xilinx has used 6-Sigma columns for ~10 years with Virtex-II family• 6-Sigma has done V4QV and V5QV column replacements for many customers• Many Xilinx customers have already qualified V5QV with 6-Sigma columns

– FR-4 PCB pad diameter will be 0.8mm• 0.8mm pad diameter is per 6-Sigma

specification (IBM spec. is 0.7 mm)

Board Level Reliability (BLR) Tests

Page 12


Xilinx Space-Grade Roadmap

2008 201120102009 2012 201520142013 2016

V4 Release

10k Hr LifetestV5 Design, Qual., & Release

ADQ Flow 38535 Class Y (JC13/G12)

…

V5QV class Y Certification

Next Gen.RT FPGAs

CN Pkg Qualification

10k Hr Lifetest

V5 Radiation Characterization (XRTC & NASA/GSFC)

V5QV QML Product Offering

QML

Page 13


Why RT for Next Gen. Space Parts

Flip-Flops

Distributed RAM

Block RAM

Configuration RAM#

Z

12T SRAM Cell needed for 100% Configuration RAMs– Implemented at 65nm for V5QV (25% silicon growth)– RH-BD requires the same spacing “Z” for

all smaller nodes (28nm, 20nm, 16nm)– New generation products are much larger than

V5QV and need more Configuration RAM, implementing12T-Cell no longer effective in silicon architecture

Rad-Tolerant (RT) approach is more suitable for next generation Space FPGA

– Xilinx is evaluating 20nm and 16nm technologies– Will offer a single technology node for next generation Space parts

FPGA Overhead

Page 14


Missions with Virtex-5QV

DLR H2 Comm. Sat. (2017 Launch)

LCRD(2017 Launch)

Orion2014 / 2018 Launch

OSIRIS-REx(2016 Launch)

NovaSAR Grace Follow-On2017 Launch

Iridium Next (66+6+9)(2015 Launch)

Glonass-K

Formosat-5(2015 Launch)

Page 15


Elevates Users from Programmable Logic Designs to Programmable System Integrations

Reprogrammable FPGAs enable platform designs, hardware/IP re-use, hardware consolidation– The best solution for faster development time with lower costs– Reduces project risk and maintains schedule

Rich resource of Logic Cells, DSPs, and Connectivity hard IPs suitable for – High bandwidth data processing– High throughput IO connectivity– Reduction of BOM– In-Orbit Updates/Optimizations/Repairs

V5QV is the most optimized RH-BD FPGAfor Space Payload Applications

Summary

Page 16


Thanks

Documents

MRQW 2015, 27-28 January 2015, El Segundo