C.A.V.EChatur Automatic Verification Environment

M.S Ganapathy SubramaniamSiddartha Ravichandran

Vivek SVijay Murali

INTRODUCTION

For implementing a hardware design successfully, it is important for design to be verified. Verification is a tedious job to be done manually and is usually error-prone. C.A.V.E provides an automatic verification environment which generates the e-code, which serves as a test bench which compares the actual output with the expected output. C.A.V.E is a generic verification environment which can be used for a various designs for a set of inputs.

Port List

Top Module

Scanner.py

Design.v

E Code Generator

Cave_e.e

C.A.V.E

Cave.py

1

2

OutputInput

Calling the program

Purpose:

To verify a design automatically for different inputs.

FUNCTIONALITY:

Features:

1.Scans the verilog file for keywords.2.Generates a specman e code file that serves as a test bench for verification of the design.3.Runs the e code with desirable inputs.4.Compares the output with the expected output.5.If expected output does not match with the outcome, the ports where the mismatch occurs is found and the error is reported to the designers.

Requirements:

Linux Operating systemSpecman e CompilerPython compilerVerilog Compiler

•The design(verilog) should contain the stimulus module.

Operating Environment:LinuxLanguage used: PythonVerification Tool:Specman e

ARCHITECTURE:AVE contains the following modules:1.Scanner.py2.Generator.py3.testst.txt

Scanner.pyThe scanner program reads the verilog file given by the designers and checks for keywords, module definitions, port lists and instances using pre-defined state machines depending on verilog grammar.

The keywords that are checked using state machines are: and, nand, nor, or, xor, xnor, buf, not input, output, inout, always, if, initial else, for, while, repeat, function, task case,end, begin,module.

After scanning the module's details like module names, port-lists, module instance names are retrieved. The modules that are instantiated in each module are stored.Based on the property that top-module is not instantiated in any other module, the algorithm finds the top-module and ports of the modules instantiated in it.

To synchronise between Specman and verilog a synchroniser clock is defined in a generated module which instantiates the top-module. The program also appends the extraction of input and expected output data fromtheir respective files to the generated module.

CAVE.pyThis program imports scanner.py, e-generator and the c-generator programs and runs them one by one.Thus it acts as an interface that connects all modules.

e-code Generator

This program generates e-code which interacts with verilog and compares the outputfrom verilog with the expected output.It also creates the necessary the structures and units which performs the above action.

It creates three structures input, inout and output which contains the variables that areextracted from the port-lists.The E-Code Generator does the following:

-> Generates data object.-> Generates the function header.-> Generates Driver object.-> Generates Reciever object.-> Generates Checker Object.-> Generates verificattion function.-> Writes the above contents to a file and thus generating an e file.

Inputs & Outputs• Inputs: The design file to be verified(Verilog) *Should be in the same order of the port-list as specified in design file

*No two Input and Expected outputs should be in the same line.*Design should be in a single file.

• The file containing inputs and expected outputs(Text)• Output: File containing results of the comparison (Text)