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Lalit Sharma , MCA II nd Semester, Lachoo Memorial College of Sc.& Tech., Jodhpur Mobile : 9414412879

24/02/2005

Computer Organization & Architecture

A well defined shape is termed as an architecture, where a logical constituent comprising

of several components working together for an objective is termed an organization.Thus computer architecture is defined as the collection of physical components

like CPU, Memory, Input / Output, devices etc. arranged in a particular fashion.The logical status defining the working of system at different point of time. Given

situations is termed computer organization. Conceptually a logical organization is buildup, architecture is constructed and the organization is defined to work.

Memory

A location with a specific address that holds an entity called data, where with reference to

the address the data can be accessed i.e. read or write is termed a Memory.

25/02/2005

MEMORY

Volatile Non Volatile

- RAM - ROM

- SRAM - ROM- DRAM - PROM- EPROM- EAPROM / E 2PROM

Semiconductor Technology -----------------------------------------------------------------

- CORE - Magnetic Disk

- MBM - Soft Disk - Hard Disk (Serial Access) (Floppy Disk)

- Magnetic Drum

- Magnetic Tape(Serial Access) Magnetic Technology ------------------------------------------------------------------------

- CCDs - CD ROM- DVD

Optical Technology ---------------------------------------------------------------------------

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Memory can be classified into two categories: Volatile and Non Volatile.The memory that losses its content when the power is switched off, is termed a

Volatile Memory. Where as the memory that retains the content even after power isswitched off, is termed a Non Volatile Memory.

With reference to technology the memory can be constructed in three fundamental

ways, they are (1) Semiconductor Memories(2) Magnetic Memories(3) Optical Memories.

The memory elements constructed with the help of Diodes and Transistors aretermed as Semiconductor Memories. Where as the memories that are made up with thehelp of magnetic sensitive material are termed Magnetic Memories. Where as thememories that uses laser technology for reading and writing data are termed OpticalMemories.

With reference to access the memories can be classified as Serial AccessMemories and Direct Access Memories.The memory whose Nth record is needed to be read and if is read after reading

(N-1) records, is termed a Serial Access memory. Where as the memory whose locationcan be directly retrieve for reading or writing, is termed Direct Access Memory.

Semiconductor Memories:-

SRAM

Figure 1

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SRAM

Figure 2

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8 X 4 SRAM

Figure - 3

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03/03/2005

RAM Random Access Memory is generally a volatile memory constructed with thehelp of semi-conductor technology. The name Random Access carries from a

phenomenon that any location of this memory can be accessed directly. These memories

are also called RWMs (Read-Write Memories). With reference to semiconductor technology, RAMs can be classified into two major categories:(1) S-RAM: Static Random Access Memory(2) D-RAM: Dynamic Random Access Memory

(1) S-RAM:- The S-RAM called Static RAM, is one of the major component of computer memory. Where they are used to construct the primary memory of thesystem. These memories are having Flip-Flops as basic storage element that canretain the content till the power is ON and does not require any kind of elementrefreshing and thus the name Static.

Figure 1 illustrates a typical binary cell, a single unit used for storing one bit of information. The circuit comprises of a R-S Flip-Flop (using NOR gates) as basicelement and is associated with three AND gates and two Inverters. The various controllines are

(i) Select : It is used to select or deselect the Binary Cell (BC). If select is set thecell is active else the complete cell is Tri-stated.

(ii) D in : It is Data input terminal used to write-in binary information.(iii) D out : The Data out terminal is used to read-out the data from Binary Cell.(iv) R / W : The R / W control terminal is used to carry out the cell access in form

of reading and writing.If R / W = 0 then a write operation is carried out else if it is 1 a read is carriedout.

Read operation:- Keeping select 1 if R / W is made 1 then the output AND gate isactivated but the input gates are inactive. Depending on the content of Flip-Flop a binaryvalue appears at D out.

Write operation:- Keeping select 1 if R / W is made 0 then the input AND gates areactivated while the output AND gate is disabled. Now whatever data is given at D in islatched into Flip-Flop when the clock is applied.

4 X 3 SRAM

A Static RAM can be constructed using a matrix of binary cells as depicted in Figure 2.The circuit comprises of a 2 X 4 Decoder associated with 12 Binary Cells arranged inmatrix form. The control lines of decoder acts as address for selecting a particular row,where upon by providing binary control information over R / W, the data is either written- in or read-out.

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(2) DRAM:-

04/03/2005

A Dynamic RAM is composed of a matrix comprising of binary cells made up with thehelp of MOSFAT transistor. A typical D-RAM binary cell is illustrated in above figurecomprising of three transistors T 1, T 2 and T 3 (P-Channel). The transistor T 3 is dopedheavily such that between source and gate terminal of this transistor a virtual holdcapacitor is generated. This capacitor is fundamental component used to store the binaryinformation. A charge present over this capacitor indicates logic one whereas a dischargecapacitor indicates a logic zero.

Due to the inherent property of the capacitor, it discharges with time and thusafter certain threshold value the capacitor is needed to be refreshed. This property of capacitor creates the memory Dynamic and so the name D-RAM.

Write operation This operation is carried out with reference to write data (D in) and write bus (W) terminals. When W goes low and when Din is zero then the capacitor is chargedholding logic one. Similarly keeping W zero if Din is equals one then the capacitor discharges holding logic zero.

Read operation This operation is carried out using two terminals: Read data (D out) andRead bus (R). When R goes low and if capacitor is charged then D out goes high. If R equals zero and capacitor is discharged then logic zero is appears at D out.The read operation of dynamic RAM cell is DRO type i.e. Destructive Read Out, thecapacitor discharges and hence when the logic one is read out from a cell, the cell isneeded to be recharged for retaining the logic(memory).

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Comparison between SRAM and DRAM (1) Physical size : The size of SRAM much greater then DRAM hence the packing

density of DRAM is much higher as compare to SRAM.(2) Speed : The speed of DRAM is much higher as compare to SRAM (Due to

propagation delays of gates).

(3) Data retention : The SRAM cell can retain data till the power is availablewhereas a DRAM cell discharges over time even if power is there and thusrequires a refresh system which is an overhead.

(4) Read-out : The SRAM cell is NDRO (Non Destructive Read Out) type whereasDRAM is DRO (Destructive Read Out) type. Thus after reading DRAM a cell isneeded to be discharged, again it is an overhead.

ROM (Read Only Memory) :

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17/03/2005

ROM: The Read Only Memories are a category of memory that can be read from but cannot be written under normal circumstances. To write to a ROM we require some specialhardware and software arrangement. The ROM made up with the help of semiconductor

technology can be classified as ROMPROMEPROMEEPROM / EAPROM

ROM The simplest Read Only Memory called ROM is generally manufactured(Programmed) at the industrial site where it gets manufactured. The ROM is produced by

providing a mask pattern over the memory grid array. Where in the memory matrix for logic one a diode is fabricated and for logic zero there is no fabrication of diode.

Thus a ROM is programmed only at the time of its manufacturing and cannot bealtered with its content by any other device or software.

PROM The Programmable Read Only Memory is a technology step ahead of ROM.Where the memory matrix is provided with all intersection filled up by diodes. Thus a

blank PROM carries all ones at all locations. The user can program this memory onlyonce at site. To do so, the respective address is generated and the data lines are providedwith some voltage pulses (Typically 12 to 18.5 volt). The bit where a zero is needed to bewritten, a voltage pulse is passed. This action blows up the intersecting diode of theselected data line and selected address. For a logic one no voltage pulse is provided. Thesequence of writing zero at various locations blows up or burns up the respective diodesand hence the process is called burning of ROM. This burning is possible only ones i.e. if a zero is written, the grid position is can never been altered with, thus a PROM isProgrammable once.

EPROM The PROM suffers from a drawback that it can be program only once and if some data is to blown up than it is not possible to revert it and a new chip is needed for every data modification .To overcome this the PROM was extended with an technologyadvancement comprises of special semiconductor transistor that can be programelectrically (logic 0) and can be erased by ultra violet rays (writing logic 1), This memoryhas a capability that it is reprogrammable. Thus the programming is carried outElectronically Programmable Read Only Memory.

The EPROM also do posses a drawback that a single correction is needed thatthen entire chip is needed to be erased and reprogram which is time consuming job. Alsothe erasing of chip requires at least 20 minutes.(NVRAM Non Volatile RAM, Mean Time Between Failure (MTBF) is 11 years).

E2PROM / EAPROM The Electrically Erasable Programmable Read Only Memoryalso called Electrically Alterable PROM has an advantage that the erasing of the chip can

be done electronically as well a single location can be erased at one time. This technologygives more flexibility of programming and also is a time saving process. Again the chipcan be erased or program on code i.e. not possible in other chips.

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18/03/2005 Magnetic Memories:-

The memories that are built up with the help of ferrous material where the data isstored in form of magnetization of particles are term Magnetic Memories. The essence of magnetic memory is the magnetization of particle where either magnetization represents

logic. The working principle of magnetic memory is based on thumb rule of electromagnetism. They are

(1) A moving or charging electric field produces magnetic field.(2) A moving or charging magnetic field or produces electric field.

In short E B and these fundamental thumb rules are used for writing and reading over magnetic memory.

1. WRITE OPERATION Consider a non ferrous surface coated with fine powder of ferric material. We have a non-magnetized particle situation that is themagnetization of particle is available in scattered form that doesnt represent anylogic. Refer Figure 1.

Now considering a coil over this material, if we pass the current through the coilin counter clockwise direction than due to induced magnetization the particleunderneath will be magnetize to right hand side. Similarly, if the current is passedin clockwise direction the magnetization of particle underneath will be towardsleft hand side. This magnetization can be retained for a very long period and is

basis of magnetic memories.The magnetization done in either direction can be considered to represent

logic. For example if left magnetization is 0 logic than the right magnetizationwill be logic 1 and vice-versa.

Thus by charging the direction of current in the R / W coil the passing particles can be magnetized to hold the binary information.

2. READ OPERATION Reading from magnetic memory is just the reverse process of writing. To do so we provide a constant current through the Read/Writecoil in one fixed direction keeping a current value constant. This is called biascurrent. When the magnetized particle passes under this coil then the movingmagnetic field produces an induced current opposite to the magnetic of the

particles. Thus the bias current varies by a factor of i, where i is proportionalto the logic that was written. This variation is in bias current ban be sensedthrough an amplifier that provides a relevant logic voltage level and hence readout is carried.

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FLOPPY DISK Floppy disk also called magnetic disk is one of the prominent portable magnetic media.

The Floppy Disk is a Direct Access Storage Device (DASD). Figure shows a typicalFloppy Disk. It comprises of a protective jacket comprising of cleansing media and aMylar disc, the medium over which the data is stored. The jacket of the floppy disk is

provided with many cuts and holes. They are (1) A centre hub This hole is used by the spindle mechanism that allows the

disk to be gripped between centering hole such that the spindle motor rotatethe disc. The disc rotates at a constant speed of 360 RPM.

(2) Index hole The index hole is a provision for keeping the disc rotating atconstant angular velocity. The index hole is sensed by a light sensor pair withreference to which timing signals is generated and over the signals correctionsare made out to keep disc rotation constant.

(3) R / W notch This notch is used by the R / W head such that the linear moment of R / W head can access the track passing underneath.

(4) Write protect notch This notch enables or disables the write permissionover the disk. It is sensed a light sensor of the disk mechanism. If it permitslight, the write operation is allowed else it is denied.

(5) Aligners These are very small slots on the top of the disk that fits to thedrive mechanism holders such that the protective jacket remains stable whilethe disc is rotating.

Cleansing Pads These are special pads pasted at the inner side of the jacket whichkeeps the rotating disc free from dust and debris.The Mylar disc is coated with very fine powder of magnetic material. When the disk isformatted then it is logically divided into concentric circles called tracks. Where further each track is divided into equal sized parts called a sector. A sector carries unit of information and typically it is 512 bytes. The typical storage capacities are 160 K, 320 K,640 K, 720 K, 1.2 MB, 1.44 MB etc.

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19/03/2005 MAGNETIC TAPE

Magnetic tape is one of the most widely used auxiliary devices (back up) used for storingthe information. They are assumed to be most reliable media so far. A magnetic tape

comprises of fine plastic tape coated with magnetic material. A magnetic tape is calledsequential access storage device i.e. to read the k th record out of N records we require to

pass through (K-1) records.

Figure shows a typical snap shot of magnetic tape. Some prominent logical unitsof tape are

(3) SOT The Start Of Tape is a special marks when passes under read head indicates the tape has started.

(4) EOT The End Of Tape is again a special marker indicating thefinish of tape such that the drive mechanism can be stopped after sensing it or a visual indication can be produced.

(5) IBG The Inter Block Gap is a delegate space paste between tworecords that provides a settle time between two block accessoperations.

Block A block is basic unit of magnetic tape that holds data. The block is alsoencapsulated between special entries called

(1) SOB (Start Of Block)(2) Header (3) Footer(4) EOB (End Of Block)

The inner most portion of a block is called data area that carries one unit of information.

Typically it is 512 bytes. The data area can be unit track or multi track type.

SOB The Start Of Block is a special marker that indicates read head that a block isgoing to start.EOB The End Of Block marker indicates that the block has passed.Header The header entry is a Meta information block that holds the information aboutdata area. Some of the prominent entries of header are

1. File name2. File size3. The number of blocks occupied4. The current block number

5. Current Block size6. Current block data value7. Time and date of file creation8. Time and date of last modification etc.

Footer The footer comprises of error detection and correction code for the respective blocks.

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MAGNETIC DRUM It is one of most oldest storage media that uses magnetic technology for data storage. Amagnetic drum is built up with the help of a hollow aluminum cylinder coated with finemagnetic material. During the manufacturing. The cylinder is provided with 3 specialtracks called control tracks with reference to which R/W operation are synchronized.These are:-

1. MTT The Master Timing Track also called rotation identifier comprise of only one identification spot. Such that when it passesunderneath a control sensor, a mater pulse is generated.This pulse is used to indicate finishing of one rotation and startof another.

2. STT Sector Timing Track comprises of several equidistancemagnetic spots that are used to divide and identify the sector of the drum. When a sector timing indicator (spot) passesunderneath the control than it indicates finish of one sector andthe start of another.The STT spot coinciding MTT indicator indicates the first sector

starts.3. BTT The Bit Timing Track is a clock generator track comprising of several spots within the sector range. When thesespots are sensed by control circuit generating clock withreference to which read or write operation is carried out.

Other than the above defined tracks the cylinder is logically partitioned into data tracksthus in a 2-D view we have mesh (grid) structure comprising of row as sector and columnas track. The cell formed due to this intersection is called data cell and also sector thatholds one unit of information. The angular momentum or rotation of cylinder places asector underneath R/W head. Whereas the longitudinal momentum of R/W head accessesa track.

Timing diagram

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31/03/2005 Memory Hierarchy

A computer system basically a triad comprises of CPU, Memory and Input/Output. Dueto various theoretical and practical aspects the memory is divided into various componenttypes each dedicated for specific purpose constituting a memory hierarchy. In other words the memory of a computer system is define as a hierarchy structure stating various

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label of memory components according to their usage. Figure illustrates a typicalmemory hierarchy comprising of following components 1. Register 2. Cache3. Primary Memory

4. Secondary Memory5. Auxiliary Memory

Registers It is the fastest memory component of the computer system running at thespeed of CPU itself. All the instructions of the program are executed with reference tothese registers. The registers are also the smallest memory component of the hierarchyand thus are the costliest one.

Primary Memory The memory that is the directly addressable by the CPU is termed a primary memory. The primary memory is in nature is a volatile memory structure and itholds all the processes that are in execution needs the execution or has been executed.

The normal instruction execution takes place between primary memory and the CPU. Thesize of primary memory varies from 10 Kilo Bytes to maximum of bytes and dependingon the CPU addressing capacity. The primary memory speed is 1/3 rd to 1/4 th of the CPUspeed.

NOTE: Generally the primary memory speed is referred to as front side bus.Since the speed of primary memory is a bottle neck with reference to the

computational speed and hence an intermediate memory called Cache memory is bridged between the CPU and the primary memory and the Cache memory thus, acts as ledgewire between the two enhancing the computational speed.

Cache Memory An analysis done over thousands of program has given a result that atany given point of time the instruction requirement for execution is in a close viscidity of the current instruction and is termed as Locality of reference. This phenomenon has led tothe development of cache memory. Thus the cache as an intermediately pre fetches theinstructions from primary memory and supplies them to CPU for execution increasing thesystem true put (output). In general, the cache memory is available as L1 cache and L2cache. L1 is normally embedded inside the CPU whereas L2 is the external one.

The above specified memories suffers from two drawbacks 1. They are very limited2. They are volatile

Thus, to hold the softwares we require some permanent memories that are large and non-volatile in nature. Typically they are called Secondary memory and Auxiliary memories.

Secondary Memory The memory not directly under the control of CPU insteadrequires a separate processor for date handling and that is of non-volatile nature is calleda secondary memory. Typically hard disk or under this category and most general mediaused for this purpose.

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Auxiliary Memory The memories permanently in nature other than the secondarymemory used for data backup for data portability are termed auxiliary memories. CDROM, DVDs, Magnetic Tapes etc. falls under this category.

Hierarchy Description

As we move from top to bottom along memory hierarchy. The size increases as wellwhen we move from bottom to top, the speed and cost per bit increases.

Computer follows the following steps when system started

15/04/2005

VIRTUAL MEMORY:-

o Virtual Address (Address Space)o Physical Address (Memory Space)o Pageo Block o Page Faulto Thrashing

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16/04/2005In multiprogramming systems there are many programs running simultaneously in thegiven system. Due to the limited physical memory it is sometimes not possible toaccommodate all the programs or if a program is too large it may not be accommodatedcompletely in the primary memory. To overcome this situation we use a concept, a part

of memory management scheme called the Virtual Memory.Virtual Memory is a concept where the secondary memory is imitated to act as primary memory. Where the user is given and ill user that he / she is having a very large primary memory at disposal although practically it is not or in other words using thesecondary memory storage in form of primary references is term Virtual Memory.

In Virtual Memory concept, the address generated by a program is termed virtualaddress and a collection of virtual addresses constitutes an address space. Similarly theaddress of main memory is referred to as physical address or a location and a collectionof locations is called memory space.

Implementation:The Virtual Memory Manager is provided with some segment value, typically of size 1K.

This segment value becomes the basis for primary and secondary memory division. The primary memory segments are typically terms Blocks whereas the secondary memorysegments are termed Pages.

Thus a Virtual Memory System comprises of set of Pages and set of Blocks. Thenumber of pages are always muck greater then the number of blocks but the system givesillusion that the primary memory is available as the total pages size where actually it isavailable as total block size.

Memory table for mapping a Virtual Address

04/05/2005

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Virtual Memory Address Mapping:

Figure illustrates a typical mapping of virtual addresses to actual addresses. To performthe mapping operation the virtual memory management scheme requires a memory

mapping table, typically called memory page table that comprises of page entries whereevery page entry is associated with a presence bit and the block address. A 1 in presence bit is an indication that the page is available in one of the block where the block value can be found by accessing the block entry. The size of memory page table is equivalent to thenumber of pages created whereas the block entry size is equivalent to the number of

block bits. The presence bit is a Boolean value.When a virtual address is submitted by the CPU for accessing a location, the

address is transferred to memory mapping table, if the presence bit is 1, the respective block address is generated and if the presence bit is a 0 then a page fault is indicated.Eventually all the processing are stop and the page fetch algorithm (along with pagereplacement) is called and the requisite page is brought into one of the block.

In virtual memory system if page fault occurrences are too high then the phenomenon is called Thrashing that leads to a lower throughput.

Figure 2 illustrates a typical example of virtual memory. Here we consider 8K AddressSpace and 4K Memory Space with the segment size of 1K. thus we have 8 pages labeledPage 0, Page 1, , Page 7 and we have 4 blocks Block 0, , Block 3. Thememory page table thus comprises of 8 entries, where the page number is used to accessthe table entry. Each table entry comprises of two bit block value (since there are 4

blocks) and one bit presence bit. The virtual address generated by CPU is divided intotwo parts as page number of three bits and line number of 10 bits (1K=10 Bits) when anaddress is generated, the most significant 3 bit are used as table address, the memory

page table is reference, if the presence bit is found 1, the respective block bits are prefixed to the line number generating the physical address, with reference to examplePage 0, Page 3, Page 4 and page 7 will cause Page Fault.

Associative memory:C-- -A- --M -AT

1. CAT 1 1 0 12. MAT 0 1 0 13. RAT 0 1 0 14. CAR 1 1 0 05. CAD 1 1 0 0

6. CAM 1 1 1 07. RAM 0 1 1 08. MAD 0 1 0 09. MEM 0 0 1 010. CAP 1 1 0 011. RED 0 0 0 012. ROM 0 0 1 0Cache Memory:

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05/05/2005

One of the bottle-neck of computer systems in achieving high speed performance is theCPU-Memory speed mismatch. Generally this ratio is 1:3 i.e. the speed of primarymemory is almost 1/3 rd the speed of CPU. This speed mismatch thus leads to poor

response time of the program under execution. This speed mismatch can well becompensated by incorporating an intermediate memory called Cache Memory betweenthe CPU and the primary memory. The Cache memory acts as a reservoir between the

primary memory and the CPU increasing the response time of the program. Since cachememory die-casted along with the CPU and hence it approaches the speed of CPU. Theconcept of cache memory comes from a phenomenon called Locality Of Reference whichstates that given a program if we are executing instruction at line number X then some K instruction will be in viscidity to that s.t. those will be executed after current instruction.Keeping this concept in mind, prior to execution of instructions, a block of instruction isfirst transferred from primary to cache where over the content of cache CPU executes andmean while the cache controller fills up the cache. The process continues and thus anincrease in program performance is achieve (Here performance is measured as executionspeed).

The cache memory thus is similar to the concept of virtual memory. During theexecution of an instruction if a memory word is referenced by the CPU and if it isavailable in cache, it is called a HIT whereas if the desired word is not found it is called aMISS. The performance of cache is measured in form of HIT Ratio, where it is defined as

HIT Ratio = Number of HITS / (Number of HITS + Number of MISS)

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Page replacement policies:

Example 1

FIFO (First In First Out):

1* 3* 1 2* 5* 0* 1* 7 6* 5* 6 3* 1* 0* 2* 5* 7*

Block 1 11 04 03 02 01 54 53 52 51 24 23 22 2 32 31 14 13 12 11 34 33 32 31 54 53

3 23 22 21 74 73 72 71 14 13 12 11 74

4 54 53 52 51 64 63 62 61 04 03 02 01

LRU (Least Recently Used):

1* 3* 1 2* 5* 0* 1 7* 6* 5* 6 3* 1* 0* 2* 5* 7*

Block 1 11 12 11 12 13 14 11 12 13 14 15 31 32 33 34 51 52 2 __ 3 1 32 33 34 01 02 03 04 51 52 53 54 01 02 03 04

3 __ __ __ 2 1 22 23 24 71 72 73 74 75 11 12 13 14 71

4 __ __ __ __ 5 1 52 53 54 61 62 61 62 63 64 21 22 23

Example 2

FIFO:

4* 2* 0* 1* 2 6* 1 4* 0 1 0 2* 3* 5* 7*

Block 1 41 64 63 62 61 54 53 2 22 21 44 43 42 41 74 3 03 02 01 24 23 22 21 4 14 13 12 11 34 33 32

LRU:

4* 2* 0* 1* 2 6* 1 4* 0* 1 0 2* 3* 5* 7*

Block 1 41 42 43 44 45 61 62 63 64 65 66 21 22 23 24

2 __ 2 1 22 23 21 22 23 24 01 02 01 02 03 04 71

3 __ __ 0 1 02 03 04 05 41 42 43 44 45 31 32 33 4 __ __ __ 1 1 12 13 11 12 13 11 12 13 14 51 52

Example 3

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Pages are 8, Blocks are 3 given the sequence8 1 2 3 1 4 1 5 3 4 1 4 3 2 3 1 2 8 1 2

Perform FIFO and LRU replacement policies.

FIFO:

8* 1* 2* 3* 1 4* 1* 5* 3* 4* 1* 4 3 2* 3* 1 2 8* 1* 2*

Block 1 81 33 32 31 53 52 51 13 12 11 83 82 81

2 1 2 11 43 42 41 33 32 31 23 22 21 13 12

3 2 3 22 21 13 12 11 43 42 41 33 32 31 23

LRU:

8* 1* 2* 3* 1 4* 1 5* 3* 4* 1* 4 3 2 3 1 2 8* 1 2

Block 1 81 82 83 31 32 33 34 51 52 53 11 12 23 21 22 23 21 22 23 21

2 __ 1 1 12 13 11 12 11 12 13 41 42 41 12 13 14 11 12 13 11 12 3 __ __ 2 1 22 23 41 42 43 31 32 33 34 31 32 31 32 33 81 82 83

06/05/2005

Writing into Cache:In a cache organized CPU, a variable is available at a location in cache as well as it isalso available in primary memory. If the CPU accesses this variable from cache and

modifies it in accordance with some instruction then there is an ambiguity in values of variable between cache and primary memory. Thus we require to update the primarymemory by the content of cache to maintain the data consistency. The technique of modification is typically called writing into cache. There are two fundamentalapproaches

1. Writing Through Cache2. Writing Back Cache

1. Writing Through Cache In write through cache technique, as the variable ismodified, it is simultaneously modified in primary memory. This techniquesuffers from a draw back that every time when variable modifies, a memory write

is perform that decreases the through-put of the system or slows the execution of program. Whereas the advantage is that the data value remains consistent.2. Writing Back Cache In this approach the cache variable words are associated

with a special flag called a Dirty Bit such that when the cache variable ismodified, this bit is set. The variable modifications are perform only in the cacheand when the variable is no longer needed or is needed to be swapped out then thedirty bit is checked and if found set, the content of primary memory are over written. This method although perform a better performance regarding

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The Cache Memory Management is one of the strongest requirement for CacheOrganized CPUs. A management of cache in proper way enables the system to providefaster responses in terms of program execution. There are three fundamental mappingtechniques used for cache management. They are

1. Associative Mapping 2. Direct Mapping 3. Set associative mapping

1. Associative Mapping : The associative mapping is the most easy cachemanagement technique. It fundamentally requires that every cache location must

be written with two values (a) The address of primary memory at which data lie.And(b) The data value at that address in the primary memory.

Figure 1 illustrates the associative mapping of a cache organized CPU. Here every cachelocation is of size 27 bits, where first 15 are used to identified the address and the

remaining 12 provides the data value. To access a word from cache, an argument register is used that consist of a size equivalent CPUs addressing capacity. When the CPUgenerates an address, then the address bits are transferred to argument register thatsuccessively is used in form of a comparison register with every cache location. If amatch is found a HIT is generated and the data part is moved to CPU. If a MISS is therethen the word is brought from primary memory.

The advantage of this technique is its simple approach of implementation but do suffersfrom two major draw back

(i) Every cache location size must be equal to primary memory (MAR + MBR)size.

(ii) Before declare a MISS the entire memory is needed to be check that wastes aconsiderable amount of time. Leading to low through put.

2. Direct Mapping : Direct Mapping Cache Organization comprises of a Tag bitentry where the address of cache location is used as an Index. Combining the Tagvalue and Index (Address) of cache, the primary address can be generated. Theadvantage of this technique is faster search. By simply moving to an Index usingHash function and determining the Tag we can directly confirm the availability toword. If available HIT is generated else a MISS is produced and respectivehandling procedures are called.

The advantage of this technique is faster search with a draw back that if the indices of two words are same then only one of them can reside in cache thus a conflict handlingmay be needed in swapping of common index word.

The drawback of direct mapping, the conflict of indexes can well be removed byextending the capacity of cache location such that it can occupies two words at the sameindex with different Tags. This organization is topically term Set AssociativeOrganization and is an important its predecessor enhancing the computability of thesystem.10/05/2005

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CD ROM (Compact Disc) / DVD (Digital Versatile Disc) CD Capacity

- 640 MB- 700 MB

DVD Capacity DVD 5 4.7 GB SSSL (Single Side Single Layer) DVD 9 8.5 GB SSDL (Single Side Double Layer) DVD 10 9.4 GB DSSL (Double Side Single Layer) DVD 18 17 GB DSDL (Double Side Double Layer)

1.2 mm. Thickness and 12 cm. Diameter for CD ROM.

A B CWhere, For CD = 150 Kb/s (Kilo bits / second)

For DVD = 1350 Kb/s (Kilo bits / second)A = Write SpeedB = Rewrite SpeedC = Read Speed

For CD Red Book (Audio)Yellow Book (Any Data Audio + Data)Orange Book (Mixed Audio + Video + Data)

LASER L ight Amplification through Simulated E mission & R adiation.

Audio CD works for 44.1 KHz PCM (Pulse Code Modulation).TAO Track At OnceDAO Disc At Once

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12/05/2005

Compact Disc Read Only Memory called CD ROM is an optical media widely usednow a day for storing of data, pictures, video etc. The CD ROM data storage followsthree fundamental standards called Red Book, Yellow Book and Orange Book standards

layed out for different type of data representation.A Compact Disc is now available in Re Writable mode also and is typically

called CD RW. The physical dimension of disc is Size (1) diameter,(2) 1.2 mm. thickness.

The standard data storage capacities are 640 MB (72 Minutes), 700 MB (80 Minutes).

Figure illustrates a typical cross section of a CD ROM. At top it is provided with labelfollowed by a reflective coating also called recording surface of the disc. In earlier timesthe reflective coating was metallic, whereas now a day it is dye paste. It is followed by

plastic typically polycarbonate material that gives the disc its strength as well as it provides protection to the recording surface. The data over disc is recorded in form of LANDs and PITs, where a LAND represents logic zero and PIT to LAND & LAND toPIT transition represents logic one. Several other data encoding method for writing

binary information are also available.

WRITING: A high watt laser beam is used to write-in the data over the disc. Theconcentrated laser beam deforms the metal of the disc writing the desired information.Thus by providing switching the data can be burned onto the disc. This is called disc

burning.

READING: Reading from CD ROM is the reverse of writing. A low watt laser is madeincident onto the disc where upon a LAND truly reflects it and a PIT refracted it. Thisreflection is read by a light sensor and binary interpretations are made accordingly.

The speed of CD ROM is measured by a factor , where the value of isstandardized as 150 Kilo bits per second. The speed of CD Re Writers are depicted asA- B- C, where A represents fresh writing speed, B represents the rewrite speed andC the read speed.

DVD The Digital Versatile Disc loosely spoken Digital Video Disc is an enhancementto CD ROMs with same disc parameters a DVD can hold high amount of data. Thestandard DVD versions are

DVD 5 4.7 GB SSSL (Single Side Single Layer) DVD 9 8.5 GB SSDL (Single Side Double Layer) DVD 10 9.4 GB DSSL (Double Side Single Layer) DVD 18 17 GB DSDL (Double Side Double Layer)

The measures in DVD is 1350 Kilo bits per second.

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Hard Disk Drive (H.D.D.):

SCSI (Skuzzy) Small Computer System InterfaceIDE Integrated Drive Electronics (Hardware)

Integrated Development Environment (Software)PATA Parallel Advanced Technology Adapter SATA Serial Advanced Technology Adapter 14/05/2005

Sessional (13/05/2005)Question: Explain the page fault comparisons, giving reasons.

Answer: In virtual memory concept regarding page replacement techniques it is not necessary that if we increase thenumber of blocks then the page fault decreases on the contrary the page fault may increases. This typically calledBaladies Anamoly.

12/05/2005

A Hard disk also known as Winchester disk is one of the prominent mass storagesecondary device. The principle and working of recording and playback over hard disk issimilar to that of a floppy disk.

Figure illustrates a typical hard disk drive internal view. It comprises of a stack of aluminum plates coated with magnetic oxide on both side and thus the name hard disk.The stack of disc shares a common spindle i.e. connected to high RPM (Rotation Per Minute) motor by which all the disc rotates simultaneously at approximately in a range of 4000 to 10000 RPM. Every plate of the hard disk is associated with two Read Writeheads, one for each side and thus for an n plate disc there exist 2n Read Write heads.

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All the heads moves simultaneously back-and-forth and accesses various sectorsat the same time. The group of sectors accessed at the same time constitutes a cylinder.

Generally the hard disks are available with parallel wire and are typically calledATA (Advanced Technology Adapter) drives. Now a days high speed serial drives are

available and are called SATA drives. The storage capacity of hard disk varies from fewMBs to GBs and may be in future to some TBs (Tera Bytes).

VDU (Video Display Unit)

The Video Display Unit is the most common default output device used for generating

the soft copy output (i.e. the most popular softcopy output device). The VDU areavailable in various sizes with different resolution.It is used with terminals connected to large computer system and as a monitor for microcomputer systems. This type of video display screen is used to allow the operator toview data entry and computer output.It comprises of two fundamental units:

1. A Cathode Ray Tube (CRT), and2. Control Circuit / Unit.

1. The CRT stands for Cathode Ray Tube, which is a glass envelope coated with a phosphorous coat over the front surface which is illuminated at several points todisplay an image.

The CRTs screen display is made up of small picture elements, called PIXELSfor short. The smaller the pixels (the more points that can be illuminated on the screen),the better the image clarity, or resolution.The CRT comprises of following components (items):

(a) CATHODE: It is an electrode that is charged negatively such that electrons areemitted from it.

(b) HEATER: It is a low power driven coils that oxide the electrons of the cathode toleave the surface generating free charges.

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Computer System Architecture

Input Output Architecture

A computer system organization is defined as a collection of component connectedtogether in a logical sense, i.e. the logical structure of a computer system is termedcomputer organization.

The collection of physical component such as CPU, Memory, I/O arranged constitutescomputer architecture. Thus the physical definition of the system is architecture.

Organization = LogicalArchitecture = Physical

TRIAD

A computer system can be defined as a TRIAD comprising of three fundamentalcomponents:

(1) The CPU (2) The Memory & (3) The I/O

These three devices communicates with each other with the help of a set of wires calledSystem Bus, where the System Bus comprises of three buses as

1. The Address Bus2. The Data Bus and3. The Control Bus.

A computer system requires an interface with the user to execute a program. Theinteraction is accomplished with the help of I/O devices. (The Input Output subsystemof a computer, referred to as I/O, provides an efficient mode of communication betweenthe central system and the outside environment).

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The I/O devices are connected to an entity called an interface (I/F) to have an interactionwith the system.

Organization and Architecture

In describing computer system, a distinction is often made between computer architectureand computer organization. Computer architecture refers to those attributes of a systemvisible to a programmer or put another way, those attributes that have a direct impact onthe logical execution of a program. Computer organization refers to the operational units

and their interconnections that realize the architectural specifications. Example of architectural attributes include the instruction set, the number of bits used to representvarious data types (e.g. numbers, characters), I/O mechanisms, and techniques for addressing memories. Organizational attributes include those hardware details transparentto the programmer, such as control signals, interface between the computer and

peripherals and the memory technology used.

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CPU Memory I/O I/F

Programmed I/O

Memory Mapped I/O

A computer system with CPU, Memory and I/O requires mapping of memory and I/Odevices such that the CPU can access them. There are two fundamental approach of defining memory space and I/O space. These are

1. Memory Mapped I/O2. Isolated I/O

1.Memory Mapped I/O

Figure shows a typical memory mapped I/O scheme comprising of (i) CPU(ii) Main Memory(iii) I/O Ports

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The device defined above shares three buses; The Address Bus, the Data Bus and Read Write signals (i.e. Control Bus). The address is assumed to be generated only by CPU,the Read Write signals are also generated by CPU.

Here the addressing range of CPU is divided into two parts where the lower partis dedicated to memory addressing and the higher order address are defined for I/O

devices. The configuration in this manner does not discriminated between memory andI/O and hence simple Read Write signals can be used to read or write both memory aswell as input output devices. Assuming 1K addressing range and 8 bit data, we have10 address lines and 8 data lines. Again the addressing is divided as 0 511 for memoryand 512 1023 for I/O. if the CPU generates an instruction Read [235] then a memorylocation is read and if a CPU generates an instruction Read [812] then the CPU reads anI/O. thus a single type of instruction can be used to access both Memory as well as I/O.

The advantage of this concept is that the architecture is simple, same set of R-Winstruction can be used to read or write both memory and I/O.

The disadvantage of this technique is that if we increase the memory addressing,the I/O addressing decreases and vise-versa. Thus for lower addressing this technique is

useful and if memory requirement is too high along with high I/O, this technique is notused.

2. Isolated I/O

Isolated I/O

A = 10 bitsMemory: 0 1023I/O: 0 1023

MR MW I/O R I/O W0 0 0 0 No Operation1 0 0 0 Memory Read0 1 0 0 Memory Write0 0 1 0 I/O Read0 0 0 1 I/O Write

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Read Memory [Address] Read I/O [Address]Write Memory [Address] Write I/O [Address]

The draw backs of memory Mapped I/O can be overcome by Isolated I/O scheme. It is

also called as I/O Mapped I/O. The figure shows a typical isolated I/O scheme. Itcomprises of CPU, Memory and I/O devices. All the three devices shares a commonaddress bus as well as data bus but the control bus can be of two types:

Type 1: Separate R-W signals for both memory and I/O.Type 2: Same R-W signals for both memory and i/O with an additional IO/M

signals to discriminate between them (Shown by dotted lines).

Here the same addressing range is available for both the memory and I/O devices.Assuming 10 bit address, the range 0 1023 is available for both memory as well as I/O.To read a memory, a read memory instruction is used where as to read I/O a read I/Oinstruction is used. Thus in this concept separate R W instruction is needed which is an

overhead in form of pins of CPU as well as in form of instruction.In other concept we have same R W instruction but we have to generate aseparate discriminates signal in form of IO/M such that when it is 1 an I/O is read or written and when it is 0 a memory is read or written.

The advantage of this technique is that a large address range is available for thecapability of CPU for both memory & I/O.

The disadvantage of this technique is large instruction is requirement or a separatesignal generator which is an overhead.

Direct Memory Access (DMA)

Direct Memory Access: The Direct Memory Access is a mechanism of transferring data between memory and I/O devices without intervention of CPU but under the control of CPU.

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Under normal circumstances called PROGRAM IO MODE, the data transfer between I/O devices and Memory is through CPU i.e. the CPU reads memory than givesdata to I/O or CPU reads data from I/O and provides it to memory. In this concept aconsiderable system time as well as the CPU time is wasted in simply transferring thedata between memory & I/O.

To speed up the data transfer and to save the system time, DMA is used. Figureillustrates a typical DMA mechanism. It comprises of three elements: CPU, Memory &DMAC (Direct Memory Access Controller).

The CPU is shown with PRORAM COUNTER: The most Special PurposeRegister (SPR) that holds the address of next location to be accessed and theACCUMULATOR: The most General Purpose Register (GPR) for reading and writingdata.The DMA Controller comprises of

1. IOAR: The Input Output Address Register used to generate the address of memory that is to be accessed.

2. IODR: The Input Output Data Register is used to read data from memory or isused to write data.3. DC: The Data Count register is a special register which holds a value of the

number of data to be transferred during DMA operation.

The CPU and DMAC are associated with two hand shake signals 1. DMA Request2. DMA Grant

DMA Transfer: Under normal circumstances the CPU access the memory. When a I/Odevices wants a transfer from memory than it generates the address in IOAR, fills the DCwith numbers of transfer required and then generated the DMA request consequently theCPU responds by generating DMA Grant signal. At this point the CPU is isolated frommemory and the DMAC gets the control of memory. The DMAC than transfer the dataand decrement the DC register. The transfer is goes on till DC is not equal to zero.

When DC reaches zero, the DMAC disable DMA Request and subsequently theCPU disable DMA Grant. The CPU then regains the control of memory and resumenormally.

CYCLE STEALING: During the DMA operation, when the DMA is transferring thedata from memory at that time if the CPU wants the memory transfer than it disable theDMA Grant signal. On receiving DMA Grant low the DMAC should disable the DMARequest but before disabling DMA Request the DMAC may transfer few bits. This iscalled Cycle Stealing.

In another concept of Cycle Stealing may transfer some bytes sensing the CPUnot accessing the memory.

INSTRUCTION: Operation Operand(s)

ADD A, B A (Operation) (Operand) A (Operation) +(Operand) B (Operation)

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0 0 ADD OPR1 / OPR 20 1 SUB Register A 0 0 01 0 AND Register B 0 0 11 1 OR Register C 0 1 0

Register D 0 1 1Register E 1 0 0Register F 1 0 1Register G 1 1 0Register H 1 1 1

Example: ADD A, B Example: AND C, D00 000 001 10 010 011

01 H 93 H

Arithmetic Logic Destination / Source

000 NOP NOP 000 Register A001 ADD AND 001 Register B010 SUB OR 010 Register C011 MUL XOR 011 Register D100 DIV NOT 100 Register E101 INR ____ 101 Register F110 DCR ____ 110 Register G111 ____ ____ 111 Register H

Instruction Format:1. Opcode2. Address field3. Mode field

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1. Single Register (Accumulator Based) One address2. Multi Register (General Register)

- 3 Address- 2 Address

3. Zero Register (Stack Oriented) Zero address

One address: ADD B(Source) : A A + BDefault destination is accumulator

Three address: ADD A(Destination), B(Source S1), C(Source S2) : A B + C

Two address: ADD A(Destination D / Source S1), B(Source S2) : A A + B

Zero address:- PUSH- POP

- ADD(On Stack)

Instruction Format: Computer program comprises of a sequence of instructionswhere an instruction is defined as a collection of operators and operand. The operatorsmay be arithmetical, logical, relational, assignment etc. whereas the operands are thevalues stored in register, memory or the value of I/O port. The way of representing theoperators and the operands with a mechanism how to access operands is termed as aninstruction format. Thus an instruction format is a sequence of bit representation wherethe bits are divided into groups called fields and the binary value of each field is definedto carry out a specific task.

For example if we consider 8 bit instruction format than 1. Two bits for operation:(a) 00 ADD(b) 01 SUB(c) 10 MUL(d) 11 DIV

2. 3 + 3 bits for any of six register and memory, i.e.,(a) 000 Register A(b) 001 Register B(c) 010 Register C(d) 011 Register D

(e) 100 Register E(f) 101 Register F(g) 110 Register G(h) 111 Register H

Thus, ADD A,B in instruction format is written as0 1

00 000 001 ADD A B

Thus 01 H becomes a code for this instruction.

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The most common fields found in an instruction format are:1. An operation code field specifying what operation to do.2. An operation field(s) specifying the address of source and destination operands.3. The MOD (mode) field that specifies the way of accessing operands.

The instruction format typically depends on the computer organization i.e., dependson the capability of CPU.A computer system may have several instructions with several instructions formats.

Most computers fall in one of the three types of CPU organization:1. Single accumulator organization.2. General register organization.3. Stack organization.

A CPU comprising of only one register called accumulator represented by A or R 0 wherethe CPU does not have any other GPR is termed a Single accumulator organization. Hereall the instruction with respect to computational tasks are executed over accumulator

only.The General register organization comprises of more than one register i.e., other thanaccumulator there are several GPRs in this kind of system there exist a flexibility of defining large instruction set increasing the computational power. For example INTEL8085 falls in this category.

In Stack organization system the CPU do not posses any kind of GPR and hence alloperations are carried out with reference the data structure called stack. This is also calledzero register organization.

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One address instruction: This instruction is available in single register organizationas well as in general registers organization. The instruction comprises of two fields only:The operation and the operand. Here the default destination is accumulator register or inother words the operation is performed over specified operand and accumulator, storeresult in accumulator.

Zero address instruction: This instruction format is exist in stack oriented system,where the operands are stored onto the stack and the specified operations are carried outover the content of stack only.

Addressing ModeThe way to access an operand in an instruction is termed as addressing mode or the way

of getting an operand (OPr) from the system memory or register to carry out aninstruction is defined as an addressing mode. The addressing mode technique provides agreater facility of accessing the operands while creating pointers indexes and relocations.The different addressing modes available are:

1. Implied addressing mode: In this mode the instruction itself is self explanatoryshowing the operation to be carried out over the operands i.e. abbreviated in instructionitself.For example CMA, complement accumulator instruction indicates that the content of accumulator is to be complemented. The zero address instruction or stack orientedinstruction also falls in this category.For example ADD, automatically adds the two top contents of stack.

2. Immediate mode: In this mode the operand is specified in the instruction itself i.e.,the operand value is part of instruction or one of the field of instruction is operand.

For example CPI 32H; MVI A, data; ANI 0FH; etc.

3. Register direct mode: In this mode the operand lie in one of the register of CPU.Thus, in this mode one field of instruction holds an address of a register.For example MOV A, B; ADD B

4. Register indirect mode: In this addressing mode the specified register or register pair holds the address of operand i.e., on field of the instruction specifies a register andthe specified register holds an address of operand.

5. Auto increment / auto decrement:

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This addressing mode is similar to that of register indirect mode accept that beforeaccessing the memory contents, the value of register is incremented or decremented

before or after wards.For example:

Let R = B

B = 06R R + 1 B = 7B ADD I [R] A A + [M] R+1 A = A + [M] 7

R R 1 B = 5B ADD D [R] A A + [M] R1 A = A + [M] 5

A ADD I [R] A A + [M] R A A + [M] 6R R + 1 B = 7

A ADD D [R] A A + [M] R A A + [M] 6R = R 1 B = 5

Direct Address Mode

Example: LDA 5900ADD 6501

The direct addressing mode indicates that the address of operand is specified as part of instruction. In other words one field of instruction comprises the address of the operand.

Indirect Address Mode

EA (Effective Address) = PC (Program Counter) + offset

In this mode the specified address field contains the address of operand indirectly, i.e. thespecified location holds the address of the operand.For example ILDA 25 indicates the location 25 contains the address of the operand.

Relative Addressing Mode

5904 : REL ADD 50 (2 bytes)5906 :

EA = 5906+50

5956

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Arithmetic Circuit: A binary parallel adder can be used to perform some fundamental

arithmetic operation over the operands. Thus, a simple arithmetic circuit can beconstructed with the help of parallel adder and by providing different inputs in form of A,B and Ci, many arithmetic operations can be carried out. Some fundamental arithmeticoperations can be obtained by a parallel adder is shown in figure

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S1 S0 Ci Output Remark 0 0 0 F : A Transfer A0 0 1 F : A+1 Increment A0 1 0 F : A+B ADD B to A0 1 1 F : A+B+1 ADD B to A with carry

1 0 0 F : A+B ADD B to A1 0 1 F : A+B+1 Subtract B from A1 1 0 F : A-1 Decrement A1 1 1 F : A Transfer A

Logic Circuit:

S1 S0 Fi0 0 I0 A^B=>A.B AND operation0 1 I1 AB=>A+B OR operation1 0 I2 A B XOR operation1 1 I3 Complement of A

Logic Circuit: A logic unit basically carries out logical operations over the content of CPU registers. The given figure illustrates a simple logic circuit created with the help of some fundamental gates and a multiplexer. The circuit accepts two inputs Ai and Bi (a bitof value A and value B) and with reference to control S1 & S0, perform a relevant logicoperations as depicted in table. When S1, S0 equals 00, the unit produces A.B output.

This one stage of the logic circuit can be repeated n number of times to carry outlogic operation over n bit data.

Arithmetic and Logic Unit

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The ALU can be constructed by simply combining the arithmetic unit along with thelogic unit to carry out the arithmetic and logic operations. Figure illustrate a typical ALUwhere it comprises of one stage of arithmetic unit and one stage of logic unit connected toa 2x1 multiplexer. The circuit now has an additional control S2 which selects one of theoperation i.e., arithmetic or logic produced at output. On whole the circuit now comprises

of three controls S2, S1 and S0 that selects a arithmetic or logic operation. The arithmeticoperation selection is also depending on the carry input Ci. The table below shows all theoperations that are carried out in the above circuit.

S2 S1 S0 Ci FUNCTION0 0 0 0 Transfer A

Arithmetic

Operation

0 0 0 1 Increment A0 0 1 0 ADD B to A0 0 1 1 ADD B to A with carry0 1 0 0 ADD 1s complement of B to A0 1 0 1 Subtracts B from A

0 1 1 0 Decrement A0 1 1 1 Transfer A1 0 0 A.B (A AND B)

LogicalOperation

1 0 1 A+B (A OR B)1 1 0 A B (A XOR B)1 1 1

Computer Instruction:

Computer instructions are normally stored in consecutive locations and are executedsequentially one at a time. In stored program concept the instruction and data are requiredto be stored in memory prior to the execution of the program. Figure shows a basiccomputer system comprising of CPU and memory. The memory is assumed 4K 16 with

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MAR equal to 12 bits (2 12 = 4096) and the size of MBR = 16 i.e., the word length of memory. The CPU is defined to have 12 bit program counter, a 16 bit accumulator associated with one bit end around carry, a indirect bit register I and a 3 bit operandregister labeled OPR.

The instruction is thus considered 16 bit where it is divided into three fields:

I : Indirect BitOP : Operation BitsAD : Address Bits

Depending on I and OPR field, four kind of instruction can be created. They are 1. DMRI : The instruction whose opcode start nibble is in range 0 6.2. IDMRI : The instruction whose opcode start nibble is in range 8 E.3. RRI : The instruction whose starting nibble is 7.4. IORI : The instruction whose starting address is F.Thus, the instruction format gives us a facility to create memory register and IO referenceinstruction. In register and IO reference the remaining 12 bits can be used in verity of ways to define different register and IO operations. In other words when we fetch an

instruction we simply first checks I bit. If it is 0 and the consecutive bits yielding 7 thenits RRI. If I is 1 and the next three bits yields a 7 then its IORI. If first bit is 0 and nextthree bits are not 111 then it is a direct memory else it is indirect memory.

Timing and Control

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F R Decoder O/P Computer cycles0 0 C0 Fetch Cycle0 1 C1 Indirect Cycle1 0 C2 Execute Cycle1 1 C3 Interrupt Cycle

A digital computer operates over a given set of instructions to accomplish a problemsolution. The instruction comprises of a sequence of micro operations that are needed to

be carried out when the instruction is executed.The unit of CPU that generates the sequence of micro operations for a given

instruction is termed timing and control unit. A simple computer system CPU comprisesof four machine cycle: Fetch Cycle, Indirect Cycle, Execute Cycle and Interrupt Cycle.

Figure illustrates a typical control unit block diagram. It consist of a control logiccircuit associated with several functional blocks generating various control functions for a given instruction. It consists of following:

1. 3 x 8 Decoder: It accepts the three bit operation code of instruction andaccordingly generate control signals q0.q7. For example, if OPr is 011 than q3 isenable.2. I : It is the indirect flip flop that accept a value from I field of instruction. If I is 1than q7 is determine. If q7 is 1 than an IO instruction is carried out. If I is 0 and q7 is 1than a register operation is carried out.3. 2 x 4 Timing Decoder: This decoder provides four clocks t0 t3, i.e., every cyclecomprises of four clocks. This decoder is driven by the sequence counter SC and by aenable flip flop S. if S is 1 than only the cycle is executed.4. 2 x 4 Decoder (Control 2 x4 Decoder): This decoder accepts F and R bits anddepending on their values generates the respective cycle as depicted in table.

C0 t0 : MAR PCC0 t1 : MBR M, PC PC + 1C0 t2 : OPR MBR (OP), I MBR (2)q'7 IC0t3 : R 1(q7 + I) C0t3 : F 1

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Fetch Cycle: It is the first machine cycle of every instruction cycle. The task of thiscycle is to fetch the instruction from the memory, to decode it and then to call therelevant machine cycle as either executes cycle or indirect cycle. The various tasks

performed in fetch cycle at different clocks are shown above. In first clock to the contentof program counter is transfer to MAR. In second clock t1, two tasks are carried out, i.e.

the program counter is incremented by one as well as the memory location is read out inMBR. In third clock t2, the I and OP fields are filled up from fetched instruction. Infourth clock t3, the design is taken to call indirect cycle or execute cycle. This design is

based on q7 and I. if q7 = 0 and I = 1 then indirect cycle is called else the execute cycle iscalled.

Indirect cycle: C1 t0 : MAR MBR (ADDR)C1 t1 : MBR MC1 t2 : NOPC1 t3 : F 1, R 0

The indirect cycle is used to fetch the address of operand. The indirect cycle receives the pointer value from fetch cycle. In the given machine C1 represents the indirect cycle. Onthe first clock of this machine cycle the address part obtained from the fetch cycle is usedto get the address of operand, it is done in second cycle. The third cycle is NOP (NoOPeration). The fourth cycle is used to call the execute cycle.

ADD to AC (Accumulator)q1 C2 t0 : MAR MBR (AD)q1 C2 t1 : MBR Mq1 C2 t2 : EAC AC + MBR q1 c2 t3 : Fetch Cycle Call

Instruction Cycle:An instruction cycle is a composition of various machine cycles. The general

machine cycles are:

1. Fetch instruction2. Decode instruction3. Fetch Operand if any4. Store results.5.

Every machine cycle in term is a composition of clocks where on each clock microoperations are carried out.

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Calling an executive interrupt service routine:Once the interrupt is identified the CPU saves the content of register onto the stack,transfer the control to ISR, disable interrupts, and services interrupt enable the interruptand reload the saved register values and contents.

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PRINTERS:The computer system output can be obtained in a form of soft copy or a hard copy. Thevideo display unit is a soft copy device whereas a printer is a hard copy machine. Printersare broadly classified into two categories as

1. Impact Printers

2. Non Impact PrintersThe printers that uses hammer like mechanism to print the character or image over amedia such as paper are called Impact type printers whereas all other printers fall in Non-Impact categories.Both Impact and Non Impact printers can use fully formed character technique or the bitmapped technique. The fully formed characters are initially type caste in foundry andtheir size, shape and printing characteristics cannot be changed during printing processwhereas bit map characters are formed with the help of collection of dots and hence can

be printed in various types, sizes etc. during the printing.The advantage of fully formed character printing is that it is much faster as compared tothe Bit mapped type because it requires only one hammer stroke to print the complete

character whereas it requires 10s of hammer strokes to print Bit map image.

Impact Printer:

The Impact printer uses a hammer mechanism that is constructed with the help of aspring loaded solenoid comprising of a firing pin. When current is passed throughsolenoid the firing pin moves forward and strikes over the character that is printed over the media with reference to the carbon in between.

The Impact printer has a greatest advantage that it can produce multiple copies atthe same time.

Dot Matrix Printer (DMP):

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The Dot Matrix Printer is the most general purpose Bit image Impact type of printer.DMP are available in two general forms called 80 columns and 132 columns width with a

print head specification of 9 or 24 pins. The print head pins are associated with miniaturesolenoids to which when a current is given, the pin strikes to the ribbon underneath that

produces a dot over the printing media. The Bit map image of the character is provided to

print head with displacement of head.The speed of a DMP is measured in CPS (Character Per Second). Since it is a Bitmap printer it can produce various style of characters and is the cheapest hardcopydevice.

Figure shows a typical DMP mechanism. It comprises of a roller over which the paper moves with the help of a tractor mechanism. A stepper motor drives this roller. The printing media rolls on this roller with respect to the pressure roller. The print headmoves horizontally back and forth where the firing pins are strike to print the desiredoutput. After every print of the line the roller is moved by respective displacement.

Daisy Wheel:

Daisy wheel is one of the oldest fully formed character type impact printer. The worddaisy comes from daisy flower where the character wheel is used for printing. The arms

of this wheel comprises of metallic embossed characters to which when hammer strikes,transforms the carbon from ribbon to paper of same character that is the character is printed. The rotary mechanism is in conjunction with the character to be printed thatrotates clockwise or counter clockwise in accordance with the current position of wheel.The disadvantages of this printer are:

(a) The printing speed is too slow.(b) To have different style of characters the wheel is

required to be replaced.

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character value. To print a line the character positions are calculated and with referenceto the drum rotation the respective column solenoid is emprise which prints the character.The example is given.

This printer is one of the slowest printers and the speed is measured in PPM(Paper Per Minute).

Chain / Band Printer:

It is a fully formed impact type printer where the characters are embossed over a chainand are strike by a solenoid or hammer to print a character. It is one of the cheapest

printers with draw backs that if the font is required to be changed the chain or band isrequired to be replaced. The printing speed is too slow and printer makes considerablenoise.

Inkjet Printer:

For color inkjets = CMY (Cyan, Magenta, Yellow)The inkjet printer is a non impact bit mapped image printer and comprises of an ink filled cartridge as shown in figure, consisting of print head made up of matrix of finenozzle smaller than a human hair. Every nozzle is associated with a resistor such thatwhen the resistor is heated the ink of that nozzle oozes out in form of droplet from the

nozzle and strikes to the paper underneath forming a dot. A collection of dots are produced over the paper to get the desired image.

The color inkjet printer comprises of three separate color tanks filled withsecondary colors Cyan, Magenta and Yellow that constitutes to form various colors andshades of the image.

Some higher quality printers do possess a black tank for fine printing. Theresolution of print is measured in DPI (Dots Per Inch) and printing speed is measured inPPM (Page Per Minute).

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Laser Printer:

- Cleaning of the OPC- Conditioning of the OPC- Electro statically writing image on OPC drum- Developing image- Transferring image on paper - Fusing image on paper.- OPC organic photo conductive.

Laser printer is one of the best printers that is available for providing hard copy output. Itis a bitmapped image type of non impact printer. The images in the laser printer arewritten with the help of a laser beam generated from a laser diode over an OPC drum, theorganic photo conducting drum.The laser printer mechanism is quite complicated and consists of several units that arecontrolled electromechanically.The printing mechanism or image formation process consists of six steps

(1.) Cleaning of the OPC drum Before transferring image to the OPC drum surface,the surface needs to be cleaned and prepared. The residual physical components of toner are removed by rubber cleaning plate. Whereas the surface of drum is electro staticallycleaned by erased lamps.

(2.) Conditioning of OPC This process uniformly charges the surface of drum at a potential of 600 Volt.

(3.) Electro statically writing In this process a laser beam is focused over the surfacewith the help of a scanning mirror as shown in figure. The points at which laser strikesare discharged and are at a potential of 100 Volt (i.e. the points are not to be written are

provided by laser).

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(4.) Developing image The electro statically written area of the OPC drum is passedthrough a positive charged toner (ink), fine powder of carbon. These toner particles areattracted over the highly negative surface forming an image over the drum called imagedevelopment.

(5.) Transferring image on paper The developed drum is then passed with a paper charged at high positive potential such that the toner particles of the drum are transferredto the paper.

(6.) Fusing image on paper The paper with transferred image is passed through hardrollers heated at constant temperature that milts the toner over the paper forming therequisite image.

The paper is then discharged by a discharge circuit and a printed paper is ejected.For next printing same steps are repeated.

Laser printers printing speed is measured in PPM (Paper Per Minute) and theavailable resolutions are 300, 600, 1200 and 2400 DPI (Dots Per Inch).

Plotter:

Plotter is one of the most general purpose device used to produce maps and large graphs.A plotter comprises of a set of cross sectional arms called Y Arm and X Arm. The X armmovement is over the Y arm and a pen is associated with X arm that moves it back and

forth. The pen is associated with a electromagnet when emprise plots the point over the paper.

The images that are drawn over the paper are generally vector type of images and plottersare not advisable for raster images or bit mapped images.

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Similarly the adder circuit can be obtained for lower bit values but as the number sizeincreases, 3 bits each then carry propagation takes place. Thus refinement of circuit isneeded. This can be accomplishing using a generalized mechanism as depicted in figure.Where we have all Full Adders associated with AND Gates.

BUSES:

USB Uninterrupted Serial Bus IDE Integrated Drive ElectronicsAPIC Advanced Programmable Interrupt Controller FSB Front Side BusSCSI Small Computer System Interface AGP Accelerated Graphics Port

Figure 1

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Micro Programming

Micro programming is one level lower then the machine language, prior to implementingthe actual control unit inside the CPU or the microprocessor. The control unit issimulated i.e. the control memory configuration is generated into a ROM, all the

instructions are checked against their control words are debug and if errors are found thenthey are removed. Once the simulated ROM succeeds then control memory isimplemented in the microprocessor.

A micro program control unit has several advantages over Hard Wired control unit. Theyare

1. Structured A micro program is always a structured constructs because every micro program is a sequential entity and hence the tracing of a micro program is easy. Whereasa Hard Wired control unit is a sequential as well as combinational circuit which has manygates and hardware entities, hence tracing of a hardwired program is very tough as

compare to micro programming.

2. Maintenance It is easy to maintain a micro program as compare to Hard wiredcontrol unit because of the fact that the hard wire consist of large number of gates andhence it is difficult to debug it in case of an error occurrence, also the circuit requires to

be tested timely and hence hard wired control unit are the circuits that has muchmaintenance value.

3. Size Since the micro program control unit consist of memory only thus it size is verysmall as compare to the hard wired control unit i.e. made up with the help of severalintegrated circuits.

4. Power Consumption A micro program control unit memory has less number of components as compare to the hardwired control unit and hence the micro programcontrol unit consumes much less power as compare to the hard wired control unit.

5. Adaptable to changes It is very difficult to rewire the hard wired control unit, if anew instruction is to be implemented or a change in instruction is required. Whereasmicro program control unit requires only addition of memory for enhancement.

6. Expandability The number of instruction in a micro program control unit can beincreased simply by adding more memory whereas the hard wired control unit requires

circuit reconstruction and re-fabrication.

7. Economic The number of gates requirement in a micro program control unit is veryless as compare to hard wired control unit and thus the micro program control unit ischeaper.

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Subsequently at t4 the source invalidates data.Both the above said methods suffers from a drawback that there is no confirmationexistence between the units that the data has been received / transferred / acceptedcorrectly because neither of the unit has a confirmation signal. It is only an assumptionthat during time t3 t2 the data will be accepted.

2. Handshake Method The handshake method of data transfer overcomes thedeficiency of strobe method with a confirmation that the data is transferredsuccessfully. To do so the circuit requires an arrangement of two back-to-back signals between the communicating devices. The transfer mechanism realize of these signals typically called the handshake signals. Conventionally there are twohandshake methods

(i.) Source initiated & (ii.) Destination initiated.

Source initiated transfer

Figure 1 depicts the block diagram of Source initiated handshake. Figure 2 illustratesits timing diagram and Figure 3 is the flow chart for the same.The handshake signals are labeled

(a) Data Valid (DAV) from source unit to destination unit.(b) Data Acceptance (DAC) signal from destination unit to source

unit.

The handshake transfer is defined as Source places data on data bus.Source unit generates DAV signal.Destination receives data and its response generates DACsignal.Source disables DAV signal.Source invalidates data.

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Destination disables DAC.

Destination initiated transfer

Figure 1 depicts the block diagram of Destination initiated handshake. Figure 2illustrates its timing diagram and Figure 3 is the flow chart for the same.The handshake signals are labeled

(a) Data Valid (DAV) from source unit to destination unit.(b) Request For Data (RFD) signal from destination unit to source unit.

The handshake transfer is defined as (i.) Destination generates a signal to accept data or enables

the RFD signal.(ii.) Source unit place the data on bus and enables DAV

signal.(iii.) Destination receives data and disables the RFD signal.(iv.) Source disables DAV signal.(v.) Source invalidates data.

Nested Interrupt

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Conventionally when ever interrupt occurs then before calling ISR, system calls aninstruction called Disable Interrupt (DI) and after the execution of ISR the system againenable interrupt i.e. during any ISR service system blocks any other interrupt occurrence.This phenomenon can be hazardous one for certain situation. For example if RTCinterrupt comes then under any circumstance it must be reciprocated. Thus a need of

nesting of interrupts comes into consideration.In the concept of nesting, when an interrupt occurs the system blocks all the lower priority interrupts to occur while all the higher priority interrupts are available in thesystem such that during ISR if a higher priority interrupt occurs then it is servicedimmediately and then the current interrupt service is finished. The depth of higher

priorities can go up to any level causing a Nested Interrupt Sequence.

Bus Scheduling Given a system of components as CPU, Memory & I/Os shearing a common bus, theremay be a requirement of giving the bus control by one or more device at a given time.Under this given situation we require to have a scheduling mechanism such that the

consistency of the system is maintained. To do so we require having a bus schedulingmechanism. Fundamentally there three such mechanism

(1) Daisy Chaining (2) Polling (3) Independent Request

(1) Daisy Chaining

Daisy chaining mechanism as illustrated in above figure comprises of three controlsignals called BUS GRANT, BUS REQUEST & BUS BUSY. The bus grant signal is aoutput value from the Bus Control Unit and is existing sequentially amongst theconnected devices U1, U2,.,Un.

When a Uk device want to gain a bus control then it senses bus busy and it foundfree generated the bus request signal. On receiving bus request, the Bus Control Unitinitiates bus grant that moves device to device and the requesting device when receivesthis signal generates the bus busy and gains the bus control.This mechanism suffers from two major draw backs

(i) Even if the nearby device has notgenerated bus request, may gain the buscontrol during bus grant traversal. Thusthe nearer devices has higher priority andthe farest devices may starve.

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(ii) If an intermediate device fails then the bus grant traversal is interrupted in flowand the system may collapse.

(2) Polling (Poll Count)

The draw backs of daisy chaining can be overcome by replacing the busy bus grant, asequential signal by a poll count parallel signal. Here we require having log 2n poll lines.When ever a device wants bus control it sends a bus request, consequently the BusControl Unit initiates the poll count, the device that matches poll count may generate bus

busy signal. This system also suffers from a draw back that a low poll count device hashigher priority that can be over come by a phenomenon of Count Freeze (In countfreeze mechanism suppose the k th device was want bus then on next bus request the countstarts from k+1).

(3) Independent request

The major draw back of above said method

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