Mul1slow Normal and High Report

8/3/2019 Mul1slow Normal and High Report

http://slidepdf.com/reader/full/mul1slow-normal-and-high-report 1/27

module half_5(a, b, sum, c);

input a, b;

output sum, c;

wire a, b;

wire sum, c;

ADDHXL g17(.A (a), .B (b), .S (sum), .CO (c));

endmodule

module half_2(a, b, sum, c);

input a, b;

output sum, c;

wire a, b;

wire sum, c;

ADDHXL g17(.A (a), .B (b), .S (sum), .CO (c));

endmodule

module mul1(a, b, p);

input [1:0] a;

input [3:0] b;

output [5:0] p;

wire [1:0] a;

wire [3:0] b;

wire [5:0] p;

wire [9:0] w;



full c10(w[2], w[3], w[7], p[2], w[8]);

full_1 c11(w[4], w[5], w[8], p[3], w[9]);

half_5 c12(w[6], w[9], p[4], p[5]);

half_2 c9(w[0], w[1], p[1], w[7]);

AND2XL g49(.A (a[0]), .B (b[0]), .Y (p[0]));

AND2X1 g50(.A (a[0]), .B (b[1]), .Y (w[0]));

AND2X1 g51(.A (a[0]), .B (b[2]), .Y (w[2]));

AND2X1 g52(.A (a[1]), .B (b[1]), .Y (w[3]));

AND2X1 g53(.A (a[0]), .B (b[3]), .Y (w[4]));

AND2X1 g54(.A (a[1]), .B (b[0]), .Y (w[1]));

AND2X1 g55(.A (a[1]), .B (b[2]), .Y (w[5]));

AND2X1 g56(.A (a[1]), .B (b[3]), .Y (w[6]));

endmodule

rc:/> ls

./ designs/ dex/ hdl_libraries/ libraries/ messages/object_types/

rc:/> cd /designs/

rc:/designs> ls

./ mul1/

rc:/designs> cd /designs/mul1/

rc:/designs/mul1> ls

./ dex_settings/ instances_comb/ instances_seq/ physical/ port_busses_out/ports_out/ subdesigns/

constants/ dft/ instances_hier/ nets/ port_busses_in/ ports_in/ power/timing/

rc:/designs/mul1> report po



ambiguous "po": port power power_domain

rc:/designs/mul1> report power

============================================================

Generated by: Encounter(R) RTL Compiler v09.10-s106_2

Generated on: Oct 13 2011 10:47:31 AM

Module: mul1

Technology library: slow_normal 1.0

Operating conditions: slow (balanced_tree)

Wireload mode: enclosed

Area mode: timing library

============================================================

Leakage Dynamic Total

Instance Cells Power(nW) Power(nW) Power(nW)

---------------------------------------------

mul1 16 294.299 1396.399 1690.698

c11 3 72.708 337.078 409.785

c2 1 29.679 117.705 147.384

c1 1 29.015 159.782 188.797

c10 3 72.319 304.502 376.822

c1 1 29.022 167.070 196.092

c2 1 28.858 88.104 116.962

c9 1 29.099 86.060 115.159

c12 1 29.096 104.956 134.053



rc:/designs/mul1> report timing

Warning : Possible timing problems have been detected in this design. [TIM-11]

: The design is 'mul1'.

: Use 'report timing -lint' for more information.

============================================================



Module: mul1





============================================================

Pin Type Fanout Load Slew Delay Arrival

(fF) (ps) (ps) (ps)

--------------------------------------------------------

b[2] in port 2 2.2 0 +0 0 F

g51/B +0 0

g51/Y AND2X1 1 1.9 48 +97 97 F

c10/a

c1/a

g17/A +0 97

g17/S ADDHXL 1 2.3 92 +144 240 F

c1/sum



c2/a

g17/B +0 240

g17/CO ADDHXL 1 1.1 41 +102 343 F

c2/c

g2/A +0 343

g2/Y OR2XL 1 2.3 69 +141 483 F

c10/ca

c11/c

c2/b

g17/B +0 483

g17/CO ADDHXL 1 1.1 42 +96 579 F

c2/c

g2/A +0 579

g2/Y OR2XL 1 2.3 69 +141 720 F

c11/ca

c12/b

g17/B +0 720

g17/CO ADDHXL 1 0.0 27 +84 804 F

c12/c

p[5] out port +0 804 F

--------------------------------------------------------

Timing slack : UNCONSTRAINED

Start-point : b[2]

End-point : p[5]



rc:/designs/mul1> report timing -lint

============================================================



Module: mul1





============================================================

-------------------------------------------------------------------------------

The following primary inputs have no clocked external delays. As a result the

timing paths leading from the ports have no timing constraints derived from

clock waveforms. The'external_delay' command is used to create new external

delays.

/designs/mul1/ports_in/a[0]

/designs/mul1/ports_in/a[1]

/designs/mul1/ports_in/b[0]

... 3 other warnings in this category.

Use the -verbose option for more details.

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------



The following primary outputs have no clocked external delays. As a result the

timing paths leading to the ports have no timing constraints derived from clock

waveforms. The'external_delay' command is used to create new external delays.

/designs/mul1/ports_out/p[0]



... 3 other warnings in this category.

Use the -verbose option for more details.

-------------------------------------------------------------------------------

rc:/designs/mul1> report area

============================================================



Module: mul1





============================================================

Instance Cells Cell Area Net Area Wireload

----------------------------------------------------



mul1 16 99 0 <none> (D)

c11 3 25 0 <none> (D)

c2 1 11 0 <none> (D)

c1 1 11 0 <none> (D)

c10 3 25 0 <none> (D)

c2 1 11 0 <none> (D)

c1 1 11 0 <none> (D)

c9 1 11 0 <none> (D)

c12 1 11 0 <none> (D)

(D) = wireload is default in technology library

rc:/designs/mul1> report gates

============================================================



Module: mul1





============================================================

Gate Instances Area Library

-----------------------------------------



ADDHXL 6 63.504 slow_normal

AND2X1 7 24.696 slow_normal

AND2XL 1 3.528 slow_normal

OR2XL 2 7.056 slow_normal

-----------------------------------------

total 16 98.784

Type Instances Area Area %

------------------------------

logic 16 98.784 100.0

------------------------------

total 16 98.784 100.0

rc:/designs/mul1> set_attribute library/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_highvt.lib

Error : Failed to parse attribute string. [TUI-23] [set_attribute]

: Unable to convert the string'/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_highvt.lib' to type 'library domain' for the attribute 'library_domain'.

: To see the usage/description for this attribute, type 'set_attribute -h <attr_name> *'.

Failed on set_attribute library/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_highvt.lib

rc:/designs/mul1> cd ..

rc:/designs> cd ..



rc:/> set_attribute library/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_highvt.lib

Freeing libraries in memory

(/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_normal.lib)

Warning : Black-boxes are represented as unresolved references in the design. [TUI-273]

: Cannot resolve reference to 'OR2XL'.

: To resolve the reference, either load a technology library containing the cell by appending to the'library' attribute, or read in the hdl file containing the module before performing elaboration. As thedesign is incomplete, synthesis results may not correspond to the entire design.


: Cannot resolve reference to 'ADDHXL'.


: Cannot resolve reference to 'AND2XL'.


: Cannot resolve reference to 'AND2X1'.

Setting attribute of root '/': 'library' =/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_highvt.lib

rc:/> cd /designs/

rc:/designs> ls

./ mul1/

rc:/designs> remove_design /designs/mul1/

invalid command name "remove_design"

rc:/designs> remove /designs/mul1/

ambiguous command name "remove": remove_assigns_without_optimizationremove_cdn_loop_breaker remove_inserted_sync_enable_logic



rc:/designs> remove -design /designs/mul1/


rc:/designs> read_hdl mul1.v

rc:/designs> cd ..

rc:/> read_hdl mul1.v

module mul1(a,b,p);

|

Warning : Replacing previously read Verilog description. [VLOGPT-6]

: Replacing Verilog description 'mul1' with Verilog module in file 'mul1.v' on line 1, column 11.

: A Verilog description is replaced when a new description of the same name and same library isread again.

Verilog descriptions are:

module

macromodule

SystemVerilog adds the following descriptions:

interface

program

package.

module full(a,b,c,sum,ca);

|


: Replacing Verilog description 'full' with Verilog module in file 'mul1.v' on line 20, column 11.

module half(a,b,sum,c);

|




: Replacing Verilog description 'half' with Verilog module in file 'mul1.v' on line 34, column 11.

Warning : Replacing previously read Verilog module or VHDL entity. [HPT-76]

: Replacing Verilog module 'mul1' in library 'default' with newly read Verilog module 'mul1' in thesame library in file 'mul1.v' on line 1.

: A newly read VHDL entity replaces any previously read Verilog module or VHDL entity in the samelibrary if its name matches (case-insensitively) the existing module or entity.

For instance:

VHDL 'foo' replaces VHDL {'FOO' or 'foo' or 'Foo' or ...} in the same library

VHDL 'foo' (in any library) replaces Verilog {'FOO' or 'foo' or 'Foo' or ...} in the same library

A newly read Verilog module replaces any previously read Verilog module if its name matches (case-sensitively) that module. Further, it replaces any previously read VHDL entity in the same library if itsname matches (case -insensitively) that entity.

For instance:

Verilog 'foo' replaces VHDL {'FOO' or 'foo' or 'Foo' or ...} in the same library

Verilog 'foo' replaces Verilog 'foo' only

In addition:

Verilog 'foo' does not replace Verilog 'FOO' and the two remain as distinct modules.


: Replacing Verilog module 'full' in library 'default' with newly read Verilog module 'full' in the samelibrary in file 'mul1.v' on line 20.


: Replacing Verilog module 'half' in library 'default' with newly read Verilog module 'half' in thesame library in file 'mul1.v' on line 34.

rc:/> remove /designs/mul1/


rc:/> remove_design /designs/mul1/



invalid command name "remove_design"

rc:/> elaborate

Elaborating top-level block 'mul1' from file 'mul1.v'.

Done elaborating 'mul1'.


: Cannot resolve reference to 'OR2XL'.


: Cannot resolve reference to 'ADDHXL'.


: Cannot resolve reference to 'AND2XL'.


: Cannot resolve reference to 'AND2X1'.

rc:/> synthesize -to_mapped

Mapping mul1_1 to gates.

Global mapping target info

==========================

Cost Group 'default' target slack: Unconstrained

Global mapping status

=====================

Worst

Total Neg

Operation Area Slack Worst Path



-------------------------------------------------------------------------------

global_map 99 0 N/A

Global incremental target info

==============================


Global incremental optimization status

======================================

Worst

Total Neg


-------------------------------------------------------------------------------

global_inc 99 0 N/A

Worst - - DRC Totals - -

Total Neg Max Max

Operation Area Slack Trans Cap

-------------------------------------------------------------------------------

init_iopt 99 0 0 0

Incremental optimization status

===============================


Total Neg Max Max




-------------------------------------------------------------------------------

init_delay 99 0 0 0

init_drc 99 0 0 0

init_area 99 0 0 0


===============================


Total Neg Max Max


-------------------------------------------------------------------------------

init_delay 99 0 0 0

init_drc 99 0 0 0

init_area 99 0 0 0

Done mapping mul1_1

Mapping mul1 to gates.

Global mapping target info

==========================


Global mapping status



=====================

Worst

Total Neg


-------------------------------------------------------------------------------

global_map 0 0 N/A

Global incremental target info

==============================


Global incremental optimization status

======================================

Worst

Total Neg


-------------------------------------------------------------------------------

global_inc 0 0 N/A


Total Neg Max Max


-------------------------------------------------------------------------------

init_iopt 0 0 0 0




===============================


Total Neg Max Max


-------------------------------------------------------------------------------

init_delay 0 0 0 0

init_drc 0 0 0 0

init_area 0 0 0 0


===============================


Total Neg Max Max


-------------------------------------------------------------------------------

init_delay 0 0 0 0

init_drc 0 0 0 0

init_area 0 0 0 0

Done mapping mul1

Synthesis succeeded.

rc:/> report power

Error : Multiple designs are available. Specify the design you want to use. [TUI-17] [report]

: There is no unique design here.



: Specify a design by using the cd command to change to that design's directory or specify thedesign as an argument for the command.

Failed on find_unique_design

rc:/> ls

./ designs/ dex/ hdl_libraries/ libraries/ messages/object_types/

rc:/> cd /de

ambiguous "/de": designs/ dex/

rc:/> cd /designs/

rc:/designs> ls

./ mul1/ mul1_1/

rc:/designs> cd mul1

rc:/designs/mul1> report power

Warning : Did not find power models for RTL power analysis. [PA-17]

: Design /designs/mul1 has no power models available.

: The RTL power analysis results are more accurate when detailed power models are used. Use

command 'build_rtl_power_models' to build detailed power models.

============================================================



Module: mul1

Technology library: slow_highvt 1.0




============================================================





----------------------------------------------

mul1 0 0.000 0.000 0.000

c10 0 0.000 0.000 0.000

c1 0 0.000 0.000 0.000

g17 0 0.000 0.000 0.000

c2 0 0.000 0.000 0.000

g17 0 0.000 0.000 0.000

g2 0 0.000 0.000 0.000

c11 0 0.000 0.000 0.000

c1 0 0.000 0.000 0.000

g17 0 0.000 0.000 0.000

c2 0 0.000 0.000 0.000

g17 0 0.000 0.000 0.000

g2 0 0.000 0.000 0.000

c12 0 0.000 0.000 0.000

g17 0 0.000 0.000 0.000

c9 0 0.000 0.000 0.000

g17 0 0.000 0.000 0.000

g49 0 0.000 0.000 0.000

g50 0 0.000 0.000 0.000

g51 0 0.000 0.000 0.000

g52 0 0.000 0.000 0.000

g53 0 0.000 0.000 0.000



g54 0 0.000 0.000 0.000

g55 0 0.000 0.000 0.000

g56 0 0.000 0.000 0.000

rc:/designs/mul1> cd ..

rc:/designs> mult1_1

invalid command name "mult1_1"

rc:/designs> ls

./ mul1/ mul1_1/

rc:/designs> cd /designs/mul1_1/

rc:/designs/mul1_1> report power

============================================================



Module: mul1_1





============================================================



---------------------------------------------

mul1_1 16 73.975 1375.948 1449.922



c11 3 18.150 331.300 349.450

c2 1 7.409 115.098 122.507

c1 1 7.272 156.936 164.207

c10 3 18.144 299.757 317.900

c1 1 7.293 165.989 173.282

c2 1 7.283 84.772 92.055

c12 1 7.321 104.047 111.368

c9 1 7.317 85.181 92.498

rc:/designs/mul1_1>



rc:/designs/mul1_1> report power

============================================================



Module: mul1_1





============================================================



---------------------------------------------

mul1_1 16 73.975 1375.948 1449.922

c11 3 18.150 331.300 349.450

c2 1 7.409 115.098 122.507

c1 1 7.272 156.936 164.207

c10 3 18.144 299.757 317.900

c1 1 7.293 165.989 173.282



c2 1 7.283 84.772 92.055

c12 1 7.321 104.047 111.368

c9 1 7.317 85.181 92.498

rc:/designs/mul1_1> report timing

Warning : Possible timing problems have been detected in this design. [TIM-11]

: The design is 'mul1_1'.

============================================================



Module: mul1_1





============================================================

Pin Type Fanout Load Slew Delay Arrival

(fF) (ps) (ps) (ps)

--------------------------------------------------------

b[2] in port 2 2.2 0 +0 0 F

g51/B +0 0

g51/Y AND2X1TH 1 1.8 56 +122 122 F

c10/a

c1/a



g17/A +0 122

g17/S ADDHXLTH 1 2.3 114 +187 309 F

c1/sum

c2/a

g17/B +0 309

g17/CO ADDHXLTH 1 1.0 48 +132 441 F

c2/c

g2/A +0 441

g2/Y OR2XLTH 1 2.3 84 +184 624 F

c10/ca

c11/c

c2/b

g17/B +0 624

g17/CO ADDHXLTH 1 1.0 48 +122 746 F

c2/c

g2/A +0 746

g2/Y OR2XLTH 1 2.3 84 +184 930 F

c11/ca

c12/b

g17/B +0 930

g17/CO ADDHXLTH 1 0.0 32 +108 1039 F

c12/c

p[5] out port +0 1039 F

--------------------------------------------------------

Timing slack : UNCONSTRAINED



Start-point : b[2]

End-point : p[5]

rc:/designs/mul1_1> report area

============================================================



Module: mul1_1





============================================================

Instance Cells Cell Area Net Area Wireload

----------------------------------------------------

mul1_1 16 99 0 <none> (D)

c11 3 25 0 <none> (D)

c2 1 11 0 <none> (D)

c1 1 11 0 <none> (D)

c10 3 25 0 <none> (D)

c2 1 11 0 <none> (D)

c1 1 11 0 <none> (D)

c9 1 11 0 <none> (D)

c12 1 11 0 <none> (D)



(D) = wireload is default in technology library

rc:/designs/mul1_1> report gates

============================================================



Module: mul1_1





============================================================

Gate Instances Area Library

-------------------------------------------

ADDHXLTH 6 63.504 slow_highvt

AND2X1TH 7 24.696 slow_highvt

AND2XLTH 1 3.528 slow_highvt

OR2XLTH 2 7.056 slow_highvt

-------------------------------------------

total 16 98.784



Type Instances Area Area %

------------------------------

logic 16 98.784 100.0

------------------------------

total 16 98.784 100.0

rc:/designs/mul1_1>

Documents

Mul1slow Normal and High Report