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Multi-Project Reticle Floorplanning and Wafer Dicing. Andrew B. Kahng 1 Ion I. Mandoiu 2 Qinke Wang 1 Xu Xu 1 Alex Zelikovsky 3. (1) CSE Department, University of California at San Diego. (2) CSE Department, University of Connecticut. (3) CS Department, Georgia State University. Outline. - PowerPoint PPT Presentation
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Multi-Project Reticle Floorplanning and Wafer Dicing
Andrew B. Kahng1 Ion I. Mandoiu2 Qinke Wang1 Xu Xu1 Alex Zelikovsky3
(1) CSE Department, University of California at San Diego
(2) CSE Department, University of Connecticut
(3) CS Department, Georgia State University
Introduction to Multi-Project Wafer
Outline
Side-to-side wafer dicing problemReticle floorplanning and wafer dicing problem
Conclusions and future research directionsExperimental results
Design flow
Mask and Wafer Cost
Mask cost: $1M for 90 nm technologyWafer cost: $4K per wafer
Introduction to Multi-Project Wafer
Share rising costs of mask tooling between multiple prototype and low production volume designs Multi-Project Wafer
Image courtesy of CMP and EuroPractice
History of Multi-Project Wafer
Introduced in late 1970s and early 1980sCompanies: MOSIS, CMP, TSMC
Several approaches proposedChen et al. give bottom-left fill algorithm, 2003
Anderson et al. proposed grid packing algorithm, 2003
Tools: MaskCompose, GTMuch
Introduction to Multi-Project Wafer
Outline
Side-to-side wafer dicing problemReticle floorplanning and wafer dicing problem
Conclusions and future research directionsExperimental results
Design flow
Design Flow
Unique designs
Design Flow
Custom designs Partition between reticles
Design Flow
Custom designs Partition between shuttles Reticle placement
Design Flow
Custom designs Partition between shuttles Reticle placement Stepper shot-map
shot-map
Design Flow
Custom designs Partition between shuttles Reticle placement Stepper shot-map Dicing plan design
Design Flow
Custom designs Partition between shuttles Reticle placement Stepper shot-map Dicing plan design
Design Flow
Custom designs Partition between shuttles Reticle placement Stepper shot-map Dicing plan design Extract dice
Introduction to Multi-Project Wafer
Outline
Side-to-side wafer dicing problemReticle floorplanning and wafer dicing problem
Conclusions and future research directionsExperimental results
Design flow
Why Dicing a Problem?
Sliced out
A die is sliced out if and only if:- Four edges are on the cut lines- No cut lines pass through the die
Dicing is easy for standard wafers.All dice will be sliced out.
Dicing is complex for MPW.Most dice will be destroyed if placement is not well aligned.
Side-to-side dicing is the prevalent wafer dicing technology
Side-to-side Dicing Problem
Given:• reticle placement• wafer shot-map• required volume for each die
Find: • Set of horizontal and vertical
cut lines (dicing plan)
To Minimize:• w = # wafers used
H-Conflict
dice are in H-Conflict if they can not be sliced out horizontally.
1 2
43
1 and 2 are in H-conflict
Die 1 is in H-Conflict with entire row of Die 2.
12
43
12
43
12
43
Horizontal Dicing Plan
• A horizontal Dicing Plan (DP) is a set of lines which dice one row of prints• A set of dice which are pairwise not in H-conflict can be sliced out by a DP• We seek such maximal horizontal independent sets
MHIS (MVIS) = set of all horizontal (vertical) DPs
The dicing plan which slices out dice 1 and 4
1 2
43
1 2
43
1 2
43
Interval Coloring• Two dice are in H-conflict iff their vertical projections overlap• Interval graph, which can be optimally colored• All dice of the same color can be horizontally sliced out
12
43
12
43
1 2
43
1 2
43
1 2
3 4
Non-Linear Programming Formulation
Assume the wafer is a rectangular array of prints.
• fH= # rows (with DP H)
rowsfH H # one DP per row
HD
H
i
f = # rows whose dicing plans slice out Di
Non-Linear Programming Formulation
Assume the wafer is a rectangular array of prints.•gV= # columns (with DP V)
columnsgV V #
VD
V
i
g = # columns whose dicing plans slice out Di
one DP per column
Non-Linear Programming Formulation
N(Di)= # required copies of die Di
z=1/(# wafer)
zDNgf iVD
VHD
H
ii
)())((
623 copies sliced out
3HD
H
i
f
2VD
V
i
g
Must slice out at least the required volume
Non-Linear Programming FormulationAssume the wafer is a rectangular array of prints.• fH= # rows (with DP H)• gV= # columns (with DP V)• N(Di)= # required copies of die Di
Maximize: z = 1/(# wafers)
Subject to:
columnsg
rowsf
zDNgf
V V
H H
iVD
VHD
H
ii
#
#
)())((
rHf
rf
rH
MHISHrH
,}1,0{
1
,
,
Integer Linear Programming Formulation
rMHIS
r
r
f
f
f
|,|
,2
,1
...
One DP per row
cVf
cf
cV
MVISVcV
,}1,0{
1
,
,
Integer Linear Programming Formulation
One DP per column
cMVIScc fff |,|,2,1 ...
cVrHf
cVrHfff
cVrH
cVrHcVrH
,,,}1,0{
,,,2/)(
,,,
,,,,,
Integer Linear Programming Formulation
cVrHf ,,,
rHf ,
cVf ,
The print at rth row and cth column is diced by DP H and V iff we use H at the rth row and V at the cth column
VHD
VHDq
DzDNfq
i
iDVH
iicr VH
cVrHDVH
i
i
0
1
)(
,
, ,,,,,
Integer Linear Programming Formulation
cVrHf ,,,
0
1
,,,,,
VHcVrH
DVH fq i
Di sliced out
otherwise
Sliced out at least required volume
cVrHf
cVf
rHf
DzDNfq
cVrHfff
cf
rf
cVrH
cV
rH
iicr VH
cVrHDVH
cVrHcVrH
MVISVcV
MHISHrH
i
,,,}1,0{
,}1,0{
,}1,0{
)(
,,,2/)(
1
1
,,,
,
,
, ,,,,,
,,,,,
,
,
Integer Linear Programming Formulation
Maximize: z = 1/(# wafers)
Subject to:
Iterative Augment and Search Algorithm (IASA)
• Choose initial dicing plan using interval graph coloring
DP1
DP2
Iterative Augment and Search Algorithm (IASA)
• Choose initial dicing plan using interval graph coloring
• In each iteration, first check whether z will increase by changing the dicing plan for one row or column
DP1,…,DP|MVIS|
DP1
DP2
DP1,…,DP|MHIS|
Iterative Augment and Search Algorithm (IASA)
• Choose initial dicing plan using interval graph coloring
• In each iteration, first check whether z will increase by changing the dicing plan for one row or column
DP1
DP2
DP1,…,DP|MHIS|
• Choose one dicing plan for one new row or column which maximizes z
DP3
Experiment Setup
• Ten random testcases with different numbers of dice • Required production volume is 40 for all dice• Assume a wafer has 10 rows and 10 columns of prints• We used CPLEX 8.100 to solve LP• We used LINGO 6.0 to solve NLP• We implemented the IASA heuristic in C• All tests are run on an Intel Xeon 2.4GHz CPU
Experimental Results for SSDPTest Case
# dice
NLP-Lingo LP-CPLEX IASA
40z CPU(s) 40z CPU(s) 40z CPU(s)
1 5 25 0.3 25 0.3 25 0.0
2 6 25 0.2 25 0.2 25 0.0
3 7 21 1.4 21 0.1 21 0.0
4 8 14 27.1 14 6.7 14 0.0
5 9 14 40.7 14 2.5 14 0.0
6 10 25 0.2 25 4.3 25 0.0
7 11 18 4.1 18 2.7 18 0.0
8 14 16 294.1 16 51.4 16 0.0
9 16 12 1236.4 12 91.4 12 0.0
10 21 20 12.2 20 179.7 20 0.0
• Performance of IASA is much better
Introduction to Multi-Project Wafer
Outline
Side-to-side wafer dicing problemReticle floorplanning and wafer dicing problem
Conclusions and future research directionsExperimental results
Design flow
What Floorplan is Good?
40 wafers needed for 40 copies
1 243
• Min-area floorplan high wafer cost 1 2
43
1 243
1 243
1 243
What Floorplan is Good?
40 wafers needed for 40 copies
1 243
• Min-area floorplan High wafer cost 1 2
43
1 243
1 243
1 243
• Diagonal floorplan Larger reticleHigh wafer cost 1
24
3
What Floorplan is Good?
40 wafers needed for 40 copies
1 243
• Min-area floorplan high wafer cost 1 2
43
1 243
1 243
1 243
• Diagonal floorplan high mask cost
12
4
3
20 wafers needed for 40 copies
• Good floorplan 1 2
4 3
1 24 3
1 24 3
1 24 3
1 24 3
Reticle Design and Wafer Dicing Problem
Given: n dice Di (i=1…n), reticle size
Find: placement of dice within the reticle and a dicing plan To Minimize: w, the number of wafers used
Shelf Packing and Shifting
• Sort dice according to height
Shelf Packing and Shifting
• Sort dice according to height
• For all possible shelf widths, insert the dice into the shelves
Shelf Packing and Shifting
• Sort dice according to height
• For all possible shelf widths, insert the dice into the shelves
• Shift the dice to align them with the dice on other shelves and calculate z using IASA
Shelf Packing and Shifting
• Choose the placement with the max z
• Sort dice according to height
• For all possible shelf widths, insert the dice into the shelves
• Shift the dice to align them with the dice on other shelves and calculate z using IASA
Simulated Annealing Placement
Get a shelf packing floorplan as the initial floorplan Calculate Objective Value =(1-α) area+ α(100-z) While (not converge and # of move < Move_Limit) { choose a uniform random number r make a random move according to r calculate δ= New Objective Value - Old Objective value
If (δ <0) Accept the move Else Accept the move with probability exp(- (δ/T)) T=β T }
Introduction to Multi-Project Wafer
Outline
Side-to-side wafer dicing problemReticle floorplanning and wafer dicing problem
Conclusions and future research directionsExperimental results
Design flow
Experimental Results for RDWDPTest Case
# Die
Die area
GTMuch Shelf+shift SA+IASA
40z area 40z area CPU 40z area CPU
1 10 231 18 255 16 276 0.0 28 288 80
2 18 226 16 285 21 253 0.2 25 270 783
3 11 252 15 280 16 280 0.0 30 294 132
4 9 203 18 221 25 224 0.0 30 288 118
5 10 226 12 272 25 280 0.0 25 260 94
6 15 227 10 285 18 238 0.0 18 238 226
7 15 234 14 285 15 288 0.0 20 285 782
8 14 232 20 285 20 288 0.0 20 288 152
9 10 231 20 285 16 276 0.0 28 288 161
10 20 215 6 304 15 255 0.0 20 260 1020
Total 2277 149 2757 187 2668 0.0 244 2757• GTMuch is a commercial tool for MPW • Improve wafer yield z by 37.7% compared with GTMuch• Improve wafer yield z by 30.5% compared with shelf+shift
Solutions for Testcase 1
GTMuchParquet
Simulated annealingShelf+shift
Introduction to Multi-Project Wafer
Outline
Side-to-side wafer dicing problemReticle floorplanning and wafer dicing problem
Conclusions and future research directionsExperimental results
Design flow
Conclusions
We presented a MPW design flow
We propose practical mathematical programming formulations and efficient heuristics, which can be extended to the case when margins are allowed
By using the simulated annealing code, we can further improve wafer-dicing yield by 30.5% at the expense of an increase of area by 3.3%.
The shelf packing and shifting algorithm can improve yield by 37.7% while reducing reticle area by 3.3% compared to GTMuch.
Future Research
Validate proposed methods on industry testcases
Extend the proposed algorithms to round wafer
Multiple dicing plans
Thank you for your attention!