MUP Intel X86

Computer Architecture (P. Leong) Pentium Architecture - Intro (page 1)

The Intel Pentium Architecture(Introduction)

Philip Leong


Intel x86/Pentium Family

Name Date Transistors Feature size Frequency Data width MIPS 8080 1974 6,000 6 2 MHz 8 bits 0.64 8088 1979 29,000 3 5 MHz 16 bits, 8-bit bus 0.33 80286 1982 134,000 1.5 6 MHz 16 bits 1 80386 1985 275,000 1.5 16 MHz 32 bits 5 80486 1989 1,200,000 1 25 MHz 32 bits 20 Pentium 1993 3,100,000 0.8 60 MHz 32 bits, 64-bit bus 100 Pentium II 1997 7,500,000 0.35 233 MHz 32 bits, 64-bit bus ~300 Pentium III 1999 9,500,000 0.25 450 MHz 64-bit bus ~510Pentium IV 2000 42,000,000 0.18 1.7 GHz 64-bit bus ~1,700

check out CPU Info Center: http://bwrc.eecs.berkeley.edu/CIC/


Registers 8086 -> 80286 (-> Pentium)

BH BLBX Base IndexCH CLCX CountDH DLDX Data

16-bitStack PointerSP

Base PointerBP

Source IndexSI

Dest. IndexDI

AH ALAX Accumulator15 8 7 0

“General Purpose”


Registers 80386 -> Pentium

Base PointerSource IndexDest. Index

ESPEBPESIEDI

32-bitStack PointerSP

BPSIDI

“General-Purpose”

AXBXCXDX

AccumulatorBase IndexCountData

EAXEBXECXEDX

31 16 15 0

Can also access ..H and ..L regs


Some Special Register UsesThe General Purpose Registers also have some special uses:

EAX - Implied Operand for Multiply and Divide instructions

EBX - Often used as a pointer to data in the Data segment

ECX - Counter for string and loop instructions

EDX - Extension to AX for multiply and divide operations, I/O pointer

ESP - Stack pointer in Stack segment

EBP - Pointer to data on the stack in the Stack segment


Segment Registers 8086 –> Pentium16-bitRegister

Code SegmentCSData SegmentDSExtra SegmentESStack SegmentSS

FSGS

386 -> Pentium Only


Real-Mode Memory Model 8086 –> Pentium

000000000

FFFFF

1Mb Max

64KbSegment

16 bitsCS, DS, ES, SS

Linear Address = Segment Reg * 16 + Offset Value

+

16 bits

Offset Value

Offset value is sometimes called the Effective Address

Linear Address20-bits


Segment Registers

physical address = 16 × [ segment-reg ] + offset Segment/offset addressing


Which Segment Register?Here’s a set of (simplified) rules to follow:

Fetching an Instruction -> CS (Code Segment)

Pushing/Popping data to the Stack -> SS (Stack Segment)

Memory Operand & Base Register = EBP (or ESP) -> SS (Stack Segment)

Otherwise -> DS (Data Segment)

We can normally override the default segment register by prefixing operands explicitly with a segment register

There are a few odd instructions which use the Extra Segment, e.g. Intel String instructions.


Instruction Pointer Register

16-bit IP 8086 -> Pentium

386 -> PentiumEIP32-bit

Instruction Pointer Register holds offset in the Code Segment of the next instruction to be executed.

Updated indirectly by some instructions, e.g. CALL, JMP, RET


Flags Register

16-bit FLAGS 8086 -> Pentium

EFLAGS 386 -> Pentium32-bit

Carry Flag (Bit 0) Set (=1) if carry or borrow out of MS-bit, cleared (=0) otherwise. Used in multi-precision arithmetic

Parity Flag (Bit 2) Set if LS-byte of result contains an even number of bits, cleared otherwise.

Zero Flag (Bit 6) Set if the result is zero, cleared otherwise.Sign Flag (Bit 7) Set to MS-bit of result, which is the sign bit of a signed

integer.Direction Flag (Bit 10) If set, string instructions auto-decrement, else auto-

decrementOverflow Flag (Bit 11) Set if result is too large a positive number or too small a

negative number, cleared otherwise.


Basic Data Types

WordWord7 0

NLowHigh

15 8

N+1ByteByte

7 0

N <- Address

DoublewordDoublewordN

Low Word31 16 15 0

N+2High Word

QuadwordQuadwordN

Low Doubleword63 32 31 0

N+4High Doubleword


Main Memory

Byte Addressable, Little Endian, Non-Aligned Accesses Allowed

12 31 CB 74 EF F0 0B 23 A4 1F 36 06 FE 7A FF 450 1 2 3 4 5 6 7 8 9 A B C D E FAddress

Byte at address 9H?Byte at address 0BH?Word at address 1H?Word at address 2H?Word at address 6H?Doubleword at address 0AH?Quadword at address 6H?

1F06CB3174CB

7AFE....0B


A machine code programSource code: 0100 SUB AX,AX ; Initialise AX to zero 0102 ADD AX,[BX] ; Add word pointed to by BX to AX 0104 ADD BX,2 ; BX points to next word in memory 0107 CMP DX,BX ; IF DX >= BX 0109 JNS 0102 ; THEN go to 0102

Machine code0100 2B C0 0102 03 07 0104 83 C3 02 0107 3B D3 0109 79 F7

Programs are written in assembler using mnemonics and comments Sum contents of memory from [BX] to [DX] into AX


First instruction


Second instruction


Third & fourth instruction


Compare instruction

Subtracts source from destination and updates status flags Without saving result (register contents unaffected) Later instructions can check flags CMP DX,BX performs (DX − BX) if BX > DX result will be negative - Sign bit will be set (to 1) CMP & TEST instructions set/reset flags Flags can affect later instructions (e.g. Conditional jumps)


Fifth instruction


Jump if not signJumps to new address if Sign flag = 0 0009 79 F7 JNS 0102 79 means JNS displacement = F7 = 1111 0111 Two's Complement: msb = 1 so negativeInvert bits: 0000 1000 Add 1: 0000 1001 = 9 Therefore F7 represents -9

After fetching 79 F7, Instruction Pointer = 010B Adding -9 to IP gives 0102 Associate a label with an address to use a jump translated to equivalent displacement by the assembler


Jump on condition

Key:•A above•B below•E equal•Z zero•G greater than•L less than•N not•S sign•O overflow•P parity


BooksIntroduction to Assembly Language Programming, Sivarama Dandamudi, Springer, 1998. Good introduction to Intel assembly programming

Inner Loops, Rick Booth, Addison Wesley, 1997. Code optimisation for 486, Pentium & Pentium Pro

Michael Abrash's Graphics Programming Black Book: Special Edition, Michael Abrash, Coriolis, 1997. Chapters 1-22 cover Intel code optimisation. Rest cover graphics for games (e.g. Quake)

Intel Pentium Manuals,http://developer.intel.com/design/pentiumiii/manuals/The definitive references.


Think about1. What the segment registers do.2. The advantages and disadvantages of having a lot of registers.3. The disadvantages associated with having special purpose registers.4. The flags registers and why we need them.5. The difference between all of the addressing modes.6. How programs are stored in memory.7. How assembly code is translated to machine code.8. Differences and similarities between the 8086 and Toy1.

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