D(5, 6, 7, 8)

G(4)

S(1, 2, 3)

8

1 2 3 4

7 6 5

AM15810v1

FeaturesOrder code VDS RDS(on) max. ID

STL4N10F7 100 V 70 mΩ 4.5 A

• Excellent FoM (figure of merit)• Low Crss/Ciss ration for EMI immunity• High avalanche ruggedness

Applications• Switching applications

DescriptionThis N-channel Power MOSFET utilizes STripFET™ F7 technology with anenhanced trench gate structure that results in very low on-state resistance, while alsoreducing internal capacitance and gate charge for faster and more efficient switching.

Maturity status link

STL4N10F7

Device summary

Order code STL4N10F7

Marking 4N1F7

Package PowerFLAT™3.3x3.3

Packing Tape and reel

N-channel 100 V, 62 mΩ typ., 4.5 A STripFET™ F7 Power MOSFET in a PowerFLAT™ 3.3x3.3 package

STL4N10F7

Datasheet

DS9354 - Rev 5 - February 2018For further information contact your local STMicroelectronics sales office.

www.st.com/Power Transistors

1 Εlectrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VDS Drain-source voltage 100 V

VGS Gate-source voltage ±20 V

ID(1)Drain current (continuous) at Tpcb = 25 °C 4.5 A

Drain current (continuous) at Tpcb = 100 °C 3.2 A

IDM(1)(2) Drain current (pulsed) 18 A

PTOT(1) Total dissipation at Tpcb = 25 °C 2.9 W

ID(3)Drain current (continuous) at Tc = 25 °C 17 A

Drain current (continuous) at Tc = 100 °C 11 A

IDM (2)(3) Drain current (pulsed) 68 A

PTOT(3) Total dissipation at Tc = 25 °C 35.7 W

Tj Operating junction temperature range-55 to 150

°C

Tstg Storage temperature range °C

1. This value is rated according to Rthj-pcb.

2. Pulse width is limited by safe operating area.3. This value is rated according to Rthj-case.

Table 2. Thermal resistance

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case 3.5 °C/W

Rthj-pcb(1) Thermal resistance junction-pcb 42.8 °C/W

1. When mounted on an 1-inch2 FR-4 board, 2oz Cu, t < 10 s

STL4N10F7Εlectrical ratings

DS9354 - Rev 5 page 2/14

2 Electrical characteristics

(TC= 25 °C unless otherwise specified)

Table 3. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSSDrain-source breakdownvoltage VGS = 0 V, ID = 250 µA 100 V

IDSSZero gate voltage draincurrent

VGS = 0 V, VDS = 100 V 1 µA

VGS = 0 V, VDS = 100 V,TC= 125 °C(1) 100 µA

IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V 100 nA

VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 4.5 V

RDS(on)Static drain-source on-resistance VGS = 10 V, ID = 2.25 A 62 70 mΩ

1. Defined by design, not subject to production test.

Table 4. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitanceVDS = 50 V, f = 1 MHz,VGS = 0 V

- 408 - pF

Coss Output capacitance - 112 - pF

Crss Reverse transfer capacitance - 10 - pF

Qg Total gate charge VDD = 50 V, ID = 4.5 A,VGS = 0 to 10 V

(see Figure 15. Test circuit forgate charge behavior)

- 7.8 - nC

Qgs Gate-source charge - 3 - nC

Qgd Gate-drain charge - 1.7 - nC

Table 5. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time VDD = 50 V, ID = 2.25 A,

RG = 4.7 Ω, VGS = 10 V

(see Figure 14. Test circuit forresistive load switching timesand Figure 19. Switching timewaveform)

- 6.3 - ns

tr Rise time - 3 - ns

td(off) Turn-off delay time - 11 - ns

tf Fall time - 4 - ns

Table 6. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

VSD (1) Forward on voltage ISD = 2.25 A, VGS = 0 V - 1.1 V

STL4N10F7Electrical characteristics

DS9354 - Rev 5 page 3/14

Symbol Parameter Test conditions Min. Typ. Max. Unit

trr Reverse recovery time ISD = 2.25 A, di/dt = 100 A/µs,

VDD = 80 V,Tj = 150 °C

(see Figure 16. Test circuit forinductive load switching anddiode recovery times)

- 30 ns

Qrr Reverse recovery charge - 24 nC

IRRM Reverse recovery current - 1.6 A

1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

STL4N10F7Electrical characteristics

DS9354 - Rev 5 page 4/14

2.1 Electrical characteristics (curves)Figure 3. Safe operating area

GADG240120181033SOA

10 1

10 0

10 -1

10-1 10 0 10 1

ID (A)

VDS (V)

Operation in this areais limited by RDS(on)

tp =10 µs

tp =100 µs

tp =1 ms

tp =10 ms

Figure 4. Thermal impedance

GADG240120181033ZTH

10 -1

10 -2

10 -5 10 -4 10 -3 10 -2 10 -1

K

tp (s)

δ = 0.5

δ = 0.2

δ = 0.1δ = 0.05

δ = 0.02

δ = 0.01Single pulse

Figure 5. Output characteristics

ID

18

12

6

00 4 VDS(V)

(A)

2 6

24

30

6 V

5 V

7 V

8 V9 V

VGS= 10 V

8

GIPG200120141028FSR

Figure 6. Transfer characteristics

ID

15

10

5

04 VGS(V)

(A)

2 6

20

25

30VDS= 9V

108

GIPG200120141040FSR

Figure 7. Gate charge vs gate-source voltage

6

4

2

02 QG (nC)

DD= 50 VID= 4.5 A

8 6

GIPG200120141048FSR

0 4

8

10

12V

VGS(V)

6

4

2

02 QG (nC)

DD= 50 VID= 4.5 A

8 6

GIPG200120141048FSR

0 4

8

10

12V

VGS(V)

Figure 8. Static drain-source on-resistance

RDS(on)

62

61.6

61.2

60.80.5 1.5 ID(A)

(mΩ)

1 2

62.4

VGS=10V

2.5

GIPG210120141012FSR

STL4N10F7Electrical characteristics (curves)

DS9354 - Rev 5 page 5/14

Figure 9. Capacitance variations

C

400

300

200

100

0 40 VDS(V)

(pF)

20

500

60

Ciss

CossCrss

800

GIPG200120141330FSR

Figure 10. Normalized V(BR)DSS vs temperature

V(BR)DSS

1.0

0.98

0.96-75 TJ(°C)

(norm)

-25 7525 125

1.02

1.04ID= 250µA

GIPG210120141040FSR

Figure 11. Normalized gate threshold voltage vstemperature

VGS(th)

0.8

0.7

0.6-75 TJ(°C)

(norm)

-25

1.1

7525 125

0.9

1

ID=250 µAVDS=VGS

GIPG210120141020FSR

Figure 12. Normalized on-resistance vs temperature

RDS(on)

1.3

0.9

0.5-75 TJ(°C)

(norm)

-25 7525 125

1.7

VGS=10VID=2.25 A

GIPG210120141030FSR

Figure 13. Source-drain diode forward characteristics

VSD

0.5 1.5 ISD(A)

(V)

1 2 2.50.4

0.6

0.8

TJ=-55°C

TJ=175°C

TJ=25°C1.0

1.2

GIPG210120141051FSR

STL4N10F7Electrical characteristics (curves)

DS9354 - Rev 5 page 6/14

3 Test circuits

Figure 14. Test circuit for resistive load switching times

AM01468v1

VD

RG

RL

D.U.T.

2200μF VDD

3.3μF+

pulse width

VGS

Figure 15. Test circuit for gate charge behavior

AM01469v1

47 kΩ1 kΩ

47 kΩ

2.7 kΩ

1 kΩ

12 V

IG= CONST100 Ω

100 nF

D.U.T.

+pulse width

VGS

2200μF

VG

VDD

Figure 16. Test circuit for inductive load switching anddiode recovery times

AM01470v1

AD

D.U.T.S

B

G

25 Ω

A A

B B

RG

GD

S

100 µH

µF3.3 1000

µF VDD

D.U.T.

+

_

+

fastdiode

Figure 17. Unclamped inductive load test circuit

AM01471v1

VD

ID

D.U.T.

L

VDD+

pulse width

Vi

3.3µF

2200µF

Figure 18. Unclamped inductive waveform

AM01472v1

V(BR)DSS

VDDVDD

VD

IDM

ID

Figure 19. Switching time waveform

AM01473v1

0

VGS 90%

VDS

90%

10%

90%

10%

10%

ton

td(on) tr

0

toff

td(off) tf

STL4N10F7Test circuits

DS9354 - Rev 5 page 7/14

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®

packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitionsand product status are available at: www.st.com. ECOPACK® is an ST trademark.

STL4N10F7Package information

DS9354 - Rev 5 page 8/14

4.1 PowerFLAT™ 3.3x3.3 package information

Figure 20. PowerFLAT™ 3.3x3.3 package outline

BOTTOM VIEW

SIDE VIEW

TOP VIEW

8465286_2

STL4N10F7PowerFLAT™ 3.3x3.3 package information

DS9354 - Rev 5 page 9/14

Table 7. PowerFLAT™ 3.3x3.3 package mechanical data

Dim.mm

Min. Typ. Max.

A 0.70 0.80 0.90

b 0.25 0.30 0.39

c 0.14 0.15 0.20

D 3.10 3.30 3.50

D1 3.05 3.15 3.25

D2 2.15 2.25 2.35

e 0.55 0.65 0.75

E 3.10 3.30 3.50

E1 2.90 3.00 3.10

E2 1.60 1.70 1.80

H 0.25 0.40 0.55

K 0.65 0.75 0.85

L 0.30 0.45 0.60

L1 0.05 0.15 0.25

L2 0.15

θ 8° 10° 12°

STL4N10F7PowerFLAT™ 3.3x3.3 package information

DS9354 - Rev 5 page 10/14

Figure 21. PowerFLAT™ 3.3x3.3 recommended footprint (dimensions in mm)

8465286_footprint

STL4N10F7PowerFLAT™ 3.3x3.3 package information

DS9354 - Rev 5 page 11/14

Revision history

Table 8. Document revision history

Date Revision Changes

10-Jul-2013 1 First release.

21-Jan-2014 2Inserted Section 2.1: Electrical characteristics (curves).

Document status promoted form preliminary to production data.

19-Feb-2014 3

Added: ID (at TC = 25 °C and 125 °C), IDM and PTOT in Table 2

Modified: Figure 2 and 3

Minor text changes

10-Mar-2014 4Modified: marking in Table 1

Minor text changes

01-Feb-2018 5

Updated title, features and description on cover page.

Removed maturity status indication from cover page.

Updated Section 1 Εlectrical ratings.

Updated Table 6. Source drain diode.

Updated Section 2.1 Electrical characteristics (curves).

Minor text changes

STL4N10F7

DS9354 - Rev 5 page 12/14

Contents

1 Εlectrical ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Electrical characteristics (curves). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.1 PowerFLAT™ 3.3x3.3 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

STL4N10F7Contents

DS9354 - Rev 5 page 13/14

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to STproducts and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. STproducts are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2018 STMicroelectronics – All rights reserved

STL4N10F7

DS9354 - Rev 5 page 14/14