Nano Scale Low Power Amplifier Using Cascode

and Cascade Nutrilization in 45nm CMOS

Lavlesh Sharma and Shyam Akashe Electronics Department, ITM College, Gwalior, (M.P.), India

Email: lavlesh13@gmail.com, shyam.akashe@itmuniversity.ac.in

Abstract—A low voltage power amplifier mastered by

nanoscale CMOS technology has been designed for

communication technology and simulated using cadence

tool. Basically working of amplifier comprises of boosting

up the input to produce a larger version at the output of the

devices. An input signal is basically small i.e. a few millivolts

to a few microvolt. The main factors concerning small signal

amplifier are normally linearity of amplification and

magnitude of the output signal, since the value of voltage

and current are small in a small-signal amplifier, the

amount of power-bearing capacity and efficiency factor are

not of much consideration. An amplifier produces greater

amount of voltage at the output terminal with reference to

the input signal. Large-signal amplifiers, on the side

basically offer enough power to the output terminal of

power handling device, ranging from few watts to some

nano watt. An important function of a large-signal amplifier

is the power efficiency of circuit i.e. the maximum amount

of power bearing capacity of the circuit, and the impedance

of the output device. It is a small dimensional circuit due to

the use of nanoscale technology topologies. Basically the

circuit has been designed by using feed-back mechanism of

two stage amplifier, first is the differential amplifier which

helps in differently amplifying the signal between its two

inputs and the other is the common drain amplifier that

helps in producing low power to this power amplifier. The

circuit has been designed using 45nm technology. The main

objective of the circuit is to produce circuit as minimize as

possible in nanoscale or nanometres to produce circuit

parameters best suited for latest miniature technology.

Index Terms—VLSI devices, nanoscale technology, CMOS

technology, cascade amplifier, cascode amplifier, slew rate

I. INTRODUCTION

With the advent of technology new electronic devices

with precise parameters and increased future output are

designed. The technology lays more emphasis on

physical parameters of the devices to reduce the size of

device as much as possible, For achieving these

objectives we rely on VLSI technology plays a vital role

& it has been regarded as the future of electronic devices.

For decreasing the physical parameters of devices, nano-

technology is used especially for communication devices

today. This technology deals with reduction of the

dimensions in the smallest size in nano-meters or less,

creating miniature circuits or devices which are standard

Manuscript received July 3, 2015; revised March 22, 2016.

dimension tools that are used to manufacture devices and

simple structure. Theoretically 1 nanometre is equal to a

billion of a meter (e−10m). This technology includes all

of nano-technology except molecular manufacturing that

uses nano-scale to build devices structures, and system in

a molecular level [1]. Nano-scale technology was so

designed to build devices called nano-electronic devices

that include carbon, nano-wires, nano-tubes molecular

electronic devices, single-electron devices, resonant

tunnelling diodes and QCA such as Field-Effect

Transistors (FETs), diodes and molecular and mechanical

switches. The experimental of nano-scale devices can

prove non-volatile devices which maintain the states in a

few molecules [2]. This technology is the latest one to

fabricte integrated circuits. The dimension of device has

been applied consistently with many generations of

technology are in the nanometre scale that are suitable to

design smaller devices [3]. The CMOS technology

prefers high frequency operation and high integration

[4].

A. Power Amplifier

The power amplifier seems to be leading the output

voltage power with respect to the input supply given,

The two stage power amplifier was designed in this

current technology and results are noted below.

CMOS power amplifier is a type of power amplifier

designed by using CMOS transistors connected together

and get the output gain of amplifier [5]. The basic circuit

of CMOS power amplifier is displayed in Fig. 1.

Figure 1. Schematics of CMOS power amplifier

In the above figure Vin is the applied voltage to the

power amplifier having RB , Rc , & RE being the base,

collector and emitter resistance to the transistor Q1.

𝑅𝐵

𝑉𝑜𝑢𝑡

𝑉𝑖𝑛

𝑅𝐸

𝑅𝐶

𝑉𝐷

Q

International Journal of Electronics and Electrical Engineering Vol. 4, No. 6, December 2016

©2016 Int. J. Electron. Electr. Eng. 525doi: 10.18178/ijeee.4.6.525-529

B. Differential Amplifier

The power amplifier seems to be leading to

configurations which take advantage of a common source

type output stage in order to achieve higher load current

capability along with a higher output swing as mentioned

in reference. Differential amplifier is used to amplify the

difference between signals at its two inputs port. It

consists of two nMos0 Transistor one current and voltage

source and two resistance circuits. It is very easy to

design a specific gain because the input impedance of

amplifier is very high [6]. Basic structure of the

differential amplifier is depicted in Fig. 2. Where Q1, Q2

are two transistors having Vout as the output voltage and

R1 & R2 are the resistence.

Figure 2. Schematics of differential amplifier [7]

Here the drain current of the two complementary N-

MOS transistors is:

ID1 =Kn

2(VC − VX − VT1)

2 (1)

ID2=Kn

2(VC − VX − VT2)2 (2)

Small signal analysis of the circuit yields of the

differential gain of this circuit is:

∂(V01−V02 )

∂( VC−VC

) = - R.gm (3)

gm = ∂ID

∂VGS = √knID (4)

The differential output of the amplifier can be raised

sufficiently by using active loads instead of resistors and

by using cascode configuration, i.e., an intermediary

common gate stage between the common-source

transistors and the load transistors. Finally, the

differential output of the cascode stage must be converted

into single-ended output, by using a level-shifter and

buffer stage.

C. Common Drain Amplifier

The schematics of the common drain amplifier has

been shown in the Fig. 3. It consist of a voltage source,

current source a transistor and voltage out. Common

drain amplifier or source-follower amplifier uses a field-

effect transistor. The input signal is ejected between gate

port and drain.While the output is held between source

and drain port [8].

Figure 3. Schematics common drain amplifier [9]

D. Cascade and Cascode Amplifier

The circuit mainly comprises of two stages of power

amplifier circuits Cascade amplifier and Cascade

amplifier.

Cascade amplifier is a differential two stage amplifier

consisting of transistor and conductor amplifier. The

basic circuit of cascade is often designed from two

transistors as shown in figure below. The structure of

cascade amplifier is inter-connected between one acting

as common emitter or common source and other as

common base or common gate. It comprises of series of

amplifier stage interconnected one another amplifier

stage in which the output of one amplifier stage is

connected to the input of other amplifier stage [10]. It

offers low output gain whereas it requires low supply

Voltage, Cascade amplifier circuit is given in Fig. 4

below.

Figure 4. Schematics cascade amplifier circuit [11]

Cascode amplifier is basically a differential amplifier.

Cascode amplifier offers low output gain but requires

low supply voltage. The cascode amplifier is presented in

the Fig. 5.

𝑄2

𝑉𝑂𝑈𝑇 𝑄1

𝑉𝑑𝑐

𝑉𝑠𝑠

𝑅2 𝑅1

Q2 Q1

Vout

RL1

RE2

RB1

RL2

RE1

VDD

Vin

𝑉𝐷𝐷

𝑉𝑖𝑛 𝑉𝑜𝑢𝑡

𝐼𝐵

𝑄𝐵

International Journal of Electronics and Electrical Engineering Vol. 4, No. 6, December 2016

©2016 Int. J. Electron. Electr. Eng. 526

Figure 5. Schematics cascode amplifier circuit [12]

Basic circuit is designed from two transistors, One of

which acts as a common emitter or common source while

the other behaves as a common base or common gate

[12], [13]. It proves high output gain and high input

impedance but requires low power, two transistors and

high supply voltage [14].

II. PROPOSED CIRCUIT

The proposed circuit of the power amplifier is

presented in the Fig. 6, It comprises of feedback

mechanism., The output of one amplifier is connected to

the input of the second amplifier. The circuit is so

designed to have basic size as small as possible by

connecting various nano-scale based devices. It is

basically an arrangement in which output of cascode

amplifier is produced connected to the input of cascade

amplifier i.e. the overall circuit is followed up by a

feedback mechanism.

Figure 6. Proposed power amplifier

The circuit comprises of five RF CMOS transistor i.e.

3 NMOS and 2 PMOS transistor namely Modn1, Modn2,

Modn3, Modp1, Modp2, load resister (R), inductor (L),

input voltage (Vin), input bias (I), drain voltage (ad) and

source voltage (Vs). All the input values to the

parameters used in the circuit has been defined by the

means of table as under. The dimensions of all the

transistors given are taken to be equal in length but the

weight of the output transistor Modn3 is taken to be

double then that of other transistor, as it has to take the

load of the output produce. One Inductor and one

Resistor are also used to act as an impedance circuit of

respective dimensions. The circuit has been simulated

using cadence tool and has a major objective to acquire

smaller dimension and power consumption, for this

purpose 45 nano meter technology has been used.

Fig. 7 depicted the layout design of the proposed

power amplifier in which different connecting layers has

been shown side-wise.

Figure 7. Layout design of the proposed power amplifier circuit

III. RESULTS

The proposed power amplifier was simulated with

0.7V of drain voltage, -0.7V of source voltage and

350µA of bias current, In this circuit, the simulation of

frequency is shown below. The diameters of the circuit

parameters is shown below in the Table I.

TABLE I. DIMENSIONS

S. no. Elements Dimension

1 Modp1,Modp2 0.4um and 5um by length and

weight respectively

2 Modn1,Modn2 0.4um and 5um by length and

weight respectively

3 Modn3 0.4um and 10um by length and

weight respectively

4 Inductor 1uH

5 Resistor 100 ohms

The simulation values of the circuit parameters taken

very precisely has been shown in the Table II.

All the parameters are calculated with great precision

using 45nm technology to carry out the simulation

process and output has been noted at each point, From

the produced result it is concluded that the total power of

this amplifier is in micro-watt ranges which is achieved

International Journal of Electronics and Electrical Engineering Vol. 4, No. 6, December 2016

©2016 Int. J. Electron. Electr. Eng. 527

by having lower delays and targeted performance and

feedback mechanism.

TABLE II. OBSERVED OUTPUT PARAMETERS

S. no Parameters Technology Used

Input Supply

Output Output at 180nm

1 Total Power

(µw) 45nm 0.7V 175.0 70.5

2 Average power (µw)

45nm 0.7V 436 470

3 Slew Rate

(V/µs) 45nm 0.7V 129.2 36.54

4 Voltage gain (V)

45nm 0.7V 2.90 12.11

5 Settling

Time (ns) 45nm 0.7V 10 18

6 Leakage current

45nm 0.7V 390 452.16

7 Common

mode gain 45nm 0.7V 5 30

8 CMMR 45nm 0.7V 10 20

In the proposed mechanism both the amplifier cascade

and cascade amplifier are so connected that the input to

first amplifier after simulation of first stage is fed to the

input of second amplifier stage. The average power of the

circuit has also been calculated to be 436µs which is also

of great importance whereas the circuit working is

concerned, Moreover the parameters are observed at the

communicating frequency range i.e. 1.56MHZ which

help in implementation of various communicating

devices and settlements. The system setup time is also as

much low as 10ns i.e. also a very good factor in

determining the time taken by the circuit to respond to an

input value and voltage at .7V is observed to be 2.90V.

Power = Pi (dc) = Vcc . Icc (5)

Figure 8. Output response of power amplifier simulated at 180nm technology

The output response as compare to the 180nm is

shown in the Fig. 8 and it has been observed that the

leekages are very high in this case.

AC power delivered to the load RC may be:

Output power:

Po (𝑎𝑐) = VCE (rms) IC(𝑟𝑚𝑠) (6)

Po(𝑎𝑐) = IC2(rms) RC (7)

PO(𝑎𝑐) = VC

2(rms)

RC (8)

Similarly, efficiency of amplifier represents the

amount of ac power delivered from the dc source.

Efficiency of the amplifier can be calculated as:

% η = Po (ac )

Pi (dc ) * 100 % (9)

Slew Rate (SR) is the maximum possible rate of

change of the operational amplifier output voltage.

SR = dv0

dt |max V µ sec ⁄ (10)

SR = Imax

C (11)

In a similar manner, the amplifier gain & Common

Mode Rejection Ratio (CMRR) of the amplifier can be

calculated as:

𝐴𝑑 = 𝑣0

𝑣𝑖𝑑 = 𝑔𝑚 (𝑅𝐷||𝑟0) (12)

where, 𝐴𝑑 = differential gain, 𝑣0 = output voltage, 𝑣𝑖𝑑 =

differential input, 𝑔𝑚 = transconductance, 𝑅𝐷 = drain

resistance, and 𝑟0 = output resistance.

Common mode gain:

𝐴𝑐𝑚1 = 𝐴𝑐𝑚2 = 𝑣01

𝑣𝑖𝑐𝑚 =

𝑣02

𝑣𝑖𝑐𝑚 = -

𝑅𝐷1

𝑔𝑚 + 2𝑅𝑠𝑠

= - 𝑅𝐷

2𝑅𝑠𝑠 (13)

where: 𝐴𝑐𝑚1 = 𝐴𝑐𝑚2 = common mode gain and 𝑅𝑠𝑠 =

source resistance:

CMMR = Differential mode gain

Common mode gain =

Ad

Acm = gm Rss (14)

IV. CONCLUSION

Power amplifier has been generally used in the

electronic circuit for boosting up or strengthening the

applied signal, this has been done to obtain high variation

in the signal applied. The power amplifier based on 45nm

technology has been designed and simulated in this paper,

the amplifier output response is compared with the

180nm technology response, and all the result produced

is noted down precisely to obtain high accuracy and

circuit precision. The simulation results are observed at

1.56GHZ frequency i.e. is the input frequency of the

circuit, which is defined as the communication frequency

range that is more often used in communicating devices

and in technologies. The output voltage obtained is

2.90V at 1.56GHZ frequency. The output power of this

amplifier is noted to be 436 us at 1.56GHz frequency

with supply 0.7v which is very efficient as concern to

modern electronics. The power amplifier has very small

dimensions due to the involvement of nanoscale

technology this has been done to obtain miniaturisation

of circuit to be fitted and an inductor and resistor for

observing high gain.

The output response of the proposed power amplifier

is shown in Fig. 9 and all the circuit important factors

values has been shown side wise and in comparison to

180nm cmos the technology 45nm has produced some of

very vital and precise parametric values, leekages has

been efficiently reduced, power factors has also been

increased. It is also to be noted that the values of the

various leekages produced that are responsible for

International Journal of Electronics and Electrical Engineering Vol. 4, No. 6, December 2016

©2016 Int. J. Electron. Electr. Eng. 528

reducing the circuit efficiency has also reduced

effectively.

Figure 9. Output response of power amplifier simulated at 45nm

technology

ACKNOWLEDGEMENT

The Author would like to thanks ITM Universe

Gwalior and Cadence Pvt. Ltd. Bangalore.

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Lavlesh Sharma was born on 8th May 1988.

He received his Bachelor degree in Electronics and Communication (EC) from

Gwalior Engineering College, Gwalior (M.P.),

India in 2010. He is currently pursuing M.Tech degree in VLSI Design at Institute of

Technology and Management, Gwalior (M.P.),

India. His current research interests are nano-scale devices for reducing physical perameters

of electronics devices such as Amplifier also

minimizing various input values to give the desird output.

Shyam Akashe was born on 22nd May 1976. He received his M.Tech. from Institute of

Technology and Management, Gwalior (M.P.),

India in 2006. He is currently working as associate Professor in Electronics and

Instrumentation Engineering Department of

Institute of Technology and Management, Gwalior. Currently, he is pursuing his Ph.D.

from Thapar University, Patiala on the topic

of Low Power Memory Cell Design. His researches interests are VLSI Design, Low power and VLSI signal

processing, FPGA Design and communication.

International Journal of Electronics and Electrical Engineering Vol. 4, No. 6, December 2016

©2016 Int. J. Electron. Electr. Eng. 529

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