NATIONAL RADIO ASTRONOMY OBSERVATORY

CHARLOTTESVILLEJ VIRGINIA

ELECTRONICS DIVISION INTERNAL REPORT No. 235

LOW NOISE, 15 GHz, COOLED, GAAsFET AMPLIFIER

S. WEINREB

R. HARRIS

SEPTEMBER 1983

NUMBER OF COPIES: 150

LOW NOISE, 15 GHz, COOLED, GaAsFET AMPLIFIER

Table of Contents

I. Introduction • . • • • • • • • • • • • • • • • • • • . . . . 3II. Construction • • • • • • • • • • • • • • • • • • . . 5III. Adjustment and Test . • • • • • • 10

Figures

Figure 1 Amplifier Configuration • . • • . • • • • • . 4Figure 2 Three-Stage Amplifier Without Cover. . • • • 4Figure 3 Schematic of Single Amplifier Stage . • • • • . • • . • 7Figure 4 Amplifier Without Coaxial Components • • • • • • • • . 8Figure 5 Coaxial Components . • . • • • • • • • . 8Figure 6 Middle-Stage View of Amplifier • • • • • . • 9Figure 7 Close-Up View of FET • • • • • . 9Figure 8 Cryogenic Test Configuration • • • • • • . • 11Figure 9 Test Receiver • . • • • • . . • . 11Figure 10 Typical Gain and Noise Temperature . . • . • 12

References • • • • • • • • • • • • 14

Appendices

Appendix I Parts List for Ku-Band FET Amp (15.1 GHz) • • • • • • 15Appendix II (Drawings)

. 2.A. Amplifier Cover • • • • • • • ..

1 09B. Transistor Strap • • • • • . . • .C. Transformer Slug • • • . . 21D. Chassis •• • • • • • • • • • • . . .

22E. Chassis Details • • • • • • • • • • .F. Interstage Sup. • • • • • • • • • . . 24

• • 2625. . ::

.

G. Interstage Inner Conductor • • • • • • • • .H. Output Endplate . • . • • • • • • • • • • • .I. Input Endplate • • • • • • • • • • • • • • .J. Input SMA Modification • • • • • • • . . • . . 28K. Output SMA Modification . . . . • • • • • • .L. Mounting Plate with Output Transition • •. . • . 30

LOW NOISE 15 GHz COOLED GaAsFET AMPLIFIER

S. Weinreb and R. Harris

I. Introduction

This report describes the testing and construction of 60 amplifiers for

the VLA with the following specifications at a physical temperature of 15K:

FREQUENCY NOISE (including GAIN (including 5 toGHz isolator) 10 dB pad)

15.1 < 57K 19 + 1 dB

15.4 < 66K 19 + 3 dB

14.4 < 106K 19 + 3 dB

The amplifier is incorporated with an input isolator, output attenuator (for

matching), and a SMA to waveguide adaptor as shown in Figure 1. This configuration

is designed to easily fit the existing VLA dewar and improve the system noise

temperature from 300K to 100K.

Background information on the amplifier design is given in a paper [1]

by Tomassetti, Weinreb and Wellington describing a similar 10.7 GHz amplifer

and in a report [2] by Sierra describing noise parameter measurements and

computer programs used for the amplifier design. The major characteristics

of the design are as follows:

1) GaAs FET's in the 1.75 mm square package are used. Early experiments

with chips gave similar results and it was believed that better reliability

would be achieved with packaged devices.

2) A coaxial geometry with a round center conductor in a square groove

as suggested by Tomassetti is used. The characteristic impedance of this

-4 -

,

4.00ez, tzvl4,4

T H S34

1 1101110111110.100,

Fig. 1. Input isolator (lower left), amplifier, output 8 dB pad, and outputcoax-to-waveguide transition mounting plate. The isolator inputconnects via a short .141 coaxial cable to an input coax-to-waveguidetransition which is part of a gapped waveguide thermal transitionto 300K.

N

Fig. 2. Three-stage amplifier with cover removed. Input is at left andoutput and DC bias connector are at right.

geometry is given by Wheeler 3]. Tuning is accomplished by moving small X/4

slugs on the center conductor and DC blocks are formed by enclosing the FET

leads, cut to specified length, in Teflon tubing within a hollow center conductor.

DC bias is provided by small wires, X/4 long, soldered directly to the FET

package. This configuration has been found to be reliable, mechanically stable,

repeatable, and amenable to theoretical analysis.

3) The amplifier input and output return loss is reasonable ( 10 dB)

but an input isolator and output attenuator are used to provide > 20 dB return

loss. The FET source lead inductance is kept to a minimum.

II. Construction

The chassis is milled from copper stock and plated with 1.2 pm of gold.

A 7/64" carbide mill is useful for the rectangular slot. A thermostatically

controlled hot plate, low power microscope, and a 60W, 700°F soldering iron

with q, 1 mm tip are needed for construction. The assembly procedure is as

follows:

1) With chassis heated on a hot plate to 175-200°C, solder the input

end plate to the chassis, all chip capacitors except the ATC111 0.8 pF gate

bias.bypass, and the ground wire posts utilizing Ersin SN62-.028 rosin filled,

2% silver solder. Clean chassis with flux remover and check all chip

capacitor values with a capacitance meter.

2) Using the small soldering iron, solder chip resistors, bias resistors,

and protection diodes with SN62 solder.

3) Using the hot plate again, but at a temperature of 100°-120°C,

solder the ATC111 0.8 pF gate bias bypass capacitors using Alpha 20E2 solder

and Superior #30 flux.

-6-

4) Glue the rexolite support on interstage center conductors as shown

in Figure 5 using Eastman 910 adhesive.

5) Trim the leads on the MGF1412-09 second-stage FET to 1.8 mm on both

source leads and to the values given in Figure 3 for gate and drain leads.

Solder #40 enameled-copper bias leads to the FET.

6) Install #22 Teflon tubing (OD = 0.94 mm, ID = 0.43 mm) in the center

conductors cutting off the tubing 0.25 mm beyond the end of the center conductor.

Install tuning slugs on center conductors checking for a firm, sliding fit.

7) Install second-stage FET together with both interstage networks into

the chassis and fasten source lead champs.

8) Prepare MGF1412-10 third-stage FET as in paragraph 5), above, and

install in chassis by bending the gate lead.

9) Using the hot plate at 200°C, solder the DC bias connector into the

output end plate with SN62 solder. Solder #32 enameled copper bias wires to

the connector pins using the small soldering iron and SN62 solder. Bolt the

output end plate to the chassis and solder bias wires to chip capacitors.

10) Prepare and install the NE67383 first-stage FET as in paragraph 5),

above.

11) Solder all FET bias wires using SN62 solder except the tie connection

to the ATC111 gate bias bypass capacitor is made with 20E2 solder.

12) Install input and output SMA connectors complete with Teflon tubing

and tuning slugs.

13) Apply a small amount of polystyrene cement to the FET lead to Teflon

tubing interface points.

BIAS

GAT

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-8-

104W, ,V 'A'

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Fig. 4. Amplifier with coaxial components removed.

Fig. 5. Close-up view of sliding transformers (top), centerconductor, and Teflon-tubing DC blocks.

-9-

Fig. 6. Middle-stage view of amplifier.

Fig. 7. Close-up view of FET, bias leads (#40 enameled copper wire), and0.8 pF gate bypass capacitor. Note the Teflon tubing protrudingfrom within center conductor and pressing against FET for mechanicalstability.

-10-

III. Adjustment and Test

The test configuration for the amplifier is shown in Figures 8 and 9;

this equipment is used in conjunction with an Apple computer, ADIOS A/D

interface [4], and NOISE1 program to give data output as shown in Figure 10.

The accuracy of the low-noise temperature measurements is increased by

utilizing a cooled 20 dB Narda Model 4779 attenuator at the amplifier input.

By cooling this attenuator from 300K to 15K, the temperature added to the

amplifier noise temperature of ix , 40K is decreased from 300K to 18K. The

error due to noise source or detector-law inaccuracy is then reduced by a

factor of (300 + 40)/(18 + 40) = 5.9.

The noise source, input coaxial line, attenuator cascade was calibrated

at the isolator input connector by comparison with a NRAO liquid nitrogen

and room temperature noise standard. This was performed with the test dewar

open at 300K. The change in the attenuation value due to cooling from 300K

to 15K was measured at DC and was an increase of 0.18 + .01 dB for two Narda

attenuators. This is approximately compensated by a decrease in the loss of

the coaxial lines as determined from measurements described in a previous

report [5]. An error of 0.1 dB in the noise source excess noise temperature

ratio would produce an amplifier noise temperature error of 1.3K. The

temperature of the cooled attenuator is monitored with a Lake Shore Cryotronics

DG-400 sensor.

The amplifier is tuned at 300K for minimum noise at 15.1 GHz and for

gain flatness. An initial bias of 5V, 5 mA; 5.5V, 10 mA; and 4V, 10 mA is

used for the first, second and third stages respectively at 300K. These values

were then optimized at 15K for minimum noise and gain within specifications;

Tum ,SCILLA

Fig. 8. Test configuration showing HP346B noise source (top, middle), low-losscoaxial thermal transition into dewar, Narda 20 dB attenuator withtemperature sensor, Pamtech input isolator, amplifier under test,Narda 7 or 8 dB output attenuator, output transition, isolator, andtest receiver.

Fig. 9. Test receiver consisting of an Avantek 2-8 GHz YIG-tuned oscillator,Aertech RX16000 frequency doubler, isolator, directional coupler toprovide reflectometer source, and mixer-preamp for noise temperaturemeasurements.

12502

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14:27.4 06/16/83 ZERn=7.8F.GH2 NOISE GAIN,DB

DB=6 TF=15.4 -1OR=5.73F,GH2 NOISE' GAIN,08

14.4 89.3 17.7 14.5 71 20.514.6 61 21 14.7 51.1 20.814.8 44.5 20.7 14.9 43.7 20.515 47.5 19.8 15.1 47.4 15.615.2 49.6 19.4 15.3 57.1; 19.715.4 55.6 19 15.5 59.6 18.3

1 0 3001, NITH OPT ''OLD BIAS07127.2 06/17/83 TA0=376.4 TL0=33?I 15000 61=10.R GH=1? T=?q7.11

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DB=6 TF=300 -1OP=9.73F,61-1.7 NOIc.F GAIN,08

14.4 541.7 11.2 14.5 4c9.'› 12.614.6 408.3 12.7 14.7 37.;•7 12.614.8 352 12.5 14.q ' 411.1 12.215 732 11.6 15.1 341.4 11.515.2 333.5 11.3 15.7 349 11.115, 4 356 10.8 15. 386.5 10.3

Fig. 10. Typical gain and noise temperature for an amplifierincluding input isolator and output 7 dB attenuatorat physical temperatures of 15K (top) and 300K.

-13-

typical final values were 4V, 5 mA; 5.5V, 15 mA; and 4V, 8 mA. The amplifier

gain including a 7 dB pad is typically 12 dB at 300K and 19 dB at 15K as

shown in Figure 10. The typical improvement in noise temperature is a factor

of A, 8.

A large variation of cold noise temperature with the NE67383 transistor

batch was observed. An initial batch of 20 averaged 35K at optimum frequency;

a second batch 40K; and the third batch 47K. The lowest noise temperature

was 31K and A, 15% of the transistors gave noise temperatures > 50K and were

rejected. Early tests with the NE13783 produced noise temperatures above 60K.

-14-

REFERENCES

[1] G. Tomassetti, S. Weinreb, and K. Wellington, "Low-Noise 10.7 GHz Cooled

GaAs FET Amplifier," Electronics Letters, vol. 17, no. 25/26,

December 10, 1981, pp. 949-951.

[2] M. Sierra, "15 GHz Cooled GaAsFET Amplifier-Design Background Information,"

NRAO Electronics Division Internal Report No. 229, June 1982.

[3] H. A. Wheeler, "Transmission-Line Impedance Curves," Proc. IRE, vol. 38,

no. 12, December 1950, pp. 1400-1403.

[4] G. Weinreb and S. Weinreb, "ADIOS - Analog-Digital Input Output System

for Apple Computer," NRAO Electronics Division Internal Report No. 212,

April 1981.

[5] S. Weinreb, "Cryogenic Performance of Microwave Terminations, Attenuators,

Absorbers, and Coaxial Cable," NRAO Electronics Division Internal

Report No. 223, January 1982.

PARTS LIST

Ku-Band FET Amp (15.1 GHz)

DATE

June 23, 1983

REVISION

ITEM

QUANTITY

REF.

DESIG.

DESCRIPTION

MFG.

PART NUMBER

11

15 GHz FET amplifier schematic

NRAO

A2.613S-01

21

Chassis

NRAO

D2.613M-73,

sht.

1,

Chassis details

NRAO

C2.613M-73,

sht.

2

41 6

_Amplifier cover

Transistor strap

NRAO

NRAO

C2.613M-70

B2.613M-71

5

1Output end plate

.NRAO

B2.613M-77

_

.1

Input end plate

NRAO

B2.613M-78

,

4Transformer slug (15 ohm)

,

NRAO

B2.613,M-72

1Transformer slug (26 ohm)

NRAO

B2.613M-72

101

Transformer slug (22 ohm)

NRAO

B2.613M-72

112

Interstage support

NRAO

B2.613M-75

,

122

.Interstage inner conductor

.NRAO

B2.613M-76

131

Mounting plate with output transition

NRAO

.

C2.613M-81

,

141

Input SMA modification

Omni-Spectra (modified)

204CC/NRAO B2.613M79

151

..._

Output SMA modification

Omni-Spectra (modified)

_

204CC/NRAO B2.613M80

PARTS LIST

Ku-Band FET Amp (15.1 GHz)

June 23, 1983

REVISION

DATE

ITEM

QUANTITY

REF.

DESIG.

DESCRIPTION

MFG.

PART NUMBER

164

SMA connector

Omni-Spectra

201-1A

171

Power connector

Micro-Tech

ER-7S-6

186

X/4 transformer dielectric, Teflon

Alpha

AWG-24-LW

191

FET

first stage

NEC

NE67383

201

FET, second stage

Mitsubishi

MGF-1412-09

IFET bias leads, 40 AWG T2 Beldure

;-e-

8046

242

Finger stock

Instrument Specialties

256

0-80 x 3/16 Filister HD screws (goldplated

26

84-40 x 3/16 socket HD SS screws

All-Metal

273

4-4

0 x

5/1

6 socket HD SS screws

All-Metal

282

2-5

6 x

1/2

socket HD SS screws

All-Metal

29

42-5

6 x

1/4

so

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HD SS screws

All-Metal

302

2-5

6 x

3/1

6 socket HD SS screws

All-Metal

PAR

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