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NCSX Project MeetingMarch 21, 2003
G. E. OliaroSlide 2
NCSX
Primary Design Basis of WBS 5
• The NCSX Design Leverages the NSTX Technology and Experience Base and Provides a Low Risk - Cost Effective Implementation.– Commercial-Off-The-Shelf (COTS)
– Maximize Use of Open Source (Free) Software
– Just-In-Time Design & Purchase
– Steer Current NSTX Upgrades to Benefit NCSX• Network• CAMAC Replacement to CPCI & PCI• Synchronization System• Plasma Control (FIMM)
– CAMAC Instrumentation Will Not Be Used In Design
– Maximize Use of Experience Base at PPPL
NCSX Project MeetingMarch 21, 2003
G. E. OliaroSlide 3
NCSX
WBS 5 Scope
• WBS 51 TCP/IP network Infrastructure• WBS 52 Central Facilities I&C• WBS 53 Diagnostic Data Acquisition and Facility Computing• WBS 54 Facility Timing and Synchronization• WBS 55 Real Time Plasma and Power Supply Control System• WBS 56 Central Safety and Interlock System• WBS 57 Control Room Facility• WBS 58 Central I&C Management and Integration
NCSX Project MeetingMarch 21, 2003
G. E. OliaroSlide 4
NCSX
Questions in NCSX WBS5 Design at CDR
• A non-CAMAC design for a facility Timing and Synchronization System
– As of the CDR:• Use the BNL/ORNL-Spallation_Neutron_Source (10
MHz) timing system
• Upgrade NSTX (TFTR) Design to Current Technology Base
• Migration from VMS based MDSplus to UNIX
NCSX Project MeetingMarch 21, 2003
G. E. OliaroSlide 5
NCSX
WBS 54 Facility Timing and Synchronization
• Progress– A working prototype of a PCI based Timing And Synchronization
System will be deployed for the next NSTX run.
– Xilinx XC2S200, Spartan II, 200,000 logic & RAM gate FPGA
– CeSys PCI XC2S board ~$300
– Each board has 6 multi-function channels• Timing• Timed Gate• Time Interval Counter• Clock Generator• Timing & Sequencing
– A Signal Conditioning and Interface board has been designed and is being sent out for fabrication now.
NCSX Project MeetingMarch 21, 2003
G. E. OliaroSlide 6
NCSX
WBS 54 Facility Timing and Synchronization
• Specifications– Programmable base clock: 1MHz(NSTX) and 10MHz(NCSX)
– 128 Event codes
– Timing Resolution: 1us@1MHz and 100ns@10MHz
– Timed gate duration: 1.2 hours (32 bits)
– Outputs: Transformer coupled, TTL, Opto-Isolated
– Output trigger: 1us
NCSX Project MeetingMarch 21, 2003
G. E. OliaroSlide 7
NCSX
Stepper Motor Controller
PCI Timing Module 32ch, 80KHz, SSH Digitizer ($2.5K)
Stepper Motor Driver
NSTX Technology Transfer To NCSXLi Pellet Injector Control System
NCSX Project MeetingMarch 21, 2003
G. E. OliaroSlide 8
NCSX
WBS 54 Facility Timing and Synchronization
• Clock application software is essentially complete.
• A standalone Windows GUI is being used for development now.
• A Windows DLL that will used by LabView and MDSplus is being tested.
NCSX Project MeetingMarch 21, 2003
G. E. OliaroSlide 9
NCSX
WBS 53 Diagnostic Data Acquisition and Facility Computing
• VMS based MDSplus was proposed as the Data Acquisition and Data Management & Storage System for NCSX
• MDSplus services have now all been successfully ported to UNIX by the MIT developers– As of 2/24/03, all 5 CMOD CAMAC highways have been moved to
a LINUX MDSplus server: alcserv II
– MIT has 3 UNIX servers, 12 UNIX workstations, and 24 VMS workstations.
• 12 VMS workstations to be replaced with UNIX by end of FY03• MIT will be VMS free by end of FY04
NCSX Project MeetingMarch 21, 2003
G. E. OliaroSlide 10
NCSX
WBS 53 Diagnostic Data Acquisition and Facility Computing
• PPPL progress towards UNIX based MDSplus– UNIX based MDSplus has been used to store and serve TRANSP
data to local and offsite users for about a year. There are no performance issues with this port.
– NSTX Data acquisition team is now serving NSTX data trees with a test LINUX server.
– We will serve production NSTX data for the next NSTX run in October.
• PPPL will have a strong base of UNIX based MDSplus experience for NCSX design and startup requirements
NCSX Project MeetingMarch 21, 2003
G. E. OliaroSlide 11
NCSX
Conclusions
• The NCSX Design Leverages the NSTX Technology and Experience Base and Provides a Low Risk - Cost Effective Implementation.