Networks-on-Chip (NOCS 2018) October 4 – 5, 2018 12th IEEE ... · NoCs for 2.5D Integrated Systems: A Case for AWGRs Sebastian Werner, Pouya Fotouhi, Roberto Proietti, Xiao Xian

8/31/2018 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018) October 4 – 5, 2018 | Torino, Italy

https://www.nocs2018.conf.kth.se/program/ 1/15

12th IEEE/ACM International Symposium onNetworks-on-Chip (NOCS 2018) October 4 – 5, 2018| Torino, ItalyCo-located with Embedded Systems Week (ESWEEK)

Advance Program

Thursday October 4, 2018

Time Activity Location

9:00-9:10 Opening Ceremony TBD

9:10-10:10

Keynote I

Many-Core SoC in Nanoscale CMOS: Challenges &

Opportunities

Vivek De (Intel Corporation)

TBD

10:10-10:30 Posters and Co�ee Break TBD

10:30-12:35 Regular Paper Session I: Interconnected Multiprocessor

64- NoC-Based Support of Heterogeneous Cache-

Coherence Models for Accelerators

Davide Giri, Paolo Mantovani and Luca Carloni

(Columbia University)

TBD

https://www.nocs2018.conf.kth.se/



73- Exploration of Memory and Cluster Modes in

Directory-Based Many-Core CMPs

Subodha Charles (University of Florida), Chetan Arvind

Patil (Arizona State University), Umit Ogras (Arizona

State University) and Prabhat Mishra (University of

Florida)

31- Accurate Congestion Control for RDMA Transfers

Dimitrios Giannopoulos, Evangelos Mageiropoulos,

Nikolaos Chrysos, Giannis Vardas, Leandros Tzanakis

and Manolis Katevenis (Foundation for Research and

Technology Hellas)

56- Testing WiNoC-Enabled Multicore Chips with BIST

for Wireless Interconnects

Abhishek Vashist, Amlan Ganguly and Mark Indovina

(Rochester Institute of Technology)

17- Towards Energy-efficient High-throughput Photonic

NoCs for 2.5D Integrated Systems: A Case for AWGRs

Sebastian Werner, Pouya Fotouhi, Roberto Proietti, Xiao

Xian and S.J. Ben Yoo (University of California, Davis)

12:35-14:00 Lunch TBD

14:00-16:05 Best Paper Session TBD



19 (Best paper candidate) - AxNoC: Low-power

Approximate Network-on-Chips using Critical-Path

Isolation

Akram Ben Ahmed (Keio University), Daichi Fujiki

(University of Michigan), Hiroki Matsutani (Keio

University), Michihiro Koibuchi (National Institute of

Informatics, Tokyo) and Hideharo Amano (Keio

University)

50 (Best paper candidate) - DAPPER: Data Aware

Approximate NoC for GPGPU architectures

Venkata Yaswanth Raparti and Sudeep Pasricha

(Colorado State University)

68 (Best paper candidate) - FreewayNoC: A DDR NoC

with Pipeline Bypassing

Ahsen Ejaz (Chalmers University of Technology),

Vassilios Papaefstathiou (Foundation for Research &

Technology – Hellas) and Ioannis Sourdis (Chalmers

University of Technology)

34- Brownian Bubble Router: Enabling Deadlock

Freedom via Guaranteed Forward Progress

Mayank Parasar, Ankit Sinha and Tushar Krishna

(Georgia Institute of Technology)



74- Abetting Planned Obsolescence by Aging 3D

Networks-on-Chip

Sourav Das (Washington State University), Kanad Basu

(New York University), Jana Doppa (Washington State

University), Partha Pratim Pande (Washington State

University), Ramesh Karri (New York University) and

Krishnendu Chakrabarty (Duke University)


16:30-17:45

Special Session I: "Securing Networks-on-Chip: A Cross-

Technology Perspective”

Session organizer: Sudeep Pasricha (Colorado State

University)

Session speakers: Sudeep Pasricha (Colorado State

University), Tushar Krishna (Georgia Institute of

Technology), Travis Boraten (Ohio University)

TBD

17:45-18:00 Poster Session

57- A Learning-Based Thermal-Sensitive Routing for

Power Optimization of Optical NoCs

Yaoyao Ye, Zhe Zhang, Renjie Yao and Weichen Liu

59- Approximate Communication for Energy Efficient

Networks on Chip

TBD



Maurizio Palesi, Davide Patti, Salvatore Monteleone,

Giuseppe Ascia, John Jose and Vincenzo Catania

45- Improving the Efficiency of Router Bypass

Iván Pérez, Enrique Vallejo and Ramón Beivide

62- An Operating System Service for Remote Memory

Accesses in Low-Power NoC-Based Manycores

Pedro Henrique Penna, Matheus Souza, Emmanuel

Podestá Junior, Bruno Marques do Nascimento, Márcio

Castro, François Broquedis, Henrique Freitas and Jean-

François Méhaut

19:00 ~ Banquet [https://www.nocs2018.conf.kth.se/events/] TBD

Friday October 5, 2018

Time Activity Location

9:00-10:00

Keynote II

NoCs: a short history of success and a long future

Giovanni De Micheli (EPF Lausanne, Switzerland)

TBD


10:30-11:45 Regular Paper Session II: Cutting-Edge Network-on-Chip

21- A Low-overhead Multicast Bufferless Router with

Reconfigurable Banyan Network

TBD

https://www.nocs2018.conf.kth.se/events/



Chaochao Feng (National University of Defense

Technology Changsha), Zhuofan Liao (Changsha

University of Science & Technology), Zhenyu Zhao

(National University of Defense Technology Changsha)

and Xiaowei He (National University of Defense

Technology Changsha)

63- Critical Packet Prioritisation by Slack-Aware Re-

routing in On-Chip Networks

Abhijit Das (Indian Institute of Technology Guwahati),

Sarath Babu (Government Engineering College, Idukki),

John Jose (Indian Institute of Technology Guwahati),

Sangeetha Jose (Government Engineering College,

Idukki) and Maurizio Palesi

(University of Catania)

32- A Diversity Scheme to Enhance the Reliability of

Wireless NoC in Multi-Path Channel Environment

Joel Ortiz Sosa (University of Rennes), Olivier Sentieys

(University of Rennes) and Christian Roland (Université

Bretagne Sud)

11:45-12:35

Tutorial: "Approximate Computing for Networks on Chip"

Session organizers: Dr. Jie Han (University of Alberta)

and Dr. Eun Jung (EJ) Kim (Texas A&M University)

TBD



12:35-14:00 Lunch TBD

14:00~15:15

Industrial Session

1- Challenges and Opportunities for Edge Cloud

architectures

Francesc Guim (Intel Corporation)

2- Identifying the gaps between academic research and

physical realization of NoCs

Zhiguo Ge (Huawei International Pte Ltd.)

3- Co-Design and Abstraction of a Network-on-Chip

Using Deterministic Network Calculus

Benoît Dupont de Dinechin (Kalray S.A.)

TBD

15:15-16:05

Special Session II: “Networks Meet Network: Shaping the

On-chip Network for Complex Networks”

Session organizers: Xiaohang Wang (South China

University of Technology) and Amit Kumar Singh

(University of Essex)

Session speakers: Masoud Daneshtalab (Mälardalen

University), Amit Kumar Singh (University of Essex)

TBD


16:30-17:45 Special Session III: “Realistic Wireless Channel Modelling for

Parallel Applications on NoC-based MPSoC”

TBD



Session organizers and speakers: Jean-Philippe Diguet

(Lab-STICC), Sujay Deb (IIIT Delhi), Sergi Abadal

(Universitat Politècnica de Catalunya)

17:45-18:00 Closing Remark with Best Paper Announcement TBD

Keynote Talks

Keynote 1

Date: October 4th, 2018

Speaker: Vivek De (Intel)

Title: Many-Core SoC in Nanoscale CMOS: Challenges & Opportunities

Abstract

Many-core SoC designs in scaled CMOS process demand wide dynamic

voltage-frequency operating range, spanning multi-threaded high-throughput

near-threshold voltage (NTV) to single-threaded burst performance modes, as

well as fine-grain multi-voltage design and spatio-temporal power

management to deliver maximum performance under stringent thermal and

energy constraints. Interconnect scaling bottlenecks, process-voltage-

temperature variations and aging-induced degradation pose major challenges

going forward. We present key circuit and design techniques for logic,

memory and on-die interconnect networks that enable efficient, variation-

tolerant and resilient many-core SoC designs in nanoscale CMOS.

Biography



Vivek De is an Intel Fellow and Director of Circuit Technology Research in

Intel Labs. He is responsible for providing strategic technical directions for

long term research in future circuit technologies and leading energy efficiency

research across the hardware stack. He has 269 publications in refereed

international conferences and journals with a citation H-index of 73, and 220

patents issued with 30 more patents filed (pending). He received an Intel

Achievement Award for his contributions to an integrated voltage regulator

technology. He received a Best Paper Award at the 1996 IEEE International

ASIC Conference, and nominations for Best Paper Awards at the 2007

IEEE/ACM Design Automation Conference (DAC) and 2008 IEEE/ACM

International Conference on Computer-Aided Design (ICCAD). He also co-

authored a paper nominated for the Best Student Paper Award at the 2017

IEEE International Electron Devices Meeting (IEDM). One of his publications

was recognized in the 2013 IEEE/ACM Design Automation Conference (DAC)

as one of the "Top 10 Cited Papers in 50 Years of DAC". Another one of his

publications received the “Most Frequently Cited Paper Award” in the IEEE

Symposium on VLSI Circuits at its 30th Anniversary in 2017. He was

recognized as a Prolific Contributor to the IEEE International Solid-State

Circuits Conference (ISSCC) at its 60th Anniversary in 2013, and a Top 10

Contributor to the IEEE Symposium on VLSI Circuits at its 30th Anniversary in



2017 . He served as an IEEE/EDS Distinguished Lecturer in 2011 and an

IEEE/SSCS Distinguished Lecturer in 2017-18. He received the 2017

Distinguished Alumnus Award from the Indian Institute of Technology (IIT)

Madras. He received a B.Tech from IIT Madras, India, a MS from Duke

University, Durham, North Carolina, and a PhD from Rensselaer Polytechnic

Institute, Troy, New York, all in Electrical Engineering. He is a Fellow of the

IEEE.

Keynote 2

Date: October 5th, 2018

Speaker: Giovanni De Micheli (EPF Lausanne, Switzerland)

Title: NoCs: a short history of success and a long future

Abstract

The broad application of NoCs in IC design has been enabled by NoC

synthesis tools that evolved from university prototypes to full commercial

synthesis flows. NoC embodiments are ubiquitously present in circuits and

systems. As systems evolve to include new components and features, NoCs

will play even a more important role as the smart connect that can enable

heterogeneity.Thus this field will both evolve in diversity of implementations as

well in the search of both higher performance and lower power solutions.

Biography



Giovanni De Micheli is Professor and Director of the Institute of Electrical

Engineering and of the Integrated Systems Centre at EPF Lausanne,

Switzerland. He is program leader of the Nano-Tera.ch program. Previously,

he was Professor of Electrical Engineering at Stanford University.He holds a

Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D.

degree in Electrical Engineering and Computer Science (University of

California at Berkeley, 1980 and 1983).

Prof. De Micheli is a Fellow of ACM and IEEE, a member of the Academia

Europaea and an International Honorary member of the American Academy of

Arts and Sciences. His research interests include several aspects of design

technologies for integrated circuits and systems, such as synthesis for

emerging technologies, networks on chips and 3D integration. He is also

interested in heterogeneous platform design including electrical components

and biosensors, as well as in data processing of biomedical information. He is

author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994,

co-author and/or co-editor of eight other books and of over 750 technical

articles. His citation h-index is 93 according to Google Scholar. He is member



of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D)

and STMicroelectronics.

Prof. De Micheli is the recipient of the 2016 IEEE/CS Harry Goode award for

seminal contributions to design and design tools of Networks on Chips, the

2016 EDAA Lifetime Achievement Award, the 2012 IEEE/CAS Mac Van

Valkenburg award for contributions to theory, practice and experimentation in

design methods and tools and the 2003 IEEE Emanuel Piore Award for

contributions to computer-aided synthesis of digital systems. He received also

the Golden Jubilee Medal for outstanding contributions to the IEEE CAS

Society in 2000, the D. Pederson Award for the best paper on the IEEE

Transactions on CAD/ICAS in 1987, and several Best Paper Awards,

including DAC (1983 and 1993), DATE (2005), Nanoarch (2010 and 2012)

and Mobihealth(2016).

He has been serving IEEE in several capacities, namely: Division 1 Director

(2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-

7), President of the IEEE CAS Society (2003), Editor in Chief of the IEEE

Transactions on CAD/ICAS (1997-2001). He has been Chair of several

conferences, including Memocode (2014) DATE (2010), pHealth (2006), VLSI

SOC (2006), DAC (2000) and ICCD (1989).

Special Sessions and Tutorial

Special Sessions

1. “Securing Networks-on-Chip: A Cross-Technology Perspective”

Organizer: Sudeep Pasricha, Colorado State University



Other Speakers: Tushar Krishna, Georgia Institute of Technology; Travis Boraten, Ohio University

Abstract: This special session will discuss the security challenges in NoC design across the electrical,

photonic, and wireless implementation domains, and propose several promising solutions to overcome

them. The NOCS community will �nd the topic of this special session to be extremely relevant and

interesting as traditionally the community has not focused on security as much as other design metrics

such as performance or energy. Not only will the special session educate and inform attendees about

security issues in NoCs across a broad set of implementation technologies, but many of the solutions that

will be presented are likely to spark new ideas for NOCS attendees to integrate security into their sub-

domain of expertise. This special session will foster a valuable cross-domain exchange of ideas between

experts in security, emerging technologies, and NoC design, that is very likely to bene�t the industry

practitioners and researchers in the NOCS community.

2. “Realistic Wireless Channel Modelling for Parallel Applications on NoC-based MPSoC”

Organizers/Speakers: Jean-Philippe Diguet, Lab-STICC, France; Sujay Deb, IIIT Delhi, India; Sergi Abadal,

Universitat Politècnica de Catalunya, Spain

Abstract: Wireless Network-on-Chip (WNoC) is considered as a promising solution in the context of

manycore architectures. Unfortunately, WNoC still su�er from important limitations. The �rst one is the

power consumption of the analog part of the transceivers with is one order of magnitude (tens mW)

larger than the power consumption of digital components. Secondly, at network level no feasible

simulation is possible today with the existing setup. Apart from transceiver component in WNoC, channel

modelling is one of the major concerns. Finally, multiple important radio parameters with strong impacts

on communication quality and e�ciency are not considered or based on simple and non-meaningful

models. The special session addresses this speci�c but key challenge for future NoC. Research in that

area require multidisciplinary teams including NoC experts (architecture, protocols, simulators) and High

Frequency radio experts (channel modeling, transceiver design along with digital components, antennas).

It will be based on talks and papers from three research groups that investigate this important problem

with a multidisciplinary approach.

3. “Networks Meet Network: Shaping the On-chip Network for Complex Networks”

Organizers: Xiaohang Wang, South China University of Technology; Amit Kumar Singh, University of Essex,

UK.

Speakers: Masoud Daneshtalab, Amit Kumar Singh

Abstract: Various emerging applications are in the form of complex networks, e.g., neural networks, deep

learning, social networks, protein networks, brain neural connections, and many other applications. A key

feature of these applications are "linked", i.e., time varying topologies, complex connection structure, and

highly dynamic runtime behaviors. Conventional many-core architecture are ine�cient for these "linked"

complex network applications, as most of them are using �xed, low-degree mesh network for sustaining

on-chip communication, which cannot be adapted to the highly dynamical features of these applications.

Therefore, this special session, covers the topic of the interplay of new on-chip networks which can adapt

their communication infrastructure to these complex network applications.



Tutorial

"Approximate Computing for Networks on Chip"

Organizers: Dr. Jie Han (University of Alberta) and Dr. Eun Jung (EJ) Kim (Texas A&M University).

1. Part I: "Approximate Arithmetic Circuits"

Speaker: Dr. Jie Han

Abstract: The demand of higher speed and power e�ciency, as well as the feature of error

resilience in many applications (e.g., multimedia, recognition and data analytics), have driven the

development of approximate computing circuits. Often as the most important arithmetic modules

in a processor, adders, multipliers and dividers determine the performance and energy e�ciency of

many computing tasks. In this talk, a review and classi�cation are presented for the current designs

of approximate arithmetic circuits including adders, multipliers and dividers. A comprehensive and

comparative evaluation of their error and circuit characteristics is performed for understanding the

features of various designs. Image processing and cerebellar models are considered to show the

e�ectiveness of the approximate arithmetic circuits in improving the energy e�ciency and

performance of computation-intensive applications.

2. Part II: "Approximate Networks on Chip"

Speaker: Dr. Eun Jung (EJ) Kim

Abstract: The trend of unsustainable power consumption and large memory bandwidth demands in

massively parallel multicore systems, with the advent of the big data era, has brought upon the

onset of alternate computation paradigms utilizing heterogeneity, specialization, processor-in-

memory and approximation. Approximate Computing is being touted as a viable solution for high

performance computation by relaxing the accuracy constraints of applications. This trend has been

accentuated by emerging data intensive applications in domains like image/video processing,

machine learning and big data analytics that allow inaccurate outputs within an acceptable

variance. Leveraging relaxed accuracy for high throughput in Networks-onChip (NoCs), which have

rapidly become the accepted method for connecting a large number of on-chip components, has

not yet been explored. In this talk, I will present APPROX-NoC, a hardware data approximation

framework with an online data error control mechanism for high performance NoCs. APPROX-NoC

facilitates approximate matching of data patterns, within a controllable value range, to compress

them thereby reducing the volume of data movement across the chip.

Industrial Session

1. "Challenges and Opportunities for Edge Cloud architectures"

Francesc Guim (Intel Corporation)

2. "Identifying the gaps between academic research and physical realization of NoCs"

Zhiguo Ge (Huawei International Pte Ltd)



3. "Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus"

Benoît Dupont de Dinechin (Kalray S.A.)

Documents

Networks-on-Chip (NOCS 2018) October 4 – 5, 2018 12th IEEE ... · NoCs for 2.5D Integrated Systems: A Case for AWGRs Sebastian Werner, Pouya Fotouhi, Roberto Proietti, Xiao Xian