New channel engineering for the low power CMOS … · Stress Memorization Technique (SMT) ... K.Rim et al., IEDM 2003, [2] ... Surface carrier concentration N s (cm-2) 30nm BOX NiSi

1 © 2010 Toshiba Corporation 1

New channel engineering for the low power CMOS technology

東芝グループは、持続可能な

地球の未来に貢献します。

Akira Nishiyama Corporate R & D Center, Toshiba Corporation


SMART Community: 3 Major Streams

* Intelligent Transport System

Smart Grid → Stream of Energy

Cloud Computing →Stream of Information

Intelligent Transport System Smart logistics

Contribution of Semiconductor Industry ?

→ Stream of people, goods


E-mail

PhotographNewspaper

Phone（1hr）

Music（1hr）

TV（1hr）

HD-TV（1hr）2k*4k

4K*8k

100

1000

10000

100000

1E+06

1E+07

1E+08

1E+09

1E+10

1E+11

1E+12

1E+13

1E+14

1E+15

1E+16

Media （without comperssion）

Dat

a[bi

t]

Explosion of Information

1000 words

３Ｄ TV

Larger Data Files Ｘ More Frequent Access ll • High Speed Processing • Large data capacity with low cost

Data Center of Apple (50,000m2) (P.30, Bussinessweek Sept.6, 2010)

Social Demands


Power Consumption increase for IT facilities

Large Power Consumption by IT facilities → Measures for Dramatic Energy Saving Requested.

Power Consumption (x1E8 kWh) x

World IT facilities 15% of world

total power

Source: METI Japan http://www.meti.go.jp/committee/materials/downloadfiles/g80520c03j.pdf


Sensor Network Market inside Japan

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

1 2

健康管理

その他

設備管理

防災・環境

交通

セキュリティー

２００７２０１５

Security

Environment Facility

Health Care

Nikkei Electronics 2009 December 28

～13B$ market in 2015 (Japan Only)

Mar

ket

[T¥]

Transportation system

10B$


Sensor Network and Sensor Node

S

S

S

S

S コイン電池１個で何年間も動作させることが必要。

Power Manager + Battery

ProgramMemory

DataMemoryCPU

MAC

ADC

RFsignal

sensor

コイン電池１個で何年間も動作させることが必要。

Power Manager + Battery

ProgramMemory

DataMemoryCPU

MAC

ADC

RFsignal

sensor

Vast numbers of sensors, active for several years with a tiny battery or a solar cell （ex.10mW level、100kbps 10m Wireless Network）

Sensor network for Social Security and Information Grid

Sensor Node

S


• Power Saving - Low power , long battery life • Data processing speed – high speed

processing with very low power and limited memory capacity

• Large band width – high speed network • Cost - smaller and cheaper ! • Flexibility with universal protocol • Information security – Certification between

nodes

Issues for Sensor Nodes

Basic requirement


Dennard’s Scaling Law

Source: Intel (http://www.intel.com), from presentation at ISSCC 2003

パラメータ記号 ScalingElectric Field E　∝　V/ｘ 1

Tr density 1/WL K2

Current I　∝　WV2/(LTox) 1/K

Capacitance Cload　∝　LW/Tox 1/K

Speed τ　∝　Cload*V/I 1/KPower density P ∝　VI/LW 1

High speed processing and low power consumption was satisfied by scaling at

the same time.

http://www.intel.com/


ITRS device trend: Device Speed vs Power Consumption

0

1E+12

2E+12

3E+12

4E+12

5E+12

6E+12

7E+12

1000 1500 2000 2500 3000 3500 4000

Power [kW/cm2]

Spe

ed

[GH

z]

系列1

High-k/ MetalG

UT SOI

Bulk Conv.

HP

UT SOI Bulk Conv.

LSTP

Power Consumption per unit Area (A.U.)

1.0 1.5 2.0 2.5 3.0 3.5 4.0

7

Spe

ed

(Gat

e D

elay

) [T

Hz]

6

3

2

1

0

5

4

From: ITRS* Roadmap 2009

(2009- 2024 trend)

Ideal situation is not expected for further scaling ! Why??

ideal

ITRS: International Technology Roadmap for Semiconductors


Power Voltage Trend Forecast in ITRS

0

0.2

0.4

0.6

0.8

1

1.2

0 10 20 30 40 50 60

系列1

LSTP

HP

2009

2024

Half Pitch [nm]

Pow

er V

olta

ge V

dd [V

]

Insufficient Power Voltage Reduction

Scaling Law Requirement

Major Barriers for Power Voltage Reduction

• Small Ion (Device Speed

Degradation)

• Off Leakage Current Ioff Increase (Standby Power Consumption Increase)

• Relative Threshold Voltage Fluctuation Increase

From: ITRS* Roadmap 2009


Approach: Non-planer structure + Ion Booster

① Large Id ⇒ Stress engineering , High-mobility channel material ② Steep subthreshold ⇒Multi-gate

Multi-gate + Ion Booster Multi-gate Bulk Planer

Vg

Log(

I d)

0 VDD

I on

I off

①

②

Multi-Gate

Channel Cross Section

Gate

New channel

strain Gate

Si BOX

Id


Low power consumption CMOS Development

0

1

2

3

4

5

6

2008 2012 2016 2020

Pow

er

Consu

mpt

ion

（A

.U.）

0

0.2

0.4

0.6

0.8

1

1.2

Vdd

（V

)

New Concept Device

Green CMOS Si Nanowire

High Mobility Channel

Power= α・f・Cload・Vdd2 ・n + Ioff・Vdd・n

Active power Standby Power

α: Activation Ratio, f: Clock Freq., Cload:Load Capacitance,

Vdd:Supply Voltage, Ioff, n: Amount of devices

ITRS trend


Si NW: Short Channel Effect Suppression

1x10-12

1x10-10

1x10-8

1x10-6

1x10-4

0.01

-1 -0.5 0 0.5 1 1.5 2 2.5 3

Dra

in C

urre

nt (A

/µm

)

Gate Voltage (V)

Lg = 26nmWnw = 16nm H

nw = 24nm

nMOSFET Vd = 1V

Vd = 10mV

w/ S/D epi

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.01 0.1 1

DIB

L (V

/mV)

Lg (µm)

nMOSFET Vd : 1V

Wnw : 101,31, 21,11nm

0

30

60

90

120

150

0.01 0.1 1

S Fa

ctor

(mV/

dec)

Lg (µm)

nMOSFET

Wnw : 101,31, 21,11nm

Vd : 1VWire width reduction leads to steeper subthreshold swing

Gate

Source Drain

Tox=3nm


(Simulation)

⇒Further NW thinning is desired


Si NW: Parasitic Resistance Reduction SiN

TEOS sidewallPoly Gate

BOX

Epi-Si（25nm）

Source Drain

SiN

TEOS sidewallPoly Gate

BOX

Epi-Si（25nm）

Source Drain

(111)面

BOX

+25nm

+20nm<001>

<110>

(111)面

BOX

+25nm

+20nm<001>

<110>

Cross sectional View of NW after Epigrowth on S/D

200nm

Source

Drain

Gate

NW channel

Enlarged by Epi-growth

200nm

Source

Drain

Gate

NW channel

Enlarged by Epi-growth


NW: Parasitic Resistance Reduction

1x10-11

1x10-10

1x10-9

1x10-8

1x10-7

1x10-6

1x10-5

1x10-4

0 100 200 300 400 500 600Ion (µA/µm) @ Vg = 0.7 V

I off (A

/µm

) @ V

g = -0

.3 V

Vd = 1 V

x 2.4

nMOSFETWnw : 20nm

w/o S/D Epi

w/ S/D EpiSOI

BOX

GateTEOSSW

Silicide

NW

Rsw

Repi

RcSOI

BOX

GateTEOSSW

Silicide

NW

Rsw

Repi

Rc

Ion increase by a factor of 2.4 was obtained. ⇒Parasitic resistance reduction is important

especially for NW transistors.


3D stress engineering for NW MOSFETs

• In addition to longitudinal stress, transversal and vertical stress is effective for NW MOSFETs

BOX

Si substrate

SOI Fin

Vertical stress Longitudinal stress

Transversal Stress


Stress engineering to nanowire channel is highly effective for the performance improvement of nanowire transistors.

Si Nanowire Transistors: Stain Technique

30nm

SOI

Lg : 15nm Epi Si : 25nm Spacer :

10nm

<110>

HNW : 15nm

WNW :11nm

Stress Memorization Technique (SMT) of Poly-Si Gate

0 200 400 600 800 1000I of

f @ V

g = -0

.4V

(A/µ

m)

Ion @ Vg = 0.6V (µA/µm)

+58 %

<110> NW nFETWNW ~ 15nm

w/ SMT

w/o SMT

Vd = 1V

Tinv = 3.8nm

10-5

10-6

10-7

10-8

10-9

10-10

10-11

10-12


Strain is especially effective for thinner NW.

Dependence on wire width

Cross-sectional View

Planer view

Planar(W=1µm)

1

1.1

1.2

1.3

1.4

1.5

1.62.7

3

0 20 40 60 80 100WNW (nm)

NW nFETL ~ 70nmVg - Vth = 1 V

I dlin

Enh

ance

men

t Rat

io b

y SM

T

<110><100>

30nm

ナノワイヤ

Lg : 15nmEpi Si

Gate電極

Spacer

30nm

ナノワイヤ

Lg : 15nmEpi Si

Gate電極

Spacer

Wire Width [nm]


Performance of SMT NW CMOS

CMOS performance is greatly improved by NW .

Ieff-1 : Measure of CMOS inverter delay

0.5

0.6

0.7

0.8

0.9

1I ef

f,nM

OS-1

+ I ef

f,pM

OS-1

w/o SMT

Ioff

= 100nA/µm

<110> NW CMOS

w/ SMT

15nm

w/ SMTnMOS :pMOS : w/o SMT w/ SMT w/o SMT w/o SMT

w/ SMT

24nmHNW :

Large Ion(nMOS)Increase by SMT

Slight Ion(pMOS)Decrease by SMT

µ Increaseby Tall NW


High-mobility channels for CMOS

Material Strain

Normalized mobility (vs. unstrained Si) Remarks n p

Si biaxial 2 [1] 1.4 [1]

uniaxial 1.7 [2] 3 - 4 [2, 10]

Si1-xGex biaxial 2.3 [3] 6~10 [4]

x=0.42 x=0.92

Ge

No 1.4 [5] 3 [7]

2 [6] with high-k theory

Uniaxial biaxial

4.1 [7] 10~20 [8,9]

theory buried channel

GaAs No 6.3 [2] 0.8 [2] Low field/bulk

InAs No 13-20 [2] 0.2-0.9 [2] Low field/bulk

[1] K.Rim et al., IEDM 2003, [2] S. E. Thompson, IEDM 2006, [3] T.Tezuka et al., IEDM 2001, [4] T.Tezuka et al., 2004 Symp. on VLSI Tech. [5] H. Shang et al., IEDM 2002, [6] C. Chui et al.,IEDM 2002, [7] Y.-J. Yang et al., APL 91,102103 (2007).[8] M. L. Lee et al., IEDM 2003, [9] T. Irisawa et al., APL 81, 847 (2002). [10] S. Mayuzumi et al., 2009 Symp. on VLSI Tech.

p&nFET

pFET

nFET


SiGe Nano Wire formed by Ge condensation process

Higher Ge fractions for the narrower mesas Formation of Ge-rich and narrow SiGe wires Compressive stress is imposed at the same time

20

30

40

50

60

70

80

90

100

0 100 200 300 400 500 600 G

e fra

ctio

n (%

)

Wire Width (nm)

From EDX

Before 3D Condensation RIE

BOX(SiO2) Si1-xGex

1st-Condensation

SiO2

2nd-Condensation Si1-yGey (y>x)

950°C, 2h


SGOI-wire pFETs

On/off ratio >104

Higher gm by a factor 3 due to higher Ge fraction, uniaxial compressive strain and {110}-like sidewall

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

-20 -10 0 10 20

Vg (V)

Id /

W (A

/µm

)

Vd = -0.05 VLg = 4 µm

Ge = 92%

79%

65%

53%46%

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

-20 -10 0 10 20

Vg (V)gm

/ W

(mS

/µm

)

Vd = -0.05 VLg = 4 µm Ge = 79%

65%

53%46%

92%0%

Higher x and ε


SiGe-Trigate pFET Lg=50nm

•Mobility enhancement x4.9 •Id increase 45% (Power reduction 39% by overdrive decrease)

0

1 10-5

2 10-5

3 10-5

4 10-5

5 10-5

-2 -1.5 -1 -0.5 0

SOISGOI (x=0.65)

I d / C

inv (

A µ

m/ f

F)

Gate voltage Vg-Vth (V)

Lg=50 nm

0

100

200

300

400

500

600

1012 1013

SGOI (x = 0.65)Si (100)/<110>Si (110)/<110>

Hol

e m

obili

ty µ

eff (c

m2 /V

s)

Surface carrier concentration N

s (cm-2)

30nm

BOX

NiSi

TaNHfO2

xGe=0.65一軸圧縮ひずみ:2.7%

SiGe

30nm

BOX

NiSi

TaNHfO2

30nm

BOX

NiSi

TaNHfO2

xGe=0.65一軸圧縮ひずみ:2.7%

SiGe

Uniaxial strain


How about NMOS?

2.3~4.1 times higherthan unstrained Si

Tensile strain over 1 %

2.3~4.1 times higherthan unstrained Si

Tensile strain over 1 %

• Higher electron mobility of Ge than Si Si Ge

µe 1500 3900 µh 450 1900

• Tensile strain in Ge … µe enhancement

Possibility of strained Ge-nMOS in combination with high-speed Ge-pMOSFETs

Y.-J. Yang et al., APL 91,102103 (2007).


Graphene


Tensile strain vs Ge comp. of stressors

290 295 300 305 310

X=0.7X=0.8X=0.9Ref.(Ge)

Inte

nsity

(a.u

.)

Wavenumber [cm-1]

Ge-Ge in Ge

Ge-Ge in SiGe

0

0.002

0.004

0.006

0.008

0.01

0.012

0.65 0.7 0.75 0.8 0.85 0.9 0.95

Uni

-axi

al T

ensi

le S

train

Ge Composition, x

Max.; ~1.15 % @ x=0.7

Lattice mismatch between Ge and Si0.3Ge0.7 ~1.3%

Tensile strain

Tensile uni-axial strain over 1 % was introduced @ x=0.7

Raman spectra @ Gate edges


Lg dependence of strain and Gm increase

-0.002

0

0.002

0.004

0.006

0.008

0.01

70 80 90 100 110 120 130 140

GeSiGe (x=0.8)SiGe (x=0.7)

Uni

-axi

al T

ensi

le S

trai

n

Lg + 2L

sw [nm]

Gmmax increased by a factor of 2 by Lg scaling

Average value along channel


Normalized Gm max gain by 1% strain

0

5

10

15

20

40 60 80 100 120 140

ControlGe EpiSiGe(x=0.8) EpiSiGe(x=0.7) Epi

Gm

max

(L) /

Gm

max

(L=1

µm)

Gate Length [nm]

Vd = 1V

0

5

10

15

20

40 60 80 100 120 140

ControlGe EpiSiGe(x=0.8) EpiSiGe(x=0.7) Epi

Gm

max

(L) /

Gm

max

(L=1

µm)

Gate Length [nm]

Vd = 0.05V

About 60% gain for Gmmax at Vd=0.05V About 30% gain for Gmmax at Vd=1V


Graphene : Ultimate material ?

A.H.Castro Neto, et al., Rev.Mod.Phys. B. 81(2009), 109.

Mobility > 200,000cm2/Vs K.I.Bolotina, et al., solid state commun. 146(2008), 351.


Summary

• Cloud computing and storage data explosion lead to the large power consumption of IT facilities worldwide. Sensor Network system requires vast numbers of low power sensor nodes. Measures for the dramatic reduction of power consumption of LSIs are quite important.

• Novel approach such as 3D channel structure, strain introduction, parasitic resistance reduction as well as application of new channel material is effective to meet the demands through the reduction of the power supply voltage of LSIs.

• Further research and development of this field is indispensable for the evolution of very low power electric system throughout the globe.


Acknowledgement

This presentation includes Project results partly supported by NEDO.

Documents

New channel engineering for the low power CMOS … · Stress Memorization Technique (SMT) ... K.Rim et al., IEDM 2003, [2] ... Surface carrier concentration N s (cm-2) 30nm BOX NiSi