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FPGAs for HIL and Engine Simulation
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Field-Programmable Gate Array (FPGA)
Configurable Logic Blocks (CLBs)Implement logic using flip-flops and LUTs
Multipliers and DSPsImplement signal processing using multiplier and multiplier-accumulate circuitry
Memory BlocksStore data sets or values in user defined RAM
Programmable InterconnectsRoute signals through the FPGA matrix
I/O BlocksDirectly access digital and analog I/O
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FPGAs - Why Are They Useful?
• Hard determinism – Realistic simulation timing, local intelligence
• Off-load processing – Achieve real-time performance with more complex simulations
• Custom Hardware – Create custom H/W instruments
• Reconfigurable hardware personalities – Adapt to multiple UUT types and changing UUT interfaces
• Industry standard technology – Off the shelf chips used for specific applications get COTS benefits like Moore’s Law
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FPGAs in HIL Test Systems
IO UUT
SignalConditioning
µP
Test Application
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µP IO UUT
SignalConditioning
FPGA
FPGAPersonality
Test Application
FPGAs in HIL Test Systems
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FPGAs in HIL Test Systems
µP IO UUT
SignalConditioning
FPGA
FPGAPersonality
Test Application
NI Reconfigurable I/O (RIO) Platform
Hardware I/OInterfaces
Test ApplicationInterfaces
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Mechanical Systems – Engine Sensor Simulation
µP I/O UUTFPGA
(Engine Simulatio
n)
CrankRPMs
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Free Engine Simulation Toolkit
• Fully featured for Engine Control Unit (ECU) testing• FPGA-based sensor simulation and measurement for ultra-fast pin-to-pin response time & lifetime upgradability
• Seamless integration with NI FPGA hardware and NI VeriStand• Scalable design for simple to complex ECU testing • Suitable for open loop or closed loop• Open source architecture customizable with LabVIEW FPGA
• Supports any NI FPGA device
• Deploy with NI VeriStand 2013 or later• Design with LabVIEW 2013 or later
Digital Pattern
Generation
Analog Data Replay
ECU Event Timing Capture
Knock Sensor Simulation
Directional Sensor
Simulation
ECU Event Waveform Capture
Digital Pattern
Generation
Analog Data Replay
ECU Event Timing Capture
Knock Sensor Simulation
Directional Sensor
Simulation
ECU Event Waveform Capture
Engine Simulation Toolkit Building Blocks
Angle Processing Unit (APU)
FPGA
CPU
Digital Pattern
Generation(i.e. Hall)
Analog Replay (i.e.
VR)
ECU Event Timing Capture(Inject & Ignite)
Knock Sensor Simulation
Directional Sensor
Simulation
ECU Event Waveform Capture
Speed, Crank Angle, Cycle Angle
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Engine Simulation Toolkit RoadmapItem Old AES Library
Angle Processing Unit (APU)
2 and 4 stroke engines
Digital Pattern Generation
N-M Teeth GenerationCustom Edges
Generation
Analog Replay Play back any file by angle
ECU Event Measurement
Digital input timing capture of single event
per cycle
Knock Sensor N/A
Directional Speed Sensor
N/A
FPGA space utilization
Baseline
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Engine Simulation Toolkit RoadmapItem Old AES Library Engine Simulation
Toolkit
Angle Processing Unit (APU)
2 and 4 stroke engines Improved usability
Digital Pattern Generation
N-M Teeth GenerationCustom Edges
GenerationImproved usability
Analog Replay Play back any file by angle Improved usability
ECU Event Measurement
Digital input timing capture of single event
per cycle
Windowing, multi-event per cycle, error detection, & improved
usability
Knock Sensor N/A
Pseudorandom, amplitude &
probability per cylinder.
Directional Speed Sensor
N/A
Different forward/reverse digital pulse width triggered
at tooth centers
FPGA space utilization
Baseline 3x Reduction
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Item Old AES Library Engine Simulation Toolkit
Q4 2014
Angle Processing Unit (APU)
2 and 4 stroke engines Improved usability
Digital Pattern Generation
N-M Teeth GenerationCustom Edges
GenerationImproved usability
Analog Replay Play back any file by angle Improved usability
ECU Event Measurement
Digital input timing capture of single event
per cycle
Windowing, multi-event per cycle, error detection, & improved
usability
Analog input thresholding and
waveform capture
Knock Sensor N/A
Pseudorandom, amplitude &
probability per cylinder.
Directional Speed Sensor
N/A
Different forward/reverse digital pulse width triggered
at tooth centers
FPGA space utilization
Baseline 3x Reduction
Engine Simulation Toolkit Roadmap
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Space and performance comparison
7854RPXIe 8130PXIe 1082
AES Library1 APU1 N-M generation4 Fully Custom generation1 Analog Replay12 Event Capture
Engine Simulation Toolkit1 APU5 Digital Pattern Generation1 Analog Replay12 Event Capture
Slices 6,703 of 17,280 (38.8%) 3,159 of 17,280 (18.3%)
Registers 14,882 of 69,120 (21.5%) 5,912 of 69,120 (8.6%)
LUTs 19,702 of 69,120 (28.5%) 8,239 of 69,120 (11.9%)
DSP 24 of 64 (37.5%) 2 of 64 (3.1%)
BRAM 21 of 128 (37.5%) 13 of 128 (10.2%)
40 Mhz Max 42.69 65.35
Compile time 37 minutes 21.7 minutes
RT LoopDuration
305 to 335 uS 138 to 186 uS w/ RIO 13.1132 to 165 uS w/ RIO 15.0
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Reconfigurable I/O Interfaces
µP I/OFPGA
V6 ECU
V8 ECU
Multiple UUT types
Evolution of UUT interface
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NI VeriStand System Explorer
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Analog Replay
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Analog Replay Configuration
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Analog Replay: Voltage Scaling Configuration
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Example FPGA: APU + 1 Analog Replay
Load Look Up Table
APU
Play Look Up Table
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Example FPGA : APU + 2 Analog Replay
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Digital Pattern Generation
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Digital Pattern Generation of Two Cams and a Crank
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Digital Pattern Generation Design
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Digital Pattern Generation supports complex patterns easily
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Example FPGA: 2 Digital Pattern Generations
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Knock Sensor Simulation
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Knock Sensor Simulation Configuration
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Example FPGA: Knock Sensor Simulation Loop
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Knock Sensor with 4 Cylinders
(Probably had been set to 100% with 4 different amplitudes)
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Directional Speed Sensor Simulation
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Directional Speed Sensor
• Generates pulses of different widths, depending on forward (Tf) or reverse (Tr) rotation, when passing tooth centers
• Pulse slightly delayed from center by variable microseconds (Td)
Crank
Directional sensor: forward
Directional sensor: reverse
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Directional Speed Sensor
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Example FPGA: 1 Directional Speed Sensor
Load Tooth Centers Look Up Table From APU
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ECU Event Capture
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Example FPGA : Typical MPI Injection Measurement (1 x Cylinder)
Event measurement block settings:• Angle Max (degrees)• Angle Min (degrees)• Active High (Boolean)• Time based ‘stuck active’
timeout (milliseconds)
Event capture block outputs:• Event Present (Boolean)• Start Angle (degrees)• End Angle (degrees)• Duration (milliseconds)
Digital Input
Event measurement block outputs:• Stuck active (Boolean)• Window all active (Boolean)• Window orphan start edge
(Boolean)• Window orphan end edge
(Boolean)
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Example FPGA : Typical GDI or Diesel Injection Measurement (1 x Cylinder)
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Example FPGA : Typical GDI or Diesel Injection Measurement (2 x Cylinder)
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Example FPGA : Customize Windowing Per Event
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ECU Event Capture Configuration
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ECU Event Capture Configuration
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Generation and measurement of two events neither wrapping 0 and window does not wrap 0
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Generation of one event wrapping zero and one not wrapping zero; window wraps zero and measures both
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Start of a full cycle event within window, causing an orphan start edge and a stuck active flag
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End of full cycle event within next window, causing an orphan end edge
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Future* FPGA : Typical GDI or Diesel Injection Timing & Waveform Measurement
Analog Input Thresholding Timing Measurement and Capture
Waveform capture
*Q4 2014
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Case Study
Application
Creating a flexible HIL test system with I/O interfaces that require custom timing and synchronization schemes not easily implementable with traditional hardware. NI Products
LabVIEW FPGA Module, PXI, and Reconfigurable I/O (RIO) hardware
"With LabVIEW FPGA and RIO hardware we were able to quickly
and efficiently design custom analog and digital interfaces for
our HIL test system.”
– Roy Kranz, Wineman Technology Inc.
Key Benefit
Gaining the ability to efficiently create custom hardware interfaces that can be reconfigured after deployment to adapt to different ECU types and changes to ECU interfaces.
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Summary
• FPGA-based I/O interfaces are used to expand the capabilities and performance of HIL test systems.
• Hard determinism – Realistic simulation timing and local intelligence with 25 ns resolution
• Off-load processing – Achieve real-time performance with more complex simulations
• Custom Hardware – Create custom H/W instruments
• Industry standard technology – Off the shelf chips used for specific applications get COTS benefits
• Reconfigurable hardware personalities – Test multiple UUT types and adapt to changes in UUT interfaces without changing hardware
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